/freebsd/sys/contrib/alpine-hal/ |
H A D | al_hal_pbs_regs.h | 60 /* [0x0] Conf_bus, Configuration of the SB */ 62 /* [0x4] PASW high */ 64 /* [0x8] PASW low */ 66 /* [0xc] PASW high */ 68 /* [0x10] PASW low */ 70 /* [0x14] PASW high */ 72 /* [0x18] PASW low */ 74 /* [0x1c] PASW high */ 76 /* [0x20] PASW low */ 78 /* [0x24] PASW high */ [all …]
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H A D | al_hal_udma_regs_s2m.h | 59 /* [0x0] Data write master configuration */ 61 /* [0x4] Data write master configuration */ 63 /* [0x8] Descriptor read master configuration */ 65 /* [0xc] Descriptor read master configuration */ 67 /* [0x10] Completion write master configuration */ 69 /* [0x14] Completion write master configuration */ 71 /* [0x18] Data write master configuration */ 73 /* [0x1c] Descriptors read master configuration */ 75 /* [0x20] Completion descriptors write master configuration */ 77 /* [0x24] AXI outstanding read configuration */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra124-nyan-blaze-emc.dtsi | 92 0x40040001 93 0x8000000a 94 0x00000001 95 0x00000001 96 0x00000002 97 0x00000000 98 0x00000002 99 0x00000001 100 0x00000002 101 0x00000008 [all …]
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H A D | tegra124-apalis-emc.dtsi | 108 0x40040001 0x8000000a 109 0x00000001 0x00000001 110 0x00000002 0x00000000 111 0x00000002 0x00000001 112 0x00000003 0x00000008 113 0x00000003 0x00000002 114 0x00000003 0x00000006 115 0x06030203 0x000a0502 116 0x77e30303 0x70000f03 117 0x001f0000 [all …]
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H A D | tegra124-jetson-tk1-emc.dtsi | 104 0x40040001 105 0x8000000a 106 0x00000001 107 0x00000001 108 0x00000002 109 0x00000000 110 0x00000002 111 0x00000001 112 0x00000003 113 0x00000008 [all …]
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H A D | tegra124-nyan-big-emc.dtsi | 263 0x40040001 /* MC_EMEM_ARB_CFG */ 264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ 265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ 270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ [all …]
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/freebsd/tools/test/iconv/ref/ |
H A D | UTF-7 | 1 0x09 = 0x00000009 2 0x0A = 0x0000000A 3 0x0D = 0x0000000D 4 0x20 = 0x00000020 5 0x21 = 0x00000021 6 0x22 = 0x00000022 7 0x23 = 0x00000023 8 0x24 = 0x00000024 9 0x25 = 0x00000025 10 0x26 = 0x00000026 [all …]
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/freebsd/sys/dev/sound/pci/ |
H A D | emuxkireg.h | 50 #define EMU_PTR 0x00 51 #define EMU_PTR_CHNO_MASK 0x0000003f 52 #define EMU_PTR_ADDR_MASK 0x07ff0000 53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000 55 #define EMU_DATA 0x04 57 #define EMU_IPR 0x08 58 #define EMU_IPR_RATETRCHANGE 0x01000000 59 #define EMU_IPR_FXDSP 0x00800000 60 #define EMU_IPR_FORCEINT 0x00400000 61 #define EMU_PCIERROR 0x00200000 [all …]
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H A D | t4dwave.h | 32 #define TR_REG_CIR 0xa0 33 #define TR_CIR_MASK 0x0000003f 34 #define TR_CIR_ADDRENA 0x00001000 35 #define TR_CIR_MIDENA 0x00002000 36 #define TR_REG_MISCINT 0xb0 37 #define TR_INT_ADDR 0x00000020 38 #define TR_INT_SB 0x00000004 40 #define TR_REG_DMAR0 0x00 41 #define TR_REG_DMAR4 0x04 42 #define TR_REG_DMAR11 0x0b [all …]
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H A D | csapcm.c | 99 SND_FORMAT(AFMT_U8, 1, 0), 100 SND_FORMAT(AFMT_U8, 2, 0), 101 SND_FORMAT(AFMT_S8, 1, 0), 102 SND_FORMAT(AFMT_S8, 2, 0), 103 SND_FORMAT(AFMT_S16_LE, 1, 0), 104 SND_FORMAT(AFMT_S16_LE, 2, 0), 105 SND_FORMAT(AFMT_S16_BE, 1, 0), 106 SND_FORMAT(AFMT_S16_BE, 2, 0), 107 0 109 static struct pcmchan_caps csa_playcaps = {8000, 48000, csa_playfmt, 0}; [all …]
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/freebsd/sys/powerpc/include/ |
H A D | bat.h | 76 #define BAT_PBS 0xfffe0000 /* physical block start */ 77 #define BAT_W 0x00000040 /* 1 = write-through, 0 = write-back */ 78 #define BAT_I 0x00000020 /* cache inhibit */ 79 #define BAT_M 0x00000010 /* memory coherency enable */ 80 #define BAT_G 0x00000008 /* guarded region */ 82 #define BAT_PP_NONE 0x00000000 /* no access permission */ 83 #define BAT_PP_RO_S 0x00000001 /* read-only (soft) */ 84 #define BAT_PP_RW 0x00000002 /* read/write */ 85 #define BAT_PP_RO 0x00000003 /* read-only */ 88 #define BAT_EBS 0xfffe0000 /* effective block start */ [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepMask.h | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 17 0xf0000000, 18 0xb0000000, 19 0x0fe03fe0, 20 0 }, 23 0xffc00000, 24 0x76000000, 25 0x00203fe0, 26 0 }, 29 0xff800000, [all …]
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/freebsd/contrib/expat/lib/ |
H A D | nametab.h | 34 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 35 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 36 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x04000000, 37 0x87FFFFFE, 0x07FFFFFE, 0x00000000, 0x00000000, 0xFF7FFFFF, 0xFF7FFFFF, 38 0xFFFFFFFF, 0x7FF3FFFF, 0xFFFFFDFE, 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 39 0xFFFFE00F, 0xFC31FFFF, 0x00FFFFFF, 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 40 0xFFFFFFFF, 0xF80001FF, 0x00000003, 0x00000000, 0x00000000, 0x00000000, 41 0x00000000, 0x00000000, 0xFFFFD740, 0xFFFFFFFB, 0x547F7FFF, 0x000FFFFD, 42 0xFFFFDFFE, 0xFFFFFFFF, 0xDFFEFFFF, 0xFFFFFFFF, 0xFFFF0003, 0xFFFFFFFF, 43 0xFFFF199F, 0x033FCFFF, 0x00000000, 0xFFFE0000, 0x027FFFFF, 0xFFFFFFFE, [all …]
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/freebsd/sys/contrib/dev/rtw89/ |
H A D | rtw8852c_rfk_table.c | 8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1), 9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1), 10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1), 11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1), 17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x [all...] |
H A D | rtw8852a_table.c | 10 {0xF0FF0001, 0x00000000}, 11 {0xF03300FF, 0x00000001}, 12 {0xF03500FF, 0x00000002}, 13 {0xF03200FF, 0x00000003}, 14 {0xF03400FF, 0x0000000 [all...] |
/freebsd/sys/dev/rtwn/rtl8188e/ |
H A D | r88e_tx_desc.h | 27 #define R88E_TXDW1_MACID_M 0x0000003f 28 #define R88E_TXDW1_MACID_S 0 31 #define R88E_TXDW2_AGGEN 0x00001000 32 #define R88E_TXDW2_AGGBK 0x00010000 35 #define R88E_TXDSEQ_HWSEQ_EN 0x8000
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/ |
H A D | popcountsi2.c | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 19 x = x - ((x >> 1) & 0x55555555); in __popcountsi2() 21 x = ((x >> 2) & 0x33333333) + (x & 0x33333333); in __popcountsi2() 23 x = (x + (x >> 4)) & 0x0F0F0F0F; in __popcountsi2() 28 return (x + (x >> 8)) & 0x0000003F; // (6 significant bits) in __popcountsi2()
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/freebsd/sys/dev/rtwn/rtl8192c/ |
H A D | r92c_rx_desc.h | 26 #define R92C_RXDW0_PKTLEN_M 0x00003fff 27 #define R92C_RXDW0_PKTLEN_S 0 28 #define R92C_RXDW0_CRCERR 0x00004000 29 #define R92C_RXDW0_ICVERR 0x00008000 30 #define R92C_RXDW0_INFOSZ_M 0x000f0000 32 #define R92C_RXDW0_CIPHER_M 0x00700000 34 #define R92C_RXDW0_QOS 0x00800000 35 #define R92C_RXDW0_SHIFT_M 0x03000000 37 #define R92C_RXDW0_PHYST 0x04000000 38 #define R92C_RXDW0_SWDEC 0x08000000 [all …]
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H A D | r92c_tx_desc.h | 28 #define R92C_FLAGS0_BMCAST 0x01 29 #define R92C_FLAGS0_LSG 0x04 30 #define R92C_FLAGS0_FSG 0x08 31 #define R92C_FLAGS0_OWN 0x80 34 #define R92C_TXDW1_MACID_M 0x0000001f 35 #define R92C_TXDW1_MACID_S 0 36 #define R92C_TXDW1_AGGEN 0x00000020 37 #define R92C_TXDW1_AGGBK 0x00000040 39 #define R92C_TXDW1_QSEL_M 0x00001f00 42 #define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */ [all …]
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/freebsd/sys/arm/allwinner/ |
H A D | aw_rtc.c | 50 #define LOSC_CTRL_REG 0x00 51 #define A10_RTC_DATE_REG 0x04 52 #define A10_RTC_TIME_REG 0x08 53 #define A31_LOSC_AUTO_SWT_STA 0x04 54 #define A31_RTC_DATE_REG 0x10 55 #define A31_RTC_TIME_REG 0x14 57 #define TIME_MASK 0x001f3f3f 59 #define LOSC_OSC_SRC (1 << 0) 62 #define LOSC_MAGIC 0x16aa0000 63 #define LOSC_BUSY_MASK 0x00000380 [all …]
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/freebsd/sys/dev/bhnd/cores/chipc/ |
H A D | chipcreg.h | 46 #define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0) 50 #define CHIPC_ID 0x00 51 #define CHIPC_CAPABILITIES 0x04 52 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */ 53 #define CHIPC_BIST 0x0C 55 #define CHIPC_OTPST 0x10 /**< otp status */ 56 #define CHIPC_OTPCTRL 0x14 /**< otp control */ 57 #define CHIPC_OTPPROG 0x18 58 #define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */ 60 #define CHIPC_INTST 0x20 /**< interrupt status */ [all …]
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/freebsd/sys/dev/rtwn/rtl8812a/ |
H A D | r12a_tx_desc.h | 35 #define R12A_FLAGS0_BMCAST 0x01 36 #define R12A_FLAGS0_LSG 0x04 37 #define R12A_FLAGS0_FSG 0x08 38 #define R12A_FLAGS0_OWN 0x80 41 #define R12A_TXDW1_MACID_M 0x0000003f 42 #define R12A_TXDW1_MACID_S 0 43 #define R12A_TXDW1_QSEL_M 0x00001f00 46 #define R12A_TXDW1_QSEL_BE 0x00 /* or 0x03 */ 47 #define R12A_TXDW1_QSEL_BK 0x01 /* or 0x02 */ 48 #define R12A_TXDW1_QSEL_VI 0x04 /* or 0x05 */ [all …]
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/freebsd/sys/contrib/ncsw/inc/flib/ |
H A D | fsl_fman_memac.h | 44 #define CMD_CFG_MG 0x80000000 /* 00 Magic Packet detection */ 45 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ 46 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */ 47 #define CMD_CFG_SFD_ANY 0x00200000 /* 10 Disable SFD check */ 48 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */ 49 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */ 50 #define CMD_CFG_SEND_IDLE 0x00010000 /* 15 Force idle generation */ 51 #define CMD_CFG_CNT_FRM_EN 0x00002000 /* 18 Control frame rx enable */ 52 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */ 53 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */ [all …]
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/freebsd/sys/arm/ti/ |
H A D | ti_adcreg.h | 30 #define ADC_REVISION 0x000 31 #define ADC_REV_SCHEME_MSK 0xc0000000 33 #define ADC_REV_FUNC_MSK 0x0fff0000 35 #define ADC_REV_RTL_MSK 0x0000f800 37 #define ADC_REV_MAJOR_MSK 0x00000700 39 #define ADC_REV_CUSTOM_MSK 0x000000c0 41 #define ADC_REV_MINOR_MSK 0x0000003f 42 #define ADC_SYSCFG 0x010 43 #define ADC_SYSCFG_IDLE_MSK 0x000000c0 45 #define ADC_IRQSTATUS_RAW 0x024 [all …]
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/freebsd/contrib/llvm-project/lld/ELF/Arch/ |
H A D | Hexagon.cpp | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 56 defaultMaxPageSize = 0x10000; in Hexagon() 71 return ret.value_or(/* Default Arch Rev: */ 0x60); in calcEFlags() 75 uint32_t result = 0; in applyMask() 76 size_t off = 0; in applyMask() 78 for (size_t bit = 0; bit != 32; ++bit) { in applyMask() 170 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f}, 171 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80}, 172 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0}, 173 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0}, [all …]
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