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/linux/arch/arm64/boot/dts/freescale/
H A Dtqma8xx.dtsi11 reg = <0x00000000 0x80000000 0 0x40000000>;
40 size = <0 0x20000000>;
41 alloc-ranges = <0 0x96000000 0 0x30000000>;
59 pinctrl-0 = <&pinctrl_flexspi0>;
62 flash0: flash@0 {
63 reg = <0>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_lpi2c1>;
92 reg = <0x1b>;
97 reg = <0x51>;
[all …]
H A Dimx8-apalis-v1.1.dtsi17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18 brightness-levels = <0 45 63 88 119 158 203 255>;
28 pinctrl-0 = <&pinctrl_gpio8>;
30 gpio-fan,speed-map = < 0 0
82 pinctrl-0 = <&pinctrl_wifi_pdn>;
93 pinctrl-0 = <&pinctrl_gpio7>;
105 pinctrl-0 = <&pinctrl_usbh_en>;
135 reg = <0 0x84000000 0 0x2000000>;
140 reg = <0 0x86000000 0 0x200000>;
145 reg = <0 0x86200000 0 0x200000>;
[all …]
H A Dmba8xx.dtsi15 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
26 pinctrl-0 = <&pinctrl_bl_lvds>;
27 pwms = <&adma_pwm 0 5000000 0>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
42 pinctrl-0 = <&pinctrl_gpiobuttons>;
91 pinctrl-0 = <&pinctrl_reg_pcie_1v5>;
103 pinctrl-0 = <&pinctrl_reg_pcie_3v3>;
129 pinctrl-0 = <&pinctrl_adc0>;
137 pinctrl-0 = <&pinctrl_admapwm>;
142 pinctrl-0 = <&pinctrl_fec1>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml116 reg = <0xc0100000 0x00000400>,
117 <0xc0101000 0x00000020>,
118 <0xc0102000 0x00000020>,
119 <0xc0103000 0x00000008>,
120 <0xc0104000 0x00000020>,
121 <0xc0105000 0x00000020>,
122 <0xc0106000 0x00000100>;
125 interrupts = <0 44 4>,<0 45 4>;
140 reg = <0x00001000 0x00000400>,
141 <0x00001460 0x00000020>,
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux/arch/mips/ath25/
H A Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/linux/arch/nios2/boot/dts/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
H A D10m50_devboard.dts16 #size-cells = <0>;
18 cpu: cpu@0 {
21 reg = <0x00000000>;
24 altr,exception-addr = <0xc8000120>;
25 altr,fast-tlb-miss-addr = <0xc0000100>;
32 altr,reset-addr = <0xd4000000>;
46 reg = <0x08000000 0x08000000>,
47 <0x00000000 0x00000400>;
50 sopc0: sopc@0 {
60 reg = <0x18001530 0x00000008>;
[all …]
/linux/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/linux/drivers/net/ethernet/renesas/
H A Dravb.h39 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
46 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
50 CCC = 0x0000,
51 DBAT = 0x0004,
52 DLR = 0x0008,
[all …]
/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/linux/arch/powerpc/include/asm/
H A Dkeylargo.h10 /* "Pangea" chipset has keylargo device-id 0x25 while core99
11 * has device-id 0x22. The rev. of the pangea one is 0, so we
12 * fake an artificial rev. in keylargo_rev by oring 0x100
14 #define KL_PANGEA_REV 0x100
17 #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
18 #define KEYLARGO_FCR0 0x38
19 #define KEYLARGO_FCR1 0x3c
20 #define KEYLARGO_FCR2 0x40
21 #define KEYLARGO_FCR3 0x44
22 #define KEYLARGO_FCR4 0x48
[all …]
/linux/sound/soc/fsl/
H A Dfsl_ssi.h15 /* SSI Transmit Data Register 0 */
16 #define REG_SSI_STX0 0x00
18 #define REG_SSI_STX1 0x04
19 /* SSI Receive Data Register 0 */
20 #define REG_SSI_SRX0 0x08
22 #define REG_SSI_SRX1 0x0c
24 #define REG_SSI_SCR 0x10
26 #define REG_SSI_SISR 0x14
28 #define REG_SSI_SIER 0x18
30 #define REG_SSI_STCR 0x1c
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl827c.h28 #define NV827C_SET_PRESENT_CONTROL (0x00000084)
30 #define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
31 #define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
32 #define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
36 #define NV827C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0…
37 #define NV827C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
38 #define NV827C_SET_PROCESSING (0x00000110)
39 #define NV827C_SET_PROCESSING_USE_GAIN_OFS 0:0
40 #define NV827C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
41 #define NV827C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
[all …]
H A Dcl507c.h27 #define NV_DISP_BASE_NOTIFIER_1 0x00000000
28 #define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004
29 #define NV_DISP_BASE_NOTIFIER_1__0 0x00000000
30 #define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0
33 #define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000
34 #define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001
35 #define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002
39 #define NV507C_DMA 0x00000000
41 #define NV507C_DMA_OPCODE_METHOD 0x00000000
42 #define NV507C_DMA_OPCODE_JUMP 0x00000001
[all …]
H A Dcl907c.h28 #define NV907C_SET_PRESENT_CONTROL (0x00000084)
30 #define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
31 #define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
32 #define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
33 #define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_AT_FRAME (0x00000003)
35 #define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
36 #define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
40 #define NV907C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0…
41 #define NV907C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
42 #define NV907C_SET_BASE_LUT_LO (0x000000E0)
[all …]
/linux/arch/openrisc/include/asm/
H A Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
[all …]
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]
/linux/drivers/media/platform/qcom/venus/
H A Dhfi_helper.h9 #define HFI_DOMAIN_BASE_COMMON 0
11 #define HFI_DOMAIN_BASE_VDEC 0x1000000
12 #define HFI_DOMAIN_BASE_VENC 0x2000000
13 #define HFI_DOMAIN_BASE_VPE 0x3000000
15 #define HFI_VIDEO_ARCH_OX 0x1
17 #define HFI_ARCH_COMMON_OFFSET 0
18 #define HFI_ARCH_OX_OFFSET 0x200000
20 #define HFI_OX_BASE 0x1000000
22 #define HFI_CMD_START_OFFSET 0x10000
23 #define HFI_MSG_START_OFFSET 0x20000
[all …]
/linux/drivers/pcmcia/
H A Dyenta_socket.h7 #define CB_SOCKET_EVENT 0x00
8 #define CB_CSTSEVENT 0x00000001 /* Card status event */
9 #define CB_CD1EVENT 0x00000002 /* Card detect 1 change event */
10 #define CB_CD2EVENT 0x00000004 /* Card detect 2 change event */
11 #define CB_PWREVENT 0x00000008 /* PWRCYCLE change event */
13 #define CB_SOCKET_MASK 0x04
14 #define CB_CSTSMASK 0x00000001 /* Card status mask */
15 #define CB_CDMASK 0x00000006 /* Card detect 1&2 mask */
16 #define CB_PWRMASK 0x00000008 /* PWRCYCLE change mask */
18 #define CB_SOCKET_STATE 0x08
[all …]
/linux/sound/pci/vx222/
H A Dvx222.h32 #define VX2_AKM_LEVEL_MAX 0x93
38 #define VX_RESET_DMA_REGISTER_OFFSET 0x00000008
41 #define VX_INTCSR_VALUE 0x00000001
42 #define VX_PCI_INTERRUPT_MASK 0x00000040
44 /* Constants used to access the CDSP register (0x20). */
45 #define VX_CDSP_TEST1_MASK 0x00000080
46 #define VX_CDSP_TOR1_MASK 0x00000040
47 #define VX_CDSP_TOR2_MASK 0x00000020
48 #define VX_CDSP_RESERVED0_0_MASK 0x00000010
49 #define VX_CDSP_CODEC_RESET_MASK 0x00000008
[all …]
/linux/arch/powerpc/boot/dts/
H A Damigaone.dts20 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
29 timebase-frequency = <0>; // 33.3 MHz, from U-boot
30 clock-frequency = <0>; // From U-boot
31 bus-frequency = <0>; // From U-boot
37 reg = <0 0>; // From U-boot
44 bus-range = <0 0xff>;
45 ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
46 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
[all …]
/linux/arch/mips/include/asm/txx9/
H A Dtx4927pcic.h87 #define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
88 #define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
89 #define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
92 #define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
95 #define TX4927_PCIC_PBACFG_FIXPA 0x00000008
96 #define TX4927_PCIC_PBACFG_RPBA 0x00000004
97 #define TX4927_PCIC_PBACFG_PBAEN 0x00000002
98 #define TX4927_PCIC_PBACFG_BMCEN 0x00000001
101 #define TX4927_PCIC_PBASTATUS_ALL 0x00000001
102 #define TX4927_PCIC_PBASTATUS_BM 0x00000001
[all …]
/linux/include/linux/mfd/
H A Dcs42l43-regs.h13 #define CS42L43_GEN_INT_STAT_1 0x000000C0
14 #define CS42L43_GEN_INT_MASK_1 0x000000C1
15 #define CS42L43_DEVID 0x00003000
16 #define CS42L43_REVID 0x00003004
17 #define CS42L43_RELID 0x0000300C
18 #define CS42L43_SFT_RESET 0x00003020
19 #define CS42L43_DRV_CTRL1 0x00006004
20 #define CS42L43_DRV_CTRL3 0x0000600C
21 #define CS42L43_DRV_CTRL4 0x00006010
22 #define CS42L43_DRV_CTRL_5 0x00006014
[all …]

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