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/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dtables_phy_lcn.c30 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
31 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
32 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
33 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
34 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
35 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
36 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
37 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
38 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
39 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/linux/sound/soc/codecs/
H A Dcs35l45-tables.c15 { 0x00000040, 0x00000055 },
16 { 0x00000040, 0x000000AA },
17 { 0x00000044, 0x00000055 },
18 { 0x00000044, 0x000000AA },
19 { 0x00006480, 0x0830500A },
20 { 0x00007C60, 0x1000850B },
21 { CS35L45_BOOST_OV_CFG, 0x007000D0 },
22 { CS35L45_LDPM_CONFIG, 0x0001B636 },
23 { 0x00002C08, 0x00000009 },
24 { 0x00006850, 0x0A30FFC4 },
[all …]
/linux/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/
H A Dmicroarch.json4 "EventCode": "0x0000000a",
9 "EventCode": "0x00000014",
14 "EventCode": "0x00000015",
19 "EventCode": "0x00000016",
24 "EventCode": "0x00000017",
30 "EventCode": "0x00000018",
35 "EventCode": "0x00000019",
40 "EventCode": "0x0000001a",
45 "EventCode": "0x0000001b",
50 "EventCode": "0x0000001c",
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl0080/
H A Dctrl0080fifo.h29 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID 4:0
30 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS (0x000000…
31 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD (0x000000…
32 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO (0x000000…
33 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG (0x000000…
34 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE (0x000000…
35 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY (0x000000…
36 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION (0x000000…
37 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS (0x000000…
38 #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL (0x000000…
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_sh_mask.h26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define MC_CG_SEQ_DRAMCONF_S0 0x05
44 #define MC_CG_SEQ_DRAMCONF_S1 0x06
45 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
46 #define MC_CG_SEQ_YCLK_RESUME 0x0a
48 #define SMC_RAM_END 0x8000
58 0x000008f8, 0x00000010, 0xffffffff,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dclc57d.h27 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208)
28 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
30 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0…
31 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
32 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
33 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
35 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
36 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
38 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
39 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
[all …]
/linux/arch/arm/mach-socfpga/
H A Docram.c12 #define ALTR_OCRAM_CLEAR_ECC 0x00000018
13 #define ALTR_OCRAM_ECC_EN 0x00000019
27 mapped_ocr_edac_addr = of_iomap(np, 0); in socfpga_init_ocram_ecc()
42 #define ALTR_A10_ECC_CTRL_OFST 0x08
43 #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
46 #define ALTR_A10_ECC_INITSTAT_OFST 0x0C
47 #define ALTR_A10_ECC_INITCOMPLETEA BIT(0)
50 #define ALTR_A10_ECC_ERRINTEN_OFST 0x10
51 #define ALTR_A10_ECC_SERRINTEN BIT(0)
53 #define ALTR_A10_ECC_INTSTAT_OFST 0x20
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x4018, 0x4F4C084B},
18 {0x401C, 0x084A4E52},
19 {0x4020, 0x4D504E4B},
[all …]
/linux/arch/powerpc/include/uapi/asm/
H A Dtermbits.h48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]
/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.c48 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f); in carl9170_init_power_cal()
49 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f); in carl9170_init_power_cal()
50 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f); in carl9170_init_power_cal()
51 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f); in carl9170_init_power_cal()
52 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f); in carl9170_init_power_cal()
53 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f); in carl9170_init_power_cal()
54 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f); in carl9170_init_power_cal()
55 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f); in carl9170_init_power_cal()
56 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f); in carl9170_init_power_cal()
57 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f); in carl9170_init_power_cal()
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dsoc24_enum.h52 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
53 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
54 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
55 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
63 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
64 CP_PERFMON_STATE_START_COUNTING = 0x00000001,
65 CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
66 CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
67 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
68 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
[all …]
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
H A Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
H A Dsoc21_enum.h55 DSM_DATA_SEL_DISABLE = 0x00000000,
56 DSM_DATA_SEL_0 = 0x00000001,
57 DSM_DATA_SEL_1 = 0x00000002,
58 DSM_DATA_SEL_BOTH = 0x00000003,
66 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
67 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
68 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
69 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
77 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
78 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
[all …]
/linux/arch/alpha/include/uapi/asm/
H A Dtermbits.h54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
[all …]
/linux/arch/arc/kernel/
H A Djump_label.c20 return 0x7000264a; in arc_gen_nop()
40 * s S[n:0] lower bits signed immediate (number is bitfield size)
66 if (u_offset & 0x1) in arc_gen_branch()
70 s = (u_offset >> 1) & GENMASK(9, 0); in arc_gen_branch()
71 S = (u_offset >> 11) & GENMASK(9, 0); in arc_gen_branch()
72 t = (u_offset >> 21) & GENMASK(3, 0); in arc_gen_branch()
75 instruction_l = (s << 1) | 0x1; in arc_gen_branch()
79 return (instruction_r << 16) | (instruction_l & GENMASK(15, 0)); in arc_gen_branch()
114 return 0; in branch_gen_test()
116 pr_err(SELFTEST_MSG "FAIL:\n arc_gen_branch(0x%08x, 0x%08x) != 0x%08x, got 0x%08x\n", in branch_gen_test()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar5008_initvals.h19 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
20 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
21 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
22 {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000},
23 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
24 {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab},
25 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
26 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
27 {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300},
28 {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200},
[all …]

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