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/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/linux/drivers/staging/media/ipu7/
H A Dipu7.c39 #define IPU_PCI_BAR 0
62 .info_bits = 0x20005101,
63 .refill = 0x00002726,
64 .collapse_en_bitmap = 0x1,
65 .at_sp_arb_cfg = 0x1,
71 0x0, 0x8, 0xa,
74 0x0, 0x2, 0x4,
78 0x00000f30,
81 0, 1, 0, 0
84 0x0,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
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/linux/net/core/
H A Dptp_classifier.c16 * jneq #0x800, test_ipv6 ; ETH_P_IP ?
20 * jset #0x1fff, drop_ipv4 ; don't allow fragments
21 * ldxb 4*([14]&0xf) ; load IP header len
25 * and #0xf ; mask PTP_CLASS_VMASK
26 * or #0x10 ; PTP_CLASS_IPV4
28 * drop_ipv4: ret #0x0 ; PTP_CLASS_NONE
32 * jneq #0x86dd, test_8021q ; ETH_P_IPV6 ?
38 * and #0xf ; mask PTP_CLASS_VMASK
39 * or #0x20 ; PTP_CLASS_IPV6
41 * drop_ipv6: ret #0x0 ; PTP_CLASS_NONE
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]
/linux/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/
H A Dcache.json4 "EventCode": "0x00000001",
9 "EventCode": "0x00000002",
14 "EventCode": "0x00000003",
19 "EventCode": "0x00000004",
24 "EventCode": "0x00000005",
29 "EventCode": "0x0000000c",
34 "EventCode": "0x0000000d",
39 "EventCode": "0x0000000e",
44 "EventCode": "0x0000000f",
49 "EventCode": "0x00000010",
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
126 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tl.dts191 reg = <0x10>;
210 mount-matrix = "-1", "0", "0",
211 "0", "-1", "0",
212 "0", "0", "1";
216 mount-matrix = "-1", "0", "0",
217 "0", "1", "0",
218 "0", "0", "-1";
223 mount-matrix = "0", "-1", "0",
224 "-1", "0", "0",
225 "0", "0", "1";
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Drenoir_ip_offset.h37 static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } } } };
44 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0 } },
[all …]
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
H A Ddimgrey_cavefish_ip_offset.h37 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0, 0 } } } };
44 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
45 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
46 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
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H A Dsoc24_enum.h52 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
53 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
54 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
55 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
63 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
64 CP_PERFMON_STATE_START_COUNTING = 0x00000001,
65 CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
66 CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
67 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
68 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
[all …]
H A Dnavi14_ip_offset.h37 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } } } };
44 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
45 { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
46 { { 0x00017000, 0x02402000, 0, 0, 0 } },
[all …]
H A Dnavi12_ip_offset.h37 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } } } };
44 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
45 { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
46 { { 0x00017000, 0x02402000, 0, 0, 0 } },
[all …]
/linux/sound/soc/qcom/qdsp6/
H A Dq6dsp-errno.h8 #define ADSP_EOK 0x00000000
10 #define ADSP_EFAILED 0x00000001
12 #define ADSP_EBADPARAM 0x00000002
14 #define ADSP_EUNSUPPORTED 0x00000003
16 #define ADSP_EVERSION 0x00000004
18 #define ADSP_EUNEXPECTED 0x00000005
20 #define ADSP_EPANIC 0x00000006
22 #define ADSP_ENORESOURCE 0x00000007
24 #define ADSP_EHANDLE 0x00000008
26 #define ADSP_EALREADY 0x00000009
[all …]
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn316.c33 #define DCN_BASE__INST0_SEG0 0x00000012
34 #define DCN_BASE__INST0_SEG1 0x000000C0
35 #define DCN_BASE__INST0_SEG2 0x000034C0
36 #define DCN_BASE__INST0_SEG3 0x00009000
37 #define DCN_BASE__INST0_SEG4 0x02403C00
38 #define DCN_BASE__INST0_SEG5 0
H A Ddmub_dcn315.c33 #define DCN_BASE__INST0_SEG0 0x00000012
34 #define DCN_BASE__INST0_SEG1 0x000000C0
35 #define DCN_BASE__INST0_SEG2 0x000034C0
36 #define DCN_BASE__INST0_SEG3 0x00009000
37 #define DCN_BASE__INST0_SEG4 0x02403C00
38 #define DCN_BASE__INST0_SEG5 0
H A Ddmub_dcn314.c33 #define DCN_BASE__INST0_SEG0 0x00000012
34 #define DCN_BASE__INST0_SEG1 0x000000C0
35 #define DCN_BASE__INST0_SEG2 0x000034C0
36 #define DCN_BASE__INST0_SEG3 0x00009000
37 #define DCN_BASE__INST0_SEG4 0x02403C00
38 #define DCN_BASE__INST0_SEG5 0
66 return dmub->fw_version >= DMUB_FW_VERSION(8, 0, 16); in dmub_dcn314_is_psrsu_supported()
/linux/drivers/s390/scsi/
H A Dzfcp_fsf.h17 #define FSF_QTCB_CURRENT_VERSION 0x00000001
20 #define FSF_QTCB_FCP_CMND 0x00000001
21 #define FSF_QTCB_ABORT_FCP_CMND 0x00000002
22 #define FSF_QTCB_OPEN_PORT_WITH_DID 0x00000005
23 #define FSF_QTCB_OPEN_LUN 0x00000006
24 #define FSF_QTCB_CLOSE_LUN 0x00000007
25 #define FSF_QTCB_CLOSE_PORT 0x00000008
26 #define FSF_QTCB_CLOSE_PHYSICAL_PORT 0x00000009
27 #define FSF_QTCB_SEND_ELS 0x0000000B
28 #define FSF_QTCB_SEND_GENERIC 0x0000000C
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define MC_CG_SEQ_DRAMCONF_S0 0x05
44 #define MC_CG_SEQ_DRAMCONF_S1 0x06
45 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
46 #define MC_CG_SEQ_YCLK_RESUME 0x0a
48 #define SMC_RAM_END 0x8000
58 0x000008f8, 0x00000010, 0xffffffff,
[all …]

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