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/freebsd/contrib/file/magic/Magdir/
H A Dmach4 # Mach has two magic numbers, 0xcafebabe and 0xfeedface.
17 0 name mach-o-cpu
18 >0 belong&0xff000000 0
23 >>0 belong&0x00ffffff 1
24 >>>4 belong&0x00ffffff 0 vax
25 >>>4 belong&0x00ffffff 1 vax11/780
26 >>>4 belong&0x00ffffff 2 vax11/785
27 >>>4 belong&0x00ffffff 3 vax11/750
28 >>>4 belong&0x00ffffff 4 vax11/730
29 >>>4 belong&0x00ffffff 5 uvaxI
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf700t.dts92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "
[all...]
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
H A Dtegra30-ouya.dts32 tlm,version-major = <0x0>;
33 tlm,version-minor = <0x0>;
38 reg = <0x80000000 0x40000000>;
48 alloc-ranges = <0x80000000 0x30000000>;
49 size = <0x10000000>; /* 256MiB */
56 reg = <0xbfdf0000 0x10000>; /* 64kB */
57 console-size = <0x800
[all...]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pbs_regs.h60 /* [0x0] Conf_bus, Configuration of the SB */
62 /* [0x4] PASW high */
64 /* [0x8] PASW low */
66 /* [0xc] PASW high */
68 /* [0x10] PASW low */
70 /* [0x14] PASW high */
72 /* [0x18] PASW low */
74 /* [0x1c] PASW high */
76 /* [0x20] PASW low */
78 /* [0x24] PASW high */
[all …]
H A Dal_hal_udma_regs_gen.h58 /* [0x0] Reserved register for the interrupt controller */
60 /* [0x4] Revision register */
62 /* [0x8] Reserved for future use */
64 /* [0xc] Reserved for future use */
66 /* [0x10] Reserved for future use */
68 /* [0x14] Reserved for future use */
70 /* [0x18] General timer configuration */
76 * [0x0] Mailbox interrupt generator.
80 /* [0x4] Mailbox message data out */
82 /* [0x8] Mailbox message data in */
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_ec_regs.h60 /* [0x0] Ethernet controller Version */
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
66 /* [0xc] General L2 configuration for the Ethernet controlle ... */
68 /* [0x10] Configure protocol index values */
70 /* [0x14] Configure protocol index values (extended protocols ... */
72 /* [0x18] Enable modules operation (extended operations). */
77 /* [0x0] General configuration of the MAC side of the Ethern ... */
79 /* [0x4] Minimum packet size */
81 /* [0x8] Maximum packet size */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dnvm_cfg.h43 #define NVM_CFG_version 0x83306
54 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
55 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
64 u32 generic_cont0; /* 0x0 */
65 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
66 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
67 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
68 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
69 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
70 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
H A Dkatmai.dts22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
H A Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsadefs.h43 #define REGISTER_DUMP_BUFF_SIZE 0x4000 /**< Maximum Fatal Error …
55 #define MPI_QUEUE_NORMAL 0
65 #define DIR_NODATA 0x000
66 #define DIR_READ 0x100
67 #define DIR_WRITE 0x200
70 #define TLR_MASK 0x00000003
74 #define PORTID_MASK 0x0000000F
75 #define PORTID_V_MASK 0x000000FF
76 #define PHYID_MASK 0x0000000F
77 #define PHYID_V_MASK 0x000000FF
[all …]
/freebsd/sys/powerpc/mpc85xx/
H A Dfsl_sata.h32 #define ATA_F_DMA 0x01 /* enable DMA */
33 #define ATA_F_OVL 0x02 /* enable overlap */
41 #define ATA_D_LBA 0x40 /* use LBA addressing */
42 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
47 #define ATA_E_ILI 0x01 /* illegal length */
48 #define ATA_E_NM 0x02 /* no media */
49 #define ATA_E_ABORT 0x04 /* command aborted */
50 #define ATA_E_MCR 0x08 /* media change request */
51 #define ATA_E_IDNF 0x10 /* ID not found */
52 #define ATA_E_MC 0x20 /* media changed */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312reg.h35 #define AR5315_RSTIMER_BASE 0xb1000000 /* Address for reset/timer registers */
36 #define AR5315_GPIO_BASE 0xb1000000 /* Address for GPIO registers */
37 #define AR5315_WLAN0 0xb0000000
39 #define AR5315_RESET 0x0004 /* Offset of reset control register */
40 #define AR5315_SREV 0x0014 /* Offset of reset control register */
41 #define AR5315_ENDIAN_CTL 0x000c /* offset of the endian control register */
42 #define AR5315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
44 #define AR5315_REV_MAJ 0x00f0
45 #define AR5315_REV_MIN 0x000f
47 #define AR5315_GPIODIR 0x0098 /* GPIO direction register */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dboss.ini20 { 0x00000030, 0x00000015, 0x00000015, 0x0000001d, 0x00000015 },
21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
[all …]
/freebsd/sys/contrib/xen/
H A Ddevice_tree_defs.h27 #define DT_IRQ_TYPE_NONE 0x00000000
28 #define DT_IRQ_TYPE_EDGE_RISING 0x00000001
29 #define DT_IRQ_TYPE_EDGE_FALLING 0x00000002
32 #define DT_IRQ_TYPE_LEVEL_HIGH 0x00000004
33 #define DT_IRQ_TYPE_LEVEL_LOW 0x00000008
36 #define DT_IRQ_TYPE_SENSE_MASK 0x0000000f
38 #define DT_IRQ_TYPE_INVALID 0x00000010
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5k_0007.ini19 { 0x00009800, 0x00000047 },
20 { 0x00009808, 0x00000000 },
21 { 0x0000980c, 0x09848ea6 },
22 { 0x00009810, 0x3d32e000 },
23 { 0x00009814, 0x0000076b },
24 { 0x0000981c, 0x00000000 },
25 { 0x00009820, 0x02020200 },
26 { 0x00009824, 0x00000e0e },
27 { 0x00009828, 0x0a020201 },
28 { 0x0000982c, 0x00036ffc },
[all …]
/freebsd/sys/arm/include/
H A Dvfp.h44 #define VFPSID_IMPLEMENTOR_MASK (0xff000000)
45 #define VFPSID_HARDSOFT_IMP (0x00800000)
48 #define VFPSID_SUBVERSION2_MASK (0x000f0000) /* version 1 and 2 */
49 #define VFPSID_SUBVERSION3_MASK (0x007f0000) /* version 3 */
50 #define VFP_ARCH1 0x0
51 #define VFP_ARCH2 0x1
52 #define VFP_ARCH3 0x2
54 #define VFPSID_PARTNUMBER_MASK (0x0000ff00)
56 #define VFPSID_VARIANT_MASK (0x000000f0)
57 #define VFPSID_REVISION_MASK 0x0f
[all …]

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