Lines Matching +full:0 +full:x0000000f
35 #define AR5315_RSTIMER_BASE 0xb1000000 /* Address for reset/timer registers */
36 #define AR5315_GPIO_BASE 0xb1000000 /* Address for GPIO registers */
37 #define AR5315_WLAN0 0xb0000000
39 #define AR5315_RESET 0x0004 /* Offset of reset control register */
40 #define AR5315_SREV 0x0014 /* Offset of reset control register */
41 #define AR5315_ENDIAN_CTL 0x000c /* offset of the endian control register */
42 #define AR5315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
44 #define AR5315_REV_MAJ 0x00f0
45 #define AR5315_REV_MIN 0x000f
47 #define AR5315_GPIODIR 0x0098 /* GPIO direction register */
48 #define AR5315_GPIODO 0x0090 /* GPIO data output access reg */
49 #define AR5315_GPIODI 0x0088 /* GPIO data input access reg*/
50 #define AR5315_GPIOINT 0x00a0 /* GPIO interrupt control */
54 #define AR5315_GPIODIR_I(x) 0 /* input */
56 #define AR5315_GPIOINT_S 0
57 #define AR5315_GPIOINT_M 0x3F
61 #define AR5315_WREV (-0xefbfe0) /* Revision ID register offset */
62 #define AR5315_WREV_S 0 /* Shift for WMAC revision info */
63 #define AR5315_WREV_ID 0x000000FF /* Mask for WMAC revision info */
65 #define AR5315_WREV_REVISION 0x0000000F /* Mask for WMAN Revsion version */
67 #define AR5315_RC_BB0_CRES 0x00000002 /* Cold reset to WMAC0 & WBB0 */
68 #define AR5315_RC_BB1_CRES 0x00000200 /* Cold reset to WMAC1 & WBB1n */
69 #define AR5315_RC_WMAC0_RES 0x00000001 /* Warm reset to WMAC 0 */
70 #define AR5315_RC_WBB0_RES 0x00000002 /* Warm reset to WBB0 */
71 #define AR5315_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */
72 #define AR5315_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */
77 #define AR5312_RSTIMER_BASE 0xbc003000 /* Address for reset/timer registers */
78 #define AR5312_GPIO_BASE 0xbc002000 /* Address for GPIO registers */
79 #define AR5312_WLAN0 0xb8000000
80 #define AR5312_WLAN1 0xb8500000
82 #define AR5312_RESET 0x0020 /* Offset of reset control register */
83 #define AR5312_PCICFG 0x00B0 /* MAC/PCI configuration reg (LEDs) */
85 #define AR5312_PCICFG_LEDMODE 0x0000001c /* LED Mode mask */
87 #define AR5312_PCICFG_LEDMOD0 0 /* Blnk prop to Tx and filtered Rx */
92 #define AR5312_PCICFG_LEDSEL 0x000000e0 /* LED Throughput select */
94 #define AR5312_PCICFG_LEDSEL0 0 /* See blink rate table on p. 143 */
103 #define AR5312_PCICFG_LEDSBR 0x00000100 /* Slow blink rate if no
104 activity. 0 = blink @ lowest
111 #define AR5312_GPIOCR 0x0008 /* GPIO Control register */
112 #define AR5312_GPIODO 0x0000 /* GPIO data output access reg */
113 #define AR5312_GPIODI 0x0004 /* GPIO data input access reg*/
116 #define AR5312_WREV 0x0090 /* Revision ID register offset */
118 #define AR5312_WREV_ID 0x000000FF /* Mask for WMAC revision info */
120 #define AR5312_WREV_REVISION 0x0000000F /* Mask for WMAN Revsion version */
122 #define AR5312_RC_BB0_CRES 0x00000004 /* Cold reset to WMAC0 & WBB0 */
123 #define AR5312_RC_BB1_CRES 0x00000200 /* Cold reset to WMAC1 & WBB1n */
124 #define AR5312_RC_WMAC0_RES 0x00002000 /* Warm reset to WMAC 0 */
125 #define AR5312_RC_WBB0_RES 0x00004000 /* Warm reset to WBB0 */
126 #define AR5312_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */
127 #define AR5312_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */
129 #define AR_RAD2112_SREV_MAJOR 0x40 /* 2112 Major Rev */
132 AR5312_POWER_MODE_FORCE_SLEEP = 0,