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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
H A Dtegra30-lg-p880.dts17 pinctrl-0 = <&state_default>;
120 emc-timings-0 {
122 nvidia,ram-code = <0>;
127 nvidia,emem-configuration = < 0x00050001 0xc0000010
128 0x00000001 0x00000001 0x00000002 0x00000000
129 0x00000003 0x00000001 0x00000002 0x00000004
130 0x00000001 0x00000000 0x00000002 0x00000002
131 0x02020001 0x00060402 0x77230303 0x001f0000 >;
137 nvidia,emem-configuration = < 0x00020001 0xc0000010
138 0x00000001 0x00000001 0x00000002 0x00000000
[all …]
H A Dtegra30-lg-p895.dts12 pinctrl-0 = <&state_default>;
123 nvidia,emem-configuration = < 0x00020001 0xc0000010
124 0x00000001 0x00000001 0x00000002 0x00000000
125 0x00000003 0x00000001 0x00000002 0x00000004
126 0x00000001 0x00000000 0x00000002 0x00000002
127 0x02020001 0x00060402 0x77230303 0x001f0000 >;
133 nvidia,emem-configuration = < 0x00030003 0xc0000010
134 0x00000001 0x00000001 0x00000002 0x00000000
135 0x00000003 0x00000001 0x00000002 0x00000004
136 0x00000001 0x00000000 0x00000002 0x00000002
[all …]
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "
[all...]
H A Dtegra30-pegatron-chagall.dts49 reg = <0x80000000 0x40000000>;
59 alloc-ranges = <0x80000000 0x30000000>;
60 size = <0x10000000>; /* 256MiB */
67 reg = <0xbeb00000 0x10000>; /* 64kB */
68 console-size = <0x8000>; /* 32kB */
69 record-size = <0x400>; /* 1kB */
74 reg = <0xbfe0000
[all...]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra30-ouya.dts32 tlm,version-major = <0x0>;
33 tlm,version-minor = <0x0>;
38 reg = <0x80000000 0x40000000>;
48 alloc-ranges = <0x80000000 0x30000000>;
49 size = <0x10000000>; /* 256MiB */
56 reg = <0xbfdf0000 0x10000>; /* 64kB */
57 console-size = <0x800
[all...]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Daltera_tse.txt41 - #size-cells: Must be <0>.
56 reg = <0x00000001 0x00000000 0x00000400>,
57 <0x00000001 0x00000460 0x00000020>,
58 <0x00000001 0x00000480 0x00000020>,
59 <0x00000001 0x000004A0 0x00000008>,
60 <0x00000001 0x00000400 0x00000020>,
61 <0x00000001 0x00000420 0x00000020>;
64 interrupts = <0 41 4>, <0 40 4>;
78 #size-cells = <0>;
79 phy0: ethernet-phy@0 {
[all …]
/freebsd/sys/dev/et/
H A Dif_etreg.h57 #define ET_PCIR_DEVICE_CAPS 0x4C
58 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */
59 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0
60 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1
62 #define ET_PCIR_DEVICE_CTRL 0x50
63 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */
64 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000
66 #define ET_PCIR_MAC_ADDR0 0xA4
67 #define ET_PCIR_MAC_ADDR1 0xA8
69 #define ET_PCIR_EEPROM_STATUS 0xB2 /* XXX undocumented */
[all …]
/freebsd/sys/dev/jme/
H A Dif_jmereg.h36 #define VENDORID_JMICRON 0x197B
41 #define DEVICEID_JMC250 0x0250
42 #define DEVICEREVID_JMC250_A0 0x00
43 #define DEVICEREVID_JMC250_A2 0x11
48 #define DEVICEID_JMC260 0x0260
49 #define DEVICEREVID_JMC260_A0 0x00
51 #define DEVICEID_JMC2XX_MASK 0x0FF0
54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */
56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
[all …]
/freebsd/sys/dev/ispfw/
H A Dasm_2400.h33 0x0401f1be, 0x00112000, 0x00100000, 0x0000c79b,
34 0x00000008, 0x00000007, 0x00000000, 0x00009496,
35 0x00000003, 0x00000000, 0x20434f50, 0x59524947,
36 0x48542032, 0x30313720, 0x514c4f47, 0x49432043,
37 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
38 0x32347878, 0x20466972, 0x6d776172, 0x65202020,
39 0x56657273, 0x696f6e20, 0x2020382e, 0x30372e30,
40 0x30202024, 0x00000000, 0x00000000, 0x00000000,
41 0x00000000, 0x00000000, 0x00000000, 0x00000000,
42 0x00000000, 0x00000000, 0x00000000, 0x00000000,
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/usr.sbin/bhyve/
H A Dahci.h34 #define ATA_DATA 0 /* (RW) data */
37 #define ATA_F_DMA 0x01 /* enable DMA */
38 #define ATA_F_OVL 0x02 /* enable overlap */
46 #define ATA_D_LBA 0x40 /* use LBA addressing */
47 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
52 #define ATA_E_ILI 0x01 /* illegal length */
53 #define ATA_E_NM 0x02 /* no media */
54 #define ATA_E_ABORT 0x04 /* command aborted */
55 #define ATA_E_MCR 0x08 /* media change request */
56 #define ATA_E_IDNF 0x10 /* ID not found */
[all …]
/freebsd/sys/dev/gem/
H A Dif_gemreg.h37 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
38 #define GEM_CONFIG 0x0004 /* config reg */
39 #define GEM_STATUS 0x000c /* status reg */
40 /* Note: Reading the status reg clears bits 0-6. */
41 #define GEM_INTMASK 0x0010
42 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
43 #define GEM_STATUS_ALIAS 0x001c
46 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */
47 #define GEM_SEB_RXWON 0x00000004
50 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */
[all …]
/freebsd/sys/dev/age/
H A Dif_agereg.h36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h28 #define PCI_VENDOR_ATHEROS 0x168c
30 #define PCI_PRODUCT_ATHEROS_AR5210 0x0007
31 #define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
36 #define AR_CR 0x0008 /* Command register */
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
38 #define AR_CFG 0x0014 /* Configuration and status register */
39 #define AR_ISR 0x001c /* Interrupt status register */
40 #define AR_IMR 0x0020 /* Interrupt mask register */
[all …]
/freebsd/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]
/freebsd/sys/dev/ale/
H A Dif_alereg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR81XX 0x1026
43 #define ALE_SPI_CTRL 0x200
44 #define SPI_VPD_ENB 0x00002000
46 #define ALE_SPI_ADDR 0x204 /* 16bits */
48 #define ALE_SPI_DATA 0x208
50 #define ALE_SPI_CONFIG 0x20C
52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */
54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */
56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
[all …]

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