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/linux/arch/powerpc/platforms/83xx/
H A Dkm83xx.c39 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
59 ret = of_address_to_resource(np_par, 0, &res); in quirk_mpc8360e_qe_enet10()
73 * write 0b01 to UCC1 bits 18:19 in quirk_mpc8360e_qe_enet10()
74 * write 0b01 to UCC2 option 1 bits 4:5 in quirk_mpc8360e_qe_enet10()
75 * write 0b01 to UCC2 option 2 bits 16:17 in quirk_mpc8360e_qe_enet10()
77 clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000); in quirk_mpc8360e_qe_enet10()
83 * write 0b01 to UCC2 option 2 bits 16:17 in quirk_mpc8360e_qe_enet10()
84 * write 0b0101 to UCC1 bits 20:23 in quirk_mpc8360e_qe_enet10()
85 * write 0b0101 to UCC2 option 1 bits 24:27 in quirk_mpc8360e_qe_enet10()
87 clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550); in quirk_mpc8360e_qe_enet10()
[all …]
/linux/arch/powerpc/include/asm/
H A Dpnv-ocxl.h16 #define PNV_OCXL_ATSD_LNCH 0x00
18 #define PNV_OCXL_ATSD_LNCH_R PPC_BIT(0)
20 * 0b00 Just invalidate TLB.
21 * 0b01 Invalidate just Page Walk Cache.
22 * 0b10 Invalidate TLB, Page Walk Cache, and any
29 * 0b00 Invalidate just the target VA.
30 * 0b01 Invalidate matching PID.
33 /* 0b1: Process Scope, 0b0: Partition Scope */
45 * L=0b0 for 4KB pages
46 * L=0b1 for large pages)
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H A Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
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/linux/include/linux/irqchip/
H A Darm-gic-v5.h19 #define GICV5_HWIRQ_ID GENMASK(23, 0)
21 #define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)
23 #define GICV5_HWIRQ_TYPE_PPI UL(0x1)
24 #define GICV5_HWIRQ_TYPE_LPI UL(0x2)
25 #define GICV5_HWIRQ_TYPE_SPI UL(0x3)
30 #define GICV5_ARCH_PPI_S_DB_PPI 0x0
31 #define GICV5_ARCH_PPI_RL_DB_PPI 0x1
32 #define GICV5_ARCH_PPI_NS_DB_PPI 0x2
33 #define GICV5_ARCH_PPI_SW_PPI 0x3
34 #define GICV5_ARCH_PPI_HACDBSIRQ 0xf
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/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_cle.c41 buf[0] = SET_VAL(CLE_DROP, dbptr->drop); in xgene_cle_dbptr_to_hw()
52 u32 i, j = 0; in xgene_cle_kn_to_hw()
56 for (i = 0; i < kn->num_keys; i++) { in xgene_cle_kn_to_hw()
74 u32 i, j = 0; in xgene_cle_dn_to_hw()
85 for (i = 0; i < dn->num_branches; i++) { in xgene_cle_dn_to_hw()
114 ret = 0; in xgene_cle_poll_cmd_done()
131 int ret = 0; in xgene_cle_dram_wr()
136 for (i = 0; i < nparsers; i++) { in xgene_cle_dram_wr()
143 for (j = 0; j < nregs; j++) in xgene_cle_dram_wr()
165 for (i = 0; i < cle->parsers; i++) { in xgene_cle_enable_ptree()
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/linux/drivers/net/mdio/
H A Dmdio-aspeed.c17 #define ASPEED_MDIO_CTRL 0x0
20 #define ASPEED_MDIO_CTRL_ST_C45 0
23 #define MDIO_C22_OP_WRITE 0b01
24 #define MDIO_C22_OP_READ 0b10
25 #define MDIO_C45_OP_ADDR 0b00
26 #define MDIO_C45_OP_WRITE 0b01
27 #define MDIO_C45_OP_PREAD 0b10
28 #define MDIO_C45_OP_READ 0b11
31 #define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
33 #define ASPEED_MDIO_DATA 0x4
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/linux/include/uapi/linux/
H A Dcciss_defs.h12 #define CMD_SUCCESS 0x0000
13 #define CMD_TARGET_STATUS 0x0001
14 #define CMD_DATA_UNDERRUN 0x0002
15 #define CMD_DATA_OVERRUN 0x0003
16 #define CMD_INVALID 0x0004
17 #define CMD_PROTOCOL_ERR 0x0005
18 #define CMD_HARDWARE_ERR 0x0006
19 #define CMD_CONNECTION_LOST 0x0007
20 #define CMD_ABORTED 0x0008
21 #define CMD_ABORT_FAILED 0x0009
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/linux/Documentation/i2c/busses/
H A Di2c-mlxcpld.rst28 CPBLTY 0x0 - capability reg.
29 Bits [6:5] - transaction length. b01 - 72B is supported,
32 CTRL 0x1 - control reg.
34 HALF_CYC 0x4 - cycle reg.
37 I2C_HOLD 0x5 - hold reg.
40 CMD 0x6 - command reg.
41 Bit 0, 0 = write, 1 = read.
44 NUM_DATA 0x7 - data size reg.
46 NUM_ADDR 0x8 - address reg.
48 STATUS 0x9 - status reg.
[all …]
/linux/Documentation/hwmon/
H A Dspd5118.rst11 https://www.jedec.org/standards-documents/docs/jesd300-5b01
17 Addresses scanned: I2C 0x50 - 0x57
/linux/drivers/usb/host/
H A Docteon-hcd.h53 #define CVMX_USBCXBASE 0x00016F0010000000ull
56 ((bid) & 1) * 0x100000000000ull)
59 (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32)
61 #define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid)
62 #define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid)
63 #define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid)
64 #define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid)
65 #define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid)
66 #define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid)
67 #define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid)
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/linux/arch/arm/include/asm/
H A Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
16 #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
18 #define V7M_SCB_VTOR 0x08
20 #define V7M_SCB_AIRCR 0x0c
21 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
24 #define V7M_SCB_SCR 0x10
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/linux/arch/loongarch/include/asm/
H A Dhw_breakpoint.h13 #define LOONGARCH_BREAKPOINT_EXECUTE (0 << 0)
16 #define LOONGARCH_BREAKPOINT_LOAD (1 << 0)
32 #define LOONGARCH_BREAKPOINT_LEN_1 0b11
33 #define LOONGARCH_BREAKPOINT_LEN_2 0b10
34 #define LOONGARCH_BREAKPOINT_LEN_4 0b01
35 #define LOONGARCH_BREAKPOINT_LEN_8 0b00
45 #define CSR_CFG_ADDR 0
59 if (T == 0) \
63 } while (0)
67 if (T == 0) \
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/linux/arch/powerpc/kvm/
H A Dbook3s_hv_tm_builtin.c27 * rfid, rfebb, and mtmsrd encode bit 31 = 0 since it's a reserved bit in kvmhv_p9_tm_emulation_early()
29 * instructions. For the tsr. instruction if bit 31 = 0 then it is per in kvmhv_p9_tm_emulation_early()
32 * to handle TM-related invalid forms that have bit 31 = 0. Moreover, in kvmhv_p9_tm_emulation_early()
39 /* XXX do we need to check for PR=0 here? */ in kvmhv_p9_tm_emulation_early()
43 return 0; in kvmhv_p9_tm_emulation_early()
54 return 0; in kvmhv_p9_tm_emulation_early()
58 return 0; in kvmhv_p9_tm_emulation_early()
62 return 0; in kvmhv_p9_tm_emulation_early()
74 /* XXX do we need to check for PR=0 here? */ in kvmhv_p9_tm_emulation_early()
75 rs = (instr >> 21) & 0x1f; in kvmhv_p9_tm_emulation_early()
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/linux/arch/powerpc/kernel/
H A Dcpu_setup_power.c45 * LPES = 0b01 (HSRR0/1 used for 0x500)
46 * PECE = 0b111
48 * HDICE = 0
49 * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
50 * VRMASD = 0b10000 (L=1, LP=00)
56 lpcr |= (0x10ull << LPCR_VRMASD_SH) & LPCR_VRMASD; in init_LPCR_ISA206()
101 mtspr(SPRN_MMCRC, 0); in init_PMU_HV()
106 mtspr(SPRN_MMCRH, 0); in init_PMU_HV_ISA207()
111 mtspr(SPRN_MMCRA, 0); in init_PMU()
113 mtspr(SPRN_MMCR1, 0); in init_PMU()
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/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst42 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0xffff/
43 $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt,port=0xffff/
52 b) By event type, such as "event=0xXXXX, event=0x1XXXX".
56 …$# perf stat -e "{hisi_pcie0_core0/rx_mwr_latency,port=0xffff/,hisi_pcie0_core0/rx_mwr_cnt,port=0x…
73 "bdf" filter will be in effect, because "bdf=0" meaning 0000:000:00.0.
83 bitmap should be set, port=0x1; if target Root Port is 0000:00:04.0 (x4
84 lanes), bit8 is set, port=0x100; if these two Root Ports are both
85 monitored, port=0x101.
89 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0x1/ sleep 5
97 For example, "bdf=0x3900" means BDF of target Endpoint is 0000:39:00.0.
[all …]
H A Dhisi-pmu.rst13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
32 e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
35 e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
57 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
65 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
67 This will only count the operations from core/thread 0 and 1 in this cluster.
79 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
97 $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
98 hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5
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/linux/sound/soc/sdw_utils/
H A Dsoc_sdw_rt_amp.c63 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A5D")
70 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A5E")
78 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0B00")
85 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0B01")
92 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0AFF")
99 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0AFE")
117 return 0; in rt_amp_add_device_props()
122 props[0] = PROPERTY_ENTRY_U8_ARRAY("realtek,bq-params", params); in rt_amp_add_device_props()
177 if (strcmp(codec_name, "rt1308") == 0) in get_codec_name_and_route()
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/linux/drivers/mfd/
H A Docelot-spi.c30 #define REG_DEV_CPUORG_IF_CTRL 0x0000
31 #define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
33 #define CFGSTAT_IF_NUM_VCORE (0 << 24)
38 #define VSC7512_DEVCPU_ORG_RES_START 0x71000000
39 #define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
41 #define VSC7512_CHIP_REGS_RES_START 0x71070000
42 #define VSC7512_CHIP_REGS_RES_SIZE 0x14
64 * our CPU. These are two bits (0 and 1) but they're repeated such that in ocelot_spi_initialize()
68 * 0b00: little-endian, MSB first in ocelot_spi_initialize()
72 * 0b01: big-endian, MSB first in ocelot_spi_initialize()
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/linux/arch/arm64/include/asm/
H A Dkvm_nested.h26 ((tcr & TCR_EL2_DS) ? TCR_DS : 0) | in translate_tcr_el2_to_tcr_el1()
27 ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) | in translate_tcr_el2_to_tcr_el1()
135 xn &= 0b10; in kvm_s2_trans_exec_el0()
138 case 0b00: in kvm_s2_trans_exec_el0()
139 case 0b01: in kvm_s2_trans_exec_el0()
151 xn &= 0b10; in kvm_s2_trans_exec_el1()
154 case 0b00: in kvm_s2_trans_exec_el1()
155 case 0b11: in kvm_s2_trans_exec_el1()
238 *elr = 0xbad9acc0debadbad; in kvm_auth_eretax()
253 u8 shift = 0; \
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/linux/include/linux/usb/
H A Daudio-v2.h8 * in http://www.usb.org/developers/devclass_docs/Audio2.0_final.zip
16 /* v1.0 and v2.0 of this standard have many things in common. For the rest
22 * From the USB Audio spec v2.0:
27 * present then the bit pair must be set to 0b00.
29 * set to 0b01. If a Control is also Host programmable, the bit
30 * pair must be set to 0b11. The value 0b10 is not allowed.
36 return (bmControls >> ((control - 1) * 2)) & 0x1; in uac_v2v3_control_is_readable()
41 return (bmControls >> ((control - 1) * 2)) & 0x2; in uac_v2v3_control_is_writeable()
49 __le16 bcdADC; /* 0x0200 */
79 #define UAC_CLOCK_SOURCE_TYPE_EXT 0x0
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/linux/arch/powerpc/include/asm/book3s/64/
H A Dradix.h26 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
27 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
28 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
31 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
32 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
33 #define RADIX_P4D_BAD_BITS 0x60000000000000e0UL
56 * +------------------+ Kernel virtual map (0xc008000000000000)
60 * 0b11......+------------------+ Kernel linear map (0xc....)
64 * 0b10......+------------------+
68 * 0b01......+------------------+
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/linux/arch/arc/kernel/
H A Dsignal.c62 #define MAGIC_SIGALTSTK 0x07302004
68 int err = 0; in save_arcv2_regs()
77 v2abi.r58 = v2abi.r59 = 0; in save_arcv2_regs()
86 int err = 0; in restore_arcv2_regs()
140 return err ? -EFAULT : 0; in stash_usr_regs()
185 return 0; in restore_usr_regs()
193 return 0; in is_do_ss_needed()
243 return 0; in SYSCALL_DEFINE0()
260 /* ATPCS B01 mandates 8-byte alignment */ in get_sigframe()
274 unsigned int magic = 0; in setup_rt_frame()
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/linux/drivers/iio/addac/
H A Dad74413r.c31 #define AD74413R_CRC_POLYNOMIAL 0x7
96 #define AD74413R_REG_NOP 0x00
98 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x))
99 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0)
101 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x))
105 #define AD74413R_ADC_RANGE_10V 0b000
106 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001
107 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010
108 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011
109 #define AD74413R_ADC_REJECTION_50_60 0b00
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.h43 #define SPEED_AUTO_NEG 0
46 #define I2C_DEV_ADDR_A0 0xa0
47 #define I2C_DEV_ADDR_A2 0xa2
50 #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
52 #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
54 #define SFP_EEPROM_PART_NO_ADDR 0x28
56 #define SFP_EEPROM_REVISION_ADDR 0x38
58 #define SFP_EEPROM_SERIAL_ADDR 0x44
60 #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
62 #define SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
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/linux/arch/powerpc/platforms/powernv/
H A Docxl.c8 #define PNV_OCXL_TL_P9_RECV_CAP 0x000000000000000Full
15 #define AFU_INDEX_MASK 0x3F000000
17 #define ACTAG_MASK 0xFFF
87 return 0; in find_dvsec_from_pos()
92 int vsec = 0; in find_dvsec_afu_ctrl()
102 return 0; in find_dvsec_afu_ctrl()
120 return 0; in get_max_afu_index()
135 return 0; in get_actag_count()
194 link->fn_desired_actags[PCI_FUNC(dev->devfn)] = 0; in pnv_ocxl_fixup_actag()
195 for (i = 0; i <= afu_idx; i++) { in pnv_ocxl_fixup_actag()
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