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/linux/arch/arm64/kvm/hyp/
H A Dexception.c75 * This performs the exception entry at a given EL (@target_mode), stashing PC
77 * The EL passed to this function *must* be a non-secure, privileged mode with
85 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
86 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
140 // See ARM DDI 0487E.a, page D5-2579. in enter_exception64()
144 // See ARM DDI 0487E.a, page D5-2578. in enter_exception64()
150 // See ARM DDI 0487E.a, page D2-2452. in enter_exception64()
153 // See ARM DDI 0487E.a, page D1-2306. in enter_exception64()
156 // See ARM DDI 0487E.a, page D13-3258 in enter_exception64()
161 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. in enter_exception64()
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/linux/Documentation/trace/coresight/
H A Dcoresight-cpu-debug.rst11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
44 registers naming convention is a bit different between them, AArch64 uses
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
46 'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52 If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
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/linux/tools/testing/selftests/arm64/signal/
H A Dsve_helpers.c37 * terminating, bail out here when we find a higher VL than in sve_fill_vls()
39 * See the ARM ARM, DDI 0487K.a, B1.4.2: I_QQRNR and I_NWYBP. in sve_fill_vls()
/linux/Documentation/arch/arm64/
H A Dhugetlbpage.rst18 These are regular hugepages where a pmd or a pud page table entry points to a
26 The architecture provides a contiguous bit in the translation table entries
27 (D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
28 contiguous set of entries that can be cached in a single TLB entry.
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dhugetlbpage.rst29 架构中转换页表条目(D4.5.3, ARM DDI 0487C.a)中提供一个连续
H A Dbooting.txt4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
175 ARM DDI 0487A
233 ARM DEN 0022A：用于 ARM 上的电源状态协调接口系统软件）中描述的
236 *译者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dhugetlbpage.rst32 架構中轉換頁表條目(D4.5.3, ARM DDI 0487C.a)中提供一個連續
H A Dbooting.txt6 original document maintainer directly. However, if you have a problem
9 or if there is a problem with the translation.
179 ARM DDI 0487A
237 ARM DEN 0022A：用於 ARM 上的電源狀態協調接口系統軟件）中描述的
240 *譯者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。
/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cpu-debug.yaml17 reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
53 A phandle to the cpu this debug component is bound to.
59 A phandle to the debug power domain if the debug logic has its own
/linux/drivers/acpi/arm64/
H A Dgtdt.c127 * Return: true if the timer HW state is lost when a CPU enters an idle state,
154 * @platform_timer_count: It points to a integer variable which is used
227 * See ARM DDI 0487A.k_iss10775, page I1-5129, Table I1-3 in gtdt_parse_timer_block()
277 * See ARM DDI 0487A.k_iss10775, page I1-5130, Table I1-4 in gtdt_parse_timer_block()
311 * @timer_count: It points to a integer variable which is used for storing the
341 * Initialize a SBSA generic Watchdog platform device info from GTDT
360 pr_debug("found a Watchdog (0x%llx/0x%llx gsi:%u flags:0x%x).\n", in gtdt_import_sbsa_gwdt()
377 * Add a platform device named "sbsa-gwdt" to match the platform driver. in gtdt_import_sbsa_gwdt()
/linux/arch/arm64/include/asm/
H A Dkgdb.h43 * To expand a little on the "most versions of it"... when the gdb remote
44 * protocol for AArch64 was developed it depended on a statement in the
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
47 * protocol. In fact this statement is still present in ARM DDI 0487A.i.
49 * Unfortunately "is a 32-bit register" has a very special meaning for
51 * RES0.". RES0 is heavily used in the ARM architecture documents as a
52 * way to leave space for future architecture changes. So to translate a
54 * manuals, what "is a 32-bit register" actually means in this context is
55 * "is a 64-bit register but one with no meaning allocated to any of the
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H A Dcache.h93 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
H A Dtraps.h54 * to indicate whether this ESR has a RAS encoding. CPUs without this feature
55 * have a ISS-Valid bit in the same position.
56 * If this bit is set, we know its not a RAS SError.
58 * errors share the same encoding as an all-zeros encoding from a CPU that
75 * Return the AET bits from a RAS SError's ESR.
86 /* Not a RAS error, we can't interpret the ESR. */ in arm64_ras_serror_get_severity()
119 * Put the registers back in the original format suitable for a in arm64_mops_reset_regs()
121 * Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH. in arm64_mops_reset_regs()
126 /* Format is from Option A; forward set */ in arm64_mops_reset_regs()
140 /* Format is from Option A */ in arm64_mops_reset_regs()
H A Dkvm_arm.h89 * AMO: Override CPSR.A and enable signaling with VA
93 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
152 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
168 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
186 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
223 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
228 * algorithm determines the alignment of a table base address at a given
232 * depending on the T0SZ, the value of "x" is defined based on a
233 * Magic constant for a given PAGE_SIZE and Entry Level. The
255 * We have a magic formula for the Magic_N below:
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H A Dcpufeature.h32 * The safe value of a CPUID feature field is dependent on the implications
39 * a field when EXACT is specified, failing which, the safe value specified
44 FTR_EXACT, /* Use a predefined safe value */
80 * A @mask field set to full-1 indicates that the corresponding field
81 * in @val is a valid override.
83 * A @mask field set to full-0 with the corresponding @val field set
86 * A @mask field set to full-0 with the corresponding @val field set
125 * 1) Scope of Detection : The system detects a given capability by
127 * value of a field in CPU ID feature register or checking the cpu
128 * model. The capability provides a call back ( @matches() ) to
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-cpu-debug.c125 * According to ARM DDI 0487A.k, before access external debug
218 * As described in ARM DDI 0487A.k, if the processing in debug_read_regs()
228 * A read of the EDPCSR normally has the side-effect of in debug_read_regs()
359 * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to in debug_init_arch_data()
/linux/arch/arm64/mm/
H A Dhugetlbpage.c146 * Changing some bits of contiguous entries requires us to follow a
148 * before we can change any entries. See ARM DDI 0487A.k_iss10775,
192 * Changing some bits of contiguous entries requires us to follow a
194 * before we can change any entries. See ARM DDI 0487A.k_iss10775,
405 * For a contiguous huge pte range we need to check whether or not write
407 * all the contiguous ptes we need to check whether or not there is a
511 * levels (PUD, CONT PMD, PMD, CONT PTE) for a given base in hugetlbpage_init()
/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h21 * C5.2, version:ARM DDI 0487A.f)
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
956 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
1141 * The "Z" constraint normally means a zero immediate, but when combined with
1172 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
/linux/arch/arm64/kernel/
H A Dptrace.c99 * @name: the name of a register
101 * regs_query_register_offset() returns the offset of a register in struct
169 * Handle hitting a HW-breakpoint.
626 * Ensure target->thread.uw.fpsimd_state is up to date, so that a in __fpr_set()
960 * If setting a different VL from the requested VL and there is in sve_set_common()
979 * FPSIMD regs, so that a short copyin leaves trailing in sve_set_common()
981 * configuring normal SVE, a system with streaming SVE may not in sve_set_common()
1166 * If setting a different VL from the requested VL and there is in za_set()
1679 * ZA is a single register but it's variably sized and
2091 * Convert a virtual register number into an index for a thread_info
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H A Dcpufeature.c7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
14 * user-visible instructions are available only on a subset of the available
17 * CPU when bringing them up. If there is a mismatch, then we update the
20 * "sanitised" value of a feature register.
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
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/linux/tools/perf/util/
H A Dcs-etm.c56 * happen in cases like between a fork and an exec.
62 * everything in a buffer comes from the same process regardless of
122 * Same as traceid_list, but traceid_list may be a reference to another
123 * queue's which has a matching sink ID.
142 * A struct auxtrace_heap_item only has a queue_nr and a timestamp to
244 /* Disallow re-mapping a different traceID to metadata pair. */ in cs_etm__insert_trace_id_node()
446 * Get a metadata index for a specific cpu from an array.
463 * Get a metadata for a specific cpu from an array.
478 * but a CPU / Trace ID association changing during a session is an error.
529 * When a timestamp packet is encountered the backend code in cs_etm__etmq_set_traceid_queue_timestamp()
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/linux/drivers/clocksource/
H A Darm_arch_timer.c57 * The minimum amount of time a generic counter is guaranteed to not roll over
106 * Makes an educated guess at a valid counter width based on the Generic Timer
109 * 2) a roll-over time of not less than 40 years
111 * See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details.
236 * if we don't have the cp15 accessors we won't have a problem.
548 /* Iterate over the ACPI OEM info array, looking for a match */ in arch_timer_check_acpi_oem_erratum()
598 * late in the game (with a per-CPU erratum, for example), so in arch_timer_enable_workaround()
660 #define arch_timer_check_ool_workaround(t,a) do { } while(0) argument
920 /* ECV is likely to require a large divider. Use the EVNTIS flag. */ in arch_timer_evtstrm_enable()
1062 * probed has a clock-frequency property, this overrides the HW register.
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/linux/arch/arm64/kvm/
H A Darm.c141 * kvm_arch_init_vm - initializes a VM data structure
259 * - both Address and Generic auth are implemented for a given in kvm_has_full_ptr_auth()
261 * - only a single algorithm is implemented. in kvm_has_full_ptr_auth()
563 * Ensure a VMID is allocated for the MMU before programming VTTBR_EL2, in kvm_arch_vcpu_load()
567 * time of rollover, so KVM might need to grab a new VMID for the MMU if in kvm_arch_vcpu_load()
574 * vcpu. If detecting that a vcpu from the same VM has in kvm_arch_vcpu_load()
757 * A significant bit can be either 0 or 1, and will only appear in in kvm_init_mpidr_data()
764 * Don't let userspace fool us. If we need more than a single page in kvm_init_mpidr_data()
792 * performed each time we get a new thread dealing with this vcpu.
816 * Map the VGIC hardware resources before running a vcpu the in kvm_arch_vcpu_run_pid_change()
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