Home
last modified time | relevance | path

Searched +full:0487 +full:a (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/trace/coresight/
H A Dcoresight-cpu-debug.rst11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
44 registers naming convention is a bit different between them, AArch64 uses
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
46 'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52 If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
[all …]
/linux/tools/testing/selftests/arm64/signal/
H A Dsve_helpers.c37 * terminating, bail out here when we find a higher VL than in sve_fill_vls()
39 * See the ARM ARM, DDI 0487K.a, B1.4.2: I_QQRNR and I_NWYBP. in sve_fill_vls()
/linux/Documentation/arch/arm64/
H A Dhugetlbpage.rst18 These are regular hugepages where a pmd or a pud page table entry points to a
26 The architecture provides a contiguous bit in the translation table entries
27 (D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
28 contiguous set of entries that can be cached in a single TLB entry.
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dhugetlbpage.rst29 架构中转换页表条目(D4.5.3, ARM DDI 0487C.a)中提供一个连续
H A Dbooting.txt4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
175 ARM DDI 0487A
233 ARM DEN 0022A：用于 ARM 上的电源状态协调接口系统软件）中描述的
236 *译者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dhugetlbpage.rst32 架構中轉換頁表條目(D4.5.3, ARM DDI 0487C.a)中提供一個連續
H A Dbooting.txt6 original document maintainer directly. However, if you have a problem
9 or if there is a problem with the translation.
179 ARM DDI 0487A
237 ARM DEN 0022A：用於 ARM 上的電源狀態協調接口系統軟件）中描述的
240 *譯者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。
/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cpu-debug.yaml17 reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
53 A phandle to the cpu this debug component is bound to.
59 A phandle to the debug power domain if the debug logic has its own
/linux/arch/arm64/mm/
H A Dhugetlbpage.c142 * Changing some bits of contiguous entries requires us to follow a
144 * before we can change any entries. See ARM DDI 0487A.k_iss10775,
189 * Changing some bits of contiguous entries requires us to follow a
191 * before we can change any entries. See ARM DDI 0487A.k_iss10775,
395 * For a contiguous huge pte range we need to check whether or not write
397 * all the contiguous ptes we need to check whether or not there is a
491 * levels (PUD, CONT PMD, PMD, CONT PTE) for a given base in hugetlbpage_init()
/linux/arch/arm64/include/asm/
H A Dtlbflush.h28 * on whether a particular TLBI operation takes an argument or
49 /* This macro creates a properly formatted VA operand for the TLBI */
123 * a non-hinted invalidation. Any provided level outside the hint range
198 * This macro creates a properly formatted VA operand for the TLB RANGE. The
211 * 0487J.a section C5.5.60 "TLBI VAE1IS, TLBI VAE1ISNXS, TLB Invalidate by VA,
230 * significant for a maximum of MAX_TLBI_RANGE_PAGES pages. If
314 * kernel mappings rather than a particular user address space.
329 * Invalidate a single kernel mapping for address 'addr' on all
336 * The invalidation operations are issued at a granularity
341 * perform a non-hinted invalidation. flags may be TLBF_NONE (0) or
[all …]
H A Dsysreg.h22 * C5.2, version:ARM DDI 0487A.f)
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
85 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
941 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
1174 * The "Z" constraint normally means a zero immediate, but when combined with
1200 * to force XZR generation if (v) is a constant 0 value but LLVM does not
1201 * yet understand that modifier/constraint combo so a conditional is required
1202 * to nudge the compiler into using XZR as a source for a 0 constant value.
1214 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
/linux/drivers/perf/
H A Darm_brbe.c23 * purpose but BRBCR_ELx.TS needs to have a valid value from all
32 * entries each. An individual branch record in a given bank could
268 * Arm ARM (DDI 0487K.a) D.18.4 rule PPBZP requires explicit sync in select_brbe_bank()
291 * fail silently. PERF_SAMPLE_BRANCH_HV is a special case that is selectively
325 * either individually or as a group i.e ORing multiple filters
410 * a given exception level, then addresses which falls in branch_type_to_brbcr()
500 * Discard existing records to avoid a discontinuity, e.g. records in brbe_enable()
542 * ensures ordering and in the interrupt handler this is a NOP as in brbe_disable()
721 /* We can only have a half record if permissions have not been expanded */ in filter_branch_privilege()
726 * If record is within a single exception level, just need to either in filter_branch_privilege()
H A Darm_spe_pmu.c102 /* Convert a free-running index from perf into an SPE buffer offset */
394 * The PMSIDR_EL1.Interval field (stored in spe_pmu->min_period) is a in arm_spe_event_sanitise_period()
395 * recommendation for the minimum interval, not a hardware limitation. in arm_spe_event_sanitise_period()
397 * According to the Arm ARM (DDI 0487 L.a), section D24.7.12 PMSIRR_EL1, in arm_spe_event_sanitise_period()
399 * states: "Software must set this to a nonzero value". Use 1 as the in arm_spe_event_sanitise_period()
504 * so that the worst case is half a buffer of records, as in arm_spe_pmu_next_snapshot_off()
505 * opposed to a single record. in arm_spe_pmu_next_snapshot_off()
535 * a record when generating a buffer management event. in __arm_spe_pmu_next_off()
576 * If there's a wakeup before we wrap, arrange to be woken up by in __arm_spe_pmu_next_off()
624 /* Start a new aux session */ in arm_spe_perf_aux_output_begin()
[all …]
/linux/tools/perf/util/
H A Dcs-etm.c57 * happen in cases like between a fork and an exec.
63 * everything in a buffer comes from the same process regardless of
106 * not possible to change thread in a single branch sample so no need to
134 * Same as traceid_list, but traceid_list may be a reference to another
135 * queue's which has a matching sink ID.
154 * A struct auxtrace_heap_item only has a queue_nr and a timestamp to in cs_etm__get_v7_protocol_version()
256 /* Disallow re-mapping a different traceID to metadata pair. */ in cs_etm__insert_trace_id_node()
476 * Get a metadat
[all...]
/linux/drivers/scsi/lpfc/
H A Dlpfc_init.c17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
20 * more details, a copy of which can be found in the file COPYING *
69 /* Used when mapping IRQ vectors in a driver centric manner */
257 /* dump mem may return a zero when finished or we got a in lpfc_config_port_prep()
308 * into a human readable string and store it in OptionROMVersion.
329 /* Decode the Option rom version word to a readable string */ in lpfc_dump_wakeup_param_cmpl()
357 * If the name is empty or there exists a soft name in lpfc_update_vport_wwn()
731 * structure for use as a delayed link up mechanism with the
752 * structure for use as a delayed link up mechanism with the
1187 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
[all …]