Lines Matching +full:0487 +full:a

17  * code with the proper names is a pain, use a helper to map the names
92  * AMO:		Override CPSR.A and enable signaling with VA
96  * PTW:		Take a stage2 fault if a stage1 walk steps in device memory
154  * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
170  * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
188  * Where TGRAN_SL0_BASE is a magic number depending on the page size:
225  * descriptors in section D4.2.8 in ARM DDI 0487C.a.
230  * algorithm determines the alignment of a table base address at a given
234  * depending on the T0SZ, the value of "x" is defined based on a
235  * Magic constant for a given PAGE_SIZE and Entry Level. The
257  * We have a magic formula for the Magic_N below:
284  * levels for a given IPA size (which we do, see stage2_pt_levels())
320  * them, but that at least those that are not advertised to a guest