| /linux/Documentation/dev-tools/ |
| H A D | kasan.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 --------
11 designed to find out-of-bounds and use-after-free bugs.
16 2. Software Tag-Based KASAN
17 3. Hardware Tag-Based KASAN
23 Software Tag-Based KASAN or SW_TAGS KASAN, enabled with CONFIG_KASAN_SW_TAGS,
26 using it for testing on memory-restricted devices with real workloads.
28 Hardware Tag-Based KASAN or HW_TAGS KASAN, enabled with CONFIG_KASAN_HW_TAGS,
29 is the mode intended to be used as an in-field memory bug detector or as a
37 The Generic and the Software Tag-Based modes are commonly referred to as the
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| /linux/Documentation/admin-guide/media/ |
| H A D | technisat.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 -----------------------------
19 .. code-block:: none
21 lspci -vvv for a PCI device (lsusb -vvv for an USB device) will show you for example:
22 02:0b.0 Network controller: Techsan Electronics Co Ltd B2C2 FlexCopII DVB chip /
26 DVB: registering frontend 0 (Conexant CX24123/CX24109)...
29 -------------------
37 (except ``Simple tuner support`` for ATSC 3rd generation only -> see case 9 please).
41 - Main module part:
50 - Frontend / Tuner / Demodulator module part:
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| /linux/arch/powerpc/include/asm/ |
| H A D | pmac_feature.h | 12 * Note: I removed media-bay details from the feature stuff, I believe it's
13 * not worth it, the media-bay driver can directly use the mac-io
22 * error when negative, 0 is the default success result. Some functions
27 * When either is not used, pass 0.
48 * all of the Grand-Central based machines. We currently don't
51 #define PMAC_TYPE_PSURGE 0x10 /* PowerSurge */
52 #define PMAC_TYPE_ANS 0x11 /* Apple Network Server */
54 /* Here is the infamous serie of OHare based machines
56 #define PMAC_TYPE_COMET 0x20 /* Believed to be PowerBook 2400 */
57 #define PMAC_TYPE_HOOPER 0x21 /* Believed to be PowerBook 3400 */
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| /linux/Documentation/devicetree/bindings/arm/stm32/ |
| H A D | stm32.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
17 - description: emtrion STM32MP1 Argon based Boards
19 - const: emtrion,stm32mp157c-emsbc-argon
20 - const: emtrion,stm32mp157c-emstamp-argon
21 - const: st,stm32mp157
22 - items:
23 - enum:
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| /linux/drivers/usb/serial/ |
| H A D | io_usbvend.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * USBVEND.H Vendor-specific USB definitions
7 * must be kept backward-compatible with older firmware.
28 #define USB_VENDOR_ID_ION 0x1608 // Our VID
29 #define USB_VENDOR_ID_TI 0x0451 // TI VID
30 #define USB_VENDOR_ID_AXIOHM 0x05D9 /* Axiohm VID */
34 // We break the USB-defined PID into an OEM Id field (upper 6 bits)
40 // ION-device OEM IDs
41 #define ION_OEM_ID_ION 0 // 00h Inside Out Networks
50 // ION-device Device IDs
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| /linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | floating-point.json | 4 "EventCode": "0x00",
6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
7 "UMask": "0x0f"
11 "EventCode": "0x00",
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
14 "UMask": "0x08"
18 "EventCode": "0x00",
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
21 "UMask": "0x04"
25 "EventCode": "0x00",
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| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | floating-point.json | 4 "EventCode": "0x00",
5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
7 "UMask": "0xf0"
11 "EventCode": "0x00",
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
14 "UMask": "0x80"
18 "EventCode": "0x00",
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
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| /linux/Documentation/arch/arm/ |
| H A D | sunxi.rst | 10 ------------
11 Linux kernel mach directory: arch/arm/mach-sunxi
15 * ARM926 based SoCs
16 - Allwinner F20 (sun3i)
20 * ARM Cortex-A8 based SoCs
21 - Allwinner A10 (sun4i)
25 http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
28 …http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
30 - Allwinner A10s (sun5i)
34 http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
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| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 4 "Counter": "0,1",
5 "EventCode": "0xC4",
8 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
13 "Counter": "0,1",
14 "EventCode": "0xC4",
17 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
19 "UMask": "0x80"
23 "Counter": "0,1",
24 "EventCode": "0xC4",
27 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
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| /linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | floating-point.json | 4 "EventCode": "0x00",
6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
7 "UMask": "0x0f"
11 "EventCode": "0x00",
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
14 "UMask": "0x08"
18 "EventCode": "0x00",
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
21 "UMask": "0x04"
25 "EventCode": "0x00",
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| /linux/drivers/gpu/drm/i915/gt/uc/abi/ |
| H A D | guc_communication_mmio_abi.h | 1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2014-2021 Intel Corporation
10 * DOC: GuC MMIO based communication
12 * The MMIO based communication between Host and GuC relies on special
16 * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H)
20 * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8,
22 * itself uses an 4-element array to store the H2G message.
24 * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which
27 * The MMIO based communication is mainly used during driver initialization
28 * phase to setup the `CTB based communication`_ that will be used afterwards.
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| /linux/drivers/gpu/drm/xe/abi/ |
| H A D | guc_communication_mmio_abi.h | 1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2014-2021 Intel Corporation
10 * DOC: GuC MMIO based communication
12 * The MMIO based communication between Host and GuC relies on special
16 * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H)
20 * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8,
22 * itself uses an 4-element array to store the H2G message.
24 * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which
27 * The MMIO based communication is mainly used during driver initialization
28 * phase to setup the `CTB based communication`_ that will be used afterwards.
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| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0xE6",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0xE6",
18 "UMask": "0x10"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xE6",
27 "UMask": "0x8"
31 "Counter": "0,1,2,3",
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| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0xE6",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0xE6",
18 "UMask": "0x10"
22 "Counter": "0,1,2,3",
23 "EventCode": "0xE6",
27 "UMask": "0x8"
31 "Counter": "0,1,2,3",
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| /linux/Documentation/networking/device_drivers/ethernet/cirrus/ |
| H A D | cs89x0.rst | 1 .. SPDX-License-Identifier: GPL-2.0
33 2.1 CS8900-based Adapter Configuration
34 2.2 CS8920-based Adapter Configuration
46 5.2.1 Diagnostic Self-Test
66 The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow
67 IEEE 802.3 standards and support half or full-duplex operation in ISA bus
69 in 16-bit ISA or EISA bus expansion slots and are available in
70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5
73 CS8920-based adapters are similar to the CS8900-based adapter with additional
85 or loaded at run-time as a device driver module.
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| /linux/Documentation/userspace-api/media/drivers/ |
| H A D | thp7312.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
6 The THP7312 driver implements the following driver-specific controls:
9 Enable/Disable auto-adjustment, based on lighting conditions, of the frame
10 rate when auto-exposure is enabled.
13 Set method of auto-focus. Only takes effect when auto-focus is enabled.
15 .. flat-table::
16 :header-rows: 0
17 :stub-columns: 0
20 * - ``0``
21 - Contrast-based auto-focus
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| /linux/sound/soc/sof/amd/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
29 This option is not user-selectable but automatically handled by
65 This option is not user-selectable but automatically handled by
73 tristate "SOF support for SoundWire based AMD platforms"
92 AMD ACP6.3 version based platforms.
93 Say Y if you want to enable SOF on ACP6.3 based platform.
97 tristate "SOF support for ACP7.0/ACP7.1 platforms"
104 AMD ACP7.0/ACP7.1 version based platforms.
105 Say Y if you want to enable SOF on ACP7.0/ACP7.1 based platforms.
|
| /linux/include/drm/ |
| H A D | drm_vma_manager.h | 37 #define DRM_FILE_PAGE_OFFSET_START ((0xFFFFFFFFUL >> PAGE_SHIFT) + 1)
38 #define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFFUL >> PAGE_SHIFT) * 256)
40 #define DRM_FILE_PAGE_OFFSET_START ((0xFFFFFFFUL >> PAGE_SHIFT) + 1)
41 #define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFUL >> PAGE_SHIFT) * 16)
84 * drm_vma_offset_exact_lookup_locked() - Look up node by exact address
86 * @start: Start address (page-based, not byte-based)
87 * @pages: Size of object (page-based)
103 return (node && node->vm_node.start == start) ? node : NULL; in drm_vma_offset_exact_lookup_locked()
107 * drm_vma_offset_lock_lookup() - Lock lookup for extended private use
120 * Note: You're in atomic-context while holding this lock!
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | brcm,bcm63xx-hsspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
16 early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
17 controller was carried over to recent ARM based chips, such as BCM63138,
18 BCM4908 and BCM6858. The old MIPS based chip should continue to use the
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| /linux/sound/core/ |
| H A D | pcm_dmaengine.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 * Based on:
7 * imx-pcm-dma-mx
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| /linux/drivers/usb/storage/ |
| H A D | unusual_datafab.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
9 UNUSUAL_DEV( 0x07c4, 0xa000, 0x0000, 0x0015,
11 "MDCFE-B USB CF Reader",
13 0),
16 * The following Datafab-based devices may or may not work
17 * using the current driver...the 0xffff is arbitrary since I
20 * The 0xa003 and 0xa004 devices in particular I'm curious about.
23 * other Datafab-based cards operational with this driver, I've decided
26 UNUSUAL_DEV( 0x07c4, 0xa001, 0x0000, 0xffff,
30 0),
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| /linux/drivers/fsi/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 FSI - the FRU Support Interface - is a simple bus for low-level
12 access to POWER-based hardware.
25 by one so that chip 0 will have /dev/scom1 and chip1 /dev/scom2
29 symlinks in /dev/fsi/by-path when this option is enabled.
32 tristate "GPIO-based FSI master"
47 tristate "FSI master based on Aspeed ColdFire coprocessor"
77 This option enables an FSI based SCOM device driver.
83 This option enables an FSI based SBEFIFO device driver. The SBEFIFO is
84 a pipe-like FSI device for communicating with the self boot engine
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| /linux/Documentation/arch/x86/x86_64/ |
| H A D | fsgs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 memory can use segment register based addressing mode. The following
10 Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
18 In 32-bit mode the CPU provides 6 segments, which also support segment
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
22 always 0 to provide a full 64bit address space. The FS and GS segments are
23 still functional in 64-bit mode.
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| /linux/drivers/net/can/sja1000/ |
| H A D | plx_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
37 /* Pointer to device-dependent reset function */
44 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */
45 #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
50 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
58 #define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */
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| /linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,sa8255p-geni-se-qup.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Praveen Talari <quic_ptalari@quicinc.com>
13 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
22 const: qcom,sa8255p-geni-se-qup
28 "#address-cells":
31 "#size-cells":
39 dma-coherent: true
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