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/linux/arch/mips/include/asm/
H A Dunaligned-emul.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 __asm__ __volatile__ (".set\tnoat\n" \
11 "1:\t"type##_lb("%0", "0(%2)")"\n" \
12 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
13 "sll\t%0, 0x8\n\t" \
14 "or\t%0, $1\n\t" \
15 "li\t%1, 0\n" \
16 "3:\t.set\tat\n\t" \
17 ".insn\n\t" \
18 ".section\t.fixup,\"ax\"\n\t" \
[all …]
/linux/arch/mips/kernel/
H A Dmips-r2-to-r6-emul.c28 #include <asm/mips-r2-to-r6-emul.h>
59 int mipsr2_emulation = 0;
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
86 return 0; in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
95 return 0; in mipsr6_emul()
[all …]
/linux/arch/arc/include/asm/
H A Duaccess.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -__clear_user( ) called multiple times during elf load was byte loop
10 * -Hand crafted constant propagation for "constant" copy sizes
11 * -stock kernel shrunk by 33K at -O3
14 * -Added option to (UN)inline copy_(to|from)_user to reduce code sz
15 * -kernel shrunk by 200K even at -O3 (gcc 4.2.1)
16 * -Enabled when doing -Os
30 long __ret = 0; /* success by default */ \
41 * Returns 0 on success, -EFAULT if not.
[all …]
/linux/arch/sparc/include/asm/
H A Dxor_32.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Optimized RAID-5 checksumming functions for 32-bit Sparc.
23 "ldd [%0 + 0x00], %%g2\n\t" in sparc_2()
24 "ldd [%0 + 0x08], %%g4\n\t" in sparc_2()
25 "ldd [%0 + 0x10], %%o0\n\t" in sparc_2()
26 "ldd [%0 + 0x18], %%o2\n\t" in sparc_2()
27 "ldd [%1 + 0x00], %%o4\n\t" in sparc_2()
28 "ldd [%1 + 0x08], %%l0\n\t" in sparc_2()
29 "ldd [%1 + 0x10], %%l2\n\t" in sparc_2()
30 "ldd [%1 + 0x18], %%l4\n\t" in sparc_2()
[all …]
/linux/arch/csky/lib/
H A Dusercopy.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
8 unsigned long n) in raw_copy_from_user() argument
13 "0: cmpnei %1, 0 \n" in raw_copy_from_user()
14 " bf 7f \n" in raw_copy_from_user()
15 " mov %3, %1 \n" in raw_copy_from_user()
16 " or %3, %2 \n" in raw_copy_from_user()
17 " andi %3, 3 \n" in raw_copy_from_user()
18 " cmpnei %3, 0 \n" in raw_copy_from_user()
19 " bf 1f \n" in raw_copy_from_user()
[all …]
/linux/drivers/staging/media/starfive/camss/
H A Dstf-isp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * StarFive Camera Subsystem - ISP Module
7 * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
13 #include <media/v4l2-subdev.h>
15 #include "stf-video.h"
19 #define STF_ISP_REG_OFFSET_MAX 0x0fff
23 #define ISP_REG_CSI_INPUT_EN_AND_STATUS 0x000
29 #define CSI_EN_S BIT(0)
31 #define ISP_REG_CSIINTS 0x008
32 #define CSI_INTS(n) ((n) << 16) argument
[all …]
/linux/drivers/media/pci/solo6x10/
H A Dsolo6x10-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
17 #include "solo6x10-offsets.h"
20 #define SOLO_SYS_CFG 0x0000
21 #define SOLO_SYS_CFG_FOUT_EN 0x00000001
22 #define SOLO_SYS_CFG_PLL_BYPASS 0x00000002
23 #define SOLO_SYS_CFG_PLL_PWDN 0x00000004
24 #define SOLO_SYS_CFG_OUTDIV(__n) (((__n) & 0x003) << 3)
25 #define SOLO_SYS_CFG_FEEDBACKDIV(__n) (((__n) & 0x1ff) << 5)
26 #define SOLO_SYS_CFG_INPUTDIV(__n) (((__n) & 0x01f) << 14)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_util.c1 /* SPDX-License-Identifier: MIT */
33 const int log_2 = ((x >> 23) & 255) - 128; in _log()
39 in = ((-1.0f / 3) * in + 2) * in - 2.0f / 3; in _log()
50 val = 0; in dml_util_is_420()
53 val = 0; in dml_util_is_420()
56 val = 0; in dml_util_is_420()
65 val = 0; in dml_util_is_420()
68 val = 0; in dml_util_is_420()
71 ASSERT(0); in dml_util_is_420()
81 if ((int)exp == 0) in dcn_bw_pow()
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
16 #include "pinctrl-tegra.h"
24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
194 /* All non-GPIO pins follow */
198 /* Non-GPIO pins */
199 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1538 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1539 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1541 #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
[all …]
H A Dpinctrl-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
16 #include "pinctrl-tegra.h"
24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
208 /* All non-GPIO pins follow */
212 /* Non-GPIO pins */
213 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1705 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1706 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1707 #define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
[all …]
H A Dpinctrl-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "pinctrl-tegra.h"
22 #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
177 /* All non-GPIO pins follow */
181 /* Non-GPIO pins */
182 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1266 #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
1267 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1269 #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1270 #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
[all …]
/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
13 #define CHNL_CTRL 0x0000
17 #define CHNL_CTRL_CHAIN_BUF(n) ((n) << 25) argument
19 #define CHNL_CTRL_CHAIN_BUF_NO_CHAIN 0
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16) argument
24 #define CHNL_CTRL_MIPI_VC_ID(n) ((n) << 6) argument
26 #define CHNL_CTRL_SRC_TYPE(n) ((n) << 4) argument
28 #define CHNL_CTRL_SRC_TYPE_DEVICE 0
30 #define CHNL_CTRL_SRC_INPUT(n) ((n) << 0) argument
[all …]
/linux/tools/testing/selftests/x86/
H A Dtest_FCOMI.c1 // SPDX-License-Identifier: GPL-2.0
18 CF = 1 << 0,
29 /* qNaN is s|111 1111 1|0xx xxxx xxxx xxxx xxxx xxxx (some x must be nonzero) */
30 int snan = 0x7fc11111;
31 int qnan = 0x7f811111;
34 unsigned short snan80[5] = { 0x1111, 0x1111, 0x1111, 0x8111, 0x7fff };
40 asm ("\n" in test()
42 " push %0""\n" in test()
43 " popf""\n" in test()
44 " fld1""\n" in test()
[all …]
/linux/arch/arm/mm/
H A Dcopypage-feroceon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/copypage-feroceon.S
18 .arch armv5te \n\ in feroceon_copy_user_page()
19 1: ldmia %1!, {r2 - r7, ip, lr} \n\ in feroceon_copy_user_page()
20 pld [%1, #0] \n\ in feroceon_copy_user_page()
21 pld [%1, #32] \n\ in feroceon_copy_user_page()
22 pld [%1, #64] \n\ in feroceon_copy_user_page()
23 pld [%1, #96] \n\ in feroceon_copy_user_page()
24 pld [%1, #128] \n\ in feroceon_copy_user_page()
25 pld [%1, #160] \n\ in feroceon_copy_user_page()
[all …]
/linux/arch/sh/include/asm/
H A Duaccess_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2003 - 2008 Paul Mundt
18 retval = 0; \
36 } while (0)
42 "1:\n\t" \
43 "mov." insn " %2, %1\n\t" \
44 "2:\n" \
45 ".section .fixup,\"ax\"\n" \
46 "3:\n\t" \
47 "mov #0, %1\n\t" \
[all …]
H A Dspinlock-llsc.h1 /* SPDX-License-Identifier: GPL-2.0
3 * include/asm-sh/spinlock-llsc.h
18 #define arch_spin_is_locked(x) ((x)->lock <= 0)
32 "1: \n\t" in arch_spin_lock()
33 "movli.l @%2, %0 ! arch_spin_lock \n\t" in arch_spin_lock()
34 "mov %0, %1 \n\t" in arch_spin_lock()
35 "mov #0, %0 \n\t" in arch_spin_lock()
36 "movco.l %0, @%2 \n\t" in arch_spin_lock()
37 "bf 1b \n\t" in arch_spin_lock()
38 "cmp/pl %1 \n\t" in arch_spin_lock()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/nvfw/
H A Dacr.c28 nvkm_debug(subdev, "wprHeader\n"); in wpr_header_dump()
29 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); in wpr_header_dump()
30 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); in wpr_header_dump()
31 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); in wpr_header_dump()
32 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); in wpr_header_dump()
33 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); in wpr_header_dump()
39 nvkm_debug(subdev, "wprHeader\n"); in wpr_header_v1_dump()
40 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); in wpr_header_v1_dump()
41 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); in wpr_header_v1_dump()
42 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); in wpr_header_v1_dump()
[all …]
/linux/arch/powerpc/platforms/44x/
H A Dfsp2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * FSP-2 board specific routines
7 * Copyright 2002-2005 MontaVista Software Inc.
10 * Copyright (c) 2003-2005 Zultys Technologies
31 #define FSP2_BUS_ERR "ibm,bus-error-irq"
32 #define FSP2_CMU_ERR "ibm,cmu-error-irq"
33 #define FSP2_CONF_ERR "ibm,conf-error-irq"
34 #define FSP2_OPBD_ERR "ibm,opbd-error-irq"
35 #define FSP2_MCUE "ibm,mc-ue-irq"
36 #define FSP2_RST_WRN "ibm,reset-warning-irq"
[all …]
/linux/arch/m68k/lib/
H A Dchecksum.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de>
18 * A: At some points, the sum (%0) was used as
19 * length-counter instead of the length counter
22 * data-registers to hold input values and one tries to
43 * is aligned on either a 2-byte or 4-byte boundary. in csum_partial()
45 __asm__("movel %2,%3\n\t" in csum_partial()
46 "btst #1,%3\n\t" /* Check alignment */ in csum_partial()
47 "jeq 2f\n\t" in csum_partial()
48 "subql #2,%1\n\t" /* buff%4==2: treat first word */ in csum_partial()
[all …]
/linux/arch/mips/mm/
H A Dsc-ip22.c1 // SPDX-License-Identifier: GPL-2.0
3 * sc-ip22.c: Indy cache management functions.
24 #define SC_SIZE 0x00080000
26 #define CI_MASK (SC_SIZE - SC_LINE)
27 #define SC_INDEX(n) ((n) & CI_MASK) argument
34 " .set push # indy_sc_wipe \n" in indy_sc_wipe()
35 " .set noreorder \n" in indy_sc_wipe()
36 " .set mips3 \n" in indy_sc_wipe()
37 " .set noat \n" in indy_sc_wipe()
38 " mfc0 %2, $12 \n" in indy_sc_wipe()
[all …]
/linux/sound/isa/galaxy/
H A Dgalaxy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
48 MODULE_PARM_DESC(mpu_port, "MPU-401 port # for " CRD_NAME " driver.");
54 MODULE_PARM_DESC(mpu_irq, "MPU-401 IRQ # for " CRD_NAME " driver.");
64 #define DSP_PORT_RESET 0x6
65 #define DSP_PORT_READ 0xa
66 #define DSP_PORT_COMMAND 0xc
67 #define DSP_PORT_STATUS 0xc
68 #define DSP_PORT_DATA_AVAIL 0xe
70 #define DSP_SIGNATURE 0xaa
72 #define DSP_COMMAND_GET_VERSION 0xe1
[all …]
/linux/security/ipe/
H A Dpolicy_tests.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2024 Microsoft Corporation. All rights reserved.
19 "policy_name=allowall policy_version=0.0.0\n"
21 0,
25 "policy_name=trailing_comment policy_version=152.0.0 #This is comment\n"
27 0,
31 "policy_name=allowallnewline policy_version=0.2.0\n"
32 "DEFAULT action=ALLOW\n"
33 "\n",
34 0,
[all …]
/linux/arch/nios2/mm/
H A Duaccess.c13 asm(".global raw_copy_from_user\n"
14 " .type raw_copy_from_user, @function\n"
15 "raw_copy_from_user:\n"
16 " movi r2,7\n"
17 " mov r3,r4\n"
18 " bge r2,r6,1f\n"
19 " xor r2,r4,r5\n"
20 " andi r2,r2,3\n"
21 " movi r7,3\n"
22 " beq r2,zero,4f\n"
[all …]
/linux/arch/sh/kernel/cpu/sh4/
H A Dfpu.c1 // SPDX-License-Identifier: GPL-2.0
22 #define FPSCR_RCHG 0x00000000
46 asm volatile ("sts.l fpul, @-%0\n\t" in save_fpu()
47 "sts.l fpscr, @-%0\n\t" in save_fpu()
48 "lds %2, fpscr\n\t" in save_fpu()
49 "frchg\n\t" in save_fpu()
50 "fmov.s fr15, @-%0\n\t" in save_fpu()
51 "fmov.s fr14, @-%0\n\t" in save_fpu()
52 "fmov.s fr13, @-%0\n\t" in save_fpu()
53 "fmov.s fr12, @-%0\n\t" in save_fpu()
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_dump.c1 // SPDX-License-Identifier: GPL-2.0
23 {IGC_RDLEN(0), "RDLEN"},
24 {IGC_RDH(0), "RDH"},
25 {IGC_RDT(0), "RDT"},
26 {IGC_RXDCTL(0), "RXDCTL"},
27 {IGC_RDBAL(0), "RDBAL"},
28 {IGC_RDBAH(0), "RDBAH"},
32 {IGC_TDBAL(0), "TDBAL"},
33 {IGC_TDBAH(0), "TDBAH"},
34 {IGC_TDLEN(0), "TDLEN"},
[all …]

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