Lines Matching +full:0 +full:- +full:n
1 // SPDX-License-Identifier: GPL-2.0
22 #define FPSCR_RCHG 0x00000000
46 asm volatile ("sts.l fpul, @-%0\n\t" in save_fpu()
47 "sts.l fpscr, @-%0\n\t" in save_fpu()
48 "lds %2, fpscr\n\t" in save_fpu()
49 "frchg\n\t" in save_fpu()
50 "fmov.s fr15, @-%0\n\t" in save_fpu()
51 "fmov.s fr14, @-%0\n\t" in save_fpu()
52 "fmov.s fr13, @-%0\n\t" in save_fpu()
53 "fmov.s fr12, @-%0\n\t" in save_fpu()
54 "fmov.s fr11, @-%0\n\t" in save_fpu()
55 "fmov.s fr10, @-%0\n\t" in save_fpu()
56 "fmov.s fr9, @-%0\n\t" in save_fpu()
57 "fmov.s fr8, @-%0\n\t" in save_fpu()
58 "fmov.s fr7, @-%0\n\t" in save_fpu()
59 "fmov.s fr6, @-%0\n\t" in save_fpu()
60 "fmov.s fr5, @-%0\n\t" in save_fpu()
61 "fmov.s fr4, @-%0\n\t" in save_fpu()
62 "fmov.s fr3, @-%0\n\t" in save_fpu()
63 "fmov.s fr2, @-%0\n\t" in save_fpu()
64 "fmov.s fr1, @-%0\n\t" in save_fpu()
65 "fmov.s fr0, @-%0\n\t" in save_fpu()
66 "frchg\n\t" in save_fpu()
67 "fmov.s fr15, @-%0\n\t" in save_fpu()
68 "fmov.s fr14, @-%0\n\t" in save_fpu()
69 "fmov.s fr13, @-%0\n\t" in save_fpu()
70 "fmov.s fr12, @-%0\n\t" in save_fpu()
71 "fmov.s fr11, @-%0\n\t" in save_fpu()
72 "fmov.s fr10, @-%0\n\t" in save_fpu()
73 "fmov.s fr9, @-%0\n\t" in save_fpu()
74 "fmov.s fr8, @-%0\n\t" in save_fpu()
75 "fmov.s fr7, @-%0\n\t" in save_fpu()
76 "fmov.s fr6, @-%0\n\t" in save_fpu()
77 "fmov.s fr5, @-%0\n\t" in save_fpu()
78 "fmov.s fr4, @-%0\n\t" in save_fpu()
79 "fmov.s fr3, @-%0\n\t" in save_fpu()
80 "fmov.s fr2, @-%0\n\t" in save_fpu()
81 "fmov.s fr1, @-%0\n\t" in save_fpu()
82 "fmov.s fr0, @-%0\n\t" in save_fpu()
83 "lds %3, fpscr\n\t":"=r" (dummy) in save_fpu()
84 :"0"((char *)(&tsk->thread.xstate->hardfpu.status)), in save_fpu()
96 asm volatile ("lds %2, fpscr\n\t" in restore_fpu()
97 "fmov.s @%0+, fr0\n\t" in restore_fpu()
98 "fmov.s @%0+, fr1\n\t" in restore_fpu()
99 "fmov.s @%0+, fr2\n\t" in restore_fpu()
100 "fmov.s @%0+, fr3\n\t" in restore_fpu()
101 "fmov.s @%0+, fr4\n\t" in restore_fpu()
102 "fmov.s @%0+, fr5\n\t" in restore_fpu()
103 "fmov.s @%0+, fr6\n\t" in restore_fpu()
104 "fmov.s @%0+, fr7\n\t" in restore_fpu()
105 "fmov.s @%0+, fr8\n\t" in restore_fpu()
106 "fmov.s @%0+, fr9\n\t" in restore_fpu()
107 "fmov.s @%0+, fr10\n\t" in restore_fpu()
108 "fmov.s @%0+, fr11\n\t" in restore_fpu()
109 "fmov.s @%0+, fr12\n\t" in restore_fpu()
110 "fmov.s @%0+, fr13\n\t" in restore_fpu()
111 "fmov.s @%0+, fr14\n\t" in restore_fpu()
112 "fmov.s @%0+, fr15\n\t" in restore_fpu()
113 "frchg\n\t" in restore_fpu()
114 "fmov.s @%0+, fr0\n\t" in restore_fpu()
115 "fmov.s @%0+, fr1\n\t" in restore_fpu()
116 "fmov.s @%0+, fr2\n\t" in restore_fpu()
117 "fmov.s @%0+, fr3\n\t" in restore_fpu()
118 "fmov.s @%0+, fr4\n\t" in restore_fpu()
119 "fmov.s @%0+, fr5\n\t" in restore_fpu()
120 "fmov.s @%0+, fr6\n\t" in restore_fpu()
121 "fmov.s @%0+, fr7\n\t" in restore_fpu()
122 "fmov.s @%0+, fr8\n\t" in restore_fpu()
123 "fmov.s @%0+, fr9\n\t" in restore_fpu()
124 "fmov.s @%0+, fr10\n\t" in restore_fpu()
125 "fmov.s @%0+, fr11\n\t" in restore_fpu()
126 "fmov.s @%0+, fr12\n\t" in restore_fpu()
127 "fmov.s @%0+, fr13\n\t" in restore_fpu()
128 "fmov.s @%0+, fr14\n\t" in restore_fpu()
129 "fmov.s @%0+, fr15\n\t" in restore_fpu()
130 "frchg\n\t" in restore_fpu()
131 "lds.l @%0+, fpscr\n\t" in restore_fpu()
132 "lds.l @%0+, fpul\n\t" in restore_fpu()
134 :"0" (tsk->thread.xstate), "r" (FPSCR_RCHG) in restore_fpu()
140 * denormal_to_double - Given denormalized float number,
144 * @n: Index to FP register
146 static void denormal_to_double(struct sh_fpu_hard_struct *fpu, int n) in denormal_to_double() argument
149 unsigned long x = fpu->fpul; in denormal_to_double()
150 int exp = 1023 - 126; in denormal_to_double()
152 if (x != 0 && (x & 0x7f800000) == 0) { in denormal_to_double()
153 du = (x & 0x80000000); in denormal_to_double()
154 while ((x & 0x00800000) == 0) { in denormal_to_double()
156 exp--; in denormal_to_double()
158 x &= 0x007fffff; in denormal_to_double()
162 fpu->fp_regs[n] = du; in denormal_to_double()
163 fpu->fp_regs[n + 1] = dl; in denormal_to_double()
168 * ieee_fpe_handler - Handle denormalized number exception
176 unsigned short insn = *(unsigned short *)regs->pc; in ieee_fpe_handler()
180 (insn >> 12) & 0xf, in ieee_fpe_handler()
181 (insn >> 8) & 0xf, in ieee_fpe_handler()
182 (insn >> 4) & 0xf, in ieee_fpe_handler()
183 insn & 0xf in ieee_fpe_handler()
186 if (nib[0] == 0xb || (nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) in ieee_fpe_handler()
187 regs->pr = regs->pc + 4; /* bsr & jsr */ in ieee_fpe_handler()
189 if (nib[0] == 0xa || nib[0] == 0xb) { in ieee_fpe_handler()
191 nextpc = regs->pc + 4 + ((short)((insn & 0xfff) << 4) >> 3); in ieee_fpe_handler()
192 finsn = *(unsigned short *)(regs->pc + 2); in ieee_fpe_handler()
193 } else if (nib[0] == 0x8 && nib[1] == 0xd) { in ieee_fpe_handler()
195 if (regs->sr & 1) in ieee_fpe_handler()
196 nextpc = regs->pc + 4 + ((char)(insn & 0xff) << 1); in ieee_fpe_handler()
198 nextpc = regs->pc + 4; in ieee_fpe_handler()
199 finsn = *(unsigned short *)(regs->pc + 2); in ieee_fpe_handler()
200 } else if (nib[0] == 0x8 && nib[1] == 0xf) { in ieee_fpe_handler()
202 if (regs->sr & 1) in ieee_fpe_handler()
203 nextpc = regs->pc + 4; in ieee_fpe_handler()
205 nextpc = regs->pc + 4 + ((char)(insn & 0xff) << 1); in ieee_fpe_handler()
206 finsn = *(unsigned short *)(regs->pc + 2); in ieee_fpe_handler()
207 } else if (nib[0] == 0x4 && nib[3] == 0xb && in ieee_fpe_handler()
208 (nib[2] == 0x0 || nib[2] == 0x2)) { in ieee_fpe_handler()
210 nextpc = regs->regs[nib[1]]; in ieee_fpe_handler()
211 finsn = *(unsigned short *)(regs->pc + 2); in ieee_fpe_handler()
212 } else if (nib[0] == 0x0 && nib[3] == 0x3 && in ieee_fpe_handler()
213 (nib[2] == 0x0 || nib[2] == 0x2)) { in ieee_fpe_handler()
215 nextpc = regs->pc + 4 + regs->regs[nib[1]]; in ieee_fpe_handler()
216 finsn = *(unsigned short *)(regs->pc + 2); in ieee_fpe_handler()
217 } else if (insn == 0x000b) { in ieee_fpe_handler()
219 nextpc = regs->pr; in ieee_fpe_handler()
220 finsn = *(unsigned short *)(regs->pc + 2); in ieee_fpe_handler()
222 nextpc = regs->pc + instruction_size(insn); in ieee_fpe_handler()
226 if ((finsn & 0xf1ff) == 0xf0ad) { in ieee_fpe_handler()
230 if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR)) in ieee_fpe_handler()
232 denormal_to_double(&tsk->thread.xstate->hardfpu, in ieee_fpe_handler()
233 (finsn >> 8) & 0xf); in ieee_fpe_handler()
235 return 0; in ieee_fpe_handler()
237 regs->pc = nextpc; in ieee_fpe_handler()
239 } else if ((finsn & 0xf00f) == 0xf002) { in ieee_fpe_handler()
243 int n, m, prec; in ieee_fpe_handler() local
246 n = (finsn >> 8) & 0xf; in ieee_fpe_handler()
247 m = (finsn >> 4) & 0xf; in ieee_fpe_handler()
248 hx = tsk->thread.xstate->hardfpu.fp_regs[n]; in ieee_fpe_handler()
249 hy = tsk->thread.xstate->hardfpu.fp_regs[m]; in ieee_fpe_handler()
250 fpscr = tsk->thread.xstate->hardfpu.fpscr; in ieee_fpe_handler()
254 && (prec && ((hx & 0x7fffffff) < 0x00100000 in ieee_fpe_handler()
255 || (hy & 0x7fffffff) < 0x00100000))) { in ieee_fpe_handler()
260 | tsk->thread.xstate->hardfpu.fp_regs[n + 1]; in ieee_fpe_handler()
262 | tsk->thread.xstate->hardfpu.fp_regs[m + 1]; in ieee_fpe_handler()
264 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32; in ieee_fpe_handler()
265 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff; in ieee_fpe_handler()
267 && (!prec && ((hx & 0x7fffffff) < 0x00800000 in ieee_fpe_handler()
268 || (hy & 0x7fffffff) < 0x00800000))) { in ieee_fpe_handler()
271 tsk->thread.xstate->hardfpu.fp_regs[n] = hx; in ieee_fpe_handler()
273 return 0; in ieee_fpe_handler()
275 regs->pc = nextpc; in ieee_fpe_handler()
277 } else if ((finsn & 0xf00e) == 0xf000) { in ieee_fpe_handler()
281 int n, m, prec; in ieee_fpe_handler() local
284 n = (finsn >> 8) & 0xf; in ieee_fpe_handler()
285 m = (finsn >> 4) & 0xf; in ieee_fpe_handler()
286 hx = tsk->thread.xstate->hardfpu.fp_regs[n]; in ieee_fpe_handler()
287 hy = tsk->thread.xstate->hardfpu.fp_regs[m]; in ieee_fpe_handler()
288 fpscr = tsk->thread.xstate->hardfpu.fpscr; in ieee_fpe_handler()
292 && (prec && ((hx & 0x7fffffff) < 0x00100000 in ieee_fpe_handler()
293 || (hy & 0x7fffffff) < 0x00100000))) { in ieee_fpe_handler()
298 | tsk->thread.xstate->hardfpu.fp_regs[n + 1]; in ieee_fpe_handler()
300 | tsk->thread.xstate->hardfpu.fp_regs[m + 1]; in ieee_fpe_handler()
301 if ((finsn & 0xf00f) == 0xf000) in ieee_fpe_handler()
305 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32; in ieee_fpe_handler()
306 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff; in ieee_fpe_handler()
308 && (!prec && ((hx & 0x7fffffff) < 0x00800000 in ieee_fpe_handler()
309 || (hy & 0x7fffffff) < 0x00800000))) { in ieee_fpe_handler()
311 if ((finsn & 0xf00f) == 0xf000) in ieee_fpe_handler()
315 tsk->thread.xstate->hardfpu.fp_regs[n] = hx; in ieee_fpe_handler()
317 return 0; in ieee_fpe_handler()
319 regs->pc = nextpc; in ieee_fpe_handler()
321 } else if ((finsn & 0xf003) == 0xf003) { in ieee_fpe_handler()
325 int n, m, prec; in ieee_fpe_handler() local
328 n = (finsn >> 8) & 0xf; in ieee_fpe_handler()
329 m = (finsn >> 4) & 0xf; in ieee_fpe_handler()
330 hx = tsk->thread.xstate->hardfpu.fp_regs[n]; in ieee_fpe_handler()
331 hy = tsk->thread.xstate->hardfpu.fp_regs[m]; in ieee_fpe_handler()
332 fpscr = tsk->thread.xstate->hardfpu.fpscr; in ieee_fpe_handler()
336 && (prec && ((hx & 0x7fffffff) < 0x00100000 in ieee_fpe_handler()
337 || (hy & 0x7fffffff) < 0x00100000))) { in ieee_fpe_handler()
342 | tsk->thread.xstate->hardfpu.fp_regs[n + 1]; in ieee_fpe_handler()
344 | tsk->thread.xstate->hardfpu.fp_regs[m + 1]; in ieee_fpe_handler()
348 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32; in ieee_fpe_handler()
349 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff; in ieee_fpe_handler()
351 && (!prec && ((hx & 0x7fffffff) < 0x00800000 in ieee_fpe_handler()
352 || (hy & 0x7fffffff) < 0x00800000))) { in ieee_fpe_handler()
355 tsk->thread.xstate->hardfpu.fp_regs[n] = hx; in ieee_fpe_handler()
357 return 0; in ieee_fpe_handler()
359 regs->pc = nextpc; in ieee_fpe_handler()
361 } else if ((finsn & 0xf0bd) == 0xf0bd) { in ieee_fpe_handler()
362 /* fcnvds - double to single precision convert */ in ieee_fpe_handler()
367 m = (finsn >> 8) & 0x7; in ieee_fpe_handler()
368 hx = tsk->thread.xstate->hardfpu.fp_regs[m]; in ieee_fpe_handler()
370 if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR) in ieee_fpe_handler()
371 && ((hx & 0x7fffffff) < 0x00100000)) { in ieee_fpe_handler()
375 llx = ((long long)tsk->thread.xstate->hardfpu.fp_regs[m] << 32) in ieee_fpe_handler()
376 | tsk->thread.xstate->hardfpu.fp_regs[m + 1]; in ieee_fpe_handler()
378 tsk->thread.xstate->hardfpu.fpul = float64_to_float32(llx); in ieee_fpe_handler()
380 return 0; in ieee_fpe_handler()
382 regs->pc = nextpc; in ieee_fpe_handler()
386 return 0; in ieee_fpe_handler()
397 int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.xstate->hardfpu.fpscr); in float_rounding_mode()
407 fpu_exception_flags = 0; in BUILD_TRAP_HANDLER()
409 tsk->thread.xstate->hardfpu.fpscr &= in BUILD_TRAP_HANDLER()
411 tsk->thread.xstate->hardfpu.fpscr |= fpu_exception_flags; in BUILD_TRAP_HANDLER()
412 /* Set the FPSCR flag as well as cause bits - simply in BUILD_TRAP_HANDLER()
414 tsk->thread.xstate->hardfpu.fpscr |= (fpu_exception_flags >> 10); in BUILD_TRAP_HANDLER()
417 task_thread_info(tsk)->status |= TS_USEDFPU; in BUILD_TRAP_HANDLER()
418 if ((((tsk->thread.xstate->hardfpu.fpscr & FPSCR_ENABLE_MASK) >> 7) & in BUILD_TRAP_HANDLER()
419 (fpu_exception_flags >> 2)) == 0) { in BUILD_TRAP_HANDLER()