| /linux/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
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| /linux/arch/powerpc/boot/ |
| H A D | wii-head.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/wii-head.S
6 * Copyright (C) 2008-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
16 * - if the high BATs are enabled or not
29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
32 mflr 8
33 clrlwi 8, 8, 3 /* convert to a real address */
34 addi 8, 8, _mmu_off - 1b
[all …]
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| H A D | gamecube-head.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/gamecube-head.S
6 * Copyright (C) 2004-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
31 mflr 8
32 clrlwi 8, 8, 3 /* convert to a real address */
33 addi 8, 8, _mmu_off - 1b
34 mtsrr0 8
[all …]
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| /linux/Documentation/driver-api/media/drivers/ccs/ |
| H A D | ccs-regs.asc | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
[all …]
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| /linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
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| /linux/arch/powerpc/perf/ |
| H A D | hv-gpci-requests.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 #include "req-gen/_begin.h"
22 * - starting_index_kind is one of the following, depending on the event:
24 * hw_chip_id: hardware chip id or -1 for current hw chip
28 * 0xffffffffffffffff: or -1, which means it is irrelavant for the event
43 * - expose secondary index (if any counter ever uses it, only 0xA0
45 * - embed versioning info
46 * - include counter descriptions
49 #define REQUEST_NUM 0x10
52 REQUEST(__count(0, 8, processor_time_in_timebase_cycles)
[all …]
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| /linux/fs/nls/ |
| H A D | nls_ucs2_utils.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 MODULE_DESCRIPTION("NLS UCS-2");
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
31 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
32 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
33 -32, -32, -32, -32, -32, /* 060-06f */
[all …]
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| /linux/drivers/pinctrl/samsung/ |
| H A D | pinctrl-exynos-arm.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
43 #define S5P_PIN_PULL_DISABLE 0
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
[all …]
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| /linux/drivers/media/test-drivers/vicodec/ |
| H A D | codec-fwht.c | 1 // SPDX-License-Identifier: LGPL-2.1+
6 * 8x8 Fast Walsh Hadamard Transform in sequency order based on the paper:
8 * A Recursive Algorithm for Sequency-Ordered Fast Walsh Transforms,
15 #include "codec-fwht.h"
20 * Note: bit 0 of the header must always be 0. Otherwise it cannot
21 * be guaranteed that the magic 8 byte sequence (see below) can
25 #define DUPS_MASK 0x1ffe
27 #define PBLOCK 0
33 0,
34 1, 8,
[all …]
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| /linux/Documentation/gpu/ |
| H A D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
31 * Component 0: R
36 fourcc:modifier pair. In general, component '0' is considered to
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
[all …]
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| /linux/arch/arm64/crypto/ |
| H A D | sha3-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
24 .inst 0xce000000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
28 .inst 0xce608c00 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
32 .inst 0xce200000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
36 .inst 0xce800000 | .L\rd | (.L\rn << 5) | ((\imm6) << 10) | (.L\rm << 16)
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
[all …]
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| /linux/include/sound/ |
| H A D | ump_msg.h | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 UMP_MSG_STATUS_PER_NOTE_RCC = 0x0,
11 UMP_MSG_STATUS_PER_NOTE_ACC = 0x1,
12 UMP_MSG_STATUS_RPN = 0x2,
13 UMP_MSG_STATUS_NRPN = 0x3,
14 UMP_MSG_STATUS_RELATIVE_RPN = 0x4,
15 UMP_MSG_STATUS_RELATIVE_NRPN = 0x5,
16 UMP_MSG_STATUS_PER_NOTE_PITCH_BEND = 0x6,
17 UMP_MSG_STATUS_NOTE_OFF = 0x8,
18 UMP_MSG_STATUS_NOTE_ON = 0x9,
[all …]
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| /linux/arch/arm/crypto/ |
| H A D | aes-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions
12 .arch armv8-a
13 .fpu crypto-neon-fp-armv8
17 aese.8 \state, \key
18 aesmc.8 \state, \state
22 aesd.8 \state, \key
23 aesimc.8 \state, \state
38 aese.8 q0, \key2
44 aesd.8 q0, \key2
[all …]
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| H A D | aes-neonbs-core.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
15 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
67 vtbl.8 \out\()l, {\tbl}, \in\()l
69 vtbl.8 \out\()h, {\tmp}, \in\()h
71 vtbl.8 \out\()h, {\tbl}, \in\()h
77 vldr \out\()h, \sym + 8
262 vld1.8 {\t0-\t1}, [bskey, :256]!
264 vld1.8 {\t2-\t3}, [bskey, :256]!
269 vld1.8 {\t0-\t1}, [bskey, :256]!
[all …]
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| H A D | ghash-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2015 - 2017 Linaro Ltd.
12 .arch armv8-a
13 .fpu crypto-neon-fp-armv8
101 * This implementation of 64x64 -> 128 bit polynomial multiplication
102 * using vmull.p8 instructions (8x8 -> 16) is taken from the paper
105 * Ricardo Dahab (https://hal.inria.fr/hal-01506572)
107 * It has been slightly tweaked for in-order performance, and to allow
111 vext.8 t0l, \ad, \ad, #1 @ A1
113 vext.8 t4l, \bd, \bd, #1 @ B1
[all …]
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| /linux/drivers/mfd/ |
| H A D | mt6360-core.c | 1 // SPDX-License-Identifier: GPL-2.0
20 MT6360_SLAVE_TCPC = 0,
36 #define MT6360_TCPC_SLAVEID 0x4E
37 #define MT6360_PMIC_SLAVEID 0x1A
38 #define MT6360_LDO_SLAVEID 0x64
39 #define MT6360_PMU_SLAVEID 0x34
41 #define MT6360_REG_TCPCSTART 0x00
42 #define MT6360_REG_TCPCEND 0xFF
43 #define MT6360_REG_PMICSTART 0x100
44 #define MT6360_REG_PMICEND 0x13B
[all …]
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| /linux/drivers/media/usb/dvb-usb/ |
| H A D | af9005.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Common header-file of the Linux driver for the Afatech 9005
3 * USB1.1 DVB-T receiver.
9 * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
15 #include "dvb-usb.h"
18 #define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
19 #define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
20 #define deb_rc(args...) dprintk(dvb_usb_af9005_debug,0x04,args)
21 #define deb_reg(args...) dprintk(dvb_usb_af9005_debug,0x08,args)
22 #define deb_i2c(args...) dprintk(dvb_usb_af9005_debug,0x10,args)
[all …]
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| /linux/lib/zlib_inflate/ |
| H A D | inffixed.h | 1 /* inffixed.h -- table for decoding fixed codes
11 {96,7,0},{0,8,80},{0,8,16},{20,8,115},{18,7,31},{0,8,112},{0,8,48},
12 {0,9,192},{16,7,10},{0,8,96},{0,8,32},{0,9,160},{0,8,0},{0,8,128},
13 {0,8,64},{0,9,224},{16,7,6},{0,8,88},{0,8,24},{0,9,144},{19,7,59},
14 {0,8,120},{0,8,56},{0,9,208},{17,7,17},{0,8,104},{0,8,40},{0,9,176},
15 {0,8,8},{0,8,136},{0,8,72},{0,9,240},{16,7,4},{0,8,84},{0,8,20},
16 {21,8,227},{19,7,43},{0,8,116},{0,8,52},{0,9,200},{17,7,13},{0,8,100},
17 {0,8,36},{0,9,168},{0,8,4},{0,8,132},{0,8,68},{0,9,232},{16,7,8},
18 {0,8,92},{0,8,28},{0,9,152},{20,7,83},{0,8,124},{0,8,60},{0,9,216},
19 {18,7,23},{0,8,108},{0,8,44},{0,9,184},{0,8,12},{0,8,140},{0,8,76},
[all …]
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| /linux/arch/arc/include/asm/ |
| H A D | arcregs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
10 #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
11 #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
12 #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
13 #define ARC_REG_CRC_BCR 0x62
14 #define ARC_REG_VECBASE_BCR 0x68
15 #define ARC_REG_PERIBASE_BCR 0x69
16 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
17 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
[all …]
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap3-echo.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
14 compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3";
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
24 reg = <0x80000000 0xc600000>; /* 198 MB */
28 compatible = "regulator-fixed";
29 regulator-name = "vcc5v";
[all …]
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| /linux/tools/perf/arch/x86/tests/ |
| H A D | insn-x86-dat-src.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * "Test x86 instruction decoder - new instructions"
8 * gen-insn-x86-dat.awk script and have the format:
12 * If this file is changed, remember to run the gen-insn-x86-dat.sh
15 * Refer to insn-x86.c for more details.
20 /* Following line is a marker for the awk script - do not change */ in main()
23 /* Test fix for vcvtph2ps in x86-opcode-map.txt */ in main()
29 /* AVX-512: Instructions with the same op codes as Mask Instructions */ in main()
32 asm volatile("cmovno 0x12345678(%rax),%rcx"); in main()
33 asm volatile("cmovno 0x12345678(%rax),%cx"); in main()
[all …]
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| /linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
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| /linux/arch/powerpc/platforms/ps3/ |
| H A D | hvcall.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #define lv1call .long 0x44000022; extsw r3, r3
22 stdu r1, -STACK_FRAME_MIN_SIZE(r1); \
46 std r3, -8(r1); \
47 stdu r1, -STACK_FRAME_MIN_SIZE-8(r1); \
52 addi r1, r1, STACK_FRAME_MIN_SIZE+8; \
53 ld r11, -8(r1); \
54 std r4, 0(r11); \
66 std r3, -8(r1); \
67 std r4, -16(r1); \
[all …]
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| /linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
| H A D | tie.h | 9 * Copyright (C) 1999-2009 Tensilica Inc.
16 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
17 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
18 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
24 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
25 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
28 #define XCHAL_CP0_SA_SIZE 0
30 #define XCHAL_CP2_SA_SIZE 0
32 #define XCHAL_CP3_SA_SIZE 0
34 #define XCHAL_CP4_SA_SIZE 0
[all …]
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| /linux/drivers/pinctrl/mediatek/ |
| H A D | pinctrl-mt8173.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
15 #include "pinctrl-mtk-common.h"
16 #include "pinctrl-mtk-mt8173.h"
18 #define DRV_BASE 0xb00
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
22 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
[all …]
|