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1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
10 #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
11 #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
12 #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
13 #define ARC_REG_CRC_BCR 0x62
14 #define ARC_REG_VECBASE_BCR 0x68
15 #define ARC_REG_PERIBASE_BCR 0x69
16 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
17 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
18 #define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
19 #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
20 #define ARC_REG_SLC_BCR 0xce
21 #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
22 #define ARC_REG_AP_BCR 0x76
23 #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
24 #define ARC_REG_XY_MEM_BCR 0x79
25 #define ARC_REG_MAC_BCR 0x7a
26 #define ARC_REG_MPY_BCR 0x7b
27 #define ARC_REG_SWAP_BCR 0x7c
28 #define ARC_REG_NORM_BCR 0x7d
29 #define ARC_REG_MIXMAX_BCR 0x7e
30 #define ARC_REG_BARREL_BCR 0x7f
31 #define ARC_REG_D_UNCACH_BCR 0x6A
32 #define ARC_REG_BPU_BCR 0xc0
33 #define ARC_REG_ISA_CFG_BCR 0xc1
34 #define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
35 #define ARC_REG_RTT_BCR 0xF2
36 #define ARC_REG_IRQ_BCR 0xF3
37 #define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
38 #define ARC_REG_SMART_BCR 0xFF
39 #define ARC_REG_CLUSTER_BCR 0xcf
40 #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
41 #define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
42 #define ARC_REG_FPU_CTRL 0x300
43 #define ARC_REG_FPU_STATUS 0x301
46 #define ARC_REG_STATUS32 0x0A
63 * ECR: Exception Cause Reg bits-n-pieces
65 * [15: 8] = Exception Cause Code
66 * [ 7: 0] = Exception Parameters (for certain types only)
69 #define ECR_V_MEM_ERR 0x01
70 #define ECR_V_INSN_ERR 0x02
71 #define ECR_V_MACH_CHK 0x20
72 #define ECR_V_ITLB_MISS 0x21
73 #define ECR_V_DTLB_MISS 0x22
74 #define ECR_V_PROTV 0x23
75 #define ECR_V_TRAP 0x25
77 #define ECR_V_MEM_ERR 0x01
78 #define ECR_V_INSN_ERR 0x02
79 #define ECR_V_MACH_CHK 0x03
80 #define ECR_V_ITLB_MISS 0x04
81 #define ECR_V_DTLB_MISS 0x05
82 #define ECR_V_PROTV 0x06
83 #define ECR_V_TRAP 0x09
84 #define ECR_V_MISALIGN 0x0d
89 #define ECR_C_PROTV_INST_FETCH 0x00
90 #define ECR_C_PROTV_LOAD 0x01
91 #define ECR_C_PROTV_STORE 0x02
92 #define ECR_C_PROTV_XCHG 0x03
93 #define ECR_C_PROTV_MISALIG_DATA 0x04
98 #define ECR_C_MCHK_DUP_TLB 0x01
101 #define ECR_C_BIT_DTLB_LD_MISS 8
106 #define AUX_EXEC_CTRL 8
107 #define AUX_INTR_VEC_BASE 0x25
108 #define AUX_VOL 0x5e
112 * Status regs are read-only (build-time) so need not be saved/restored
114 #define ARC_AUX_FP_STAT 0x300
115 #define ARC_AUX_DPFP_1L 0x301
116 #define ARC_AUX_DPFP_1H 0x302
117 #define ARC_AUX_DPFP_2L 0x303
118 #define ARC_AUX_DPFP_2H 0x304
119 #define ARC_AUX_DPFP_STAT 0x305
122 * DSP-related registers
126 #define ARC_AUX_DSP_BUILD 0x7A
127 #define ARC_AUX_ACC0_LO 0x580
128 #define ARC_AUX_ACC0_GLO 0x581
129 #define ARC_AUX_ACC0_HI 0x582
130 #define ARC_AUX_ACC0_GHI 0x583
131 #define ARC_AUX_DSP_BFLY0 0x598
132 #define ARC_AUX_DSP_CTRL 0x59F
133 #define ARC_AUX_DSP_FFT_CTRL 0x59E
135 #define ARC_AUX_AGU_BUILD 0xCC
136 #define ARC_AUX_AGU_AP0 0x5C0
137 #define ARC_AUX_AGU_AP1 0x5C1
138 #define ARC_AUX_AGU_AP2 0x5C2
139 #define ARC_AUX_AGU_AP3 0x5C3
140 #define ARC_AUX_AGU_OS0 0x5D0
141 #define ARC_AUX_AGU_OS1 0x5D1
142 #define ARC_AUX_AGU_MOD0 0x5E0
143 #define ARC_AUX_AGU_MOD1 0x5E1
144 #define ARC_AUX_AGU_MOD2 0x5E2
145 #define ARC_AUX_AGU_MOD3 0x5E3
154 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
164 unsigned int chip_id:16, cpu_id:8, family:8;
166 unsigned int family:8, cpu_id:8, chip_id:16;
173 pad1:12, ver:8;
175 unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
182 unsigned int pad:8, prod:8, maj:8, min:8;
184 unsigned int min:8, maj:8, prod:8, pad:8;
190 unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
194 ways:4, ver:8;
200 unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
205 pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
211 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
213 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
227 unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
229 unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
243 unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
245 unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
251 unsigned int base:16, pad:5, sz:3, ver:8;
253 unsigned int ver:8, sz:3, pad:5, base:16;
259 unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
261 unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
267 unsigned int res:21, sz:3, ver:8;
269 unsigned int ver:8, sz:3, res:21;
275 unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
277 unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
284 unsigned int fast:1, ver:8;
286 unsigned int ver:8, fast:1;
292 unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
294 unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
300 unsigned int pad:21, min:1, num:2, ver:8;
302 unsigned int ver:8, num:2, min:1, pad:21;
310 unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
312 unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
318 unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
320 unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
327 unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
329 unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
344 unsigned int pad:16, entries:8, ver:8;
346 unsigned int ver:8, entries:8, pad:16;
352 unsigned int info:24, ver:8;
354 unsigned int ver:8, info:24;