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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/drivers/staging/media/atomisp/pci/
H A Dsh_css_params.c1 // SPDX-License-Identifier: GPL-2.0
50 #include "anr/anr_1.0/ia_css_anr.host.h"
51 #include "cnr/cnr_1.0/ia_css_cnr.host.h"
52 #include "csc/csc_1.0/ia_css_csc.host.h"
53 #include "de/de_1.0/ia_css_de.host.h"
54 #include "dp/dp_1.0/ia_css_dp.host.h"
55 #include "bnr/bnr_1.0/ia_css_bnr.host.h"
56 #include "dvs/dvs_1.0/ia_css_dvs.host.h"
57 #include "fpn/fpn_1.0/ia_css_fpn.host.h"
58 #include "gc/gc_1.0/ia_css_gc.host.h"
[all …]
/linux/drivers/media/usb/gspca/
H A Dsn9c2028.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 unsigned char to_read; /* length to read. 0 means no reply requested */
44 .sizeimage = 640 * 480 * 3 / 4,
46 .priv = 0},
53 .sizeimage = 352 * 288 * 3 / 4,
55 .priv = 0},
58 /* the bytes to write are in gspca_dev->usb_buf */
64 command[0], command[1], command[2], in sn9c2028_command()
65 command[3], command[4], command[5]); in sn9c2028_command()
67 memcpy(gspca_dev->usb_buf, command, 6); in sn9c2028_command()
[all …]
/linux/include/sound/
H A Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /* MIDI 1.0 / 2.0 Status Code (4bit) */
10 UMP_MSG_STATUS_PER_NOTE_RCC = 0x0,
11 UMP_MSG_STATUS_PER_NOTE_ACC = 0x1,
12 UMP_MSG_STATUS_RPN = 0x2,
13 UMP_MSG_STATUS_NRPN = 0x3,
14 UMP_MSG_STATUS_RELATIVE_RPN = 0x4,
15 UMP_MSG_STATUS_RELATIVE_NRPN = 0x5,
16 UMP_MSG_STATUS_PER_NOTE_PITCH_BEND = 0x6,
17 UMP_MSG_STATUS_NOTE_OFF = 0x8,
[all …]
/linux/arch/arc/include/asm/
H A Duaccess.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -__clear_user( ) called multiple times during elf load was byte loop
10 * -Hand crafted constant propagation for "constant" copy sizes
11 * -stock kernel shrunk by 33K at -O3
14 * -Added option to (UN)inline copy_(to|from)_user to reduce code sz
15 * -kernel shrunk by 200K even at -O3 (gcc 4.2.1)
16 * -Enabled when doing -Os
30 long __ret = 0; /* success by default */ \
34 case 4: __arc_get_user_one(*(k), u, "ld", __ret); break; \
[all …]
/linux/drivers/ata/pata_parport/
H A Dkbic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * (c) 1997-1998 Grant R. Guenther <grant@torque.net>
5 * This is a low-level driver for the KBIC-951A and KBIC-971A
23 #define r12w() (delay_p, inw(pi->port + 1) & 0xffff)
25 #define j44(a, b) ((((a >> 4) & 0x0f) | (b & 0xf0)) ^ 0x88)
26 #define j53(w) (((w >> 3) & 0x1f) | ((w >> 4) & 0xe0))
30 * cont = 0 - access the IDE register file
31 * cont = 1 - access the IDE command set
33 static int cont_map[2] = { 0x80, 0x40 };
41 switch (pi->mode) { in kbic_read_regr()
[all …]
/linux/sound/soc/codecs/
H A Drt1318.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt1318.h -- Platform data for RT1318
36 #define RT1318_PLL_N_MAX 0x1ff
37 #define RT1318_PLL_K_MAX 0x1f
38 #define RT1318_PLL_M_MAX 0x1f
47 #define RT1318_CLK1 0xc001
48 #define RT1318_CLK2 0xc003
49 #define RT1318_CLK3 0xc004
50 #define RT1318_CLK4 0xc005
51 #define RT1318_CLK5 0xc006
[all …]
H A Dpcm512x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define PCM512x_VIRT_BASE 0x100
16 #define PCM512x_PAGE_LEN 0x100
19 #define PCM512x_PAGE 0
21 #define PCM512x_RESET (PCM512x_PAGE_BASE(0) + 1)
22 #define PCM512x_POWER (PCM512x_PAGE_BASE(0) + 2)
23 #define PCM512x_MUTE (PCM512x_PAGE_BASE(0) + 3)
24 #define PCM512x_PLL_EN (PCM512x_PAGE_BASE(0) + 4)
25 #define PCM512x_SPI_MISO_FUNCTION (PCM512x_PAGE_BASE(0) + 6)
26 #define PCM512x_DSP (PCM512x_PAGE_BASE(0) + 7)
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-evm-gesi-exp-board.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/net/ti-dp83867.h>
17 #include "k3-pinctrl.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
24 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsamsung-sxgbe.txt4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Length.
16 Supported values are 1, 2, 4, 8, 16, or 32.
17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
19 Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled.
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
38 /* The rest of these are firmware-defined */
39 #define MC_SMEM_P0_PDU_OFST 0x008
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/linux/drivers/video/fbdev/riva/
H A Driva_tbl.h3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
38 /* The rest of these are firmware-defined */
39 #define MC_SMEM_P0_PDU_OFST 0x008
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt8112-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 reg = <0x100 4>;
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 reg = <0x108 4>;
[all …]
H A Ds8001-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
11 reg = <0x80000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
20 reg = <0x80008 4>;
[all …]
H A Dt8011-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
11 reg = <0x80000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
20 reg = <0x80008 4>;
[all …]
/linux/arch/x86/lib/
H A Dmemmove_32.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 * -mregparm=3 passes these in registers:
31 * Save all callee-saved registers, because this function is going to clobber
46 cmpl $0x10, n
62 andl $0xff, tmp0
65 subl $0x10, n
69 subl $0x10, n
70 movl 0*4(src), tmp0
71 movl 1*4(src), tmp1
72 movl tmp0, 0*4(dest)
[all …]
/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.c24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
48 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f); in carl9170_init_power_cal()
49 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f); in carl9170_init_power_cal()
50 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f); in carl9170_init_power_cal()
51 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f); in carl9170_init_power_cal()
52 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f); in carl9170_init_power_cal()
53 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f); in carl9170_init_power_cal()
54 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f); in carl9170_init_power_cal()
55 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f); in carl9170_init_power_cal()
56 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f); in carl9170_init_power_cal()
[all …]
/linux/arch/arm64/kernel/vdso/
H A Dvgetrandom-chacha.S1 // SPDX-License-Identifier: GPL-2.0
27 * number of blocks of output with nonce 0, taking an input key and 8-bytes
30 * This implementation avoids d8-d15 because they are callee-save in user
39 * x1: 32-byte key input
40 * x2: 8-byte counter input/output
41 * x3: number of 64-byte block to write to output
45 /* copy0 = "expand 32-byte k" */
46 mov_q x8, 0x3320646e61707865
47 mov_q x9, 0x6b20657479622d32
48 mov copy0.d[0], x8
[all …]
/linux/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
17 #include <asm/gpr-num.h>
23 * [20-19] : Op0
24 * [18-16] : Op1
25 * [15-12] : CRn
26 * [11-8] : CRm
27 * [7-5] : Op2
30 #define Op0_mask 0x3
32 #define Op1_mask 0x7
[all …]
/linux/include/dt-bindings/pinctrl/
H A Dpads-imx8qxp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #define IMX8QXP_PCIE_CTRL0_PERST_B 0
15 #define IMX8QXP_USB_SS3_TC0 4
189 … IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QXP_PCIE_CTRL0_PERST_B 0
190 … IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4
191 … IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QXP_PCIE_CTRL0_CLKREQ_B 0
192 … IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4
193 … IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QXP_PCIE_CTRL0_WAKE_B 0
194 … IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4
195 … IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC0 0
[all …]
H A Dpads-imx8dxl.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 #define IMX8DXL_PCIE_CTRL0_PERST_B 0
14 #define IMX8DXL_USB_SS3_TC0 4
148 … IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8DXL_PCIE_CTRL0_PERST_B 0
149 … IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4
151 … IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8DXL_PCIE_CTRL0_CLKREQ_B 0
152 … IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4
154 … IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8DXL_PCIE_CTRL0_WAKE_B 0
155 … IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4
157 … IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC0 0
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dinitvals_phy.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * (c) Copyright 2002-2010, Ralink Technology, Inc.
14 /* Bank 0 - for central blocks: BG, PLL, XTAL, LO, ADC/DAC */
15 RF_REG_PAIR(0, 0, 0x02),
16 RF_REG_PAIR(0, 1, 0x01),
17 RF_REG_PAIR(0, 2, 0x11),
18 RF_REG_PAIR(0, 3, 0xff),
19 RF_REG_PAIR(0, 4, 0x0a),
20 RF_REG_PAIR(0, 5, 0x20),
21 RF_REG_PAIR(0, 6, 0x00),
[all …]

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