Lines Matching +full:0 +full:- +full:4
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
38 /* The rest of these are firmware-defined */
39 #define MC_SMEM_P0_PDU_OFST 0x008
40 #define MC_SMEM_P1_PDU_OFST 0x108
41 #define MC_SMEM_PDU_LEN 0x100
42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43 #define MC_SMEM_P0_STATUS_OFST 0x7f8
44 #define MC_SMEM_P1_STATUS_OFST 0x7fc
46 /* Values to be written to the per-port status dword in shared
48 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
52 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
57 * least every driver must support version 0 and MCDI_PCOL_VERSION
61 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
68 * 0 7 8 16 20 22 23 24 31
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
94 #define MCDI_HEADER_OFST 0
95 #define MCDI_HEADER_CODE_LBN 0
102 #define MCDI_HEADER_SEQ_WIDTH 4
114 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
116 #define MCDI_HEADER_XFLAGS_DBRET 0x02
119 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
120 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
132 * 0 32 33 36 44 52 60
139 * - LEVEL==INFO Command succeeded
140 * - LEVEL==ERR Command failed
142 * 0 8 16 24 32
146 * LEVEL==ERR, Datalen == 0 => Reboot
150 * examining the first byte which is 0xc0. This corresponds to the
151 * non-existent MCDI command MC_CMD_DEBUG_LOG.
153 * 0 7 8
154 * | command | Resync | = 0xc0
156 * Since the event is written in big-endian byte order, this works
157 * providing bits 56-63 of the event are 0xc0.
160 * | Rsvd | Code | = 0xc0
162 * Which means for convenience the event code is 0xc for all MC
165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
170 /* Non-existent command target */
173 #define MC_CMD_ERR_EINTR 4
192 /* Read-only */
196 /* Non-recursive resource is already acquired */
216 #define MC_CMD_ERR_ALLOC_FAIL 0x1000
217 /* V-adaptor not found. */
218 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
220 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
221 /* V-switch not found. */
222 #define MC_CMD_ERR_NO_VSWITCH 0x1003
224 #define MC_CMD_ERR_VLAN_LIMIT 0x1004
226 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
228 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
229 /* Invalid v-switch type. */
230 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
231 /* Invalid v-port type. */
232 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
234 #define MC_CMD_ERR_MAC_EXIST 0x1009
236 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
238 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
240 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
245 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
247 #define MC_CMD_ERR_VLAN_EXIST 0x100e
249 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
253 * This error code is followed by a 32-bit handle that
255 #define MC_CMD_ERR_PROXY_PENDING 0x1010
256 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
260 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
264 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
266 * an operation failed due to lack of SR-IOV privilege.
271 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
275 * May also returned for other operations such as sub-variant switching. */
276 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
279 #define MC_CMD_ERR_NO_CLOCK 0x1015
282 #define MC_CMD_ERR_UNREACHABLE 0x1016
285 #define MC_CMD_ERR_QUEUE_FULL 0x1017
289 #define MC_CMD_ERR_NO_PCIE 0x1018
293 #define MC_CMD_ERR_NO_DATAPATH 0x1019
295 #define MC_CMD_ERR_VIS_PRESENT 0x101a
297 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
299 #define MC_CMD_ERR_CODE_OFST 0
304 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
305 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
306 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
307 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
308 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
309 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
310 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
311 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
315 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
316 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
317 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
319 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
320 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
321 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
323 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
324 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
325 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
328 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
336 0, 0, 0 }
356 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
357 * stack ID (which must be in the range 1-255) along with an EVB port ID.
359 #define EVB_STACK_ID(n) (((n) & 0xff) << 16)
363 * may be followed by the (0-based) number of the first argument that
366 #define MC_CMD_ERR_ARG_OFST 4
378 #define MCDI_EVENT_LEVEL_INFO 0x0
380 #define MCDI_EVENT_LEVEL_WARN 0x1
382 #define MCDI_EVENT_LEVEL_ERR 0x2
384 #define MCDI_EVENT_LEVEL_FATAL 0x3
385 #define MCDI_EVENT_DATA_OFST 0
386 #define MCDI_EVENT_DATA_LEN 4
387 #define MCDI_EVENT_CMDDONE_SEQ_OFST 0
388 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
390 #define MCDI_EVENT_CMDDONE_DATALEN_OFST 0
393 #define MCDI_EVENT_CMDDONE_ERRNO_OFST 0
396 #define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
397 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
399 #define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
401 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
403 #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
405 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
407 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
409 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
411 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
413 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
415 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
417 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
418 #define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
420 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
421 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
424 #define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
425 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
427 #define MCDI_EVENT_SENSOREVT_STATE_OFST 0
430 #define MCDI_EVENT_SENSOREVT_VALUE_OFST 0
433 #define MCDI_EVENT_FWALERT_DATA_OFST 0
436 #define MCDI_EVENT_FWALERT_REASON_OFST 0
437 #define MCDI_EVENT_FWALERT_REASON_LBN 0
440 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
441 #define MCDI_EVENT_FLR_VF_OFST 0
442 #define MCDI_EVENT_FLR_VF_LBN 0
444 #define MCDI_EVENT_TX_ERR_TXQ_OFST 0
445 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
447 #define MCDI_EVENT_TX_ERR_TYPE_OFST 0
449 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
451 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
453 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2
455 #define MCDI_EVENT_TX_ERR_2BIG 0x3
457 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5
459 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8
461 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
462 #define MCDI_EVENT_TX_ERR_INFO_OFST 0
465 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
468 #define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
469 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
471 #define MCDI_EVENT_PTP_ERR_TYPE_OFST 0
472 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
475 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
477 #define MCDI_EVENT_PTP_ERR_FILTER 0x2
479 #define MCDI_EVENT_PTP_ERR_FIFO 0x3
481 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4
482 #define MCDI_EVENT_AOE_ERR_TYPE_OFST 0
483 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
485 /* enum: AOE failed to load - no valid image? */
486 #define MCDI_EVENT_AOE_NO_LOAD 0x1
488 #define MCDI_EVENT_AOE_FC_ASSERT 0x2
490 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
492 #define MCDI_EVENT_AOE_FC_NO_START 0x4
493 /* enum: Generic AOE fault - likely to have been reported via other means too
496 #define MCDI_EVENT_AOE_FAULT 0x5
498 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
500 #define MCDI_EVENT_AOE_LOAD 0x7
502 #define MCDI_EVENT_AOE_DMA 0x8
506 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9
508 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
510 #define MCDI_EVENT_AOE_PTP_STATUS 0xb
512 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
514 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
516 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
518 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
520 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
522 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
523 /* enum: FPGA boot-flash contains an invalid image header */
524 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
526 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
528 #define MCDI_EVENT_AOE_FC_RUNNING 0x14
529 #define MCDI_EVENT_AOE_ERR_DATA_OFST 0
532 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
536 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
539 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
540 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
544 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
546 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
548 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
550 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
552 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
554 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
556 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
558 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
560 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
561 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
565 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
567 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
568 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
571 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
574 #define MCDI_EVENT_RX_ERR_RXQ_OFST 0
575 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0
577 #define MCDI_EVENT_RX_ERR_TYPE_OFST 0
579 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
580 #define MCDI_EVENT_RX_ERR_INFO_OFST 0
583 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
586 #define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
587 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
589 #define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
590 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
592 #define MCDI_EVENT_MUM_ERR_TYPE_OFST 0
593 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
595 /* enum: MUM failed to load - no valid image? */
596 #define MCDI_EVENT_MUM_NO_LOAD 0x1
598 #define MCDI_EVENT_MUM_ASSERT 0x2
600 #define MCDI_EVENT_MUM_WATCHDOG 0x3
601 #define MCDI_EVENT_MUM_ERR_DATA_OFST 0
604 #define MCDI_EVENT_DBRET_SEQ_OFST 0
605 #define MCDI_EVENT_DBRET_SEQ_LBN 0
607 #define MCDI_EVENT_SUC_ERR_TYPE_OFST 0
608 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
611 #define MCDI_EVENT_SUC_BAD_APP 0x1
613 #define MCDI_EVENT_SUC_ASSERT 0x2
615 #define MCDI_EVENT_SUC_EXCEPTION 0x3
617 #define MCDI_EVENT_SUC_WATCHDOG 0x4
618 #define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
621 #define MCDI_EVENT_SUC_ERR_DATA_OFST 0
624 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
625 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
627 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
629 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
632 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
635 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
640 #define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
641 #define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
643 #define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
646 #define MCDI_EVENT_DATA_LBN 0
661 #define MCDI_EVENT_EV_CODE_WIDTH 4
665 #define MCDI_EVENT_SW_EVENT 0x0
667 #define MCDI_EVENT_CODE_BADSSERT 0x1
669 #define MCDI_EVENT_CODE_PMNOTICE 0x2
671 #define MCDI_EVENT_CODE_CMDDONE 0x3
673 #define MCDI_EVENT_CODE_LINKCHANGE 0x4
675 #define MCDI_EVENT_CODE_SENSOREVT 0x5
677 #define MCDI_EVENT_CODE_SCHEDERR 0x6
679 #define MCDI_EVENT_CODE_REBOOT 0x7
681 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
683 #define MCDI_EVENT_CODE_FWALERT 0x9
685 #define MCDI_EVENT_CODE_FLR 0xa
687 #define MCDI_EVENT_CODE_TX_ERR 0xb
689 #define MCDI_EVENT_CODE_TX_FLUSH 0xc
691 #define MCDI_EVENT_CODE_PTP_RX 0xd
693 #define MCDI_EVENT_CODE_PTP_FAULT 0xe
695 #define MCDI_EVENT_CODE_PTP_PPS 0xf
697 #define MCDI_EVENT_CODE_RX_FLUSH 0x10
699 #define MCDI_EVENT_CODE_RX_ERR 0x11
701 #define MCDI_EVENT_CODE_AOE 0x12
703 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13
705 #define MCDI_EVENT_CODE_HW_PPS 0x14
709 #define MCDI_EVENT_CODE_MC_REBOOT 0x15
711 #define MCDI_EVENT_CODE_PAR_ERR 0x16
713 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
715 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
717 #define MCDI_EVENT_CODE_MC_BIST 0x19
719 #define MCDI_EVENT_CODE_PTP_TIME 0x1a
721 #define MCDI_EVENT_CODE_MUM 0x1b
723 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
727 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
731 #define MCDI_EVENT_CODE_DBRET 0x1e
733 #define MCDI_EVENT_CODE_SUC 0x1f
737 #define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
742 #define MCDI_EVENT_CODE_MODULECHANGE 0x21
748 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
754 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
759 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
761 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
764 * SF-122927-TC for details.
766 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
770 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
771 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
773 * SF-122927-TC for details.
775 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
779 #define MCDI_EVENT_CODE_TESTGEN 0xfa
780 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
781 #define MCDI_EVENT_CMDDONE_DATA_LEN 4
782 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
784 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
785 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
786 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
788 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
789 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4
790 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
792 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
793 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
794 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
796 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
797 #define MCDI_EVENT_TX_ERR_DATA_LEN 4
798 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
803 #define MCDI_EVENT_PTP_SECONDS_OFST 0
804 #define MCDI_EVENT_PTP_SECONDS_LEN 4
805 #define MCDI_EVENT_PTP_SECONDS_LBN 0
810 #define MCDI_EVENT_PTP_MAJOR_OFST 0
811 #define MCDI_EVENT_PTP_MAJOR_LEN 4
812 #define MCDI_EVENT_PTP_MAJOR_LBN 0
817 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
818 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
819 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
824 #define MCDI_EVENT_PTP_MINOR_OFST 0
825 #define MCDI_EVENT_PTP_MINOR_LEN 4
826 #define MCDI_EVENT_PTP_MINOR_LBN 0
830 #define MCDI_EVENT_PTP_UUID_OFST 0
831 #define MCDI_EVENT_PTP_UUID_LEN 4
832 #define MCDI_EVENT_PTP_UUID_LBN 0
834 #define MCDI_EVENT_RX_ERR_DATA_OFST 0
835 #define MCDI_EVENT_RX_ERR_DATA_LEN 4
836 #define MCDI_EVENT_RX_ERR_DATA_LBN 0
838 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0
839 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4
840 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0
842 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
843 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
844 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
846 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
847 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
848 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
851 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
852 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
853 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
855 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
873 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
883 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
884 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
885 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
887 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
888 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
889 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
892 * should resend it. A non-zero value means that the authorization has been
897 #define MCDI_EVENT_DBRET_DATA_OFST 0
898 #define MCDI_EVENT_DBRET_DATA_LEN 4
899 #define MCDI_EVENT_DBRET_DATA_LBN 0
901 #define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
902 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
903 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
905 #define MCDI_EVENT_MODULECHANGE_DATA_OFST 0
906 #define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
907 #define MCDI_EVENT_MODULECHANGE_DATA_LBN 0
910 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
911 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
912 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
915 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
916 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
917 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
920 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
921 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
922 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
927 #define MCDI_EVENT_DESC_PROXY_DATA_OFST 0
928 #define MCDI_EVENT_DESC_PROXY_DATA_LEN 4
929 #define MCDI_EVENT_DESC_PROXY_DATA_LBN 0
932 #define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
933 #define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
934 #define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
937 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
939 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
940 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
941 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
951 #define FCDI_EVENT_LEVEL_INFO 0x0
953 #define FCDI_EVENT_LEVEL_WARN 0x1
955 #define FCDI_EVENT_LEVEL_ERR 0x2
957 #define FCDI_EVENT_LEVEL_FATAL 0x3
958 #define FCDI_EVENT_DATA_OFST 0
959 #define FCDI_EVENT_DATA_LEN 4
960 #define FCDI_EVENT_LINK_STATE_STATUS_OFST 0
961 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
963 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
964 #define FCDI_EVENT_LINK_UP 0x1 /* enum */
965 #define FCDI_EVENT_DATA_LBN 0
970 #define FCDI_EVENT_EV_CODE_WIDTH 4
974 #define FCDI_EVENT_CODE_REBOOT 0x1
976 #define FCDI_EVENT_CODE_ASSERT 0x2
978 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
980 #define FCDI_EVENT_CODE_LINK_STATE 0x4
982 #define FCDI_EVENT_CODE_TIMED_READ 0x5
984 #define FCDI_EVENT_CODE_PPS_IN 0x6
986 #define FCDI_EVENT_CODE_PTP_TICK 0x7
988 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
990 #define FCDI_EVENT_CODE_PTP_STATUS 0x9
991 /* enum: Port id config to map MC-FC port idx */
992 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa
994 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb
997 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
998 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
999 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
1000 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
1001 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
1007 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
1008 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
1009 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
1011 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0
1012 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4
1013 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0
1015 #define FCDI_EVENT_PTP_STATE_OFST 0
1016 #define FCDI_EVENT_PTP_STATE_LEN 4
1017 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
1018 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
1019 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
1020 #define FCDI_EVENT_PTP_STATE_LBN 0
1024 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
1025 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
1026 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
1032 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
1033 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
1034 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
1036 #define FCDI_EVENT_BOOT_RESULT_OFST 0
1037 #define FCDI_EVENT_BOOT_RESULT_LEN 4
1040 #define FCDI_EVENT_BOOT_RESULT_LBN 0
1045 * such that bits 32-63 containing | event code, level, source etc remain the
1053 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
1055 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
1056 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
1057 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
1061 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
1066 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
1087 #define MUM_EVENT_LEVEL_INFO 0x0
1089 #define MUM_EVENT_LEVEL_WARN 0x1
1091 #define MUM_EVENT_LEVEL_ERR 0x2
1093 #define MUM_EVENT_LEVEL_FATAL 0x3
1094 #define MUM_EVENT_DATA_OFST 0
1095 #define MUM_EVENT_DATA_LEN 4
1096 #define MUM_EVENT_SENSOR_ID_OFST 0
1097 #define MUM_EVENT_SENSOR_ID_LBN 0
1101 #define MUM_EVENT_SENSOR_STATE_OFST 0
1104 #define MUM_EVENT_PORT_PHY_READY_OFST 0
1105 #define MUM_EVENT_PORT_PHY_READY_LBN 0
1107 #define MUM_EVENT_PORT_PHY_LINK_UP_OFST 0
1110 #define MUM_EVENT_PORT_PHY_TX_LOL_OFST 0
1113 #define MUM_EVENT_PORT_PHY_RX_LOL_OFST 0
1116 #define MUM_EVENT_PORT_PHY_TX_LOS_OFST 0
1117 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
1119 #define MUM_EVENT_PORT_PHY_RX_LOS_OFST 0
1122 #define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0
1125 #define MUM_EVENT_DATA_LBN 0
1130 #define MUM_EVENT_EV_CODE_WIDTH 4
1134 #define MUM_EVENT_CODE_REBOOT 0x1
1136 #define MUM_EVENT_CODE_ASSERT 0x2
1138 #define MUM_EVENT_CODE_SENSOR 0x3
1140 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
1141 #define MUM_EVENT_SENSOR_DATA_OFST 0
1142 #define MUM_EVENT_SENSOR_DATA_LEN 4
1143 #define MUM_EVENT_SENSOR_DATA_LBN 0
1145 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0
1146 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4
1147 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0
1149 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
1150 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
1151 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
1153 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0
1154 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4
1155 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0
1157 #define MUM_EVENT_PORT_PHY_TECH_OFST 0
1158 #define MUM_EVENT_PORT_PHY_TECH_LEN 4
1159 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
1160 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
1161 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
1162 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
1163 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
1164 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
1165 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
1166 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
1167 #define MUM_EVENT_PORT_PHY_TECH_LBN 0
1170 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1171 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1172 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1173 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1174 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1175 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1177 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1182 * Read multiple 32byte words from MC memory. Note - this command really
1186 #define MC_CMD_READ32 0x1
1193 #define MC_CMD_READ32_IN_ADDR_OFST 0
1194 #define MC_CMD_READ32_IN_ADDR_LEN 4
1195 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1196 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1199 #define MC_CMD_READ32_OUT_LENMIN 4
1202 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1203 #define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1204 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
1205 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
1215 #define MC_CMD_WRITE32 0x2
1224 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1225 #define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
1226 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
1227 #define MC_CMD_WRITE32_IN_ADDR_LEN 4
1228 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1229 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1235 #define MC_CMD_WRITE32_OUT_LEN 0
1240 * Copy MC code between two locations and jump. Note - this command really
1244 #define MC_CMD_COPYCODE 0x3
1257 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1258 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
1260 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1264 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
1269 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
1270 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0
1273 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0
1276 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0
1279 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0
1280 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
1282 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0
1285 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0
1289 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
1290 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
1292 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
1295 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4
1297 #define MC_CMD_COPYCODE_JUMP_NONE 0x1
1300 #define MC_CMD_COPYCODE_OUT_LEN 0
1305 * Select function for function-specific commands.
1307 #define MC_CMD_SET_FUNC 0x4
1313 #define MC_CMD_SET_FUNC_IN_LEN 4
1315 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
1316 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4
1319 #define MC_CMD_SET_FUNC_OUT_LEN 0
1326 #define MC_CMD_GET_BOOT_STATUS 0x5
1332 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1337 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1338 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
1340 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1341 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1342 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1343 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
1344 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1346 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
1349 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
1360 #define MC_CMD_GET_ASSERTS 0x6
1366 #define MC_CMD_GET_ASSERTS_IN_LEN 4
1368 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1369 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
1374 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1375 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
1377 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1378 /* enum: A system-level assertion has failed. */
1379 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1380 /* enum: A thread-level assertion has failed. */
1381 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1383 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1385 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1387 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1388 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
1391 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1396 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1399 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
1401 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
1408 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
1409 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
1411 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
1412 /* enum: A system-level assertion has failed. */
1413 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
1414 /* enum: A thread-level assertion has failed. */
1415 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
1417 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
1419 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
1421 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
1422 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
1425 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
1430 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
1433 #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
1435 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
1438 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
1446 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
1447 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
1449 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
1450 /* enum: A system-level assertion has failed. */
1451 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
1452 /* enum: A thread-level assertion has failed. */
1453 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
1455 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
1457 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
1459 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
1460 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
1463 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
1468 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
1471 #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
1473 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
1476 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
1478 /* MC firmware unique build ID (as binary SHA-1 value) */
1493 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
1494 /* MC firmware extra version info (as null-terminated US-ASCII string) */
1497 /* MC firmware build name (as null-terminated US-ASCII string) */
1507 #define MC_CMD_LOG_CTRL 0x7
1515 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
1516 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
1518 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
1520 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
1522 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
1523 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
1526 #define MC_CMD_LOG_CTRL_OUT_LEN 0
1533 #define MC_CMD_GET_VERSION 0x8
1539 #define MC_CMD_GET_VERSION_IN_LEN 0
1542 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4
1543 /* placeholder, set to 0 */
1544 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
1545 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
1548 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
1549 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
1550 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
1552 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
1554 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
1556 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
1558 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
1562 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1563 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1566 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
1567 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
1578 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1579 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1582 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
1583 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
1602 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1603 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1606 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
1607 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
1620 #define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
1622 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
1634 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
1636 /* MC firmware unique build ID (as binary SHA-1 value) */
1641 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
1642 /* MC firmware build name (as null-terminated US-ASCII string) */
1645 /* The SUC firmware version as four numbers - a.b.c.d */
1647 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
1648 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
1649 /* SUC firmware build date (as 64-bit Unix timestamp) */
1655 * indicates family, memory sizes etc. See SF-116728-SW for further details.
1658 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
1659 /* The CMC firmware version as four numbers - a.b.c.d */
1661 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
1662 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
1663 /* CMC firmware build date (as 64-bit Unix timestamp) */
1670 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
1671 * => B, ...) FPGA_VERSION[2]: Sub-revision number
1674 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
1676 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
1679 /* Board name / adapter model (as null-terminated US-ASCII string) */
1684 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
1685 /* Board serial number (as null-terminated US-ASCII string) */
1694 #define MC_CMD_PTP 0xb
1702 #define MC_CMD_PTP_IN_OP_OFST 0
1705 #define MC_CMD_PTP_OP_ENABLE 0x1
1707 #define MC_CMD_PTP_OP_DISABLE 0x2
1712 #define MC_CMD_PTP_OP_TRANSMIT 0x3
1714 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
1718 #define MC_CMD_PTP_OP_STATUS 0x5
1720 #define MC_CMD_PTP_OP_ADJUST 0x6
1722 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
1724 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
1726 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
1728 #define MC_CMD_PTP_OP_RESET_STATS 0xa
1730 #define MC_CMD_PTP_OP_DEBUG 0xb
1732 #define MC_CMD_PTP_OP_FPGAREAD 0xc
1734 #define MC_CMD_PTP_OP_FPGAWRITE 0xd
1736 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
1738 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
1742 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
1746 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
1750 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
1754 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
1756 #define MC_CMD_PTP_OP_RST_CLK 0x14
1758 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15
1760 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
1761 /* enum: Get the clock attributes. NOTE- extended version of
1764 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
1768 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
1772 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
1774 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
1778 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
1782 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
1784 #define MC_CMD_PTP_OP_MAX 0x1c
1788 #define MC_CMD_PTP_IN_CMD_OFST 0
1789 #define MC_CMD_PTP_IN_CMD_LEN 4
1790 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
1791 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
1792 /* Not used. Events are always sent to function relative queue 0. */
1794 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
1797 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
1799 #define MC_CMD_PTP_MODE_V1 0x0
1800 /* enum: PTP, version 1, with VLAN headers - deprecated */
1801 #define MC_CMD_PTP_MODE_V1_VLAN 0x1
1803 #define MC_CMD_PTP_MODE_V2 0x2
1804 /* enum: PTP, version 2, with VLAN headers - deprecated */
1805 #define MC_CMD_PTP_MODE_V2_VLAN 0x3
1807 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
1809 #define MC_CMD_PTP_MODE_FCOE 0x5
1813 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1814 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1815 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1816 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1823 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
1824 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1825 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1826 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1827 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1830 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
1840 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1841 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1842 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1843 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1847 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1848 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1849 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1850 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1854 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1855 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1856 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1857 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1861 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1862 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1863 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1864 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1871 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28
1876 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
1879 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
1882 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
1885 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
1888 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
1892 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1893 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1894 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1895 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1902 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
1907 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
1910 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
1913 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
1916 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
1919 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
1922 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
1926 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1927 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1928 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1929 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1932 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
1943 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1944 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1945 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1946 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1950 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1951 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1952 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1953 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1956 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
1960 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1961 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1962 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1963 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1967 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1968 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1969 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1970 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1973 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
1977 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1978 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1979 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1980 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1982 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
1984 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
1991 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
1992 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1993 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1994 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1995 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1997 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
2006 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2007 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2008 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2009 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2012 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
2015 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
2018 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
2021 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
2025 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2026 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2027 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2028 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2031 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
2034 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
2037 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
2040 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
2043 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
2047 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2048 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2049 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2050 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2061 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2062 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2063 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2064 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2065 /* Number of VLAN tags, 0 if not VLAN */
2067 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
2070 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
2075 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2076 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2077 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2078 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2079 /* 1 to enable UUID filtering, 0 to disable */
2081 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
2090 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2091 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2092 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2093 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2094 /* 1 to enable Domain filtering, 0 to disable */
2096 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
2099 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
2103 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2104 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2105 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2106 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2109 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
2111 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
2113 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
2117 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2118 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2119 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2120 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2124 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2125 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2127 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
2128 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
2130 #define MC_CMD_PTP_ENABLE_PPS 0x0
2132 #define MC_CMD_PTP_DISABLE_PPS 0x1
2133 /* Not used. Events are always sent to function relative queue 0. */
2135 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
2139 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2140 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2141 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2142 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2146 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2147 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2148 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2149 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2153 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2154 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2155 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2156 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2160 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2161 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2162 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2163 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2166 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
2168 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
2176 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2177 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2178 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2179 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2182 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
2184 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
2186 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
2189 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
2193 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2194 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2195 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2196 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2197 /* 1 to enable PPS test mode, 0 to disable and return result. */
2199 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
2203 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2204 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2205 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2206 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2207 /* NIC - Host System Clock Synchronization status */
2209 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
2211 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
2213 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
2218 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
2220 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
2222 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
2225 #define MC_CMD_PTP_OUT_LEN 0
2230 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
2231 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
2233 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
2234 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
2236 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
2237 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
2239 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
2240 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
2243 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
2246 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
2251 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
2252 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
2254 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
2255 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
2257 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
2258 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
2260 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
2261 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
2266 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
2267 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
2269 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
2270 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
2272 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
2273 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
2275 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
2276 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
2279 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
2284 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
2285 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
2287 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
2288 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
2291 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
2294 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
2297 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
2300 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
2303 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
2306 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
2309 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
2312 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
2315 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
2318 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
2321 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
2324 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
2327 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
2330 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
2336 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
2337 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
2339 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
2345 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
2346 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
2348 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
2349 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
2351 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
2352 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
2355 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
2358 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
2361 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
2364 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
2369 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
2370 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
2372 #define MC_CMD_PTP_MANF_SUCCESS 0x0
2374 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
2376 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
2378 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
2380 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4
2382 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
2384 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
2386 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
2388 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
2390 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
2392 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
2394 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
2396 #define MC_CMD_PTP_MANF_PPS_NS 0xc
2398 #define MC_CMD_PTP_MANF_REGISTERS 0xd
2400 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe
2402 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
2403 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
2408 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
2409 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
2411 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
2412 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
2415 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
2421 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2422 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
2423 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
2430 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
2434 * be assumed. Note this enum is deprecated. Do not add to it- use the
2437 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
2438 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
2440 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
2442 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
2443 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2444 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
2453 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
2454 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
2456 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
2458 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
2459 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2460 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
2463 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
2471 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
2472 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
2475 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
2477 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
2489 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
2491 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
2493 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
2498 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
2499 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
2501 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
2502 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
2505 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
2508 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
2513 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
2514 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
2516 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
2517 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
2520 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
2523 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
2524 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
2526 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
2527 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
2529 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
2532 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
2534 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
2535 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
2540 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
2547 #define MC_CMD_CSR_READ32 0xc
2555 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
2556 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4
2557 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
2558 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4
2560 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
2563 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
2566 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2567 #define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
2569 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
2570 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
2580 #define MC_CMD_CSR_WRITE32 0xd
2589 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
2590 #define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
2592 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
2593 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
2594 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
2595 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
2597 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
2603 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
2604 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
2605 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
2613 #define MC_CMD_HP 0x54
2620 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
2622 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
2626 #define MC_CMD_HP_IN_SUBCMD_OFST 0
2627 #define MC_CMD_HP_IN_SUBCMD_LEN 4
2628 /* enum: OCSD (Option Card Sensor Data) sub-command. */
2629 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
2630 /* enum: Last known valid HP sub-command. */
2631 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0
2632 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
2634 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
2636 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
2638 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
2642 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
2645 #define MC_CMD_HP_OUT_LEN 4
2646 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
2647 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
2649 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
2651 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2
2653 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
2660 #define MC_CMD_STACKINFO 0xf
2666 #define MC_CMD_STACKINFO_IN_LEN 0
2672 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
2673 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
2675 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
2686 #define MC_CMD_MDIO_READ 0x10
2696 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
2697 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4
2699 #define MC_CMD_MDIO_BUS_INTERNAL 0x0
2701 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1
2703 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
2704 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
2707 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
2711 #define MC_CMD_MDIO_CLAUSE22 0x20
2714 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4
2719 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
2720 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
2724 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
2725 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
2727 #define MC_CMD_MDIO_STATUS_GOOD 0x8
2734 #define MC_CMD_MDIO_WRITE 0x11
2744 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
2745 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
2747 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
2749 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
2751 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
2752 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
2755 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
2759 /* MC_CMD_MDIO_CLAUSE22 0x20 */
2762 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
2765 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
2768 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
2772 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
2773 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
2775 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
2782 #define MC_CMD_DBI_WRITE 0x12
2791 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
2792 #define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
2793 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
2796 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
2803 #define MC_CMD_DBI_WRITE_OUT_LEN 0
2807 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
2808 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
2809 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
2811 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
2812 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
2813 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4
2816 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4
2819 #define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4
2825 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
2832 * Read a 32-bit register from the indirect port register map. The port to
2835 #define MC_CMD_PORT_READ32 0x14
2838 #define MC_CMD_PORT_READ32_IN_LEN 4
2840 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
2841 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4
2846 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
2847 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
2849 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
2850 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
2855 * Write a 32-bit register to the indirect port register map. The port to
2858 #define MC_CMD_PORT_WRITE32 0x15
2863 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
2864 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
2866 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
2867 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
2870 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
2872 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
2873 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
2878 * Read a 128-bit register from the indirect port register map. The port to
2881 #define MC_CMD_PORT_READ128 0x16
2884 #define MC_CMD_PORT_READ128_IN_LEN 4
2886 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
2887 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4
2892 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
2896 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
2901 * Write a 128-bit register to the indirect port register map. The port to
2904 #define MC_CMD_PORT_WRITE128 0x17
2909 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
2910 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
2912 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
2916 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
2918 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
2919 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
2922 #define MC_CMD_CAPABILITIES_LEN 4
2924 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
2936 #define MC_CMD_CAPABILITIES_AOE_LBN 4
2952 #define MC_CMD_GET_BOARD_CFG 0x18
2958 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
2965 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
2966 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
2967 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
2968 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
2974 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
2979 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
2994 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
2999 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
3004 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
3009 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
3010 /* Siena only. This field contains a 16-bit value for each of the types of
3025 * Read DBI register(s) -- extended functionality
3027 #define MC_CMD_DBI_READX 0x19
3036 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
3037 #define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
3038 /* Each Read op consists of an address (offset 0), VF/CS2) */
3039 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
3041 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
3042 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
3048 #define MC_CMD_DBI_READX_OUT_LENMIN 4
3051 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
3052 #define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
3054 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
3055 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
3062 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
3063 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
3064 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
3066 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
3067 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
3068 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4
3071 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4
3074 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4
3083 * Set the 16byte seed for the MC pseudo-random generator.
3085 #define MC_CMD_SET_RAND_SEED 0x1a
3093 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
3097 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
3104 #define MC_CMD_LTSSM_HIST 0x1b
3107 #define MC_CMD_LTSSM_HIST_IN_LEN 0
3110 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
3113 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
3114 #define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
3115 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
3116 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
3117 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
3118 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
3132 #define MC_CMD_DRV_ATTACH 0x1c
3140 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
3141 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
3142 #define MC_CMD_DRV_ATTACH_OFST 0
3143 #define MC_CMD_DRV_ATTACH_LBN 0
3145 #define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
3146 #define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
3148 #define MC_CMD_DRV_PREBOOT_OFST 0
3151 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
3154 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
3157 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
3160 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
3161 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
3163 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
3166 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
3169 /* 1 to set new state, or 0 to just report the existing state */
3170 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
3171 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
3174 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
3176 #define MC_CMD_FW_FULL_FEATURED 0x0
3178 #define MC_CMD_FW_LOW_LATENCY 0x1
3180 #define MC_CMD_FW_PACKED_STREAM 0x2
3184 #define MC_CMD_FW_HIGH_TX_RATE 0x3
3186 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
3190 #define MC_CMD_FW_RULES_ENGINE 0x5
3192 #define MC_CMD_FW_DPDK 0x6
3193 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3196 #define MC_CMD_FW_L3XUDP 0x7
3200 * (i.e. non-production) builds.
3202 #define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
3203 /* enum: Only this option is allowed for non-admin functions */
3204 #define MC_CMD_FW_DONT_CARE 0xffffffff
3211 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
3212 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
3213 /* MC_CMD_DRV_ATTACH_OFST 0 */
3214 /* MC_CMD_DRV_ATTACH_LBN 0 */
3216 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
3217 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
3219 /* MC_CMD_DRV_PREBOOT_OFST 0 */
3222 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
3225 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
3228 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
3231 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
3232 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
3234 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
3237 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
3240 /* 1 to set new state, or 0 to just report the existing state */
3241 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
3242 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
3245 #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
3247 /* MC_CMD_FW_FULL_FEATURED 0x0 */
3249 /* MC_CMD_FW_LOW_LATENCY 0x1 */
3251 /* MC_CMD_FW_PACKED_STREAM 0x2 */
3255 /* MC_CMD_FW_HIGH_TX_RATE 0x3 */
3257 /* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
3261 /* MC_CMD_FW_RULES_ENGINE 0x5 */
3263 /* MC_CMD_FW_DPDK 0x6 */
3264 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3267 /* MC_CMD_FW_L3XUDP 0x7 */
3271 * (i.e. non-production) builds.
3273 /* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
3274 /* enum: Only this option is allowed for non-admin functions */
3275 /* MC_CMD_FW_DONT_CARE 0xffffffff */
3276 /* Version of the driver to be reported by management protocols (e.g. NC-SI)
3277 * handled by the NIC. This is a zero-terminated ASCII string.
3283 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
3285 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
3286 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
3291 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
3292 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
3294 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
3295 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
3296 /* enum: Labels the lowest-numbered function visible to the OS */
3297 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
3301 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
3303 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
3307 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
3312 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
3314 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
3315 /* enum: If set, indicates that TX only spreading is enabled. Even-numbered
3316 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
3317 * also has the effect that only even-numbered RXQs will receive traffic.
3319 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
3326 #define MC_CMD_SHMUART 0x1f
3329 #define MC_CMD_SHMUART_IN_LEN 4
3331 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
3332 #define MC_CMD_SHMUART_IN_FLAG_LEN 4
3335 #define MC_CMD_SHMUART_OUT_LEN 0
3340 * Generic per-port reset. There is no equivalent for per-board reset. Locks
3341 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
3344 #define MC_CMD_PORT_RESET 0x20
3350 #define MC_CMD_PORT_RESET_IN_LEN 0
3353 #define MC_CMD_PORT_RESET_OUT_LEN 0
3358 * Generic per-resource reset. There is no equivalent for per-board reset.
3359 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
3362 #define MC_CMD_ENTITY_RESET 0x20
3366 #define MC_CMD_ENTITY_RESET_IN_LEN 4
3370 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
3371 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
3372 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
3373 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
3377 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
3384 #define MC_CMD_PCIE_CREDITS 0x21
3388 /* poll period. 0 is disabled */
3389 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
3390 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
3392 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
3393 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
3397 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
3401 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
3419 #define MC_CMD_RXD_MONITOR 0x22
3423 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
3424 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4
3425 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
3426 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
3428 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
3432 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
3433 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
3434 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
3435 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
3437 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
3439 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
3441 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
3443 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
3445 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
3447 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
3449 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
3451 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
3453 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
3455 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
3457 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
3459 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
3461 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
3463 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
3465 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
3467 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
3469 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
3471 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
3478 #define MC_CMD_PUTS 0x23
3488 #define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
3489 #define MC_CMD_PUTS_IN_DEST_OFST 0
3490 #define MC_CMD_PUTS_IN_DEST_LEN 4
3491 #define MC_CMD_PUTS_IN_UART_OFST 0
3492 #define MC_CMD_PUTS_IN_UART_LBN 0
3494 #define MC_CMD_PUTS_IN_PORT_OFST 0
3497 #define MC_CMD_PUTS_IN_DHOST_OFST 4
3506 #define MC_CMD_PUTS_OUT_LEN 0
3514 #define MC_CMD_GET_PHY_CFG 0x24
3520 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
3525 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
3526 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
3527 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
3528 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
3530 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
3533 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
3536 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
3539 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
3540 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
3542 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
3545 #define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
3549 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
3550 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
3553 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
3564 #define MC_CMD_PHY_CAP_100FDX_LBN 4
3619 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
3622 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
3625 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
3631 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
3633 #define MC_CMD_MEDIA_XAUI 0x1
3635 #define MC_CMD_MEDIA_CX4 0x2
3637 #define MC_CMD_MEDIA_KX4 0x3
3639 #define MC_CMD_MEDIA_XFP 0x4
3641 #define MC_CMD_MEDIA_SFP_PLUS 0x5
3643 #define MC_CMD_MEDIA_BASE_T 0x6
3645 #define MC_CMD_MEDIA_QSFP_PLUS 0x7
3647 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
3649 #define MC_CMD_MMD_CLAUSE22 0x0
3650 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
3651 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
3652 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
3653 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
3654 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
3655 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
3656 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
3658 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
3659 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
3660 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
3668 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
3670 #define MC_CMD_START_BIST 0x25
3676 #define MC_CMD_START_BIST_IN_LEN 4
3678 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
3679 #define MC_CMD_START_BIST_IN_TYPE_LEN 4
3681 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
3683 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2
3685 #define MC_CMD_BPX_SERDES_BIST 0x3
3687 #define MC_CMD_MC_LOOPBACK_BIST 0x4
3689 #define MC_CMD_PHY_BIST 0x5
3691 #define MC_CMD_MC_MEM_BIST 0x6
3693 #define MC_CMD_PORT_MEM_BIST 0x7
3695 #define MC_CMD_REG_BIST 0x8
3698 #define MC_CMD_START_BIST_OUT_LEN 0
3707 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
3710 #define MC_CMD_POLL_BIST 0x26
3716 #define MC_CMD_POLL_BIST_IN_LEN 0
3721 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
3722 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
3724 #define MC_CMD_POLL_BIST_RUNNING 0x1
3726 #define MC_CMD_POLL_BIST_PASSED 0x2
3728 #define MC_CMD_POLL_BIST_FAILED 0x3
3729 /* enum: Timed-out. */
3730 #define MC_CMD_POLL_BIST_TIMEOUT 0x4
3731 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
3732 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
3737 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3738 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3741 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
3742 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
3744 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
3746 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
3748 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
3751 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
3753 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
3755 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
3756 /* enum: Intra-pair short. */
3757 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
3758 /* enum: Inter-pair short. */
3759 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
3761 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
3764 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
3769 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
3774 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
3781 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3782 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3785 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
3786 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
3788 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
3790 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
3792 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
3794 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
3796 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
3798 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
3800 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
3802 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
3804 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
3809 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3810 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3813 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
3814 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
3816 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
3817 /* enum: RAM test - walk ones. */
3818 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
3819 /* enum: RAM test - walk zeros. */
3820 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
3821 /* enum: RAM test - walking inversions zeros/ones. */
3822 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
3823 /* enum: RAM test - walking inversions checkerboard. */
3824 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
3825 /* enum: Register test - set / clear individual bits. */
3826 #define MC_CMD_POLL_BIST_MEM_REG 0x5
3828 #define MC_CMD_POLL_BIST_MEM_ECC 0x6
3831 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
3834 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
3836 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
3838 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
3840 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
3842 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
3844 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
3846 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
3848 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
3850 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
3852 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
3855 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
3858 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
3861 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
3864 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
3867 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
3879 #define MC_CMD_FLUSH_RX_QUEUES 0x27
3882 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
3885 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3886 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
3887 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
3888 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
3894 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
3901 #define MC_CMD_GET_LOOPBACK_MODES 0x28
3907 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
3912 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
3914 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
3915 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
3917 #define MC_CMD_LOOPBACK_NONE 0x0
3919 #define MC_CMD_LOOPBACK_DATA 0x1
3921 #define MC_CMD_LOOPBACK_GMAC 0x2
3923 #define MC_CMD_LOOPBACK_XGMII 0x3
3925 #define MC_CMD_LOOPBACK_XGXS 0x4
3927 #define MC_CMD_LOOPBACK_XAUI 0x5
3929 #define MC_CMD_LOOPBACK_GMII 0x6
3931 #define MC_CMD_LOOPBACK_SGMII 0x7
3933 #define MC_CMD_LOOPBACK_XGBR 0x8
3935 #define MC_CMD_LOOPBACK_XFI 0x9
3937 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa
3939 #define MC_CMD_LOOPBACK_GMII_FAR 0xb
3941 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc
3943 #define MC_CMD_LOOPBACK_XFI_FAR 0xd
3945 #define MC_CMD_LOOPBACK_GPHY 0xe
3947 #define MC_CMD_LOOPBACK_PHYXS 0xf
3949 #define MC_CMD_LOOPBACK_PCS 0x10
3950 /* enum: PMA-PMD. */
3951 #define MC_CMD_LOOPBACK_PMAPMD 0x11
3952 /* enum: Cross-Port. */
3953 #define MC_CMD_LOOPBACK_XPORT 0x12
3954 /* enum: XGMII-Wireside. */
3955 #define MC_CMD_LOOPBACK_XGMII_WS 0x13
3957 #define MC_CMD_LOOPBACK_XAUI_WS 0x14
3959 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
3961 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
3963 #define MC_CMD_LOOPBACK_GMII_WS 0x17
3965 #define MC_CMD_LOOPBACK_XFI_WS 0x18
3967 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
3969 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
3970 /* enum: PMA lanes MAC-Serdes. */
3971 #define MC_CMD_LOOPBACK_PMA_INT 0x1b
3973 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c
3975 #define MC_CMD_LOOPBACK_SD_FAR 0x1d
3976 /* enum: PMA lanes MAC-Serdes Wireside. */
3977 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
3979 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
3981 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
3983 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
3985 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22
3987 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
3989 #define MC_CMD_LOOPBACK_DATA_WS 0x24
3993 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
4028 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
4030 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
4031 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
4033 /* MC_CMD_LOOPBACK_NONE 0x0 */
4035 /* MC_CMD_LOOPBACK_DATA 0x1 */
4037 /* MC_CMD_LOOPBACK_GMAC 0x2 */
4039 /* MC_CMD_LOOPBACK_XGMII 0x3 */
4041 /* MC_CMD_LOOPBACK_XGXS 0x4 */
4043 /* MC_CMD_LOOPBACK_XAUI 0x5 */
4045 /* MC_CMD_LOOPBACK_GMII 0x6 */
4047 /* MC_CMD_LOOPBACK_SGMII 0x7 */
4049 /* MC_CMD_LOOPBACK_XGBR 0x8 */
4051 /* MC_CMD_LOOPBACK_XFI 0x9 */
4053 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
4055 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */
4057 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
4059 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */
4061 /* MC_CMD_LOOPBACK_GPHY 0xe */
4063 /* MC_CMD_LOOPBACK_PHYXS 0xf */
4065 /* MC_CMD_LOOPBACK_PCS 0x10 */
4066 /* enum: PMA-PMD. */
4067 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */
4068 /* enum: Cross-Port. */
4069 /* MC_CMD_LOOPBACK_XPORT 0x12 */
4070 /* enum: XGMII-Wireside. */
4071 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
4073 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
4075 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
4077 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
4079 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */
4081 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */
4083 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
4085 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
4086 /* enum: PMA lanes MAC-Serdes. */
4087 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */
4089 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
4091 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */
4092 /* enum: PMA lanes MAC-Serdes Wireside. */
4093 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
4095 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
4097 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
4099 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
4101 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
4103 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
4105 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */
4109 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
4160 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
4161 #define AN_TYPE_LEN 4
4162 #define AN_TYPE_TYPE_OFST 0
4163 #define AN_TYPE_TYPE_LEN 4
4165 #define MC_CMD_AN_NONE 0x0
4166 /* enum: Clause 28 - BASE-T */
4167 #define MC_CMD_AN_CLAUSE28 0x1
4168 /* enum: Clause 37 - BASE-X */
4169 #define MC_CMD_AN_CLAUSE37 0x2
4170 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
4171 * assemblies. Includes Clause 72/Clause 92 link-training.
4173 #define MC_CMD_AN_CLAUSE73 0x3
4174 #define AN_TYPE_TYPE_LBN 0
4179 #define FEC_TYPE_LEN 4
4180 #define FEC_TYPE_TYPE_OFST 0
4181 #define FEC_TYPE_TYPE_LEN 4
4183 #define MC_CMD_FEC_NONE 0x0
4184 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
4185 #define MC_CMD_FEC_BASER 0x1
4186 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */
4187 #define MC_CMD_FEC_RS 0x2
4188 #define FEC_TYPE_TYPE_LBN 0
4194 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
4197 #define MC_CMD_GET_LINK 0x29
4203 #define MC_CMD_GET_LINK_IN_LEN 0
4207 /* Near-side advertised capabilities. Refer to
4210 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
4211 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4
4212 /* Link-partner advertised capabilities. Refer to
4215 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
4216 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
4218 * reads non-zero.
4221 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
4224 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
4228 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
4230 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
4255 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
4259 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
4261 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
4275 /* Near-side advertised capabilities. Refer to
4278 #define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
4279 #define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
4280 /* Link-partner advertised capabilities. Refer to
4283 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
4284 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
4286 * reads non-zero.
4289 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
4292 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
4296 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
4298 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
4323 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
4327 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
4329 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
4341 * e.g. plugged-in module). In general, subset of
4343 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
4344 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
4348 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
4349 /* Auto-negotiation type used on the link */
4351 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
4356 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
4360 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
4362 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
4374 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
4396 * code: 0, EINVAL, ETIME, EAGAIN
4398 #define MC_CMD_SET_LINK 0x2a
4405 /* Near-side advertised capabilities. Refer to
4408 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
4409 #define MC_CMD_SET_LINK_IN_CAP_LEN 4
4411 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
4412 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
4413 #define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
4414 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
4416 #define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
4419 #define MC_CMD_SET_LINK_IN_TXDIS_OFST 4
4422 #define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
4427 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
4430 /* A loopback speed of "0" is supported, and means (choose any available
4434 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
4441 /* Near-side advertised capabilities. Refer to
4444 #define MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
4445 #define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
4447 #define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
4448 #define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
4449 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
4450 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
4452 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
4455 #define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
4458 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
4463 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
4466 /* A loopback speed of "0" is supported, and means (choose any available
4470 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
4474 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
4481 #define MC_CMD_SET_LINK_OUT_LEN 0
4486 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
4488 #define MC_CMD_SET_ID_LED 0x2b
4494 #define MC_CMD_SET_ID_LED_IN_LEN 4
4496 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
4497 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
4498 #define MC_CMD_LED_OFF 0x0 /* enum */
4499 #define MC_CMD_LED_ON 0x1 /* enum */
4500 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
4503 #define MC_CMD_SET_ID_LED_OUT_LEN 0
4508 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
4510 #define MC_CMD_SET_MAC 0x2c
4520 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
4521 #define MC_CMD_SET_MAC_IN_MTU_LEN 4
4522 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
4523 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
4529 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4
4531 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
4537 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
4539 #define MC_CMD_FCNTL_OFF 0x0
4541 #define MC_CMD_FCNTL_RESPOND 0x1
4543 #define MC_CMD_FCNTL_BIDIR 0x2
4545 #define MC_CMD_FCNTL_AUTO 0x3
4547 #define MC_CMD_FCNTL_QBB 0x4
4549 #define MC_CMD_FCNTL_GENERATE 0x5
4551 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
4553 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
4561 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
4562 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
4563 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
4564 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
4570 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
4572 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
4578 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
4580 /* MC_CMD_FCNTL_OFF 0x0 */
4582 /* MC_CMD_FCNTL_RESPOND 0x1 */
4584 /* MC_CMD_FCNTL_BIDIR 0x2 */
4586 /* MC_CMD_FCNTL_AUTO 0x3 */
4588 /* MC_CMD_FCNTL_QBB 0x4 */
4590 /* MC_CMD_FCNTL_GENERATE 0x5 */
4592 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
4594 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
4602 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
4604 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
4616 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
4620 #define MC_CMD_SET_MAC_OUT_LEN 0
4623 #define MC_CMD_SET_MAC_V2_OUT_LEN 4
4626 * to 0.
4628 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
4629 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
4636 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
4637 * statistics may be read from the message response. If DMA_ADDR != 0, then the
4638 * statistics are dmad to that (page-aligned location). Locks required: None.
4639 * Returns: 0, ETIME
4641 #define MC_CMD_PHY_STATS 0x2d
4649 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
4651 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
4652 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
4655 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
4659 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
4660 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
4663 #define MC_CMD_OUI 0x0
4664 /* enum: PMA-PMD Link Up. */
4665 #define MC_CMD_PMA_PMD_LINK_UP 0x1
4666 /* enum: PMA-PMD RX Fault. */
4667 #define MC_CMD_PMA_PMD_RX_FAULT 0x2
4668 /* enum: PMA-PMD TX Fault. */
4669 #define MC_CMD_PMA_PMD_TX_FAULT 0x3
4670 /* enum: PMA-PMD Signal */
4671 #define MC_CMD_PMA_PMD_SIGNAL 0x4
4672 /* enum: PMA-PMD SNR A. */
4673 #define MC_CMD_PMA_PMD_SNR_A 0x5
4674 /* enum: PMA-PMD SNR B. */
4675 #define MC_CMD_PMA_PMD_SNR_B 0x6
4676 /* enum: PMA-PMD SNR C. */
4677 #define MC_CMD_PMA_PMD_SNR_C 0x7
4678 /* enum: PMA-PMD SNR D. */
4679 #define MC_CMD_PMA_PMD_SNR_D 0x8
4681 #define MC_CMD_PCS_LINK_UP 0x9
4683 #define MC_CMD_PCS_RX_FAULT 0xa
4685 #define MC_CMD_PCS_TX_FAULT 0xb
4687 #define MC_CMD_PCS_BER 0xc
4689 #define MC_CMD_PCS_BLOCK_ERRORS 0xd
4691 #define MC_CMD_PHYXS_LINK_UP 0xe
4693 #define MC_CMD_PHYXS_RX_FAULT 0xf
4695 #define MC_CMD_PHYXS_TX_FAULT 0x10
4697 #define MC_CMD_PHYXS_ALIGN 0x11
4699 #define MC_CMD_PHYXS_SYNC 0x12
4700 /* enum: AN link-up. */
4701 #define MC_CMD_AN_LINK_UP 0x13
4703 #define MC_CMD_AN_COMPLETE 0x14
4705 #define MC_CMD_AN_10GBT_STATUS 0x15
4706 /* enum: Clause 22 Link-Up. */
4707 #define MC_CMD_CL22_LINK_UP 0x16
4709 #define MC_CMD_PHY_NSTATS 0x17
4717 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
4719 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
4721 * effect. Returns: 0, ETIME
4723 #define MC_CMD_MAC_STATS 0x2e
4731 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
4733 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
4734 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
4736 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4
4738 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
4750 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
4764 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
4767 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
4770 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
4774 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
4776 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
4777 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
4779 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
4780 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
4781 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
4782 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
4783 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
4784 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
4785 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
4786 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
4787 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
4788 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
4789 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
4790 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
4791 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
4792 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
4793 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
4794 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
4795 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
4796 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
4797 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
4798 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
4799 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
4800 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
4801 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
4802 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
4803 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
4804 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
4805 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
4806 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
4807 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
4808 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
4809 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
4810 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
4811 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
4812 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
4813 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
4814 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
4815 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
4816 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
4817 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
4818 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
4819 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
4820 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
4821 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
4822 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
4823 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
4824 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
4825 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
4826 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
4827 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
4828 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
4829 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
4830 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
4831 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
4832 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
4833 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
4834 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
4835 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
4836 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
4837 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
4838 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
4839 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
4843 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
4847 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
4851 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
4855 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
4859 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40
4863 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41
4867 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
4871 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
4875 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
4876 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
4879 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
4883 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
4887 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
4888 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
4889 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
4890 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
4891 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
4892 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
4893 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
4894 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
4895 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
4896 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
4897 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
4898 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
4899 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
4900 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
4901 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
4902 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
4903 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
4904 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
4905 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
4906 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
4907 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
4909 #define MC_CMD_GMAC_DMABUF_START 0x40
4911 #define MC_CMD_GMAC_DMABUF_END 0x5f
4917 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
4919 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
4920 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
4922 #define MC_CMD_MAC_GENERATION_END 0x60
4923 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
4926 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
4930 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
4932 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
4933 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
4936 #define MC_CMD_MAC_FEC_DMABUF_START 0x61
4937 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
4939 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
4940 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
4942 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
4943 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
4944 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
4945 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
4946 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
4947 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
4948 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
4949 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
4950 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
4954 #define MC_CMD_MAC_NSTATS_V2 0x68
4959 #define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
4963 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
4965 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
4966 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
4969 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
4973 #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
4977 #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
4981 #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
4983 #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
4987 #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
4991 #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
4995 #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
4999 #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
5001 * or not 32-bit aligned
5003 #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
5007 #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
5010 #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
5014 #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
5016 #define MC_CMD_MAC_CTPIO_SUCCESS 0x74
5018 #define MC_CMD_MAC_CTPIO_FALLBACK 0x75
5022 #define MC_CMD_MAC_CTPIO_POISON 0x76
5024 #define MC_CMD_MAC_CTPIO_ERASE 0x77
5028 #define MC_CMD_MAC_NSTATS_V3 0x79
5033 #define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
5037 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
5039 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
5040 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
5043 #define MC_CMD_MAC_V4_DMABUF_START 0x79
5047 #define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
5051 #define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
5055 #define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
5059 #define MC_CMD_MAC_NSTATS_V4 0x7d
5068 #define MC_CMD_SRIOV 0x30
5072 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
5073 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4
5074 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
5075 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4
5077 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
5081 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
5082 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
5083 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
5084 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
5089 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
5090 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
5091 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
5093 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
5094 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
5104 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
5105 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
5115 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
5133 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
5138 * Returns: 0, EINVAL (invalid RID)
5140 #define MC_CMD_MEMCPY 0x31
5146 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
5147 #define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
5149 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
5156 #define MC_CMD_MEMCPY_OUT_LEN 0
5163 #define MC_CMD_WOL_FILTER_SET 0x32
5170 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
5171 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
5172 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
5173 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
5175 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
5176 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
5178 #define MC_CMD_WOL_TYPE_MAGIC 0x0
5180 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
5182 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
5184 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
5186 #define MC_CMD_WOL_TYPE_BITMAP 0x5
5188 #define MC_CMD_WOL_TYPE_LINK 0x6
5190 #define MC_CMD_WOL_TYPE_MAX 0x7
5192 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
5197 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5198 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5199 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5200 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5208 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5209 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5210 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5211 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5213 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
5215 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
5223 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5224 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5225 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5226 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5238 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5239 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5240 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5241 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5255 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5256 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5257 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5258 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5260 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
5262 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
5269 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
5270 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
5271 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
5276 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
5278 #define MC_CMD_WOL_FILTER_REMOVE 0x33
5284 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
5285 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
5286 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
5289 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
5294 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
5297 #define MC_CMD_WOL_FILTER_RESET 0x34
5303 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
5304 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
5305 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
5306 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
5307 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
5310 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
5317 #define MC_CMD_SET_MCAST_HASH 0x35
5321 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
5327 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
5333 * Locks required: none. Returns: 0
5335 #define MC_CMD_NVRAM_TYPES 0x36
5341 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
5344 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
5346 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
5347 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
5349 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
5351 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1
5353 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
5355 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
5357 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
5359 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
5361 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
5363 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
5365 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
5367 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
5369 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
5371 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
5373 #define MC_CMD_NVRAM_TYPE_LOG 0xc
5375 #define MC_CMD_NVRAM_TYPE_FPGA 0xd
5377 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
5379 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf
5381 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
5383 #define MC_CMD_NVRAM_TYPE_CPLD 0x11
5385 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12
5387 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
5389 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
5394 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
5397 #define MC_CMD_NVRAM_INFO 0x37
5403 #define MC_CMD_NVRAM_INFO_IN_LEN 4
5404 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
5405 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
5411 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
5412 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
5415 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
5416 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
5418 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
5420 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
5422 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
5443 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
5445 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
5449 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
5450 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
5453 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
5454 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
5456 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
5458 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
5460 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
5475 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
5477 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
5481 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
5487 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
5494 #define MC_CMD_NVRAM_UPDATE_START 0x38
5502 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
5503 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
5504 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
5514 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
5515 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
5518 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
5519 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
5520 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
5521 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
5525 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
5531 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
5534 #define MC_CMD_NVRAM_READ 0x39
5541 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
5542 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
5545 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
5546 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
5549 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
5553 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
5554 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
5557 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
5558 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
5561 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
5565 * from. This allows it to perform a read-modify-write-verify with the write
5571 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
5576 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
5580 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
5581 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
5584 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
5590 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
5591 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
5592 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
5602 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
5605 #define MC_CMD_NVRAM_WRITE 0x3a
5615 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
5616 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
5617 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
5620 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
5621 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
5623 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
5631 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
5637 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
5640 #define MC_CMD_NVRAM_ERASE 0x3b
5647 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
5648 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
5651 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
5652 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
5654 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
5657 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
5663 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
5670 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
5679 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
5680 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
5683 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
5684 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
5692 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
5693 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
5696 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
5697 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
5699 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
5701 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
5713 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
5727 * per-partition nvram lock in firmware is only released after the verification
5730 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
5733 * the field are marked with a prefix 'Internal-error'.
5735 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
5736 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
5737 /* enum: Invalid return code; only non-zero values are defined. Defined as
5740 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
5742 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
5744 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
5746 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
5748 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
5749 /* enum: Error in message digest calculated over the reflash-header, payload
5750 * and reflash-trailer.
5752 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
5754 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
5756 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
5758 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
5760 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
5762 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
5766 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
5767 /* enum: The image contains a test-signed certificate, but the adapter accepts
5770 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
5772 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
5773 /* enum: Internal-error. The signed image is missing the 'contents' section,
5776 #define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
5777 /* enum: Internal-error. The bundle header is invalid. */
5778 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
5779 /* enum: Internal-error. The bundle does not have a valid reflash image layout.
5781 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
5782 /* enum: Internal-error. The bundle has an inconsistent layout of components or
5785 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
5786 /* enum: Internal-error. The bundle manifest is inconsistent with components in
5789 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
5790 /* enum: Internal-error. The number of components in a bundle do not match the
5793 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
5794 /* enum: Internal-error. The bundle contains too many components for the MC
5797 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
5798 /* enum: Internal-error. The bundle manifest has an invalid/inconsistent
5801 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
5802 /* enum: Internal-error. The hash of a component does not match the hash stored
5805 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
5806 /* enum: Internal-error. Component hash calculation failed. */
5807 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
5808 /* enum: Internal-error. The component does not have a valid reflash image
5811 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
5815 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
5816 /* enum: The update operation is in-progress. */
5817 #define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
5833 * REBOOT_ON_ASSERT=0.
5836 * DATALEN=0
5838 #define MC_CMD_REBOOT 0x3d
5844 #define MC_CMD_REBOOT_IN_LEN 4
5845 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
5846 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4
5847 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
5850 #define MC_CMD_REBOOT_OUT_LEN 0
5859 #define MC_CMD_SCHEDINFO 0x3e
5865 #define MC_CMD_SCHEDINFO_IN_LEN 0
5868 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
5871 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
5872 #define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
5873 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
5874 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
5885 #define MC_CMD_REBOOT_MODE 0x3f
5891 #define MC_CMD_REBOOT_MODE_IN_LEN 4
5892 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
5893 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
5895 #define MC_CMD_REBOOT_MODE_NORMAL 0x0
5896 /* enum: Power-on Reset. */
5897 #define MC_CMD_REBOOT_MODE_POR 0x2
5899 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3
5901 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
5902 #define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0
5907 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
5908 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
5909 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
5930 * backward compatibility, older host software can only use sensors in page 0.
5935 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
5941 * Locks required: None Returns: 0
5943 #define MC_CMD_SENSOR_INFO 0x41
5949 #define MC_CMD_SENSOR_INFO_IN_LEN 0
5952 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
5955 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
5959 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
5960 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
5966 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
5970 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
5971 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
5973 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
5974 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
5975 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
5976 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
5980 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
5983 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
5984 #define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
5985 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
5986 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
5988 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
5990 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
5992 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
5993 /* enum: Phy 0 temperature: degC */
5994 #define MC_CMD_SENSOR_PHY0_TEMP 0x3
5995 /* enum: Phy 0 cooling: bool */
5996 #define MC_CMD_SENSOR_PHY0_COOLING 0x4
5998 #define MC_CMD_SENSOR_PHY1_TEMP 0x5
6000 #define MC_CMD_SENSOR_PHY1_COOLING 0x6
6002 #define MC_CMD_SENSOR_IN_1V0 0x7
6004 #define MC_CMD_SENSOR_IN_1V2 0x8
6006 #define MC_CMD_SENSOR_IN_1V8 0x9
6008 #define MC_CMD_SENSOR_IN_2V5 0xa
6010 #define MC_CMD_SENSOR_IN_3V3 0xb
6012 #define MC_CMD_SENSOR_IN_12V0 0xc
6014 #define MC_CMD_SENSOR_IN_1V2A 0xd
6016 #define MC_CMD_SENSOR_IN_VREF 0xe
6018 #define MC_CMD_SENSOR_OUT_VAOE 0xf
6020 #define MC_CMD_SENSOR_AOE_TEMP 0x10
6022 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
6024 #define MC_CMD_SENSOR_PSU_TEMP 0x12
6025 /* enum: Fan 0 speed: RPM */
6026 #define MC_CMD_SENSOR_FAN_0 0x13
6028 #define MC_CMD_SENSOR_FAN_1 0x14
6030 #define MC_CMD_SENSOR_FAN_2 0x15
6032 #define MC_CMD_SENSOR_FAN_3 0x16
6033 /* enum: Fan 4 speed: RPM */
6034 #define MC_CMD_SENSOR_FAN_4 0x17
6036 #define MC_CMD_SENSOR_IN_VAOE 0x18
6038 #define MC_CMD_SENSOR_OUT_IAOE 0x19
6040 #define MC_CMD_SENSOR_IN_IAOE 0x1a
6042 #define MC_CMD_SENSOR_NIC_POWER 0x1b
6044 #define MC_CMD_SENSOR_IN_0V9 0x1c
6046 #define MC_CMD_SENSOR_IN_I0V9 0x1d
6048 #define MC_CMD_SENSOR_IN_I1V2 0x1e
6050 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
6052 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20
6054 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
6056 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
6058 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
6060 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
6062 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
6064 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
6066 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
6068 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
6070 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
6072 #define MC_CMD_SENSOR_AIRFLOW 0x2a
6074 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
6076 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
6078 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
6079 /* enum: Port 0 PHY power switch over-current: bool */
6080 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
6081 /* enum: Port 1 PHY power switch over-current: bool */
6082 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
6083 /* enum: Mop-up microcontroller reference voltage: mV */
6084 #define MC_CMD_SENSOR_MUM_VCC 0x30
6086 #define MC_CMD_SENSOR_IN_0V9_A 0x31
6088 #define MC_CMD_SENSOR_IN_I0V9_A 0x32
6090 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
6092 #define MC_CMD_SENSOR_IN_0V9_B 0x34
6094 #define MC_CMD_SENSOR_IN_I0V9_B 0x35
6096 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
6098 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
6100 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
6102 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
6104 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
6106 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
6108 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
6112 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
6114 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
6118 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
6120 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
6124 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
6126 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
6130 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
6132 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
6134 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49
6135 /* enum: Temperature of SODIMM 0 (if installed): degC */
6136 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
6138 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
6139 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
6140 #define MC_CMD_SENSOR_PHY0_VCC 0x4c
6142 #define MC_CMD_SENSOR_PHY1_VCC 0x4d
6144 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
6146 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
6148 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
6150 #define MC_CMD_SENSOR_IN_I1V8 0x51
6152 #define MC_CMD_SENSOR_IN_I2V5 0x52
6154 #define MC_CMD_SENSOR_IN_I3V3 0x53
6156 #define MC_CMD_SENSOR_IN_I12V0 0x54
6158 #define MC_CMD_SENSOR_IN_1V3 0x55
6160 #define MC_CMD_SENSOR_IN_I1V3 0x56
6162 #define MC_CMD_SENSOR_ENGINEERING_1 0x57
6164 #define MC_CMD_SENSOR_ENGINEERING_2 0x58
6166 #define MC_CMD_SENSOR_ENGINEERING_3 0x59
6167 /* enum: Engineering sensor 4 */
6168 #define MC_CMD_SENSOR_ENGINEERING_4 0x5a
6170 #define MC_CMD_SENSOR_ENGINEERING_5 0x5b
6172 #define MC_CMD_SENSOR_ENGINEERING_6 0x5c
6174 #define MC_CMD_SENSOR_ENGINEERING_7 0x5d
6176 #define MC_CMD_SENSOR_ENGINEERING_8 0x5e
6178 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
6180 #define MC_CMD_SENSOR_ENTRY_OFST 4
6182 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
6184 #define MC_CMD_SENSOR_ENTRY_MINNUM 0
6189 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
6192 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
6193 #define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
6194 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
6195 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
6198 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
6202 /* MC_CMD_SENSOR_ENTRY_OFST 4 */
6204 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
6206 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
6212 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
6214 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
6220 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
6237 * If the request does not contain the LENGTH field then only sensors 0 to 30
6247 #define MC_CMD_READ_SENSORS 0x42
6254 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6256 * If the address is 0xffffffffffffffff send the readings in the response (used
6259 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
6261 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
6262 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
6266 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6268 * If the address is 0xffffffffffffffff send the readings in the response (used
6271 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
6273 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
6274 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
6277 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
6281 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6283 * If the address is 0xffffffffffffffff send the readings in the response (used
6286 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
6288 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
6289 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
6292 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
6295 #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
6297 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
6301 #define MC_CMD_READ_SENSORS_OUT_LEN 0
6304 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
6307 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
6308 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
6310 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
6315 #define MC_CMD_SENSOR_STATE_OK 0x0
6317 #define MC_CMD_SENSOR_STATE_WARNING 0x1
6319 #define MC_CMD_SENSOR_STATE_FATAL 0x2
6321 #define MC_CMD_SENSOR_STATE_BROKEN 0x3
6323 #define MC_CMD_SENSOR_STATE_NO_READING 0x4
6325 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
6340 * code: 0
6342 #define MC_CMD_GET_PHY_STATE 0x43
6348 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
6351 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
6352 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
6353 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
6355 #define MC_CMD_PHY_STATE_OK 0x1
6357 #define MC_CMD_PHY_STATE_ZOMBIE 0x2
6362 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
6365 #define MC_CMD_SETUP_8021QBB 0x44
6369 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
6373 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
6378 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
6380 #define MC_CMD_WOL_FILTER_GET 0x45
6386 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
6389 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
6390 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
6391 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
6396 * Add a protocol offload to NIC for lights-out state. Locks required: None.
6397 * Returns: 0, ENOSYS
6399 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
6408 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
6409 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
6410 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
6411 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
6412 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
6413 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
6414 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
6415 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
6422 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
6423 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
6424 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
6427 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
6431 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
6432 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
6433 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
6441 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
6442 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
6443 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
6448 * Remove a protocol offload from NIC for lights-out state. Locks required:
6449 * None. Returns: 0, ENOSYS
6451 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
6458 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
6459 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
6460 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
6461 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
6464 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
6469 * Restore MAC after block reset. Locks required: None. Returns: 0.
6471 #define MC_CMD_MAC_RESET_RESTORE 0x48
6474 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
6477 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
6482 * Deliberately trigger an assert-detonation in the firmware for testing
6484 * required: None Returns: 0
6486 #define MC_CMD_TESTASSERT 0x49
6492 #define MC_CMD_TESTASSERT_IN_LEN 0
6495 #define MC_CMD_TESTASSERT_OUT_LEN 0
6498 #define MC_CMD_TESTASSERT_V2_IN_LEN 4
6500 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
6501 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
6505 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
6506 /* enum: Assert using assert(0); */
6507 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
6509 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
6511 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
6513 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
6515 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
6518 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0
6524 * understand the given workaround number - which should not be treated as a
6526 * workaround, that's between the driver and the mcfw on a per-workaround
6527 * basis. Locks required: None. Returns: 0, EINVAL .
6529 #define MC_CMD_WORKAROUND 0x4a
6537 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
6538 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
6540 #define MC_CMD_WORKAROUND_BUG17230 0x1
6542 #define MC_CMD_WORKAROUND_BUG35388 0x2
6544 #define MC_CMD_WORKAROUND_BUG35017 0x3
6546 #define MC_CMD_WORKAROUND_BUG41750 0x4
6548 * - before adding code that queries this workaround, remember that there's
6552 #define MC_CMD_WORKAROUND_BUG42008 0x5
6560 #define MC_CMD_WORKAROUND_BUG26807 0x6
6562 #define MC_CMD_WORKAROUND_BUG61265 0x7
6563 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
6566 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
6567 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
6570 #define MC_CMD_WORKAROUND_OUT_LEN 0
6575 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
6576 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
6577 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
6578 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
6579 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
6585 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
6588 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
6589 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
6590 * Anything else: currently undefined. Locks required: None. Return code: 0.
6592 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
6598 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
6599 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
6600 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
6606 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
6607 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
6609 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
6610 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
6611 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
6623 #define MC_CMD_NVRAM_TEST 0x4c
6629 #define MC_CMD_NVRAM_TEST_IN_LEN 4
6630 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
6631 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
6636 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
6637 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
6638 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
6640 #define MC_CMD_NVRAM_TEST_PASS 0x0
6642 #define MC_CMD_NVRAM_TEST_FAIL 0x1
6644 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
6651 * they are configured first. Locks required: None. Return code: 0, EINVAL.
6653 #define MC_CMD_MRSFP_TWEAK 0x4d
6657 /* 0-6 low->high de-emph. */
6658 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
6659 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
6660 /* 0-8 low->high ref.V */
6661 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
6662 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
6663 /* 0-8 0-8 low->high boost */
6665 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
6666 /* 0-8 low->high ref.V */
6668 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
6671 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
6676 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
6677 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
6679 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
6680 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
6683 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
6685 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
6687 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
6692 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
6696 #define MC_CMD_SENSOR_SET_LIMS 0x4e
6703 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
6704 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
6707 /* interpretation is is sensor-specific. */
6708 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
6709 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
6710 /* interpretation is is sensor-specific. */
6712 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
6713 /* interpretation is is sensor-specific. */
6715 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
6716 /* interpretation is is sensor-specific. */
6718 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
6721 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
6727 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
6730 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
6734 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
6735 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
6736 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
6737 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
6739 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
6741 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
6747 * none. Returns: 0, EINVAL (bad type).
6749 #define MC_CMD_NVRAM_PARTITIONS 0x51
6755 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
6758 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
6761 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
6762 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
6764 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
6765 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
6767 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
6768 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
6769 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
6777 * none. Returns: 0, EINVAL (bad type).
6779 #define MC_CMD_NVRAM_METADATA 0x52
6785 #define MC_CMD_NVRAM_METADATA_IN_LEN 4
6787 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
6788 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
6795 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
6797 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
6798 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
6799 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
6800 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
6801 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
6802 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
6804 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
6807 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
6812 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
6822 /* 4th component of W.X.Y.Z version number for content of this partition */
6825 /* Zero-terminated string describing the content of this partition */
6828 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
6837 #define MC_CMD_GET_MAC_ADDRESSES 0x55
6843 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
6848 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
6855 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
6858 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
6863 * Perform a CLP related operation, see SF-110495-PS for details of CLP
6865 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,
6866 * SF-120509-TC and SF-117282-PS.
6868 #define MC_CMD_CLP 0x56
6874 #define MC_CMD_CLP_IN_LEN 4
6876 #define MC_CMD_CLP_IN_OP_OFST 0
6877 #define MC_CMD_CLP_IN_OP_LEN 4
6879 #define MC_CMD_CLP_OP_DEFAULT 0x1
6881 #define MC_CMD_CLP_OP_SET_MAC 0x2
6883 #define MC_CMD_CLP_OP_GET_MAC 0x3
6885 #define MC_CMD_CLP_OP_SET_BOOT 0x4
6887 #define MC_CMD_CLP_OP_GET_BOOT 0x5
6890 #define MC_CMD_CLP_OUT_LEN 0
6893 #define MC_CMD_CLP_IN_DEFAULT_LEN 4
6894 /* MC_CMD_CLP_IN_OP_OFST 0 */
6895 /* MC_CMD_CLP_IN_OP_LEN 4 */
6898 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0
6902 /* MC_CMD_CLP_IN_OP_OFST 0 */
6903 /* MC_CMD_CLP_IN_OP_LEN 4 */
6905 * restores the permanent (factory-programmed) MAC address associated with the
6906 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
6908 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
6915 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0
6919 /* MC_CMD_CLP_IN_OP_OFST 0 */
6920 /* MC_CMD_CLP_IN_OP_LEN 4 */
6922 * restores the permanent (factory-programmed) MAC address associated with the
6923 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
6925 #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4
6931 #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4
6933 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0
6937 #define MC_CMD_CLP_IN_GET_MAC_LEN 4
6938 /* MC_CMD_CLP_IN_OP_OFST 0 */
6939 /* MC_CMD_CLP_IN_OP_LEN 4 */
6943 /* MC_CMD_CLP_IN_OP_OFST 0 */
6944 /* MC_CMD_CLP_IN_OP_LEN 4 */
6945 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4
6946 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4
6947 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4
6948 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0
6954 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
6962 /* MC_CMD_CLP_IN_OP_OFST 0 */
6963 /* MC_CMD_CLP_IN_OP_LEN 4 */
6965 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
6969 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0
6972 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4
6973 /* MC_CMD_CLP_IN_OP_OFST 0 */
6974 /* MC_CMD_CLP_IN_OP_LEN 4 */
6977 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4
6979 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
6990 #define MC_CMD_MUM 0x57
6996 #define MC_CMD_MUM_IN_LEN 4
6997 #define MC_CMD_MUM_IN_OP_HDR_OFST 0
6998 #define MC_CMD_MUM_IN_OP_HDR_LEN 4
6999 #define MC_CMD_MUM_IN_OP_OFST 0
7000 #define MC_CMD_MUM_IN_OP_LBN 0
7003 #define MC_CMD_MUM_OP_NULL 0x1
7005 #define MC_CMD_MUM_OP_GET_VERSION 0x2
7007 #define MC_CMD_MUM_OP_RAW_CMD 0x3
7009 #define MC_CMD_MUM_OP_READ 0x4
7011 #define MC_CMD_MUM_OP_WRITE 0x5
7013 #define MC_CMD_MUM_OP_LOG 0x6
7015 #define MC_CMD_MUM_OP_GPIO 0x7
7017 #define MC_CMD_MUM_OP_READ_SENSORS 0x8
7019 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
7021 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa
7025 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
7029 #define MC_CMD_MUM_OP_QSFP 0xc
7033 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd
7036 #define MC_CMD_MUM_IN_NULL_LEN 4
7038 #define MC_CMD_MUM_IN_CMD_OFST 0
7039 #define MC_CMD_MUM_IN_CMD_LEN 4
7042 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4
7044 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7045 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7050 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7051 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7053 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4
7054 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4
7056 #define MC_CMD_MUM_DEV_HITTITE 0x1
7057 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
7058 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2
7059 /* 32-bit address to read from */
7061 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4
7064 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
7070 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
7071 #define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
7073 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7074 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7076 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
7077 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
7079 /* MC_CMD_MUM_DEV_HITTITE 0x1 */
7080 /* 32-bit address to write to */
7082 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
7085 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
7095 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
7097 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7098 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7100 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
7101 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
7104 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
7107 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
7118 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7119 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7120 #define MC_CMD_MUM_IN_LOG_OP_OFST 4
7121 #define MC_CMD_MUM_IN_LOG_OP_LEN 4
7122 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
7126 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7127 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7128 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */
7129 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */
7132 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
7137 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7138 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7139 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4
7140 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4
7141 #define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4
7142 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
7144 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
7145 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
7146 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
7147 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
7148 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
7149 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
7153 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7154 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7155 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
7156 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
7160 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7161 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7162 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
7163 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
7164 /* The first 32-bit word to be written to the GPIO OUT register. */
7166 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
7167 /* The second 32-bit word to be written to the GPIO OUT register. */
7169 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
7173 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7174 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7175 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
7176 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
7180 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7181 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7182 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
7183 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
7184 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
7186 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
7187 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
7189 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
7193 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7194 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7195 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
7196 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
7200 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7201 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7202 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
7203 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
7204 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4
7207 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
7208 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
7209 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
7210 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
7211 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4
7217 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7218 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7219 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
7220 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
7224 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7225 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7226 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
7227 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
7228 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4
7234 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7235 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7236 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
7237 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
7238 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4
7244 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7245 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7246 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
7247 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
7248 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4
7255 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7256 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7257 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
7258 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
7259 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4
7260 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
7262 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4
7269 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7270 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7271 /* Bit-mask of clocks to be programmed */
7272 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
7273 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
7274 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
7275 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
7276 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
7279 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
7281 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
7293 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7294 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7296 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
7297 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
7300 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
7302 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7303 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7308 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7309 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7310 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4
7311 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4
7312 #define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4
7313 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
7314 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
7315 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
7316 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
7317 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
7318 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
7319 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
7320 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
7322 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4
7326 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7327 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7328 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
7329 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
7331 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
7333 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
7337 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7338 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7339 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
7340 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
7342 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
7344 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
7346 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
7348 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
7352 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7353 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7354 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
7355 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
7357 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
7361 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7362 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7363 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
7364 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
7366 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
7368 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
7372 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7373 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7374 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
7375 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
7377 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
7381 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7382 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7383 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
7384 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
7386 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
7389 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
7391 /* MC_CMD_MUM_IN_CMD_OFST 0 */
7392 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7395 #define MC_CMD_MUM_OUT_LEN 0
7398 #define MC_CMD_MUM_OUT_NULL_LEN 0
7402 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
7403 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
7404 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
7406 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
7413 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
7414 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
7416 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
7423 #define MC_CMD_MUM_OUT_READ_LENMIN 4
7426 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
7427 #define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
7428 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
7429 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
7435 #define MC_CMD_MUM_OUT_WRITE_LEN 0
7438 #define MC_CMD_MUM_OUT_LOG_LEN 0
7441 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
7445 /* The first 32-bit word read from the GPIO IN register. */
7446 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
7447 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
7448 /* The second 32-bit word read from the GPIO IN register. */
7449 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
7450 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
7453 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
7457 /* The first 32-bit word read from the GPIO OUT register. */
7458 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
7459 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
7460 /* The second 32-bit word read from the GPIO OUT register. */
7461 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
7462 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
7465 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
7469 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
7470 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
7471 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
7472 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
7475 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
7476 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
7477 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
7480 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
7483 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
7486 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
7489 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
7492 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
7493 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
7494 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
7495 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
7499 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0
7500 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
7502 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0
7505 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0
7510 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
7511 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
7512 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
7515 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
7518 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
7519 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
7520 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
7523 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
7527 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
7528 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
7529 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
7530 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
7531 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4
7532 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
7534 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4
7539 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
7540 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
7541 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
7547 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
7548 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
7550 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
7551 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
7552 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
7560 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
7561 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
7562 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
7563 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
7566 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
7567 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
7568 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
7575 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
7577 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
7578 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
7579 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0
7580 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
7582 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0
7586 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
7587 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
7597 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
7600 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
7602 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
7604 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
7610 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
7613 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
7614 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
7615 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
7616 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
7617 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
7618 /* enum: Values 5-15 are reserved for future usage */
7619 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
7628 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
7630 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
7632 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
7634 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
7636 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
7638 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
7640 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
7643 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
7653 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
7654 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
7655 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
7658 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
7659 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
7664 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
7669 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
7674 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
7679 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
7691 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
7692 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
7693 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
7695 /* A human-readable name for the sensor (zero terminated string, max 32 bytes)
7697 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
7705 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
7707 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
7709 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
7711 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
7713 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
7715 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
7730 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
7731 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
7732 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
7735 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
7736 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
7741 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
7743 #define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
7745 #define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
7747 #define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
7749 #define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
7751 #define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
7753 #define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
7755 #define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
7765 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
7788 #define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
7794 #define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
7800 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
7801 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
7805 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
7806 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
7810 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
7811 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
7814 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
7815 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
7833 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
7839 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
7842 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
7843 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
7845 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
7846 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
7847 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
7852 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
7855 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
7856 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
7858 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
7860 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
7882 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
7888 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
7891 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
7892 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
7894 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
7895 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
7896 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
7901 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
7904 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
7905 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
7907 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
7909 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
7919 #define MC_CMD_EVENT_CTRL 0x69
7925 #define MC_CMD_EVENT_CTRL_IN_LENMIN 0
7928 #define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
7929 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
7931 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0
7932 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
7933 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0
7937 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0
7940 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1
7942 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2
7944 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3
7946 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4
7948 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5
7951 #define MC_CMD_EVENT_CTRL_OUT_LEN 0
7954 #define EVB_PORT_ID_LEN 4
7955 #define EVB_PORT_ID_PORT_ID_OFST 0
7956 #define EVB_PORT_ID_PORT_ID_LEN 4
7958 #define EVB_PORT_ID_NULL 0x0
7960 #define EVB_PORT_ID_ASSIGNED 0x1000000
7961 /* enum: External network port 0 */
7962 #define EVB_PORT_ID_MAC0 0x2000000
7964 #define EVB_PORT_ID_MAC1 0x2000001
7966 #define EVB_PORT_ID_MAC2 0x2000002
7968 #define EVB_PORT_ID_MAC3 0x2000003
7969 #define EVB_PORT_ID_PORT_ID_LBN 0
7975 #define EVB_VLAN_TAG_VLAN_ID_LBN 0
7978 #define EVB_VLAN_TAG_MODE_WIDTH 4
7980 #define EVB_VLAN_TAG_INSERT 0x0
7982 #define EVB_VLAN_TAG_REPLACE 0x1
7987 #define BUFTBL_ENTRY_OID_OFST 0
7989 #define BUFTBL_ENTRY_OID_LBN 0
7996 /* the raw 64-bit address field from the SMC, not adjusted for page size */
7997 #define BUFTBL_ENTRY_RAWADDR_OFST 4
7999 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
8006 #define NVRAM_PARTITION_TYPE_ID_OFST 0
8009 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
8011 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
8013 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
8015 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
8017 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
8018 /* enum: Expansion ROM configuration data for port 0 */
8019 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
8021 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
8023 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
8025 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
8027 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
8028 /* enum: Non-volatile log output partition */
8029 #define NVRAM_PARTITION_TYPE_LOG 0x700
8030 /* enum: Non-volatile log output of second core on dual-core device */
8031 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
8033 #define NVRAM_PARTITION_TYPE_DUMP 0x800
8035 #define NVRAM_PARTITION_TYPE_LICENSE 0x900
8037 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
8039 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
8041 #define NVRAM_PARTITION_TYPE_FPGA 0xb00
8043 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
8045 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
8047 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
8048 /* enum: Non-volatile log output partition for FC */
8049 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
8051 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
8055 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
8056 /* enum: MUM Non-volatile log output partition. */
8057 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
8059 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
8061 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
8063 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
8065 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
8067 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
8069 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
8071 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
8073 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
8075 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
8079 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
8080 /* enum: Spare partition 4 */
8081 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
8083 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
8087 #define NVRAM_PARTITION_TYPE_STATUS 0x1600
8089 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
8091 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
8093 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
8095 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
8097 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
8099 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
8101 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
8104 #define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
8106 #define NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
8110 #define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
8111 /* enum: Bundle update non-volatile log output partition */
8112 #define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
8114 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
8116 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
8118 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
8120 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
8122 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
8123 #define NVRAM_PARTITION_TYPE_ID_LBN 0
8127 #define LICENSED_APP_ID_LEN 4
8128 #define LICENSED_APP_ID_ID_OFST 0
8129 #define LICENSED_APP_ID_ID_LEN 4
8131 #define LICENSED_APP_ID_ONLOAD 0x1
8133 #define LICENSED_APP_ID_PTP 0x2
8135 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
8137 #define LICENSED_APP_ID_SOLARSECURE 0x8
8139 #define LICENSED_APP_ID_PERF_MONITOR 0x10
8141 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
8143 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
8145 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
8147 #define LICENSED_APP_ID_TCP_DIRECT 0x100
8149 #define LICENSED_APP_ID_LOW_LATENCY 0x200
8151 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
8153 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
8155 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
8157 #define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
8159 #define LICENSED_APP_ID_DSHBRD 0x4000
8161 #define LICENSED_APP_ID_SCATRD 0x8000
8162 #define LICENSED_APP_ID_ID_LBN 0
8168 #define LICENSED_FEATURES_MASK_OFST 0
8170 #define LICENSED_FEATURES_MASK_LO_OFST 0
8171 #define LICENSED_FEATURES_MASK_HI_OFST 4
8172 #define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
8173 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
8175 #define LICENSED_FEATURES_PIO_OFST 0
8178 #define LICENSED_FEATURES_EVQ_TIMER_OFST 0
8181 #define LICENSED_FEATURES_CLOCK_OFST 0
8184 #define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0
8185 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
8187 #define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0
8190 #define LICENSED_FEATURES_RX_SNIFF_OFST 0
8193 #define LICENSED_FEATURES_TX_SNIFF_OFST 0
8196 #define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0
8199 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0
8202 #define LICENSED_FEATURES_MASK_LBN 0
8208 #define LICENSED_V3_APPS_MASK_OFST 0
8210 #define LICENSED_V3_APPS_MASK_LO_OFST 0
8211 #define LICENSED_V3_APPS_MASK_HI_OFST 4
8212 #define LICENSED_V3_APPS_ONLOAD_OFST 0
8213 #define LICENSED_V3_APPS_ONLOAD_LBN 0
8215 #define LICENSED_V3_APPS_PTP_OFST 0
8218 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0
8221 #define LICENSED_V3_APPS_SOLARSECURE_OFST 0
8224 #define LICENSED_V3_APPS_PERF_MONITOR_OFST 0
8225 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4
8227 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0
8230 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0
8233 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0
8236 #define LICENSED_V3_APPS_TCP_DIRECT_OFST 0
8239 #define LICENSED_V3_APPS_LOW_LATENCY_OFST 0
8242 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0
8245 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0
8248 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0
8251 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0
8254 #define LICENSED_V3_APPS_DSHBRD_OFST 0
8257 #define LICENSED_V3_APPS_SCATRD_OFST 0
8260 #define LICENSED_V3_APPS_MASK_LBN 0
8266 #define LICENSED_V3_FEATURES_MASK_OFST 0
8268 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0
8269 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4
8270 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
8271 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
8273 #define LICENSED_V3_FEATURES_PIO_OFST 0
8276 #define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
8279 #define LICENSED_V3_FEATURES_CLOCK_OFST 0
8282 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
8283 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
8285 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
8288 #define LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
8291 #define LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
8294 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
8297 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
8300 #define LICENSED_V3_FEATURES_MASK_LBN 0
8306 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
8308 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
8315 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
8319 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
8323 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
8327 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
8329 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
8331 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
8335 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
8342 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
8343 * be considered as 4 bits selecting which fields are included in the hash. (A
8344 * value 0 effectively disables RSS spreading for the packet type.) The YAML
8346 * but only 4 bits are relevant.
8348 #define RSS_MODE_HASH_SELECTOR_OFST 0
8350 #define RSS_MODE_HASH_SRC_ADDR_OFST 0
8351 #define RSS_MODE_HASH_SRC_ADDR_LBN 0
8353 #define RSS_MODE_HASH_DST_ADDR_OFST 0
8356 #define RSS_MODE_HASH_SRC_PORT_OFST 0
8359 #define RSS_MODE_HASH_DST_PORT_OFST 0
8362 #define RSS_MODE_HASH_SELECTOR_LBN 0
8366 #define CTPIO_STATS_MAP_LEN 4
8368 #define CTPIO_STATS_MAP_VI_OFST 0
8370 #define CTPIO_STATS_MAP_VI_LBN 0
8383 #define MC_CMD_READ_REGS 0x50
8389 #define MC_CMD_READ_REGS_IN_LEN 0
8394 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0
8396 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
8400 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4
8407 * end with an address for each 4k of host memory required to back the EVQ.
8409 #define MC_CMD_INIT_EVQ 0x80
8419 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
8421 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
8422 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
8426 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
8427 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
8431 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
8432 /* The reload value is ignored in one-shot modes */
8434 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
8437 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
8439 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
8451 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
8460 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
8462 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
8464 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
8466 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
8467 /* enum: Hold-off */
8468 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
8471 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
8477 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
8480 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
8482 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
8484 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
8486 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
8488 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
8491 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
8492 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8502 #define MC_CMD_INIT_EVQ_OUT_LEN 4
8504 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
8505 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
8512 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
8514 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
8515 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
8519 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
8520 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
8524 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
8525 /* The reload value is ignored in one-shot modes */
8527 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
8530 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
8532 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
8544 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
8554 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
8556 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
8558 * over-ridden by firmware based on licenses and firmware variant in order to
8562 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
8564 * over-ridden by firmware based on licenses and firmware variant in order to
8568 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
8569 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
8573 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
8578 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
8580 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
8582 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
8584 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
8585 /* enum: Hold-off */
8586 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
8589 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
8595 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
8598 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
8600 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
8602 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
8604 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
8606 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
8609 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
8610 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8622 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
8623 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
8625 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
8626 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
8627 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
8628 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
8630 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
8633 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
8636 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
8642 #define QUEUE_CRC_MODE_MODE_LBN 0
8643 #define QUEUE_CRC_MODE_MODE_WIDTH 4
8645 #define QUEUE_CRC_MODE_NONE 0x0
8647 #define QUEUE_CRC_MODE_FCOE 0x1
8649 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2
8651 #define QUEUE_CRC_MODE_ISCSI 0x3
8653 #define QUEUE_CRC_MODE_FCOIPOE 0x4
8655 #define QUEUE_CRC_MODE_MPA 0x5
8656 #define QUEUE_CRC_MODE_SPARE_LBN 4
8657 #define QUEUE_CRC_MODE_SPARE_WIDTH 4
8663 * arguments end with an address for each 4k of host memory required to back
8666 #define MC_CMD_INIT_RXQ 0x81
8678 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
8680 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
8681 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
8684 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
8685 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
8688 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
8693 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
8696 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
8698 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
8708 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
8723 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
8724 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8726 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
8727 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8741 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
8742 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
8746 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
8747 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
8753 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
8758 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
8761 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
8763 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
8773 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
8785 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
8787 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
8789 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
8792 * multiple fixed-size packet buffers within each bucket. For a full
8793 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
8796 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
8798 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
8805 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
8806 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
8807 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
8808 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
8809 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
8821 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
8822 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8824 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
8825 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8833 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
8838 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
8839 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
8843 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
8844 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
8850 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
8855 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
8858 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
8860 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
8870 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
8882 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
8884 #define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
8886 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
8889 * multiple fixed-size packet buffers within each bucket. For a full
8890 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
8893 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
8895 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
8902 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
8903 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
8904 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
8905 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
8906 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
8918 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
8919 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8921 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
8922 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8930 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
8936 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
8943 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
8949 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
8952 * are still no descriptors then the packet will be dropped. A timeout of 0
8957 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
8964 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0
8965 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
8969 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
8970 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
8976 #define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
8981 #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
8984 #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
8986 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0
8996 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
9008 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
9010 #define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0
9012 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1
9015 * multiple fixed-size packet buffers within each bucket. For a full
9016 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
9019 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
9021 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
9028 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */
9029 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */
9030 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */
9031 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */
9032 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */
9044 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
9045 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
9047 #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
9048 /* 64-bit address of 4k of 4k-aligned host memory buffer */
9056 #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
9062 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
9069 #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
9075 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
9078 * are still no descriptors then the packet will be dropped. A timeout of 0
9083 #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
9086 #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
9088 * to zero if using this message on non-QDMA based platforms. Currently in
9090 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
9096 #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
9103 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
9104 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
9108 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
9109 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
9115 #define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
9120 #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
9123 #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
9125 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
9135 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
9147 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
9149 #define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
9151 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
9154 * multiple fixed-size packet buffers within each bucket. For a full
9155 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
9158 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
9160 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
9167 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
9168 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
9169 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
9170 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
9171 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
9183 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
9184 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
9186 #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
9187 /* 64-bit address of 4k of 4k-aligned host memory buffer */
9195 #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
9201 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
9208 #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
9214 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
9217 * are still no descriptors then the packet will be dropped. A timeout of 0
9222 #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
9225 #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
9227 * to zero if using this message on non-QDMA based platforms. Currently in
9229 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
9235 #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
9242 #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
9245 #define MC_CMD_INIT_RXQ_OUT_LEN 0
9248 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
9251 #define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
9254 #define MC_CMD_INIT_RXQ_V4_OUT_LEN 0
9257 #define MC_CMD_INIT_RXQ_V5_OUT_LEN 0
9263 #define MC_CMD_INIT_TXQ 0x82
9275 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
9277 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
9278 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
9282 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
9283 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
9286 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
9291 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
9294 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
9296 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
9308 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
9309 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
9324 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
9325 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
9327 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
9328 /* 64-bit address of 4k of 4k-aligned host memory buffer */
9342 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
9343 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
9347 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
9348 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
9351 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
9356 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
9359 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
9361 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
9373 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
9374 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
9404 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
9405 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
9407 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
9408 /* 64-bit address of 4k of 4k-aligned host memory buffer */
9418 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
9420 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
9427 #define MC_CMD_INIT_TXQ_OUT_LEN 0
9437 #define MC_CMD_FINI_EVQ 0x83
9443 #define MC_CMD_FINI_EVQ_IN_LEN 4
9447 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
9448 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
9451 #define MC_CMD_FINI_EVQ_OUT_LEN 0
9458 #define MC_CMD_FINI_RXQ 0x84
9464 #define MC_CMD_FINI_RXQ_IN_LEN 4
9466 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
9467 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
9470 #define MC_CMD_FINI_RXQ_OUT_LEN 0
9477 #define MC_CMD_FINI_TXQ 0x85
9483 #define MC_CMD_FINI_TXQ_IN_LEN 4
9485 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
9486 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
9489 #define MC_CMD_FINI_TXQ_OUT_LEN 0
9496 #define MC_CMD_DRIVER_EVENT 0x86
9504 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
9505 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
9506 /* Bits 0 - 63 of event */
9507 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
9509 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
9513 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0
9522 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
9530 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
9531 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
9535 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
9536 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
9540 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
9541 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
9542 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
9543 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
9546 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
9553 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
9563 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)
9564 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
9565 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
9567 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
9568 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
9571 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
9582 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
9588 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
9594 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
9595 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
9596 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
9599 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
9606 #define MC_CMD_FILTER_OP 0x8a
9614 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
9615 #define MC_CMD_FILTER_OP_IN_OP_LEN 4
9616 /* enum: single-recipient filter insert */
9617 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
9618 /* enum: single-recipient filter remove */
9619 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
9620 /* enum: multi-recipient filter subscribe */
9621 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
9622 /* enum: multi-recipient filter unsubscribe */
9623 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
9624 /* enum: replace one recipient with another (warning - the filter handle may
9627 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
9629 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
9631 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
9633 /* The port ID associated with the v-adaptor which should contain this filter.
9636 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
9639 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
9641 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
9653 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
9684 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
9686 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
9688 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
9690 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
9691 /* enum: loop back to TXDP 0 */
9692 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
9694 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
9697 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
9700 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
9702 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
9704 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
9706 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
9709 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
9715 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
9716 /* transmit domain (reserved; set to 0) */
9718 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
9724 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
9726 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
9728 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
9754 /* IP protocol to match (in low byte; set high byte to 0) */
9757 /* Firmware defined register 0 to match (reserved; set to 0) */
9759 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
9760 /* Firmware defined register 1 to match (reserved; set to 0) */
9762 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
9764 * 0 for IPv4 address)
9769 * bytes to 0 for IPv4 address)
9780 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
9781 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
9785 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
9787 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
9789 /* The port ID associated with the v-adaptor which should contain this filter.
9792 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
9795 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
9797 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
9809 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
9882 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
9884 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
9886 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
9888 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
9889 /* enum: loop back to TXDP 0 */
9890 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
9892 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
9895 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
9898 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
9900 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
9902 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
9904 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
9907 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
9913 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
9914 /* transmit domain (reserved; set to 0) */
9916 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
9922 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
9924 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
9926 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
9952 /* IP protocol to match (in low byte; set high byte to 0) */
9955 /* Firmware defined register 0 to match (reserved; set to 0) */
9957 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
9959 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
9963 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
9965 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
9971 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
9973 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
9975 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
9977 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
9983 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
9985 * 0 for IPv4 address)
9990 * bytes to 0 for IPv4 address)
10025 * 0)
10029 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
10030 * to 0)
10033 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
10035 * to 0)
10038 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
10040 * order; set last 12 bytes to 0 for IPv4 address)
10045 * order; set last 12 bytes to 0 for IPv4 address)
10058 #define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
10059 #define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
10063 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
10065 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
10067 /* The port ID associated with the v-adaptor which should contain this filter.
10070 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
10073 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
10075 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
10087 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
10160 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
10162 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
10164 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
10166 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
10167 /* enum: loop back to TXDP 0 */
10168 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
10170 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
10173 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
10176 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
10178 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
10180 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
10182 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
10185 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
10191 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
10192 /* transmit domain (reserved; set to 0) */
10194 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
10200 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
10202 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
10204 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
10230 /* IP protocol to match (in low byte; set high byte to 0) */
10233 /* Firmware defined register 0 to match (reserved; set to 0) */
10235 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
10237 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
10241 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
10243 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
10249 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
10251 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
10253 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
10255 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
10261 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
10263 * 0 for IPv4 address)
10268 * bytes to 0 for IPv4 address)
10303 * 0)
10307 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
10308 * to 0)
10311 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
10313 * to 0)
10316 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
10318 * order; set last 12 bytes to 0 for IPv4 address)
10323 * order; set last 12 bytes to 0 for IPv4 address)
10329 * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything
10334 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
10336 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
10341 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
10346 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
10352 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
10357 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
10358 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4
10363 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
10365 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
10367 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
10370 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
10372 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
10377 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
10378 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
10383 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
10385 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
10387 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
10395 * Get information related to the parser-dispatcher subsystem
10397 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
10403 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
10405 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
10406 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
10408 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
10412 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
10413 /* enum: read properties relating to security rules (Medford-only; for use by
10414 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
10416 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
10421 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
10425 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
10431 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
10432 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
10434 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
10435 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
10439 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
10440 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
10445 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
10446 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
10453 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
10454 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
10458 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
10459 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
10460 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
10461 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
10473 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
10474 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
10476 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0
10477 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
10481 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
10482 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
10487 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
10488 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0
10497 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
10503 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
10506 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
10508 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
10509 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
10516 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
10522 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
10524 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
10525 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
10528 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
10535 #define MC_CMD_ALLOC_VIS 0x8b
10543 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
10544 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
10546 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
10547 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
10549 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
10554 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
10555 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
10559 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
10560 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
10565 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
10566 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
10570 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
10571 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
10572 /* Function's port vi_shift value (always 0 on Huntington) */
10574 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
10582 #define MC_CMD_FREE_VIS 0x8c
10588 #define MC_CMD_FREE_VIS_IN_LEN 0
10591 #define MC_CMD_FREE_VIS_OUT_LEN 0
10598 #define MC_CMD_GET_SRIOV_CFG 0xba
10604 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
10609 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
10610 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
10612 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
10613 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
10615 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
10617 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
10621 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
10624 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
10631 #define MC_CMD_SET_SRIOV_CFG 0xbb
10639 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
10640 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
10642 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
10643 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
10645 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
10647 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
10649 /* RID offset of first VF from PF, or 0 for no change, or
10653 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
10654 /* RID offset of each subsequent VF from the previous, 0 for no change, or
10658 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
10661 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
10669 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
10675 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
10680 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
10681 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
10685 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
10686 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
10687 /* Function's port vi_shift value (always 0 on Huntington) */
10689 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
10696 #define MC_CMD_DUMP_VI_STATE 0x8e
10702 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4
10704 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
10705 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
10710 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
10716 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
10739 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
10741 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
10770 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
10794 /* Reserved, currently 0. */
10805 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
10822 #define MC_CMD_ALLOC_PIOBUF 0x8f
10828 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
10831 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
10833 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
10834 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
10841 #define MC_CMD_FREE_PIOBUF 0x90
10847 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
10849 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
10850 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
10853 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
10863 #define MC_CMD_GET_CAPABILITIES 0xbe
10869 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0
10874 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
10875 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
10876 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0
10879 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0
10880 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
10882 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0
10885 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
10888 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0
10891 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0
10894 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0
10897 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
10900 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
10903 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
10906 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0
10909 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0
10912 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
10915 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0
10918 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0
10921 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0
10924 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0
10927 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0
10930 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0
10933 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0
10936 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0
10939 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0
10942 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0
10945 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0
10948 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0
10951 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0
10954 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
10957 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0
10960 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0
10964 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
10967 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
10969 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
10971 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
10973 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
10975 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
10977 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
10979 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10981 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10983 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10984 /* enum: RXDP Test firmware image 4 */
10985 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10987 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
10989 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10991 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10993 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10995 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10997 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
11002 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
11004 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
11006 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
11008 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
11010 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
11012 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
11014 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
11016 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
11018 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
11022 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
11026 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
11027 /* enum: reserved value - do not use (may indicate alternative interpretation
11030 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
11034 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11037 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11038 /* enum: RX PD firmware with approximately Siena-compatible behaviour
11041 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
11043 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
11045 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
11049 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11051 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
11053 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
11057 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
11059 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
11060 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11061 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
11063 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
11065 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11069 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
11073 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
11077 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
11078 /* enum: reserved value - do not use (may indicate alternative interpretation
11081 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
11085 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
11088 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11089 /* enum: TX PD firmware with approximately Siena-compatible behaviour
11092 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
11094 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
11096 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
11100 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11101 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
11105 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
11107 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
11108 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11109 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
11111 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
11113 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11116 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
11119 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
11122 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
11127 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
11128 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
11129 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0
11132 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0
11133 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
11135 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0
11138 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
11141 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0
11144 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0
11147 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0
11150 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
11153 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
11156 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
11159 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0
11162 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0
11165 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
11168 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0
11171 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0
11174 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0
11177 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0
11180 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0
11183 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0
11186 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0
11189 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0
11192 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0
11195 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0
11198 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0
11201 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0
11204 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0
11207 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
11210 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0
11213 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0
11217 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
11220 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
11222 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
11224 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
11226 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
11228 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
11230 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
11232 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
11234 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
11236 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
11237 /* enum: RXDP Test firmware image 4 */
11238 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
11240 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
11242 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
11244 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
11246 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
11248 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
11250 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
11255 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
11257 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
11259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
11261 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
11263 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
11265 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
11267 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
11269 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
11271 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
11275 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
11279 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
11280 /* enum: reserved value - do not use (may indicate alternative interpretation
11283 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
11287 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11290 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11291 /* enum: RX PD firmware with approximately Siena-compatible behaviour
11294 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
11296 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
11298 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
11302 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11304 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
11306 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
11310 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
11312 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
11313 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11314 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
11316 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
11318 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11322 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
11326 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
11330 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
11331 /* enum: reserved value - do not use (may indicate alternative interpretation
11334 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
11338 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
11341 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11342 /* enum: TX PD firmware with approximately Siena-compatible behaviour
11345 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
11347 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
11349 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
11353 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11354 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
11358 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
11360 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
11361 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11362 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
11364 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
11366 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11369 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
11372 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
11375 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
11377 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
11389 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
11491 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
11493 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
11495 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
11502 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
11510 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
11512 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
11516 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
11537 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
11538 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
11539 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0
11542 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0
11543 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
11545 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0
11548 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
11551 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0
11554 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0
11557 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0
11560 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
11563 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
11566 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
11569 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0
11572 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0
11575 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
11578 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0
11581 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0
11584 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0
11587 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0
11590 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0
11593 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0
11596 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0
11599 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0
11602 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0
11605 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0
11608 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0
11611 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0
11614 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0
11617 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
11620 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0
11623 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0
11627 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
11630 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
11632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
11634 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
11636 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
11638 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
11640 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
11642 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
11644 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
11646 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
11647 /* enum: RXDP Test firmware image 4 */
11648 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
11650 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
11652 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
11654 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
11656 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
11658 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
11660 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
11665 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
11667 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
11669 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
11671 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
11673 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
11675 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
11677 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
11679 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
11681 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
11685 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
11689 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
11690 /* enum: reserved value - do not use (may indicate alternative interpretation
11693 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
11697 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11700 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11701 /* enum: RX PD firmware with approximately Siena-compatible behaviour
11704 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
11706 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
11708 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
11712 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11714 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
11716 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
11720 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
11722 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
11723 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11724 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
11726 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
11728 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11732 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
11736 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
11740 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
11741 /* enum: reserved value - do not use (may indicate alternative interpretation
11744 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
11748 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
11751 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11752 /* enum: TX PD firmware with approximately Siena-compatible behaviour
11755 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
11757 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
11759 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
11763 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11764 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
11768 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
11770 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
11771 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11772 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
11774 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
11776 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11779 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
11782 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
11785 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
11787 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
11799 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
11901 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
11903 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
11905 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
11912 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
11920 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
11922 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
11926 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
11945 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
11950 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
11953 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
11954 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
11955 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
11956 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
11957 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
11959 * (SF-115995-SW) in the present configuration of firmware and port mode.
11964 * (SF-115995-SW) in the present configuration of firmware and port mode.
11972 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
11973 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
11974 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0
11977 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0
11978 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
11980 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0
11983 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
11986 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0
11989 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0
11992 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0
11995 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
11998 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
12001 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
12004 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0
12007 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0
12010 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
12013 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0
12016 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0
12019 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0
12022 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0
12025 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0
12028 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0
12031 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0
12034 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0
12037 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0
12040 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0
12043 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0
12046 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0
12049 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0
12052 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
12055 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0
12058 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0
12062 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
12065 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
12067 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
12069 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
12071 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
12073 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
12075 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
12077 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
12079 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
12081 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
12082 /* enum: RXDP Test firmware image 4 */
12083 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
12085 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
12087 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
12089 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
12091 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
12093 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
12095 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
12100 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
12102 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
12104 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
12106 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
12108 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
12110 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
12112 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
12114 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
12116 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
12120 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
12124 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
12125 /* enum: reserved value - do not use (may indicate alternative interpretation
12128 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
12132 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
12135 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
12136 /* enum: RX PD firmware with approximately Siena-compatible behaviour
12139 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
12141 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
12143 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
12147 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
12149 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
12151 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
12155 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
12157 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
12158 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12159 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
12161 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
12163 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
12167 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
12171 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
12175 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
12176 /* enum: reserved value - do not use (may indicate alternative interpretation
12179 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
12183 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
12186 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
12187 /* enum: TX PD firmware with approximately Siena-compatible behaviour
12190 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
12192 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
12194 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
12198 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
12199 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
12203 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
12205 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
12206 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12207 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
12209 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
12211 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
12214 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
12217 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
12220 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
12222 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
12234 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
12336 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
12338 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
12340 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
12347 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
12355 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
12357 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
12361 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
12380 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
12385 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
12388 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
12389 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
12390 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
12391 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
12392 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
12394 * (SF-115995-SW) in the present configuration of firmware and port mode.
12399 * (SF-115995-SW) in the present configuration of firmware and port mode.
12405 * hold at least this many 64-bit stats values, if they wish to receive all
12415 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
12416 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
12417 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0
12420 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0
12421 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
12423 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0
12426 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
12429 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0
12432 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0
12435 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0
12438 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
12441 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
12444 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
12447 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0
12450 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0
12453 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
12456 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0
12459 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0
12462 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0
12465 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0
12468 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0
12471 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0
12474 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0
12477 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0
12480 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0
12483 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0
12486 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0
12489 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0
12492 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0
12495 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
12498 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0
12501 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0
12505 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
12508 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
12510 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
12512 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
12514 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
12516 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
12518 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
12520 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
12522 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
12524 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
12525 /* enum: RXDP Test firmware image 4 */
12526 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
12528 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
12530 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
12532 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
12534 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
12536 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
12538 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
12543 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
12545 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
12547 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
12549 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
12551 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
12553 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
12555 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
12557 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
12559 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
12563 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
12567 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
12568 /* enum: reserved value - do not use (may indicate alternative interpretation
12571 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
12575 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
12578 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
12579 /* enum: RX PD firmware with approximately Siena-compatible behaviour
12582 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
12584 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
12586 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
12590 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
12592 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
12594 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
12598 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
12600 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
12601 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12602 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
12604 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
12606 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
12610 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
12614 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
12618 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
12619 /* enum: reserved value - do not use (may indicate alternative interpretation
12622 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
12626 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
12629 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
12630 /* enum: TX PD firmware with approximately Siena-compatible behaviour
12633 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
12635 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
12637 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
12641 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
12642 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
12646 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
12648 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
12649 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12650 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
12652 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
12654 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
12657 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
12660 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
12663 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
12665 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
12677 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
12779 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
12781 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
12783 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
12790 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
12798 /* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
12800 /* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
12804 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
12823 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
12828 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
12831 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
12832 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
12833 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
12834 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
12835 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
12837 * (SF-115995-SW) in the present configuration of firmware and port mode.
12842 * (SF-115995-SW) in the present configuration of firmware and port mode.
12848 * hold at least this many 64-bit stats values, if they wish to receive all
12855 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
12858 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
12863 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
12864 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
12865 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0
12868 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0
12869 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
12871 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0
12874 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
12877 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0
12880 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0
12883 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0
12886 #define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
12889 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
12892 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
12895 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0
12898 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0
12901 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
12904 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0
12907 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0
12910 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0
12913 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0
12916 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0
12919 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0
12922 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0
12925 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0
12928 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0
12931 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0
12934 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0
12937 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0
12940 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0
12943 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
12946 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0
12949 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0
12953 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
12956 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
12958 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
12960 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
12962 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
12964 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
12966 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
12968 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
12970 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
12972 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
12973 /* enum: RXDP Test firmware image 4 */
12974 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
12976 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
12978 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
12980 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
12982 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
12984 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
12986 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
12991 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
12993 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
12995 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
12997 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
12999 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
13001 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
13003 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13005 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13007 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
13011 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
13015 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13016 /* enum: reserved value - do not use (may indicate alternative interpretation
13019 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
13023 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13026 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13027 /* enum: RX PD firmware with approximately Siena-compatible behaviour
13030 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13032 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13034 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13038 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13040 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13042 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13046 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13048 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13049 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13050 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13052 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
13054 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13058 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
13062 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
13066 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13067 /* enum: reserved value - do not use (may indicate alternative interpretation
13070 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
13074 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
13077 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13078 /* enum: TX PD firmware with approximately Siena-compatible behaviour
13081 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
13083 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
13085 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
13089 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13090 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
13094 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
13096 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
13097 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13098 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
13100 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
13102 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13105 #define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
13108 #define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
13111 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
13113 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
13125 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
13227 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
13229 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
13231 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
13238 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
13246 /* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
13248 /* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
13252 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
13271 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13276 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13279 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
13280 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13281 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
13282 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13283 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
13285 * (SF-115995-SW) in the present configuration of firmware and port mode.
13290 * (SF-115995-SW) in the present configuration of firmware and port mode.
13296 * hold at least this many 64-bit stats values, if they wish to receive all
13303 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
13306 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
13316 #define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
13322 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0
13323 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
13324 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0
13327 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0
13328 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
13330 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0
13333 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13336 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0
13339 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13342 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0
13345 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13348 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13351 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13354 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0
13357 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0
13360 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13363 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0
13366 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0
13369 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0
13372 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0
13375 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0
13378 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0
13381 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0
13384 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0
13387 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0
13390 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0
13393 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0
13396 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13399 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0
13402 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13405 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0
13408 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0
13412 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
13415 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0
13417 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1
13419 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2
13421 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5
13423 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6
13425 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a
13427 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13429 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13431 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13432 /* enum: RXDP Test firmware image 4 */
13433 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13435 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105
13437 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13439 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13441 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13443 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13445 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c
13450 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0
13452 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1
13454 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3
13456 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5
13458 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6
13460 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d
13462 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13464 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13466 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103
13470 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0
13474 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13475 /* enum: reserved value - do not use (may indicate alternative interpretation
13478 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0
13482 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13485 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13486 /* enum: RX PD firmware with approximately Siena-compatible behaviour
13489 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13491 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13493 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13497 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13499 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13501 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13505 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13507 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13508 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13509 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13511 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa
13513 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13517 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
13521 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0
13525 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13526 /* enum: reserved value - do not use (may indicate alternative interpretation
13529 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0
13533 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
13536 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13537 /* enum: TX PD firmware with approximately Siena-compatible behaviour
13540 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
13542 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
13544 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3
13548 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13549 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
13553 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
13555 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
13556 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13557 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9
13559 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa
13561 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13564 #define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
13567 #define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
13570 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
13572 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0
13584 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
13686 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff
13688 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe
13690 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd
13697 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
13705 /* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
13707 /* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
13711 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
13730 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13735 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13738 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0
13739 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13740 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1
13741 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13742 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2
13744 * (SF-115995-SW) in the present configuration of firmware and port mode.
13749 * (SF-115995-SW) in the present configuration of firmware and port mode.
13755 * hold at least this many 64-bit stats values, if they wish to receive all
13762 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
13765 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
13775 #define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
13779 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
13781 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0
13793 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
13808 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0
13809 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
13810 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0
13813 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0
13814 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
13816 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0
13819 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13822 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0
13825 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13828 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0
13831 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13834 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13837 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13840 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0
13843 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0
13846 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13849 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0
13852 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0
13855 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0
13858 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0
13861 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0
13864 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0
13867 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0
13870 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0
13873 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0
13876 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0
13879 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0
13882 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13885 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0
13888 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13891 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0
13894 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0
13898 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
13901 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0
13903 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1
13905 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2
13907 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5
13909 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6
13911 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a
13913 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13915 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13917 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13918 /* enum: RXDP Test firmware image 4 */
13919 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13921 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105
13923 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13925 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13927 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13929 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13931 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c
13936 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0
13938 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1
13940 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3
13942 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5
13944 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6
13946 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d
13948 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13950 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13952 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103
13956 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0
13960 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13961 /* enum: reserved value - do not use (may indicate alternative interpretation
13964 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0
13968 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13971 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13972 /* enum: RX PD firmware with approximately Siena-compatible behaviour
13975 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13977 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13979 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13983 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13985 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13987 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13991 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13993 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13994 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13995 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13997 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa
13999 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14003 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14007 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0
14011 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14012 /* enum: reserved value - do not use (may indicate alternative interpretation
14015 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0
14019 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14022 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14023 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14026 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14028 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14030 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14034 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14035 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14039 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14041 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14042 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14043 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14045 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa
14047 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14050 #define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
14053 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
14056 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
14058 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0
14070 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
14172 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff
14174 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe
14176 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd
14183 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14191 /* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
14193 /* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
14197 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
14216 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14221 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14224 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0
14225 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14226 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1
14227 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14228 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2
14230 * (SF-115995-SW) in the present configuration of firmware and port mode.
14235 * (SF-115995-SW) in the present configuration of firmware and port mode.
14241 * hold at least this many 64-bit stats values, if they wish to receive all
14248 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14251 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14261 #define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14265 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
14267 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0
14279 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
14290 /* These bits are reserved for communicating test-specific capabilities to
14291 * host-side test software. All production drivers should treat this field as
14302 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0
14303 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
14304 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0
14307 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0
14308 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
14310 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0
14313 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14316 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0
14319 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14322 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0
14325 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14328 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14331 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14334 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0
14337 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0
14340 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14343 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0
14346 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0
14349 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0
14352 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0
14355 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0
14358 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0
14361 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0
14364 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0
14367 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0
14370 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0
14373 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0
14376 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14379 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0
14382 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14385 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0
14388 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0
14392 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
14395 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0
14397 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1
14399 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2
14401 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5
14403 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6
14405 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a
14407 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14409 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14411 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14412 /* enum: RXDP Test firmware image 4 */
14413 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14415 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105
14417 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14419 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14421 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14423 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14425 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c
14430 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0
14432 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1
14434 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3
14436 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5
14438 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6
14440 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d
14442 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14444 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14446 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103
14450 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0
14454 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14455 /* enum: reserved value - do not use (may indicate alternative interpretation
14458 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0
14462 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14465 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14466 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14469 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14471 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14473 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14477 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14479 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14481 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14485 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14487 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14488 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14489 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14491 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa
14493 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14497 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14501 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0
14505 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14506 /* enum: reserved value - do not use (may indicate alternative interpretation
14509 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0
14513 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14516 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14517 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14520 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14522 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14524 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14528 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14529 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14533 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14535 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14536 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14537 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14539 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa
14541 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14544 #define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
14547 #define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
14550 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
14552 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0
14564 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
14666 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff
14668 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe
14670 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd
14677 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14685 /* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
14687 /* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
14691 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
14710 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14715 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14718 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0
14719 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14720 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1
14721 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14722 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2
14724 * (SF-115995-SW) in the present configuration of firmware and port mode.
14729 * (SF-115995-SW) in the present configuration of firmware and port mode.
14735 * hold at least this many 64-bit stats values, if they wish to receive all
14742 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14745 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14755 #define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14759 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
14761 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0
14773 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
14784 /* These bits are reserved for communicating test-specific capabilities to
14785 * host-side test software. All production drivers should treat this field as
14797 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
14803 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
14809 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
14810 /* The maximum number of queues that can be used by an RSS context in even-
14811 * spreading mode. In even-spreading mode the context has no indirection table
14815 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
14821 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
14826 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
14833 #define MC_CMD_V2_EXTN 0x7f
14836 #define MC_CMD_V2_EXTN_IN_LEN 4
14838 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
14851 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
14853 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
14857 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
14864 #define MC_CMD_LINK_PIOBUF 0x92
14872 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
14873 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
14875 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
14876 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
14879 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0
14886 #define MC_CMD_UNLINK_PIOBUF 0x93
14892 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
14894 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
14895 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
14898 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
14903 * allocate and initialise a v-switch.
14905 #define MC_CMD_VSWITCH_ALLOC 0x94
14912 /* The port to connect to the v-switch's upstream port. */
14913 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
14914 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
14915 /* The type of v-switch to create. */
14916 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
14917 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
14919 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
14921 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
14923 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
14925 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
14927 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
14928 /* Flags controlling v-port creation */
14930 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
14932 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
14934 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
14935 * this must be one or greated, and the attached v-ports must have exactly this
14936 * number of tags. For other v-switch types, this must be zero of greater, and
14937 * is an upper limit on the number of VLAN tags for attached v-ports. An error
14939 * v-ports with this number of tags.
14942 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
14945 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
14950 * de-allocate a v-switch.
14952 #define MC_CMD_VSWITCH_FREE 0x95
14958 #define MC_CMD_VSWITCH_FREE_IN_LEN 4
14959 /* The port to which the v-switch is connected. */
14960 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
14961 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
14964 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0
14969 * read some config of v-switch. For now this command is an empty placeholder.
14970 * It may be used to check if a v-switch is connected to a given EVB port (if
14973 #define MC_CMD_VSWITCH_QUERY 0x63
14979 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4
14980 /* The port to which the v-switch is connected. */
14981 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
14982 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
14985 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0
14990 * allocate a v-port.
14992 #define MC_CMD_VPORT_ALLOC 0x96
14999 /* The port to which the v-switch is connected. */
15000 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
15001 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15002 /* The type of the new v-port. */
15003 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
15004 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
15006 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
15008 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
15010 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
15011 /* enum: A normal v-port receives packets which match a specified MAC and/or
15014 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
15015 /* enum: An expansion v-port packets traffic which don't match any other
15016 * v-port.
15018 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
15019 /* enum: An test v-port receives packets which match any filters installed by
15022 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
15023 /* Flags controlling v-port creation */
15025 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
15027 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
15034 * v-switch.
15037 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
15040 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
15042 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
15049 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4
15050 /* The handle of the new v-port */
15051 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
15052 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
15057 * de-allocate a v-port.
15059 #define MC_CMD_VPORT_FREE 0x97
15065 #define MC_CMD_VPORT_FREE_IN_LEN 4
15066 /* The handle of the v-port */
15067 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
15068 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
15071 #define MC_CMD_VPORT_FREE_OUT_LEN 0
15076 * allocate a v-adaptor.
15078 #define MC_CMD_VADAPTOR_ALLOC 0x98
15085 /* The port to connect to the v-adaptor's port. */
15086 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
15087 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15088 /* Flags controlling v-adaptor creation */
15090 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
15092 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
15099 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
15102 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
15105 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
15107 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
15112 /* The MAC address to assign to this v-adaptor */
15116 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
15119 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
15124 * de-allocate a v-adaptor.
15126 #define MC_CMD_VADAPTOR_FREE 0x99
15132 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4
15133 /* The port to which the v-adaptor is connected. */
15134 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
15135 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
15138 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
15143 * assign a new MAC address to a v-adaptor.
15145 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
15152 /* The port to which the v-adaptor is connected. */
15153 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
15154 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
15155 /* The new MAC address to assign to this v-adaptor */
15156 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
15160 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
15165 * read the MAC address assigned to a v-adaptor.
15167 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
15173 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
15174 /* The port to which the v-adaptor is connected. */
15175 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
15176 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
15180 /* The MAC address assigned to this v-adaptor */
15181 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
15187 * read some config of v-adaptor.
15189 #define MC_CMD_VADAPTOR_QUERY 0x61
15195 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
15196 /* The port to which the v-adaptor is connected. */
15197 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
15198 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
15203 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
15204 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
15205 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
15206 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
15207 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
15210 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
15217 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
15225 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
15226 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
15228 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
15229 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
15230 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
15231 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
15233 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
15238 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
15245 #define MC_CMD_RDWR_A64_REGIONS 0x9b
15252 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
15253 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
15254 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
15255 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
15257 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
15259 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
15260 /* Write enable bits 0-3, set to write, clear to read. */
15262 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
15270 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
15271 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
15272 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
15273 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
15275 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
15277 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
15284 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
15290 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
15292 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
15293 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15296 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
15298 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
15299 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
15306 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
15312 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
15314 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
15315 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
15318 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
15325 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
15333 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
15334 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15336 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
15337 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
15341 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
15343 * queues, but the key and indirection table are pre-configured and may not be
15344 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
15346 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
15351 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2
15356 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
15363 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
15368 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0
15369 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
15371 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
15372 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
15376 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0
15378 * queues, but the key and indirection table are pre-configured and may not be
15379 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
15381 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1
15386 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2
15391 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
15398 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
15407 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
15410 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
15412 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
15415 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
15416 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
15418 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
15425 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
15431 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
15433 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
15434 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
15437 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
15444 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
15452 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
15453 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
15454 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
15455 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
15459 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
15466 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
15472 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
15474 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
15475 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
15479 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
15480 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
15490 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
15498 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
15499 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
15500 /* The 128-byte indirection table (1 byte per entry) */
15501 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
15505 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
15514 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
15520 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
15522 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
15523 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
15527 /* The 128-byte indirection table (1 byte per entry) */
15528 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
15534 * Write a portion of a selectable-size indirection table for an RSS context.
15538 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
15547 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))
15548 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)
15550 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0
15551 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4
15552 /* An array of index-value pairs to be written to the table. Structure is
15555 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4
15556 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4
15562 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0
15565 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4
15567 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0
15569 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0
15580 * Read a portion of a selectable-size indirection table for an RSS context.
15584 #define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
15593 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))
15594 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)
15596 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0
15597 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4
15599 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4
15609 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))
15610 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)
15612 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0
15623 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
15631 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
15632 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
15635 * in this case, the MODE fields may be set to non-zero values, and will take
15639 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
15645 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
15646 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
15647 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
15648 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
15650 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
15653 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
15656 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
15659 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
15660 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
15661 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
15662 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
15664 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
15665 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
15667 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
15668 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
15670 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
15671 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
15673 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
15674 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
15676 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
15677 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
15679 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
15682 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
15689 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
15695 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
15697 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
15698 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
15704 * capability), the _EN bits report the state. If any _MODE bits are non-zero
15707 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
15715 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
15716 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
15717 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
15718 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
15720 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
15723 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
15726 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
15729 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
15730 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
15731 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
15732 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
15734 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
15735 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
15737 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
15738 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
15740 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
15741 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
15743 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
15744 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
15746 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
15747 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
15749 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
15754 * Add a MAC address to a v-port
15756 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
15763 /* The handle of the v-port */
15764 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
15765 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
15767 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
15771 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
15776 * Delete a MAC address from a v-port
15778 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
15785 /* The handle of the v-port */
15786 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
15787 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
15789 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
15793 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
15798 * Delete a MAC address from a v-port
15800 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
15806 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
15807 /* The handle of the v-port */
15808 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
15809 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
15812 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
15815 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
15816 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
15818 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
15819 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
15821 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
15823 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
15830 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
15831 * has already been passed to another function (v-port's user), then that
15834 #define MC_CMD_VPORT_RECONFIGURE 0xeb
15841 /* The handle of the v-port */
15842 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
15843 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
15845 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
15846 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
15847 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
15848 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
15850 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
15855 * v-switch.
15858 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
15861 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
15863 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
15870 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
15874 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
15877 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
15878 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
15879 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
15880 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0
15881 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
15887 * read some config of v-port.
15889 #define MC_CMD_EVB_PORT_QUERY 0x62
15895 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4
15896 /* The handle of the v-port */
15897 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
15898 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
15903 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
15904 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
15905 /* The number of VLAN tags that may be used on a v-adaptor connected to this
15908 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
15909 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
15916 #define MC_CMD_GET_CLOCK 0xac
15922 #define MC_CMD_GET_CLOCK_IN_LEN 0
15927 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
15928 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
15930 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
15931 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
15938 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
15944 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
15946 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
15947 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
15950 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
15957 #define MC_CMD_SHMBOOT_OP 0xe6
15963 #define MC_CMD_SHMBOOT_OP_IN_LEN 4
15965 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
15966 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
15968 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
15971 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0
15976 * Adjusts power supply parameters. This is a warranty-voiding operation.
15980 #define MC_CMD_SET_PSU 0xea
15987 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0
15988 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4
15989 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
15990 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4
15991 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4
15992 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
15993 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
15996 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4
15999 #define MC_CMD_SET_PSU_OUT_LEN 0
16006 #define MC_CMD_GET_FUNCTION_INFO 0xec
16012 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
16016 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
16017 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
16018 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
16019 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
16028 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
16034 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
16037 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
16042 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
16044 #define MC_CMD_READ_FUSES 0xf0
16052 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
16053 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
16055 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
16056 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
16059 #define MC_CMD_READ_FUSES_OUT_LENMIN 4
16062 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
16063 #define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)
16065 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
16066 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
16068 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
16070 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
16078 * - not used for V3 licensing
16080 #define MC_CMD_LICENSING 0xf3
16086 #define MC_CMD_LICENSING_IN_LEN 4
16088 #define MC_CMD_LICENSING_IN_OP_OFST 0
16089 #define MC_CMD_LICENSING_IN_OP_LEN 4
16090 /* enum: re-read and apply licenses after a license key partition update; note
16091 * that this operation returns a zero-length response
16093 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
16095 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
16100 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
16101 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
16105 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
16106 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
16109 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
16112 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
16116 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
16121 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
16122 /* licensing subsystem self-test report (for manftest) */
16124 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
16125 /* enum: licensing subsystem self-test failed */
16126 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
16127 /* enum: licensing subsystem self-test passed */
16128 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
16134 * - V3 licensing (Medford)
16136 #define MC_CMD_LICENSING_V3 0xd0
16142 #define MC_CMD_LICENSING_V3_IN_LEN 4
16144 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0
16145 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4
16146 /* enum: re-read and apply licenses after a license key partition update; note
16147 * that this operation returns a zero-length response
16149 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
16153 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
16158 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
16159 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
16163 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
16164 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
16167 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
16170 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
16175 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
16176 /* licensing subsystem self-test report (for manftest) */
16178 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
16179 /* enum: licensing subsystem self-test failed */
16180 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
16181 /* enum: licensing subsystem self-test passed */
16182 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
16204 * partition - V3 licensing (Medford)
16206 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
16212 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
16219 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)
16221 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
16222 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
16224 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
16225 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
16229 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
16240 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
16246 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
16248 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
16249 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
16252 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
16254 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
16255 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
16257 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
16259 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
16268 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
16278 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
16280 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
16281 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
16284 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
16286 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
16287 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
16289 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
16291 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
16300 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
16310 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
16312 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
16313 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
16317 /* states of these features - bit set for licensed, clear for not licensed */
16318 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
16320 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
16321 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
16326 * Perform an action for an individual licensed application - not used for V3
16329 #define MC_CMD_LICENSED_APP_OP 0xf6
16338 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
16339 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)
16341 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
16342 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
16344 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
16345 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
16347 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
16349 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
16352 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
16353 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
16358 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
16361 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
16362 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
16364 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
16365 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
16366 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
16373 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
16374 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
16376 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
16377 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
16385 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
16386 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
16388 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
16394 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
16395 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
16397 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
16398 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
16401 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
16404 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
16409 * Perform validation for an individual licensed application - V3 licensing
16412 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
16420 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
16431 * of two 384-bit integers, r and s, in big-endian order. The signature signs a
16432 * SHA-384 digest of a message constructed from the concatenation of the input
16434 * bytes] ... expiry_time[4 bytes] ...
16436 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
16440 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
16443 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
16445 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
16447 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
16454 /* MAC address of v-adaptor associated with the client. If no such v-adapator
16455 * exists, then the field is filled with 0xFF.
16463 * Mask features - V3 licensing (Medford)
16465 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
16473 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
16475 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
16476 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
16479 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
16481 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
16483 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
16486 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
16493 * SF-116124-SW for an overview of how this could be used. The license is
16497 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
16503 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
16505 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
16506 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
16511 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
16515 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
16519 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
16523 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
16524 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
16526 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
16530 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
16531 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
16532 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
16535 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
16536 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
16537 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
16542 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
16543 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
16545 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
16547 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
16551 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
16553 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
16555 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
16561 * Change configuration related to the parser-dispatcher subsystem.
16563 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
16572 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
16573 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
16575 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
16576 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
16577 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
16580 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
16581 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
16585 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
16589 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
16590 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
16595 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
16601 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
16606 * Read configuration related to the parser-dispatcher subsystem.
16608 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
16616 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
16617 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
16623 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
16624 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
16627 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
16630 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
16631 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
16635 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
16636 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
16646 #define MC_CMD_GET_PORT_MODES 0xff
16652 #define MC_CMD_GET_PORT_MODES_IN_LEN 0
16659 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
16660 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
16662 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
16663 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
16666 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
16673 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 0
16674 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4
16676 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4
16677 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4
16680 #define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4
16691 #define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4
16702 #define MC_CMD_OVERRIDE_PORT_MODE 0x137
16709 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0
16710 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4
16711 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0
16712 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0
16715 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4
16716 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4
16719 #define MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 0
16727 #define MC_CMD_GET_WORKAROUNDS 0x59
16736 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
16737 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
16738 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
16739 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
16741 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
16743 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
16745 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
16747 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
16749 * - before adding code that queries this workaround, remember that there's
16753 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
16755 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
16757 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
16764 #define MC_CMD_PRIVILEGE_MASK 0x5a
16771 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
16772 * 1,3 = 0x00030001
16774 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
16775 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
16776 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0
16777 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
16779 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0
16782 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
16786 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
16787 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
16788 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
16789 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
16790 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
16791 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
16792 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
16794 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
16795 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
16796 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
16797 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
16798 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
16799 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
16803 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
16807 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
16813 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
16817 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
16819 * administrator-level operations that are not allowed from the local host once
16821 * SF-117064-DG for background).
16823 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
16827 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
16830 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
16832 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
16833 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
16840 #define MC_CMD_LINK_STATE_MODE 0x5c
16848 * e.g. VF 1,3 = 0x00030001
16850 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
16851 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
16852 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0
16853 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
16855 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0
16859 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
16860 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
16861 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
16862 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
16863 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
16866 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
16869 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
16870 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
16871 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
16878 #define MC_CMD_FUSE_DIAGS 0x102
16884 #define MC_CMD_FUSE_DIAGS_IN_LEN 0
16888 /* Total number of mismatched bits between pairs in area 0 */
16889 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
16890 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
16891 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
16892 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
16893 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
16894 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
16896 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
16897 /* Checksum of data after logical OR of pairs in area 0 */
16899 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
16902 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
16905 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
16908 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
16911 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
16914 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
16917 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
16920 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
16923 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
16929 * only effects non-admin functions unless the admin privilege itself is
16932 #define MC_CMD_PRIVILEGE_MODIFY 0x60
16940 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
16941 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
16942 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
16943 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
16944 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
16945 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
16946 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
16947 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
16949 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
16950 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
16951 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4
16952 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
16954 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4
16961 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
16966 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
16969 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
16973 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
16975 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
16978 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
16980 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
16981 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
16987 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
16989 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
16997 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
17002 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
17008 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
17011 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
17012 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
17014 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
17016 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0
17017 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
17025 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
17026 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
17027 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
17034 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
17036 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0
17037 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
17043 …- on TX the send descriptor explicitly specifies encapsulation. These rules are per-VNIC, i.e. onl…
17045 #define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
17053 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0
17054 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4
17055 /* Any non-zero bits other than the ones named below or an unsupported
17059 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4
17060 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4
17061 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4
17062 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0
17064 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4
17067 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4
17070 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4
17073 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4
17074 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4
17077 * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used.
17090 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0
17093 * case of IPv4, the IP should be in the first 4 bytes and all other bytes
17105 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0
17112 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4
17115 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4
17117 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0
17118 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4
17125 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
17131 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4
17133 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0
17134 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4
17137 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0
17140 * defined in SF-120734-TC with more information in SF-122717-TC.
17142 #define FUNCTION_PERSONALITY_LEN 4
17143 #define FUNCTION_PERSONALITY_ID_OFST 0
17144 #define FUNCTION_PERSONALITY_ID_LEN 4
17146 #define FUNCTION_PERSONALITY_NULL 0x0
17147 /* enum: Function has an EF100-style function control window and VI windows
17150 #define FUNCTION_PERSONALITY_EF100 0x1
17154 #define FUNCTION_PERSONALITY_VIRTIO_NET 0x2
17158 #define FUNCTION_PERSONALITY_VIRTIO_BLK 0x3
17159 /* enum: Function is a Xilinx acceleration device - management function */
17160 #define FUNCTION_PERSONALITY_ACCEL_MGMT 0x4
17161 /* enum: Function is a Xilinx acceleration device - user function */
17162 #define FUNCTION_PERSONALITY_ACCEL_USR 0x5
17163 #define FUNCTION_PERSONALITY_ID_LBN 0
17171 #define PCIE_FUNCTION_PF_OFST 0
17176 #define PCIE_FUNCTION_PF_ANY 0xfffe
17178 #define PCIE_FUNCTION_PF_NULL 0xffff
17179 #define PCIE_FUNCTION_PF_LBN 0
17187 #define PCIE_FUNCTION_VF_ANY 0xfffe
17191 #define PCIE_FUNCTION_VF_NULL 0xffff
17195 #define PCIE_FUNCTION_INTF_OFST 4
17196 #define PCIE_FUNCTION_INTF_LEN 4
17198 #define PCIE_FUNCTION_INTF_HOST 0x0
17200 #define PCIE_FUNCTION_INTF_AP 0x1