| /linux/arch/alpha/include/asm/ |
| H A D | xor.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
51 .prologue 0 \n\
55 ldq $0,0($17) \n\
56 ldq $1,0($18) \n\
65 ldq $19,32($17) \n\
73 xor $0,$1,$0 # 7 cycles from $1 load \n\
77 stq $0,0($17) \n\
83 xor $19,$20,$19 \n\
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| /linux/lib/zstd/compress/ |
| H A D | clevels.h | 1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
18 /*-===== Pre-defined compression levels =====-*/
25 { /* "default" - for any srcSize > 256 KB */
27 { 19, 12, 13, 1, 6, 1, ZSTD_fast }, /* base for negative levels */
28 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
29 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
30 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
31 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
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| /linux/include/dt-bindings/memory/ |
| H A D | mt8195-memory-port.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
20 * modules dma-address-region larbs-ports
21 * disp 0 ~ 4G larb0/1/2/3
25 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1
26 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
35 #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0)
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| /linux/lib/crypto/arm64/ |
| H A D | sha512-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
17 * assemblers both consider the SHA-512 instructions to be part of the
20 * versions.) "sha3" doesn't make a lot of sense, since SHA-512 is part
21 * of the SHA-2 family of algorithms, and also the Arm Architecture
25 .arch armv8-a+sha3
28 * The SHA-512 round constants
33 .quad 0x428a2f98d728ae22, 0x7137449123ef65cd
34 .quad 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
35 .quad 0x3956c25bf348b538, 0x59f111f1b605d019
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| H A D | sha256-ce.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
12 .arch armv8-a+crypto
51 * The SHA-256 round constants
56 .word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
57 .word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
58 .word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
59 .word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
60 .word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
61 .word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
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| /linux/lib/crypto/powerpc/ |
| H A D | chacha-p10le-8x.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
76 mflr 0
77 std 0, 16(1)
78 stdu 1,-752(1)
85 SAVE_GPR 19, 152, 1
100 SAVE_VRS 20, 0, 9
118 SAVE_VSX 19, 272, 9
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| /linux/arch/alpha/lib/ |
| H A D | csum_ipv6_magic.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
20 .frame $30,0,$26,0
22 .prologue 0
24 ldq_u $0,0($16) # e0 : load src & dst addr words
35 ldq_u $2,0($17) # .. e1 :
39 extql $0,$16,$0 # e0 :
45 or $0,$21,$0 # .. e1 : 1st src word complete
47 addq $20,$0,$20 # .. e1 : begin summing the words
50 cmpult $20,$0,$0 # .. e1 :
64 extwh $19,7,$7 # e0 :
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| H A D | ev6-csum_ipv6_magic.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
29 * Swap <proto> (takes form 0xaabb)
31 * 0xbbaa0000 00000000
32 * Then turn it back into a sign extended 32-bit item
[all …]
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| /linux/arch/arm/mach-rpc/ |
| H A D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #define STAT 0x00
13 #define REQ 0x04
14 #define CLR 0x04
15 #define MASK 0x08
18 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
37 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
38 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
39 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
40 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
[all …]
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| /linux/lib/zlib_inflate/ |
| H A D | inffixed.h | 1 /* inffixed.h -- table for decoding fixed codes
11 {96,7,0},{0,8,80},{0,8,16},{20,8,115},{18,7,31},{0,8,112},{0,8,48},
12 {0,9,192},{16,7,10},{0,8,96},{0,8,32},{0,9,160},{0,8,0},{0,8,128},
13 {0,8,64},{0,9,224},{16,7,6},{0,8,88},{0,8,24},{0,9,144},{19,7,59},
14 {0,8,120},{0,8,56},{0,9,208},{17,7,17},{0,8,104},{0,8,40},{0,9,176},
15 {0,8,8},{0,8,136},{0,8,72},{0,9,240},{16,7,4},{0,8,84},{0,8,20},
16 {21,8,227},{19,7,43},{0,8,116},{0,8,52},{0,9,200},{17,7,13},{0,8,100},
17 {0,8,36},{0,9,168},{0,8,4},{0,8,132},{0,8,68},{0,9,232},{16,7,8},
18 {0,8,92},{0,8,28},{0,9,152},{20,7,83},{0,8,124},{0,8,60},{0,9,216},
19 {18,7,23},{0,8,108},{0,8,44},{0,9,184},{0,8,12},{0,8,140},{0,8,76},
[all …]
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| /linux/arch/arm64/tools/ |
| H A D | sysreg | 1 # SPDX-License-Identifier: GPL-2.0-only
52 # NI - Not implemented
53 # IMP - Implemented
59 Sysreg OSDTRRX_EL1 2 0 0 0 2
61 Field 31:0 DTRRX
64 Sysreg MDCCINT_EL1 2 0 0 2 0
68 Res0 28:0
71 Sysreg MDSCR_EL1 2 0 0 2 2
87 Field 19 SC2
96 Field 0 SS
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| /linux/arch/alpha/kernel/ |
| H A D | entry.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
35 .size \func, . - \func
39 * This defines the normal kernel pt-regs layout.
41 * regs 9-15 preserved by C code
42 * regs 16-18 saved by PAL-code
43 * regs 29-30 saved and set up by PAL-code
44 * JRP - Save regs 16-18 in a special area of the stack, so that
45 * the palcode-provided values are available to the signal handler.
[all …]
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| /linux/Documentation/translations/zh_CN/core-api/ |
| H A D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 3 2 1 0
66 也就是说，CPU可使用的u64的MSByte(7)位于内存偏移量0处，而u64的LSByte(0)位于内存偏移量7处。
[all …]
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| /linux/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
135 #define UNUSED 0
136 { 0, 0, NULL, NULL, 0 },
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
152 #define BB_MASK (0x1f << 11)
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| /linux/include/linux/ |
| H A D | intel_pmt_features.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define PMT_CAP_TELEM BIT(0)
26 #define PMT_CAP_PCPT_CORE_C0_RES BIT(19)
33 #define PMT_CAP_PCET_CORE_CURR_TEMP BIT(19)
46 #define PMT_CAP_RMID_CACHE_PERF BIT(19)
51 #define PMT_CAP_ACCEL_TIP_TELEM BIT(19)
55 #define PMT_CAP_UNCORE_RMID_TELEM BIT(19)
68 #define PMT_CAP_CRASHLOG_POST_RESET BIT(19)
90 #define PMT_CAP_RMID_ACTIVITY BIT(19)
94 FEATURE_INVALID = 0x0,
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| /linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu981_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
28 #define av1_dec_e AV1_DEC_REG(1, 0, 0x1)
29 #define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1)
30 #define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1)
32 #define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1)
34 #define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1)
35 #define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1)
36 #define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1)
37 #define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1)
38 #define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1)
[all …]
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| /linux/include/linux/mfd/syscon/ |
| H A D | imx6q-iomuxc-gpr.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #define IOMUXC_GPR0 0x00
12 #define IOMUXC_GPR1 0x04
13 #define IOMUXC_GPR2 0x08
14 #define IOMUXC_GPR3 0x0c
15 #define IOMUXC_GPR4 0x10
16 #define IOMUXC_GPR5 0x14
17 #define IOMUXC_GPR6 0x18
18 #define IOMUXC_GPR7 0x1c
19 #define IOMUXC_GPR8 0x20
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-sdr-pcu20be.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU20BE:
9 Planar complex unsigned 20-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
18 padded with 0. I value starts first and Q value starts at an offset
20 the 20 bits, bit 19:2 (18 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
28 :stub-columns: 0
30 * - Offset:
[all …]
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| /linux/include/dt-bindings/pinctrl/ |
| H A D | keystone.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
11 #define MUX_MODE0 0
18 #define BUFFER_CLASS_B (0 << 19)
19 #define BUFFER_CLASS_C (1 << 19)
20 #define BUFFER_CLASS_D (2 << 19)
21 #define BUFFER_CLASS_E (3 << 19)
25 #define PIN_PULLDOWN (0 << 17)
27 #define KEYSTONE_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
29 #define K2G_CORE_IOPAD(pa) KEYSTONE_IOPAD_OFFSET((pa), 0x1000)
|
| /linux/drivers/pinctrl/mediatek/ |
| H A D | pinctrl-mt8365.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-mtk-common.h"
15 #include "pinctrl-mtk-mt8365.h"
18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
29 MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
30 MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
[all …]
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| /linux/Documentation/admin-guide/acpi/ |
| H A D | cppc_sysfs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 to request performance levels and to measure per-cpu delivered performance.
27 $ ls -lR /sys/devices/system/cpu/cpu0/acpi_cppc/
29 total 0
30 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
34 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
35 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_freq
[all …]
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| /linux/drivers/accel/habanalabs/include/gaudi/asic_reg/ |
| H A D | tpc0_cfg_masks.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
9 ** This is an auto-generated file **
23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
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| /linux/drivers/net/wireless/mediatek/mt76/mt7603/ |
| H A D | mac.h | 1 /* SPDX-License-Identifier: ISC */
6 #define MT_RXD0_LENGTH GENMASK(15, 0)
18 PKT_TYPE_TXS = 0,
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
53 #define MT_RXD2_NORMAL_CLM BIT(19)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
63 #define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
76 #define MT_RXV1_HT_SHORT_GI BIT(19)
84 #define MT_RXV1_TX_RATE GENMASK(6, 0)
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| /linux/arch/microblaze/include/asm/ |
| H A D | delay.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 "1: addi %0, %0, -1\t\n" \ in __delay()
17 "bneid %0, 1b \t\n" \ in __delay()
20 : "0" (loops)); in __delay()
24 * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so
28 * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226
31 * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and
32 * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280
34 * -- paulus
50 __asm__("mulxuu %0,%1,%2" : "=r" (loops) : in __udelay()
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| /linux/drivers/pinctrl/visconti/ |
| H A D | pinctrl-tmpv7700.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include "pinctrl-common.h"
15 #define tmpv7700_MAGIC_NUM 0x4932f70e
18 #define REG_KEY_CTRL 0x0000
19 #define REG_KEY_CMD 0x0004
20 #define REG_PINMUX1 0x3000
21 #define REG_PINMUX2 0x3004
22 #define REG_PINMUX3 0x3008
23 #define REG_PINMUX4 0x300c
24 #define REG_PINMUX5 0x3010
[all …]
|