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/linux/fs/nls/
H A Dnls_ucs2_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 MODULE_DESCRIPTION("NLS UCS-2");
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
31 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
32 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
33 -32, -32, -32, -32, -32, /* 060-06f */
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dcrop.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later -->
6 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
9 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
17 viewBox="0 0 739.11388 339.6584"
25 …0,0 0,1895 4118,0 L 4118,0 0,0 Z m 3051.62,250.48 8.19,17.01 -46.93,23.31 29.61,-25.515 -38.12,8.5…
27 inkscape:connector-curvature="0"
28 style="clip-rule:evenodd" /></clipPath><clipPath
31 …0,0 0,1895 4118,0 0,-1626 -1,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 …
32 -1,0 0,1 -1,0 0,1 -1,0 0,1 -2,0 0,1 -1,0 0,2 2,0 0,-1 4,0 0,-1 5,0 0,-1 4,0 0,-1 5,0 0,-1 5,0 0,-1 …
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/linux/drivers/media/dvb-frontends/
H A Dstv090x_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #define STV090x_MID 0xf100
16 #define STV090x_OFFST_MRELEASE_FIELD 0
19 #define STV090x_DACR1 0xf113
22 #define STV090x_OFFST_DACR1_VALUE_FIELD 0
25 #define STV090x_DACR2 0xf114
26 #define STV090x_OFFST_DACR2_VALUE_FIELD 0
29 #define STV090x_OUTCFG 0xf11c
31 #define STV090x_WIDTH_OUTSERRS1_HZ_FIELD 1
33 #define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1
[all …]
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
13 # v1.1 defined in version 1.1
19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
[all …]
/linux/include/uapi/linux/
H A Dmap_to_14segment.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
14 * of (ASCII) characters to a 14-segments notation.
17 * See: https://en.wikipedia.org/wiki/Fourteen-segment_display
19 * Notation: +---a---+
23 * +-g1+-g2+
27 * +---d---+
53 * return -EINVAL;
64 #define BIT_SEG14_A 0
65 #define BIT_SEG14_B 1
87 if (c < 0 || c >= sizeof(map->table) / sizeof(map->table[0])) in map_to_seg14()
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H A Dmap_to_7segment.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
10 * of (ASCII) characters to a 7-segments notation.
15 * Notation: +-a-+
17 * +-g-+
19 * +-d-+
45 * return -EINVAL;
52 * 2005-05-31 RFC linux-kernel@vger.kernel.org
57 #define BIT_SEG7_A 0
58 #define BIT_SEG7_B 1
72 return c >= 0 && c < sizeof(map->table) ? map->table[c] : -EINVAL; in map_to_seg7()
[all …]
/linux/arch/arm/mach-omap1/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
15 #include <linux/soc/ti/omap1-io.h>
30 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
31 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
34 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
35 MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
36 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
37 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra234.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
16 #include "pinctrl-tegra.h"
1382 #define PINGROUP_REG_N(r) -1
1385 #define DRV_PINGROUP_N(r) -1
1388 .drv_reg = -1, \
1389 .drv_bank = -1, \
1390 .drvdn_bit = -1, \
1391 .drvup_bit = -1, \
1392 .slwr_bit = -1, \
[all …]
H A Dpinctrl-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
23 #include "pinctrl-tegra.h"
1281 #define PINGROUP_REG_N(r) -1
1284 #define DRV_PINGROUP_N(r) -1
1287 .drv_reg = -1, \
1288 .drv_bank = -1, \
1289 .drvdn_bit = -1, \
1290 .drvup_bit = -1, \
1291 .slwr_bit = -1, \
[all …]
H A Dpinctrl-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "pinctrl-tegra.h"
22 #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
23 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1)
177 /* All non-GPIO pins follow */
178 #define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1)
181 /* Non-GPIO pins */
182 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
183 #define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
1266 #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgf100.c37 { 0x001000, 1, 0x01, 0x00000004 },
38 { 0x0000a9, 1, 0x01, 0x0000ffff },
39 { 0x000038, 1, 0x01, 0x0fac6881 },
40 { 0x00003d, 1, 0x01, 0x00000001 },
41 { 0x0000e8, 8, 0x01, 0x00000400 },
42 { 0x000078, 8, 0x01, 0x00000300 },
43 { 0x000050, 1, 0x01, 0x00000011 },
44 { 0x000058, 8, 0x01, 0x00000008 },
45 { 0x000208, 8, 0x01, 0x00000001 },
46 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
H A Dctxnv50.c23 #define CP_FLAG_CLEAR 0
24 #define CP_FLAG_SET 1
25 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
26 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
27 #define CP_FLAG_SWAP_DIRECTION_SAVE 1
28 #define CP_FLAG_UNK01 ((0 * 32) + 1)
29 #define CP_FLAG_UNK01_CLEAR 0
30 #define CP_FLAG_UNK01_SET 1
31 #define CP_FLAG_UNK03 ((0 * 32) + 3)
32 #define CP_FLAG_UNK03_CLEAR 0
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-kirkwood.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "pinctrl-mvebu.h"
20 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
25 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31 VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
31 PowerPC,8360@0 {
33 reg = <0x0>;
34 d-cache-line-size = <32>; // 32 bytes
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x00000004},
15 {0x70C, 0x00000020},
16 {0x704, 0x601E0100},
17 {0x4000, 0x00000000},
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmtk-mdp3-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
11 #include <media/videobuf2-core.h>
12 #include "mtk-img-ipi.h"
16 * Plane count: 1, 2, 3
17 * H-subsample: 0, 1, 2
18 * V-subsample: 0, 1
19 * Color group: 0-RGB, 1-YUV, 2-raw
24 ((GROUP) << 6) | ((SWAP) << 5) | ((ID) << 0))
26 #define MDP_COLOR_IS_COMPRESS(c) ((0x20000000 & (c)) >> 29)
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-interconnect.json4 "Counter": "0,1",
5 "EventCode": "0x0F",
7 "Experimental": "1",
8 "PerPkg": "1",
10 "UMask": "0x1",
15 "Counter": "0,1",
16 "EventCode": "0x0F",
18 "Experimental": "1",
19 "PerPkg": "1",
21 "UMask": "0x2",
[all …]
/linux/Documentation/input/devices/
H A Dalps.rst1 ----------------------
3 ----------------------
6 ------------
8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
10 Since roughly mid-2010 several new ALPS touchpads have been released and
14 adequate. The design choices were to re-define the alps_model_data
24 different ALPS variants but there did not appear to be a 1:1 mapping.
29 ---------
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-usb2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
43 PHY_STATE_HS_ONLINE = 0,
44 PHY_STATE_DISCONNECT = 1,
50 * enum usb_chg_state - Different states involved in USB charger detection.
62 USB_CHG_STATE_UNDEFINED = 0,
89 * struct rockchip_chg_det_reg - usb charger detect registers
115 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car Display Unit Registers Definitions
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
13 #define DU0_REG_OFFSET 0x00000
14 #define DU1_REG_OFFSET 0x30000
15 #define DU2_REG_OFFSET 0x40000
16 #define DU3_REG_OFFSET 0x70000
18 /* -----------------------------------------------------------------------------
22 #define DSYSR 0x00000 /* display 1 */
23 #define DSYSR_ILTS (1 << 29)
[all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Duncore-memory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x02",
7 "PerPkg": "1",
8 "UMask": "0xf7",
13 "Counter": "0,1,2,3",
14 "EventCode": "0x02",
16 "Experimental": "1",
17 "PerPkg": "1",
18 "UMask": "0xf1",
23 "Counter": "0,1,2,3",
[all …]
/linux/Documentation/tools/rtla/
H A Drtla-timerlat-hist.rst4 rtla-timerlat-hist
6 ------------------------------------------------
8 ------------------------------------------------
10 :Manual section: 1
23 **osnoise:** tracepoints are enabled when using the **-T** option.
39 in the cpus *0-4*, *skipping zero* only lines. Moreover, **rtla timerlat
41 *SCHED_DEADLINE* priority, with a *100us* runtime every *1ms* period. The
42 *1ms* period is also passed to the *timerlat* tracer. Auto-analysis is disabled
45 [root@alien ~]# timerlat hist -d 10m -c 0-4 -P d:100us:1ms -p 1000 --no-aa
48 # Duration: 0 00:10:00
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