| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | clocks.txt | 1 C6X PLL Clock Controllers
2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
18 - reg: base address and size of register area
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | keystone-pll.txt | 1 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
4 PLL is controlled by a PLL controller registers along with memory mapped
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
[all …]
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| H A D | qoriq-clock.txt | 5 multiple phase locked loops (PLL) to create a variety of frequencies
14 --------------- -------------
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
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| H A D | qcom,mmcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniy
[all...] |
| H A D | qca,ath79-pll.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
6 - compatible: has to be "qca,<soctype>-pll" and one of the following
8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
14 - reg: Base address and size of the controllers memory area
15 - clock-names: Name of the input clock, has to be "ref"
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| H A D | vt8500.txt | 1 Device Tree Clock bindings for arch-vt8500
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
15 Required properties for PLL clocks:
16 - reg : shall be the control register offset from PMC base for the pll clock.
[all …]
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| H A D | brcm,iproc-clocks.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
13 - compatible:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
15 Cygnus has a compatible string of "brcm,cygnus-genpll"
17 - #clock-cells:
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
20 - reg:
22 clock control registers required for the PLL
[all …]
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| H A D | fsl,qoriq-clock-legacy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
24 - fsl,qoriq-core-mux-1.0
25 - fsl,qoriq-core-mux-2.0
[all …]
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| H A D | sophgo,sg2042-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 PLL Clock Generator
10 - Chen Wang <unicorn_wang@outlook.com>
14 const: sophgo,sg2042-pll
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
[all …]
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| H A D | silabs,si5351.txt | 5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
22 - clocks: from common clock binding; list of parent clock
[all …]
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| H A D | snps,hsdk-pll-clock.txt | 1 Binding for the HSDK Generic PLL clock
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
12 - reg : should contain base register location and length.
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
17 input_clk: input-clk {
[all …]
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| H A D | snps,pll-clock.txt | 1 Binding for the AXS10X Generic PLL clock
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
17 input-clk: input-clk {
18 clock-frequency = <33333333>;
[all …]
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-cc
[all...] |
| H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
[all …]
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| H A D | fsl,qoriq-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
[all …]
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| H A D | amlogic,c3-pll-clkc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
4 ---
5 $id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic C3 series PLL Clock Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Jerome Brunet <jbrunet@baylibre.com>
13 - Chuan Liu <chuan.liu@amlogic.com>
14 - Xianwei Zhao <xianwei.zhao@amlogic.com>
[all …]
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| H A D | amlogic,a1-peripherals-clkc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Jerome Brunet <jbrunet@baylibre.com>
12 - Jian Hu <jian.hu@jian.hu.com>
13 - Dmitry Rokosov <ddrokosov@sberdevices.ru>
17 const: amlogic,a1-peripherals-clkc
19 '#clock-cells':
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | ti,pcm512x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
13 - $ref: dai-common.yaml#
18 - ti,pcm5121
19 - ti,pcm5122
20 - ti,pcm5141
21 - ti,pcm5142
22 - ti,pcm5242
[all …]
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| H A D | pcm512x.txt | 8 - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141",
11 - reg : the I2C address of the device for I2C, the chip select
14 - AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the
19 - clocks : A clock specifier for the clock connected as SCLK. If this
20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
28 Caution: the TAS-desvices only support gpios 1,2 and 3
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | nvidia,tegra124-xusb.txt | 8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
18 - "fpci"
[all …]
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| H A D | nvidia,tegra124-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
[all …]
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| H A D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra210-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
24 - description: base and length of the XUSB IPFS registers
[all …]
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| H A D | nvidia,tegra194-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
25 reg-names:
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | allwinner,sun4i-a10-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Chen-Yu Tsai <wens@csie.org>
15 - Maxime Ripard <mripard@kernel.org>
20 - const: allwinner,sun4i-a10-hdmi
21 - const: allwinner,sun5i-a10s-hdmi
22 - const: allwinner,sun6i-a31-hdmi
23 - items:
[all …]
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| /freebsd/sys/dev/clk/allwinner/ |
| H A D | ccu_a13.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/reset/sun5i-ccu.h>
50 /* Non-exported clocks */
101 CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
103 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
104 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
105 CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
106 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
[all …]
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