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/linux/drivers/clk/mediatek/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
6 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
7 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
8 obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
9 obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
10 obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
[all …]
/linux/drivers/clk/imx/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
[all …]
H A Dclk-vf610.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
8 #include <linux/clk.h>
10 #include <dt-bindings/clock/vf610-clock.h>
12 #include "clk.h"
113 static struct clk *clk[VF610_CLK_END]; variable
131 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
137 if (IS_ERR(clk)) in vf610_get_fixed_clock()
138 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
[all …]
H A Dclk-imx5.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/imx5-clock.h>
19 #include "clk.h"
65 /* Low-power Audio Playback Mode clock */
128 static struct clk *clk[IMX5_CLK_END]; variable
133 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx5_clocks_common_init()
134 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in mx5_clocks_common_init()
135 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in mx5_clocks_common_init()
[all …]
H A Dclk-imx27.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk.h>
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/imx27-clock.h>
13 #include "clk.h"
48 static struct clk *clk[IMX27_CLK_MAX]; variable
55 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
56 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
57 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
58 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
[all …]
H A Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
20 #include "clk-scu.h"
44 * struct clk_scu - Description of one SCU clock
62 * struct clk_gpr_scu - Description of one SCU GPR clock
78 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
82 * @clk: clk type of this resource
[all …]
H A Dclk-imx35.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
15 #include "clk.h"
82 static struct clk *clk[clk_max]; variable
97 if (!aad->arm) { in _mx35_clocks_init()
98 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); in _mx35_clocks_init()
106 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
107 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
[all …]
H A Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk.h>
18 #include "clk.h"
75 static struct clk *clk[clk_max]; variable
81 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
84 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
85 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
86 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
[all …]
H A Dclk-imx31.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk.h>
16 #include "clk.h"
50 static struct clk *clk[clk_max]; variable
55 clk[dummy] = imx_clk_fixed("dummy", 0); in _mx31_clocks_init()
56 clk[ckih] = imx_clk_fixed("ckih", fref); in _mx31_clocks_init()
57 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx31_clocks_init()
58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
59 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
60 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); in _mx31_clocks_init()
[all …]
/linux/drivers/sh/clk/
H A Dcpg.c5 * Copyright (C) 2010 - 2012 Paul Mundt
11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
[all …]
H A Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
[all …]
/linux/arch/mips/lantiq/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk.h>
23 #include "clk.h"
27 static struct clk cpu_clk_generic[4];
38 struct clk *clk_get_cpu(void) in clk_get_cpu()
43 struct clk *clk_get_fpi(void) in clk_get_fpi()
49 struct clk *clk_get_io(void) in clk_get_io()
55 struct clk *clk_get_ppe(void) in clk_get_ppe()
61 static inline int clk_good(struct clk *clk) in clk_good() argument
63 return clk && !IS_ERR(clk); in clk_good()
[all …]
/linux/drivers/clk/st/
H A Dclk-flexgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
36 /* Pre-divisor's gate */
38 /* Pre-divisor */
56 struct clk_hw *pgate_hw = &flexgen->pgate.hw; in flexgen_enable()
57 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_enable()
[all …]
/linux/arch/m68k/coldfire/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
5 * clk.c -- general ColdFire CPU kernel clk handling
16 #include <linux/clk.h>
31 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
33 clk->enabled = 1; in __clk_init_enabled()
34 clk->clk_ops->enable(clk); in __clk_init_enabled()
37 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
39 clk->enabled = 0; in __clk_init_disabled()
40 clk->clk_ops->disable(clk); in __clk_init_disabled()
43 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
[all …]
/linux/drivers/clk/ux500/
H A Du8500_of_clk.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
16 #include "reset-prcc.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
[all …]
H A Dclk-sysctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/abx500/ab8500-sysctrl.h>
16 #include "clk.h"
38 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_prepare() local
40 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare()
41 clk->reg_bits[0]); in clk_sysctrl_prepare()
43 if (!ret && clk->enable_delay_us) in clk_sysctrl_prepare()
44 usleep_range(clk->enable_delay_us, clk->enable_delay_us + in clk_sysctrl_prepare()
[all …]
/linux/kernel/time/
H A Dposix-clock.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/posix-clock.h>
15 #include "posix-timers.h"
22 struct posix_clock_context *pccontext = fp->private_data; in get_posix_clock()
23 struct posix_clock *clk = pccontext->clk; in get_posix_clock() local
25 down_read(&clk in get_posix_clock()
35 put_posix_clock(struct posix_clock * clk) put_posix_clock() argument
44 struct posix_clock *clk = get_posix_clock(fp); posix_clock_read() local
61 struct posix_clock *clk = get_posix_clock(fp); posix_clock_poll() local
79 struct posix_clock *clk = get_posix_clock(fp); posix_clock_ioctl() local
98 struct posix_clock *clk = get_posix_clock(fp); posix_clock_compat_ioctl() local
116 struct posix_clock *clk = posix_clock_open() local
151 struct posix_clock *clk; posix_clock_release() local
182 posix_clock_register(struct posix_clock * clk,struct device * dev) posix_clock_register() argument
202 posix_clock_unregister(struct posix_clock * clk) posix_clock_unregister() argument
216 struct posix_clock *clk; global() member
[all...]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dbase.c41 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, in nvkm_clk_adjust() argument
44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
76 * C-States
79 nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, in nvkm_cstate_valid() argument
82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid()
83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid()
86 while (domain && domain->name != nv_clk_src_max) { in nvkm_cstate_valid()
87 if (domain->flags & NVKM_CLK_DOM_FLAG_VPSTATE) { in nvkm_cstate_valid()
88 u32 freq = cstate->domain[domain->name]; in nvkm_cstate_valid()
89 switch (clk->boost_mode) { in nvkm_cstate_valid()
[all …]
H A Dgm20b.c23 #include <subdev/clk.h>
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
168 pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) & in gm20b_pllg_read_mnp()
173 gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll) in gm20b_pllg_write_mnp() argument
[all …]
/linux/drivers/clk/spear/
H A Dspear3xx_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
11 #include <linux/clk/spear.h>
16 #include "clk.h"
30 /* CORE CLK CFG register masks */
141 struct clk *clk; in spear300_clk_init() local
143 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
145 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
147 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
149 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
[all …]
H A Dspear1340_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/spear1340_clock.c
12 #include <linux/clk/spear.h>
16 #include "clk.h"
175 /* vco-pll4 rate configuration table, in ascending order of rates */
205 * --------------------------------------------------------------------
207 * --------------------------------------------------------------------
212 * --------------------------------------------------------------------
218 * --------------------------------------------------------------------
224 * --------------------------------------------------------------------
[all …]
H A Dspear1310_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/spear1310_clock.c
12 #include <linux/clk/spear.h>
16 #include "clk.h"
241 /* vco-pll4 rate configuration table, in ascending order of rates */
262 /* For gmac phy input clk */
310 /* For parent clk = 49.152 MHz */
317 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
318 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
322 /* For parent clk = 49.152 MHz */
[all …]
H A Dspear6xx_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk/spear.h>
13 #include "clk.h"
27 /* CORE CLK CFG register masks */
116 struct clk *clk, *clk1; in spear6xx_clk_init() local
118 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear6xx_clk_init()
119 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
121 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); in spear6xx_clk_init()
122 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
124 /* clock derived from 32 KHz osc clk */ in spear6xx_clk_init()
[all …]
/linux/arch/arm/mach-omap1/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
17 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/soc/ti/omap1-io.h>
23 #include <asm/mach-types.h>
33 /* provide direct internal access (not via clk API) to some clocks */
47 unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate) in omap1_uart_recalc() argument
49 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
[all …]
/linux/drivers/clk/ti/
H A Dautoidle.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
15 #include <linux/clk/ti.h>
32 * we have some non-atomic read/write
39 static int _omap2_clk_deny_idle(struct clk_hw_omap *clk) in _omap2_clk_deny_idle() argument
41 if (clk->ops && clk->ops->deny_idle) { in _omap2_clk_deny_idle()
45 clk->autoidle_count++; in _omap2_clk_deny_idle()
46 if (clk->autoidle_count == 1) in _omap2_clk_deny_idle()
47 clk->ops->deny_idle(clk); in _omap2_clk_deny_idle()
[all …]

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