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/linux/drivers/media/platform/ti/omap3isp/
H A Dnoise_filter_table.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Noise filter table
16 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
17 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31
/linux/arch/powerpc/lib/
H A Dfeature-fixups-test.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <asm/feature-fixups.h>
9 #include <asm/asm-compat.h>
10 #include <asm/ppc-opcode.h>
48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
30 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
39 …_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
78 …_SET_DST_PITCH_V 31:0
81 …_SET_DST_WIDTH_V 31:0
84 …_SET_DST_HEIGHT_V 31:0
90 …_SET_DST_OFFSET_LOWER_V 31:0
130 …_SET_SRC_PITCH_V 31:0
[all …]
H A Dcl902d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
31 …_WAIT_FOR_IDLE_V 31:0
82 …_SET_DST_PITCH_V 31:0
85 …_SET_DST_WIDTH_V 31:0
88 …_SET_DST_HEIGHT_V 31:0
94 …_SET_DST_OFFSET_LOWER_V 31:0
146 …_SET_SRC_PITCH_V 31:0
149 …_SET_SRC_WIDTH_V 31:0
152 …_SET_SRC_HEIGHT_V 31:0
158 …_SET_SRC_OFFSET_LOWER_V 31:0
[all …]
H A Dcl5039.h2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
30 …_NO_OPERATION_V 31:0
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
65 …_SET_SRC_WIDTH_V 31:0
68 …_SET_SRC_HEIGHT_V 31:0
71 …_SET_SRC_DEPTH_V 31:0
74 …_SET_SRC_LAYER_V 31:0
78 …_SET_SRC_ORIGIN_Y 31:16
[all …]
/linux/arch/powerpc/xmon/
H A Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
173 /* The BD field in a B form instruction when the - modifier is used.
179 /* The BD field in a B form instruction when the - modifier is used
224 /* The BO field in a B form instruction when the + or - modifier is
254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
411 /* If the FXM4 operand is omitted, use the sentinel value -1. */
412 { -1, -1, NULL, NULL, 0},
[all …]
/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v2.4
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
15 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf supported
16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 -
[all...]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
90 /* MAC-Level Diagnostic Counters */
95 .start = 31,
119 /* MAC-Level Diagnostic Flags */
260 /* High-Level Diagnostic Counters */
265 .start = 31,
272 .start = 31,
279 .start = 31,
286 .start = 31,
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
/linux/drivers/hid/intel-thc-hid/intel-thc/
H A Dintel-thc-hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
247 #define THC_CFG_DID_VID_DID GENMASK(31, 16)
269 #define THC_CFG_STS_CMD_DPE BIT(31)
274 #define THC_CFG_CC_RID_BCC GENMASK(31, 24)
285 #define THC_CFG_BAR0_LOW_MEMBAR GENMASK(31, 15)
286 #define THC_CFG_BAR0_HI_MEMBAR GENMASK(31, 0)
289 #define THC_CFG_SID_SVID_SSID GENMASK(31, 16)
307 #define THC_CFG_MSIMA_MADDR GENMASK(31, 2)
308 #define THC_CFG_MSIMUA_MAUDDR GENMASK(31, 0)
319 #define THC_CFG_PMCAP_PMNP_PMCID_PMES GENMASK(31, 27)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD0_Q_IDX GENMASK(31, 25)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
67 #define MT_TXD2_FIX_RATE BIT(31)
83 #define MT_TXD3_SN_VALID BIT(31)
97 #define MT_TXD4_PN_LOW GENMASK(31, 0)
99 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
107 #define MT_TXD6_TX_IBF BIT(31)
119 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
[all …]
/linux/lib/crypto/powerpc/
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-ciu2-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 #define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31)…
32 #define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31)…
33 …EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
34 …N_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
35 …N_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
36 …X_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
37 …X_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
161 * DF2 DramBaseAddr [31:12]
162 * DF3 DramBaseAddr [31:12]
163 * DF3p5 DramBaseAddr [31:12]
171 #define DF2_BASE_ADDR GENMASK(31, 12)
183 * DF2 DramHoleBase [31:24]
184 * DF3 DramHoleBase [31:24]
185 * DF3p5 DramHoleBase [31:24]
188 * DF4 DramHoleBase [31:24]
189 * DF4p5 DramHoleBase [31:24]
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
18 /* Bits 5-31 reserved */
41 /* Bits 17-31 reserved */
52 /* Bits 22-23 reserved */
54 /* Bits 25-31 reserved */
61 [MEM_BADDR] = GENMASK(31, 16),
69 /* Bits 8-31 reserved */
83 /* Bits 1-3 reserved */
85 /* Bits 5-7 reserved */
[all …]
H A Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
16 [PROD_LOWEST] = GENMASK(31, 24),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
83 [DRBIP] = BIT(31),
95 /* Bits 29-31 reserved */
102 [MEM_BADDR] = GENMASK(31, 16),
110 /* Bits 8-31 reserved */
[all …]
H A Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
16 [PROD_LOWEST] = GENMASK(31, 24),
45 /* Bits 28-29 reserved */
47 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
84 [DRBIP] = BIT(31),
96 /* Bits 29-31 reserved */
103 [MEM_BADDR] = GENMASK(31, 16),
111 /* Bits 8-31 reserved */
119 /* Bits 8-15 reserved */
[all …]
H A Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
31 /* Bits 21-31 reserved */
67 /* Bits 30-31 reserved */
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
87 [MEM_BADDR] = GENMASK(31, 16),
95 /* Bits 8-31 reserved */
103 /* Bits 8-15 reserved */
105 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
[all …]
H A Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
18 /* Bits 5-31 reserved */
46 /* Bits 22-31 reserved */
57 /* Bits 22-23 reserved */
59 /* Bits 25-31 reserved */
66 [MEM_BADDR] = GENMASK(31, 16),
74 /* Bits 8-31 reserved */
88 /* Bits 1-3 reserved */
90 /* Bits 5-7 reserved */
[all …]
H A Dipa_reg-v4.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
32 /* Bits 22-31 reserved */
69 /* Bit 31 reserved */
80 /* Bits 22-23 reserved */
82 /* Bits 25-31 reserved */
89 [MEM_BADDR] = GENMASK(31, 16),
97 /* Bits 8-31 reserved */
105 /* Bits 8-15 reserved */
107 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
[all …]
H A Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
36 /* Bits 24-29 reserved */
38 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
75 [DRBIP] = BIT(31),
86 /* Bits 22-23 reserved */
88 /* Bits 25-31 reserved */
95 [MEM_BADDR] = GENMASK(31, 16),
103 /* Bits 8-31 reserved */
111 /* Bits 8-15 reserved */
[all …]
/linux/arch/alpha/include/asm/
H A Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
402 ldq $31, 0($17) \n\
403 ldq $31, 0($18) \n\
405 ldq $31, 64($17) \n\
406 ldq $31, 64($18) \n\
408 ldq $31, 128($17) \n\
409 ldq $31, 128($18) \n\
411 ldq $31, 192($17) \n\
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
75 #define MT_RXD6_QOS_CTL GENMASK(31, 16)
77 #define MT_RXD7_HT_CONTROL GENMASK(31, 0)
79 #define MT_RXV1_ACID_DET_H BIT(31)
95 #define MT_RXV2_SEL_ANT BIT(31)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
20 KERNEL_MODULE = base.KernelModule("hid-multitouch", "hid_multitouch")
310 Unit Exponent (-1)
335 Unit Exponent (-4)
378 Unit Exponent (-1)
397 Unit Exponent (-4)
442 Unit Exponent (-1)
467 Unit Exponent (-4)
492 …31 81 02 45 00 c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00…
[all …]

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