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/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dtaprio.json4 "name": "Add taprio Qdisc to multi-queue device (8 queues)",
15 "cmdUnderTest": "$TC qdisc add dev $ETH root handle 1: taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2
46 { global() object
148 "$IP link set dev $ETH up", global() string
174 "./scripts/taprio_wait_for_admin.sh $TC $ETH" global() string
200 "./scripts/taprio_wait_for_admin.sh $TC $ETH" global() string
218 "cbs" global() string
243 "cbs" global() string
[all...]
/linux/arch/x86/platform/ce4100/
H A Dfalconfalls.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "intel,ce4100-cp";
32 ioapic1: interrupt-controller@fec00000 {
[all …]
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_security.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
12 * goya_set_block_as_protected - set the given block as protected
20 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; in goya_pb_set_block()
68 word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
8 #include <linux/dma-mapping.h>
16 #include <linux/pci-ats.h>
23 #include <media/ipu-bridge.h>
24 #include <media/ipu6-pci-table.h>
27 #include "ipu6-bus.h"
28 #include "ipu6-buttress.h"
29 #include "ipu6-cpd.h"
30 #include "ipu6-isys.h"
[all …]
/linux/arch/xtensa/variants/de212/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
40 /* Save area for non-coprocessor optional and custom (TIE) state: */
45 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
62 * galign = group byte alignment (power of 2) (galign >= align)
63 * align = register byte alignment (power of 2)
66 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
68 * regnum = reg index in regfile, or special/TIE-user reg number
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv090x_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
48 #define STV090x_OFFST_SSTREAM_LCK_1_FIELD 2
66 #define STV090x_OFFST_SPKTDEL_LOCK_2_FIELD 2
76 #define STV090x_OFFST_SDEMOD_LOCKB_2_FIELD 2
94 #define STV090x_OFFST_SDISEQC2TX_IRQ_FIELD 2
108 #define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2
126 #define STV090x_OFFST_MPKTDEL_LOCK_2_FIELD 2
144 #define STV090x_OFFST_MDEMOD_LOCKB_2_FIELD 2
162 #define STV090x_OFFST_MDISEQC2TX_IRQ_FIELD 2
173 #define STV090x_WIDTH_12CADDR_INC_FIELD 2
[all …]
/linux/arch/arm64/crypto/
H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
16 .set .Lv\b\().2d, \b
21 * ARMv8.2 Crypto Extensions instructions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
[all …]
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
17 .set .Lv\b\().2d, \b
37 * The SHA-512 round constants
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
91 add v\i3\().2d, v\i3\().2d, v5.2d
94 sha512su0 v\in0\().2d, v\in1\().2d
[all …]
/linux/arch/xtensa/variants/csp/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
63 /* Save area for non-coprocessor optional and custom (TIE) state: */
68 #define XCHAL_TOTAL_SA_SIZE 48 /* with 16-byte align padding */
81 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
82 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
85 * galign = group byte alignment (power of 2) (galign >= align)
86 * align = register byte alignment (power of 2)
89 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
91 * regnum = reg index in regfile, or special/TIE-user reg number
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-truly-nt35597.c1 // SPDX-License-Identifier: GPL-2.0
64 struct mipi_dsi_device *dsi[2];
76 { { 0xff, 0x20 }, 2 },
77 { { 0xfb, 0x01 }, 2 },
78 { { 0x00, 0x01 }, 2 },
79 { { 0x01, 0x55 }, 2 },
80 { { 0x02, 0x45 }, 2 },
81 { { 0x05, 0x40 }, 2 },
82 { { 0x06, 0x19 }, 2 },
83 { { 0x07, 0x1e }, 2 },
[all …]
/linux/tools/testing/selftests/drivers/net/mlxsw/spectrum/
H A Dvxlan_flooding_ipv6.sh2 # SPDX-License-Identifier: GPL-2.0
9 # +-----------------------+
13 # +----|------------------+
15 # +----|----------------------------------------------------------------------+
17 # | +--|--------------------------------------------------------------------+ |
21 # | | local 2001:db8:2::1 | |
22 # | | remote 2001:db8:2::{2..21} | |
24 # | +-----------------------------------------------------------------------+ |
26 # | 2001:db8:2::0/64 via 2001:db8:3::2 |
30 # +----|----------------------------------------------------------------------+
[all …]
/linux/sound/firewire/dice/
H A Ddice-weiss.c1 // SPDX-License-Identifier: GPL-2.0
2 // dice-weiss.c - a part of driver for DICE based devices
13 // Weiss DAC202: 192kHz 2-channel DAC
15 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
16 .rx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
19 // Weiss MAN301: 192kHz 2-channel music archive network player
21 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
22 .rx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
25 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire nterface
27 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
[all …]
/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
88 * galign = group byte alignment (power of 2) (galign >= align)
89 * align = register byte alignment (power of 2)
92 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-extra-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 clk32k_out1: clk32k-out1 {
19 <2 RK_PC5 1 &pcfg_pull_none>;
25 /omit-if-no-ref/
26 eth0_pins: eth0-pins {
29 <2 RK_PC3 1 &pcfg_pull_none>;
35 /omit-if-no-ref/
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
[all …]
/linux/drivers/mfd/
H A Dqcom_rpm.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/mfd/qcom-rpm.h>
60 #define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
61 #define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
62 #define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
94 [QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
95 [QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
96 [QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
97 [QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
98 [QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
[all …]
/linux/drivers/staging/fbtft/
H A Dfb_ssd1331.c1 // SPDX-License-Identifier: GPL-2.0
16 #define DEFAULT_GAMMA "0 2 2 2 2 2 2 2 " \
17 "2 2 2 2 2 2 2 2 " \
18 "2 2 2 2 2 2 2 2 " \
19 "2 2 2 2 2 2 2 2 " \
20 "2 2 2 2 2 2 2 2 " \
21 "2 2 2 2 2 2 2 2 " \
22 "2 2 2 2 2 2 2 2 " \
23 "2 2 2 2 2 2 2" \
27 par->fbtftops.reset(par); in init_display()
[all …]
H A Dfb_ssd1351.c1 // SPDX-License-Identifier: GPL-2.0
18 #define DEFAULT_GAMMA "0 2 2 2 2 2 2 2 " \
[all...]
/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
88 * galign = group byte alignment (power of 2) (galign >= align)
89 * align = register byte alignment (power of 2)
92 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
[all …]
/linux/arch/mips/kernel/
H A Dmips-r2-to-r6-emul.c28 #include <asm/mips-r2-to-r6-emul.h>
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
101 return -SIGFPE; in mipsr6_emul()
106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
107 regs->regs[MIPSInst_RS(ir)] | in mipsr6_emul()
[all …]
/linux/drivers/video/fbdev/
H A Datafb_utils.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 * would be faster. I suspect not for simple text system - not much
30 * Unaligned read/write used requires 68020+ - think this is a problem?
55 " lsr.l #1,%1 ; jcc 1f ; move.b %2,-(%0)\n" in fb_memclear_small()
56 "1: lsr.l #1,%1 ; jcc 1f ; move.w %2,-(%0)\n" in fb_memclear_small()
57 "1: lsr.l #1,%1 ; jcc 1f ; move.l %2,-(%0)\n" in fb_memclear_small()
58 "1: lsr.l #1,%1 ; jcc 1f ; move.l %2,-(%0) ; move.l %2,-(%0)\n" in fb_memclear_small()
65 " move.l %2,%%d4; move.l %2,%%d5; move.l %2,%%d6\n" in fb_memclear_small()
66 "2: movem.l %2/%%d4/%%d5/%%d6,-(%0)\n" in fb_memclear_small()
67 " dbra %1,2b\n" in fb_memclear_small()
[all …]
/linux/tools/testing/selftests/drivers/net/mlxsw/spectrum-2/
H A Dvxlan_flooding_ipv6.sh2 # SPDX-License-Identifier: GPL-2.0
9 # +-----------------------+
13 # +----|------------------+
15 # +----|----------------------------------------------------------------------+
17 # | +--|--------------------------------------------------------------------+ |
21 # | | local 2001:db8:2::1 | |
22 # | | remote 2001:db8:2::{2..17} | |
24 # | +-----------------------------------------------------------------------+ |
26 # | 2001:db8:2::0/64 via 2001:db8:3::2 |
30 # +----|----------------------------------------------------------------------+
[all …]
/linux/drivers/hte/
H A Dhte-tegra194.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 NVIDIA Corporation
28 #define NV_AON_SLICE_INVALID -1
35 /* AON HTE line map For slice 2 */
38 #define NV_AON_HTE_SLICE2_IRQ_GPIO_2 2
80 #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN)
142 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
143 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
144 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
145 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
[all …]
/linux/Documentation/hwmon/
H A Dir35221.rst9 Addresses scanned: -
13 Author: Samuel Mendoza-Jonas <sam@mendozajonas.com>
17 -----------
19 IR35221 is a Digital DC-DC Multiphase Converter
23 -----------
32 # echo ir35221 0x70 > /sys/bus/i2c/devices/i2c-4/new_device
36 ----------------
44 curr[2-3]_label "iout[1-2]"
45 curr[2-3]_input Measured output current
46 curr[2-3]_crit Critical maximum current
[all …]
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
[all …]

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