Lines Matching +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 NVIDIA Corporation
28 #define NV_AON_SLICE_INVALID -1
35 /* AON HTE line map For slice 2 */
38 #define NV_AON_HTE_SLICE2_IRQ_GPIO_2 2
80 #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN)
142 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
143 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
144 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
145 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
146 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
147 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
148 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
149 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
151 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
152 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
153 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
154 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
156 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
157 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
158 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
159 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
160 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
161 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
162 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
163 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
165 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
166 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
167 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
171 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
172 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
173 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
174 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
175 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
181 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
182 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
183 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
184 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
185 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
186 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
187 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
188 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
190 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
191 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
192 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
193 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
199 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
200 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
201 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
202 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
203 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
204 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
205 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
206 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
208 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
209 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
210 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
219 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
220 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
221 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
222 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
223 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
230 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
231 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
232 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
233 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
234 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
235 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
236 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
237 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
239 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
240 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
241 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
242 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
244 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
245 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
246 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
247 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
248 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
249 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
250 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
251 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
253 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
254 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
255 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
257 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
258 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
259 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
260 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
261 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
262 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
263 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
264 [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
266 [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
272 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
273 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
274 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
275 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
276 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
277 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
278 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
279 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
281 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
282 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
283 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
284 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
290 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
291 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
292 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
293 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
294 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
295 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
296 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
297 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
299 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
300 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
301 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
308 [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
309 [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
310 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
311 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
312 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
313 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
314 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
315 [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
317 [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
354 return readl(hte->regs + reg); in tegra_hte_readl()
360 writel(val, hte->regs + reg); in tegra_hte_writel()
370 return -EINVAL; in tegra_hte_map_to_line_id()
372 return -EINVAL; in tegra_hte_map_to_line_id()
393 return -EINVAL; in tegra_hte_line_xlate()
396 if (gc->of_hte_n_cells < 1) in tegra_hte_line_xlate()
397 return -EINVAL; in tegra_hte_line_xlate()
399 if (args->args_count != gc->of_hte_n_cells) in tegra_hte_line_xlate()
400 return -EINVAL; in tegra_hte_line_xlate()
402 desc->attr.line_id = args->args[0]; in tegra_hte_line_xlate()
405 gs = gc->data; in tegra_hte_line_xlate()
406 if (!gs || !gs->prov_data) in tegra_hte_line_xlate()
407 return -EINVAL; in tegra_hte_line_xlate()
417 * 2) Using GPIO descriptors that can be assigned to consumer devices in tegra_hte_line_xlate()
418 * using device-tree, ACPI or lookup tables. in tegra_hte_line_xlate()
423 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { in tegra_hte_line_xlate()
424 line_id = desc->attr.line_id - gpio_device_get_base(gs->gdev); in tegra_hte_line_xlate()
425 map = gs->prov_data->map; in tegra_hte_line_xlate()
426 map_sz = gs->prov_data->map_sz; in tegra_hte_line_xlate()
427 } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { in tegra_hte_line_xlate()
428 line_id = desc->attr.line_id; in tegra_hte_line_xlate()
429 map = gs->prov_data->sec_map; in tegra_hte_line_xlate()
430 map_sz = gs->prov_data->sec_map_sz; in tegra_hte_line_xlate()
432 line_id = desc->attr.line_id; in tegra_hte_line_xlate()
437 dev_err(gc->dev, "line_id:%u mapping failed\n", in tegra_hte_line_xlate()
438 desc->attr.line_id); in tegra_hte_line_xlate()
442 if (*xlated_id > gc->nlines) in tegra_hte_line_xlate()
443 return -EINVAL; in tegra_hte_line_xlate()
445 dev_dbg(gc->dev, "requested id:%u, xlated id:%u\n", in tegra_hte_line_xlate()
446 desc->attr.line_id, *xlated_id); in tegra_hte_line_xlate()
465 return -EINVAL; in tegra_hte_en_dis_common()
467 gs = chip->data; in tegra_hte_en_dis_common()
469 if (line_id > chip->nlines) { in tegra_hte_en_dis_common()
470 dev_err(chip->dev, in tegra_hte_en_dis_common()
473 return -EINVAL; in tegra_hte_en_dis_common()
477 line_bit = line_id & (HTE_SLICE_SIZE - 1); in tegra_hte_en_dis_common()
480 spin_lock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
482 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { in tegra_hte_en_dis_common()
483 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
484 dev_dbg(chip->dev, "device suspended"); in tegra_hte_en_dis_common()
485 return -EBUSY; in tegra_hte_en_dis_common()
495 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
497 dev_dbg(chip->dev, "line: %u, slice %u, line_bit %u, reg:0x%x\n", in tegra_hte_en_dis_common()
506 return -EINVAL; in tegra_hte_enable()
514 return -EINVAL; in tegra_hte_disable()
526 if (!chip || !chip->data || !desc) in tegra_hte_request()
527 return -EINVAL; in tegra_hte_request()
529 gs = chip->data; in tegra_hte_request()
530 attr = &desc->attr; in tegra_hte_request()
532 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_request()
533 if (!attr->line_data) in tegra_hte_request()
534 return -EINVAL; in tegra_hte_request()
536 ret = gpiod_enable_hw_timestamp_ns(attr->line_data, in tegra_hte_request()
537 attr->edge_flags); in tegra_hte_request()
541 gs->line_data[line_id].data = attr->line_data; in tegra_hte_request()
542 gs->line_data[line_id].flags = attr->edge_flags; in tegra_hte_request()
555 if (!chip || !chip->data || !desc) in tegra_hte_release()
556 return -EINVAL; in tegra_hte_release()
558 gs = chip->data; in tegra_hte_release()
559 attr = &desc->attr; in tegra_hte_release()
561 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_release()
562 ret = gpiod_disable_hw_timestamp_ns(attr->line_data, in tegra_hte_release()
563 gs->line_data[line_id].flags); in tegra_hte_release()
567 gs->line_data[line_id].data = NULL; in tegra_hte_release()
568 gs->line_data[line_id].flags = 0; in tegra_hte_release()
580 return -EINVAL; in tegra_hte_clk_src_info()
582 ci->hz = HTE_TS_CLK_RATE_HZ; in tegra_hte_clk_src_info()
583 ci->type = CLOCK_MONOTONIC; in tegra_hte_clk_src_info()
592 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_get_level()
593 desc = gs->line_data[line_id].data; in tegra_hte_get_level()
598 return -1; in tegra_hte_get_level()
626 hte_push_ts_ns(gs->chip, line_id, &el); in tegra_hte_read_fifo()
646 struct tegra_hte_soc *hte_dev = chip->data; in tegra_hte_match_from_linedata()
648 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO)) in tegra_hte_match_from_linedata()
651 return hte_dev->gdev == gpiod_to_gpio_device(hdesc->attr.line_data); in tegra_hte_match_from_linedata()
655 { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte},
656 { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
657 { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte},
658 { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
674 struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); in tegra_gte_disable()
696 dev = &pdev->dev; in tegra_hte_probe()
700 return -ENOMEM; in tegra_hte_probe()
704 return -ENOMEM; in tegra_hte_probe()
706 dev_set_drvdata(&pdev->dev, hte_dev); in tegra_hte_probe()
707 hte_dev->prov_data = of_device_get_match_data(&pdev->dev); in tegra_hte_probe()
709 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); in tegra_hte_probe()
711 slices = hte_dev->prov_data->slices; in tegra_hte_probe()
716 hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_hte_probe()
717 if (IS_ERR(hte_dev->regs)) in tegra_hte_probe()
718 return PTR_ERR(hte_dev->regs); in tegra_hte_probe()
720 ret = of_property_read_u32(dev->of_node, "nvidia,int-threshold", in tegra_hte_probe()
721 &hte_dev->itr_thrshld); in tegra_hte_probe()
723 hte_dev->itr_thrshld = 1; in tegra_hte_probe()
725 hte_dev->sl = devm_kcalloc(dev, slices, sizeof(*hte_dev->sl), in tegra_hte_probe()
727 if (!hte_dev->sl) in tegra_hte_probe()
728 return -ENOMEM; in tegra_hte_probe()
733 hte_dev->hte_irq = ret; in tegra_hte_probe()
734 ret = devm_request_irq(dev, hte_dev->hte_irq, tegra_hte_isr, 0, in tegra_hte_probe()
741 gc->nlines = nlines; in tegra_hte_probe()
742 gc->ops = &g_ops; in tegra_hte_probe()
743 gc->dev = dev; in tegra_hte_probe()
744 gc->data = hte_dev; in tegra_hte_probe()
745 gc->xlate_of = tegra_hte_line_xlate; in tegra_hte_probe()
746 gc->xlate_plat = tegra_hte_line_xlate_plat; in tegra_hte_probe()
747 gc->of_hte_n_cells = 1; in tegra_hte_probe()
749 if (hte_dev->prov_data && in tegra_hte_probe()
750 hte_dev->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_probe()
751 hte_dev->line_data = devm_kcalloc(dev, nlines, in tegra_hte_probe()
752 sizeof(*hte_dev->line_data), in tegra_hte_probe()
754 if (!hte_dev->line_data) in tegra_hte_probe()
755 return -ENOMEM; in tegra_hte_probe()
757 gc->match_from_linedata = tegra_hte_match_from_linedata; in tegra_hte_probe()
759 if (of_device_is_compatible(dev->of_node, in tegra_hte_probe()
760 "nvidia,tegra194-gte-aon")) { in tegra_hte_probe()
761 hte_dev->gdev = in tegra_hte_probe()
762 gpio_device_find_by_label("tegra194-gpio-aon"); in tegra_hte_probe()
764 gpio_ctrl = of_parse_phandle(dev->of_node, in tegra_hte_probe()
765 "nvidia,gpio-controller", in tegra_hte_probe()
770 return -ENODEV; in tegra_hte_probe()
773 hte_dev->gdev = in tegra_hte_probe()
778 if (!hte_dev->gdev) in tegra_hte_probe()
779 return dev_err_probe(dev, -EPROBE_DEFER, in tegra_hte_probe()
783 hte_dev->gdev); in tegra_hte_probe()
788 hte_dev->chip = gc; in tegra_hte_probe()
790 ret = devm_hte_register_chip(hte_dev->chip); in tegra_hte_probe()
792 dev_err(gc->dev, "hte chip register failed"); in tegra_hte_probe()
797 hte_dev->sl[i].flags = 0; in tegra_hte_probe()
798 spin_lock_init(&hte_dev->sl[i].s_lock); in tegra_hte_probe()
803 (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); in tegra_hte_probe()
806 ret = devm_add_action_or_reset(&pdev->dev, tegra_gte_disable, pdev); in tegra_hte_probe()
810 dev_dbg(gc->dev, "lines: %d, slices:%d", gc->nlines, slices); in tegra_hte_probe()
819 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; in tegra_hte_resume_early()
822 tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); in tegra_hte_resume_early()
825 spin_lock(&gs->sl[i].s_lock); in tegra_hte_resume_early()
828 gs->sl[i].r_val); in tegra_hte_resume_early()
829 clear_bit(HTE_SUSPEND, &gs->sl[i].flags); in tegra_hte_resume_early()
830 spin_unlock(&gs->sl[i].s_lock); in tegra_hte_resume_early()
840 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; in tegra_hte_suspend_late()
843 gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); in tegra_hte_suspend_late()
845 spin_lock(&gs->sl[i].s_lock); in tegra_hte_suspend_late()
846 gs->sl[i].r_val = tegra_hte_readl(gs, in tegra_hte_suspend_late()
848 set_bit(HTE_SUSPEND, &gs->sl[i].flags); in tegra_hte_suspend_late()
849 spin_unlock(&gs->sl[i].s_lock); in tegra_hte_suspend_late()