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/linux/drivers/clk/meson/
H A Dvclk.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include "clk-regmap.h"
13 * struct meson_vclk_gate_data - vclk_gate regmap backed specific data
15 * @enable: vclk enable field
16 * @reset: vclk reset field
17 * @flags: hardware-specific flags
31 * struct meson_vclk_div_data - vclk_div regmap back specific data
34 * @enable: vclk divider enable field
35 * @reset: vclk divider reset field
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
4 obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) += meson-clkc-utils.o
5 obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
6 obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
7 obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
8 obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
9 obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
10 obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
11 obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
12 obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drs780_dpm.c37 struct igp_ps *ps = rps->ps_priv; in rs780_get_ps()
44 struct igp_power_info *pi = rdev->pm.dpm.priv; in rs780_get_pi()
52 struct radeon_mode_info *minfo = &rdev->mode_info; in rs780_get_pm_mode_parameters()
58 pi->crtc_id = 0; in rs780_get_pm_mode_parameters()
59 pi->refresh_rate = 60; in rs780_get_pm_mode_parameters()
61 for (i = 0; i < rdev->num_crtc; i++) { in rs780_get_pm_mode_parameters()
62 crtc = (struct drm_crtc *)minfo->crtcs[i]; in rs780_get_pm_mode_parameters()
63 if (crtc && crtc->enabled) { in rs780_get_pm_mode_parameters()
65 pi->crtc_id = radeon_crtc->crtc_id; in rs780_get_pm_mode_parameters()
66 if (crtc->mode.htotal && crtc->mode.vtotal) in rs780_get_pm_mode_parameters()
[all …]
H A Dsumo_dpm.c74 struct sumo_ps *ps = rps->ps_priv; in sumo_get_ps()
81 struct sumo_power_info *pi = rdev->pm.dpm.priv; in sumo_get_pi()
154 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
182 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
194 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
215 if (rdev->family == CHIP_PALM) in sumo_gfx_powergating_initialize()
224 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
230 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
249 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
257 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
[all …]
H A Dtrinity_dpm.c302 struct trinity_ps *ps = rps->ps_priv; in trinity_get_ps()
309 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi()
344 if (pi->override_dynamic_mgpg && (hw_rev == 0)) in trinity_gfx_powergating_initialize()
501 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
503 if (pi->enable_mg_clock_gating) in trinity_enable_clock_power_gating()
505 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
507 if (pi->enable_mg_clock_gating) { in trinity_enable_clock_power_gating()
511 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
513 if (pi->enable_gfx_dynamic_mgpg) in trinity_enable_clock_power_gating()
515 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
[all …]
H A Drv6xx_dpm.c38 struct rv6xx_ps *ps = rps->ps_priv; in rv6xx_get_ps()
45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi()
63 for (i = 0; i < rdev->usec_timeout; i++) { in rv6xx_force_pcie_gen1()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
154 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
167 pi->spll_ref_div, in rv6xx_output_stepping()
173 if (step->post_divider == 1) in rv6xx_output_stepping()
176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
[all …]
H A Drv770_dpm.c51 struct rv7xx_ps *ps = rps->ps_priv; in rv770_get_ps()
58 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi()
65 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi()
82 if (!pi->boot_in_gen2) { in rv770_enable_bif_dynamic_pcie_gen2()
152 if (rdev->family == CHIP_RV770) in rv770_mg_clock_gating_enable()
160 if (pi->mgcgtssm) in rv770_mg_clock_gating_enable()
231 return (pl->flags & ATOM_PPLIB_R600_FLAGS_LOWPOWER) ? in rv770_get_seq_value()
242 pi->soft_regs_start + reg_offset,
243 value, pi->sram_end);
253 pi->soft_regs_start + reg_offset, in rv770_write_smc_soft_register()
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
26 - const: renesas,rzg2l-mipi-dsi
33 - description: Sequence operation channel 0 interrupt
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2007-2009 Stuart Bennett
63 pclk_freq = arb->pclk_khz; in nv04_calc_arb()
64 mclk_freq = arb->mclk_khz; in nv04_calc_arb()
65 nvclk_freq = arb->nvclk_khz; in nv04_calc_arb()
66 pagemiss = arb->mem_page_miss; in nv04_calc_arb()
67 cas = arb->mem_latency; in nv04_calc_arb()
68 bpp = arb->bpp; in nv04_calc_arb()
92 m1 = clwm + cbs - 512; in nv04_calc_arb()
97 mclk_extra--; in nv04_calc_arb()
[all …]
/linux/drivers/video/fbdev/via/
H A Dvt1636.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 #include <linux/via-core.h>
16 /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
18 /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
20 /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
22 /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
24 /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
46 viafb_i2c_readbyte(plvds_chip_info->i2c_port, in viafb_gpio_i2c_read_lvds()
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_aspeed_vuart.c1 // SPDX-License-Identifier: GPL-2.0+
61 * to the host on the Host <-> BMC LPC bus. It could be different on a
67 return readb(vuart->port->port.membase + reg); in aspeed_vuart_readb()
72 writeb(val, vuart->port->port.membase + reg); in aspeed_vuart_writeb()
90 return -EINVAL; in aspeed_vuart_set_lpc_address()
134 return -EINVAL; in aspeed_vuart_set_sirq()
250 struct aspeed_vuart *vuart = uart_8250_port->port.private_data; in aspeed_vuart_startup()
265 struct aspeed_vuart *vuart = uart_8250_port->port.private_data; in aspeed_vuart_shutdown()
278 lockdep_assert_held_once(&up->port.lock); in __aspeed_vuart_set_throttle()
280 up->ier &= ~irqs; in __aspeed_vuart_set_throttle()
[all …]
/linux/drivers/video/fbdev/riva/
H A Driva_hw.c3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
73 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
78 * - VCLK0 .. VCLK3 use the same FB_DIV
79 * - V2CLK is needed when the second CRTC is used (can be used for dualhead);
82 * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO,
84 * - V2CLK is not available on all cards, most likely only the Rage LT-PRO,
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
[all …]
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a55";
23 #cooling-cells = <2>;
24 next-level-cache = <&L3_CA55>;
25 enable-method = "psci";
27 operating-points-v2 = <&cluster0_opp>;
30 L3_CA55: cache-controller-0 {
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.c27 #include "atom-types.h"
53 if (smu8_magic != hw_ps->magic) in cast_smu8_power_state()
62 if (smu8_magic != hw_ps->magic) in cast_const_smu8_power_state()
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
78 for (i = 0; i < (int)ptable->count; i++) { in smu8_get_eclk_level()
79 if (clock <= ptable->entries[i].ecclk) in smu8_get_eclk_level()
86 for (i = ptable->count - 1; i >= 0; i--) { in smu8_get_eclk_level()
87 if (clock >= ptable->entries[i].ecclk) in smu8_get_eclk_level()
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
109 for (i = 0; i < (int)table->count; i++) { in smu8_get_sclk_level()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
21 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
22 * - HDMI Pixel Clocks generation
26 * - Genenate Pixel clocks for 2K/4K 10bit formats
33 * | | | | | |--ENCI
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
35 * |__________| |_________| \ | MUX |--ENCP
36 * --VCLK2-| |--VDAC
37 * |_____|--HDMI-TX
[all …]
H A Dmeson_encoder_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <media/cec-notifier.h>
29 #include <linux/media-bus-format.h>
57 return drm_bridge_attach(encoder, encoder_hdmi->next_bridge, in meson_encoder_hdmi_attach()
58 &encoder_hdmi->bridge, flags); in meson_encoder_hdmi_attach()
65 cec_notifier_conn_unregister(encoder_hdmi->cec_notifier); in meson_encoder_hdmi_detach()
66 encoder_hdmi->cec_notifier = NULL; in meson_encoder_hdmi_detach()
72 struct meson_drm *priv = encoder_hdmi->priv; in meson_encoder_hdmi_set_vclk()
79 vclk_freq = mode->clock * 1000ULL; in meson_encoder_hdmi_set_vclk()
82 if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) in meson_encoder_hdmi_set_vclk()
[all …]
/linux/drivers/video/fbdev/sis/
H A Dinit.c10 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
27 * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
55 * Formerly based on non-functional code-fragements for 300 series by SiS, Inc.
81 SiS_Pr->SiS_SModeIDTable = SiS_SModeIDTable; in InitCommonPointer()
82 SiS_Pr->SiS_StResInfo = SiS_StResInfo; in InitCommonPointer()
83 SiS_Pr->SiS_ModeResInfo = SiS_ModeResInfo; in InitCommonPointer()
84 SiS_Pr->SiS_StandTable = SiS_StandTable; in InitCommonPointer()
86 SiS_Pr->SiS_NTSCTiming = SiS_NTSCTiming; in InitCommonPointer()
87 SiS_Pr->SiS_PALTiming = SiS_PALTiming; in InitCommonPointer()
88 SiS_Pr->SiS_HiTVSt1Timing = SiS_HiTVSt1Timing; in InitCommonPointer()
[all …]
/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_drm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
43 args->pitch = logicvc->config.row_stride * DIV_ROUND_UP(args->bpp, 8); in logicvc_drm_gem_dma_dumb_create()
53 .name = "logicvc-drm",
66 .name = "logicvc-drm",
76 regmap_read(logicvc->regmap, LOGICVC_INT_STAT_REG, &stat); in logicvc_drm_irq_handler()
79 regmap_write(logicvc->regmap, LOGICVC_INT_STAT_REG, stat); in logicvc_drm_irq_handler()
91 struct drm_device *drm_dev = &logicvc->drm_dev; in logicvc_drm_config_parse()
92 struct device *dev = drm_dev->dev; in logicvc_drm_config_parse()
93 struct device_node *of_node = dev->of_node; in logicvc_drm_config_parse()
[all …]
H A Dlogicvc_drm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2019-2022 Bootlin
57 struct clk *vclk; member
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_4_ppsmc.h27 /*! @mainpage PMFW-PPS (PPLib) Message Interface
74 #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCL…
87 #define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCL…
H A Dsmu11_driver_if_vangogh.h120 uint32_t vclk; member
149 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
186 uint16_t CoreTemperature[8]; //[centi-Celsius]
188 uint16_t L3Temperature[2]; //[centi-Celsius]
190 uint16_t GfxTemperature; //[centi-Celsius]
191 uint16_t SocTemperature; //[centi-Celsius]
216 uint16_t CoreTemperature[4]; //[centi-Celsius]
218 uint16_t L3Temperature[1]; //[centi-Celsius]
220 uint16_t GfxTemperature; //[centi-Celsius]
221 uint16_t SocTemperature; //[centi-Celsius]

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