1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/bits.h>
4 #include <linux/bitfield.h>
5 #include <linux/bug.h>
6 #include <linux/container_of.h>
7 #include <linux/dev_printk.h>
8 #include <linux/dpll.h>
9 #include <linux/err.h>
10 #include <linux/kthread.h>
11 #include <linux/math64.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/module.h>
14 #include <linux/netlink.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/sprintf.h>
18
19 #include "core.h"
20 #include "dpll.h"
21 #include "prop.h"
22 #include "regs.h"
23
24 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS
25 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE)
26
27 /**
28 * struct zl3073x_dpll_pin - DPLL pin
29 * @list: this DPLL pin list entry
30 * @dpll: DPLL the pin is registered to
31 * @dpll_pin: pointer to registered dpll_pin
32 * @label: package label
33 * @dir: pin direction
34 * @id: pin id
35 * @prio: pin priority <0, 14>
36 * @selectable: pin is selectable in automatic mode
37 * @esync_control: embedded sync is controllable
38 * @pin_state: last saved pin state
39 * @phase_offset: last saved pin phase offset
40 * @freq_offset: last saved fractional frequency offset
41 */
42 struct zl3073x_dpll_pin {
43 struct list_head list;
44 struct zl3073x_dpll *dpll;
45 struct dpll_pin *dpll_pin;
46 char label[8];
47 enum dpll_pin_direction dir;
48 u8 id;
49 u8 prio;
50 bool selectable;
51 bool esync_control;
52 enum dpll_pin_state pin_state;
53 s64 phase_offset;
54 s64 freq_offset;
55 };
56
57 /*
58 * Supported esync ranges for input and for output per output pair type
59 */
60 static const struct dpll_pin_frequency esync_freq_ranges[] = {
61 DPLL_PIN_FREQUENCY_RANGE(0, 1),
62 };
63
64 /**
65 * zl3073x_dpll_is_input_pin - check if the pin is input one
66 * @pin: pin to check
67 *
68 * Return: true if pin is input, false if pin is output.
69 */
70 static bool
zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin * pin)71 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin)
72 {
73 return pin->dir == DPLL_PIN_DIRECTION_INPUT;
74 }
75
76 /**
77 * zl3073x_dpll_is_p_pin - check if the pin is P-pin
78 * @pin: pin to check
79 *
80 * Return: true if the pin is P-pin, false if it is N-pin
81 */
82 static bool
zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin * pin)83 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin)
84 {
85 return zl3073x_is_p_pin(pin->id);
86 }
87
88 static int
zl3073x_dpll_pin_direction_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)89 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv,
90 const struct dpll_device *dpll, void *dpll_priv,
91 enum dpll_pin_direction *direction,
92 struct netlink_ext_ack *extack)
93 {
94 struct zl3073x_dpll_pin *pin = pin_priv;
95
96 *direction = pin->dir;
97
98 return 0;
99 }
100
101 /**
102 * zl3073x_dpll_input_ref_frequency_get - get input reference frequency
103 * @zldpll: pointer to zl3073x_dpll
104 * @ref_id: reference id
105 * @frequency: pointer to variable to store frequency
106 *
107 * Reads frequency of given input reference.
108 *
109 * Return: 0 on success, <0 on error
110 */
111 static int
zl3073x_dpll_input_ref_frequency_get(struct zl3073x_dpll * zldpll,u8 ref_id,u32 * frequency)112 zl3073x_dpll_input_ref_frequency_get(struct zl3073x_dpll *zldpll, u8 ref_id,
113 u32 *frequency)
114 {
115 struct zl3073x_dev *zldev = zldpll->dev;
116 u16 base, mult, num, denom;
117 int rc;
118
119 guard(mutex)(&zldev->multiop_lock);
120
121 /* Read reference configuration */
122 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
123 ZL_REG_REF_MB_MASK, BIT(ref_id));
124 if (rc)
125 return rc;
126
127 /* Read registers to compute resulting frequency */
128 rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_BASE, &base);
129 if (rc)
130 return rc;
131 rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_MULT, &mult);
132 if (rc)
133 return rc;
134 rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_M, &num);
135 if (rc)
136 return rc;
137 rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_N, &denom);
138 if (rc)
139 return rc;
140
141 /* Sanity check that HW has not returned zero denominator */
142 if (!denom) {
143 dev_err(zldev->dev,
144 "Zero divisor for ref %u frequency got from device\n",
145 ref_id);
146 return -EINVAL;
147 }
148
149 /* Compute the frequency */
150 *frequency = mul_u64_u32_div(base * mult, num, denom);
151
152 return rc;
153 }
154
155 static int
zl3073x_dpll_input_pin_esync_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack)156 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin,
157 void *pin_priv,
158 const struct dpll_device *dpll,
159 void *dpll_priv,
160 struct dpll_pin_esync *esync,
161 struct netlink_ext_ack *extack)
162 {
163 struct zl3073x_dpll *zldpll = dpll_priv;
164 struct zl3073x_dev *zldev = zldpll->dev;
165 struct zl3073x_dpll_pin *pin = pin_priv;
166 u8 ref, ref_sync_ctrl, sync_mode;
167 u32 esync_div, ref_freq;
168 int rc;
169
170 /* Get reference frequency */
171 ref = zl3073x_input_pin_ref_get(pin->id);
172 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, pin->id, &ref_freq);
173 if (rc)
174 return rc;
175
176 guard(mutex)(&zldev->multiop_lock);
177
178 /* Read reference configuration into mailbox */
179 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
180 ZL_REG_REF_MB_MASK, BIT(ref));
181 if (rc)
182 return rc;
183
184 /* Get ref sync mode */
185 rc = zl3073x_read_u8(zldev, ZL_REG_REF_SYNC_CTRL, &ref_sync_ctrl);
186 if (rc)
187 return rc;
188
189 /* Get esync divisor */
190 rc = zl3073x_read_u32(zldev, ZL_REG_REF_ESYNC_DIV, &esync_div);
191 if (rc)
192 return rc;
193
194 sync_mode = FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref_sync_ctrl);
195
196 switch (sync_mode) {
197 case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75:
198 esync->freq = (esync_div == ZL_REF_ESYNC_DIV_1HZ) ? 1 : 0;
199 esync->pulse = 25;
200 break;
201 default:
202 esync->freq = 0;
203 esync->pulse = 0;
204 break;
205 }
206
207 /* If the pin supports esync control expose its range but only
208 * if the current reference frequency is > 1 Hz.
209 */
210 if (pin->esync_control && ref_freq > 1) {
211 esync->range = esync_freq_ranges;
212 esync->range_num = ARRAY_SIZE(esync_freq_ranges);
213 } else {
214 esync->range = NULL;
215 esync->range_num = 0;
216 }
217
218 return rc;
219 }
220
221 static int
zl3073x_dpll_input_pin_esync_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack)222 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin,
223 void *pin_priv,
224 const struct dpll_device *dpll,
225 void *dpll_priv, u64 freq,
226 struct netlink_ext_ack *extack)
227 {
228 struct zl3073x_dpll *zldpll = dpll_priv;
229 struct zl3073x_dev *zldev = zldpll->dev;
230 struct zl3073x_dpll_pin *pin = pin_priv;
231 u8 ref, ref_sync_ctrl, sync_mode;
232 int rc;
233
234 guard(mutex)(&zldev->multiop_lock);
235
236 /* Read reference configuration into mailbox */
237 ref = zl3073x_input_pin_ref_get(pin->id);
238 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
239 ZL_REG_REF_MB_MASK, BIT(ref));
240 if (rc)
241 return rc;
242
243 /* Get ref sync mode */
244 rc = zl3073x_read_u8(zldev, ZL_REG_REF_SYNC_CTRL, &ref_sync_ctrl);
245 if (rc)
246 return rc;
247
248 /* Use freq == 0 to disable esync */
249 if (!freq)
250 sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF;
251 else
252 sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75;
253
254 ref_sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE;
255 ref_sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode);
256
257 /* Update ref sync control register */
258 rc = zl3073x_write_u8(zldev, ZL_REG_REF_SYNC_CTRL, ref_sync_ctrl);
259 if (rc)
260 return rc;
261
262 if (freq) {
263 /* 1 Hz is only supported frequnecy currently */
264 rc = zl3073x_write_u32(zldev, ZL_REG_REF_ESYNC_DIV,
265 ZL_REF_ESYNC_DIV_1HZ);
266 if (rc)
267 return rc;
268 }
269
270 /* Commit reference configuration */
271 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR,
272 ZL_REG_REF_MB_MASK, BIT(ref));
273 }
274
275 static int
zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * ffo,struct netlink_ext_ack * extack)276 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv,
277 const struct dpll_device *dpll, void *dpll_priv,
278 s64 *ffo, struct netlink_ext_ack *extack)
279 {
280 struct zl3073x_dpll_pin *pin = pin_priv;
281
282 *ffo = pin->freq_offset;
283
284 return 0;
285 }
286
287 static int
zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)288 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin,
289 void *pin_priv,
290 const struct dpll_device *dpll,
291 void *dpll_priv, u64 *frequency,
292 struct netlink_ext_ack *extack)
293 {
294 struct zl3073x_dpll *zldpll = dpll_priv;
295 struct zl3073x_dpll_pin *pin = pin_priv;
296 u32 ref_freq;
297 u8 ref;
298 int rc;
299
300 /* Read and return ref frequency */
301 ref = zl3073x_input_pin_ref_get(pin->id);
302 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref, &ref_freq);
303 if (!rc)
304 *frequency = ref_freq;
305
306 return rc;
307 }
308
309 static int
zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)310 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin,
311 void *pin_priv,
312 const struct dpll_device *dpll,
313 void *dpll_priv, u64 frequency,
314 struct netlink_ext_ack *extack)
315 {
316 struct zl3073x_dpll *zldpll = dpll_priv;
317 struct zl3073x_dev *zldev = zldpll->dev;
318 struct zl3073x_dpll_pin *pin = pin_priv;
319 u16 base, mult;
320 u8 ref;
321 int rc;
322
323 /* Get base frequency and multiplier for the requested frequency */
324 rc = zl3073x_ref_freq_factorize(frequency, &base, &mult);
325 if (rc)
326 return rc;
327
328 guard(mutex)(&zldev->multiop_lock);
329
330 /* Load reference configuration */
331 ref = zl3073x_input_pin_ref_get(pin->id);
332 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
333 ZL_REG_REF_MB_MASK, BIT(ref));
334
335 /* Update base frequency, multiplier, numerator & denominator */
336 rc = zl3073x_write_u16(zldev, ZL_REG_REF_FREQ_BASE, base);
337 if (rc)
338 return rc;
339 rc = zl3073x_write_u16(zldev, ZL_REG_REF_FREQ_MULT, mult);
340 if (rc)
341 return rc;
342 rc = zl3073x_write_u16(zldev, ZL_REG_REF_RATIO_M, 1);
343 if (rc)
344 return rc;
345 rc = zl3073x_write_u16(zldev, ZL_REG_REF_RATIO_N, 1);
346 if (rc)
347 return rc;
348
349 /* Commit reference configuration */
350 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR,
351 ZL_REG_REF_MB_MASK, BIT(ref));
352 }
353
354 /**
355 * zl3073x_dpll_selected_ref_get - get currently selected reference
356 * @zldpll: pointer to zl3073x_dpll
357 * @ref: place to store selected reference
358 *
359 * Check for currently selected reference the DPLL should be locked to
360 * and stores its index to given @ref.
361 *
362 * Return: 0 on success, <0 on error
363 */
364 static int
zl3073x_dpll_selected_ref_get(struct zl3073x_dpll * zldpll,u8 * ref)365 zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref)
366 {
367 struct zl3073x_dev *zldev = zldpll->dev;
368 u8 state, value;
369 int rc;
370
371 switch (zldpll->refsel_mode) {
372 case ZL_DPLL_MODE_REFSEL_MODE_AUTO:
373 /* For automatic mode read refsel_status register */
374 rc = zl3073x_read_u8(zldev,
375 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id),
376 &value);
377 if (rc)
378 return rc;
379
380 /* Extract reference state */
381 state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value);
382
383 /* Return the reference only if the DPLL is locked to it */
384 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK)
385 *ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value);
386 else
387 *ref = ZL3073X_DPLL_REF_NONE;
388 break;
389 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK:
390 /* For manual mode return stored value */
391 *ref = zldpll->forced_ref;
392 break;
393 default:
394 /* For other modes like NCO, freerun... there is no input ref */
395 *ref = ZL3073X_DPLL_REF_NONE;
396 break;
397 }
398
399 return 0;
400 }
401
402 /**
403 * zl3073x_dpll_selected_ref_set - select reference in manual mode
404 * @zldpll: pointer to zl3073x_dpll
405 * @ref: input reference to be selected
406 *
407 * Selects the given reference for the DPLL channel it should be
408 * locked to.
409 *
410 * Return: 0 on success, <0 on error
411 */
412 static int
zl3073x_dpll_selected_ref_set(struct zl3073x_dpll * zldpll,u8 ref)413 zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref)
414 {
415 struct zl3073x_dev *zldev = zldpll->dev;
416 u8 mode, mode_refsel;
417 int rc;
418
419 mode = zldpll->refsel_mode;
420
421 switch (mode) {
422 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK:
423 /* Manual mode with ref selected */
424 if (ref == ZL3073X_DPLL_REF_NONE) {
425 switch (zldpll->lock_status) {
426 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ:
427 case DPLL_LOCK_STATUS_HOLDOVER:
428 /* Switch to forced holdover */
429 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER;
430 break;
431 default:
432 /* Switch to freerun */
433 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN;
434 break;
435 }
436 /* Keep selected reference */
437 ref = zldpll->forced_ref;
438 } else if (ref == zldpll->forced_ref) {
439 /* No register update - same mode and same ref */
440 return 0;
441 }
442 break;
443 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN:
444 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER:
445 /* Manual mode without no ref */
446 if (ref == ZL3073X_DPLL_REF_NONE)
447 /* No register update - keep current mode */
448 return 0;
449
450 /* Switch to reflock mode and update ref selection */
451 mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK;
452 break;
453 default:
454 /* For other modes like automatic or NCO ref cannot be selected
455 * manually
456 */
457 return -EOPNOTSUPP;
458 }
459
460 /* Build mode_refsel value */
461 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) |
462 FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref);
463
464 /* Update dpll_mode_refsel register */
465 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id),
466 mode_refsel);
467 if (rc)
468 return rc;
469
470 /* Store new mode and forced reference */
471 zldpll->refsel_mode = mode;
472 zldpll->forced_ref = ref;
473
474 return rc;
475 }
476
477 /**
478 * zl3073x_dpll_connected_ref_get - get currently connected reference
479 * @zldpll: pointer to zl3073x_dpll
480 * @ref: place to store selected reference
481 *
482 * Looks for currently connected the DPLL is locked to and stores its index
483 * to given @ref.
484 *
485 * Return: 0 on success, <0 on error
486 */
487 static int
zl3073x_dpll_connected_ref_get(struct zl3073x_dpll * zldpll,u8 * ref)488 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref)
489 {
490 struct zl3073x_dev *zldev = zldpll->dev;
491 int rc;
492
493 /* Get currently selected input reference */
494 rc = zl3073x_dpll_selected_ref_get(zldpll, ref);
495 if (rc)
496 return rc;
497
498 if (ZL3073X_DPLL_REF_IS_VALID(*ref)) {
499 u8 ref_status;
500
501 /* Read the reference monitor status */
502 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(*ref),
503 &ref_status);
504 if (rc)
505 return rc;
506
507 /* If the monitor indicates an error nothing is connected */
508 if (ref_status != ZL_REF_MON_STATUS_OK)
509 *ref = ZL3073X_DPLL_REF_NONE;
510 }
511
512 return 0;
513 }
514
515 static int
zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * phase_offset,struct netlink_ext_ack * extack)516 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin,
517 void *pin_priv,
518 const struct dpll_device *dpll,
519 void *dpll_priv, s64 *phase_offset,
520 struct netlink_ext_ack *extack)
521 {
522 struct zl3073x_dpll *zldpll = dpll_priv;
523 struct zl3073x_dev *zldev = zldpll->dev;
524 struct zl3073x_dpll_pin *pin = pin_priv;
525 u8 conn_ref, ref, ref_status;
526 s64 ref_phase;
527 int rc;
528
529 /* Get currently connected reference */
530 rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_ref);
531 if (rc)
532 return rc;
533
534 /* Report phase offset only for currently connected pin if the phase
535 * monitor feature is disabled.
536 */
537 ref = zl3073x_input_pin_ref_get(pin->id);
538 if (!zldpll->phase_monitor && ref != conn_ref) {
539 *phase_offset = 0;
540
541 return 0;
542 }
543
544 /* Get this pin monitor status */
545 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), &ref_status);
546 if (rc)
547 return rc;
548
549 /* Report phase offset only if the input pin signal is present */
550 if (ref_status != ZL_REF_MON_STATUS_OK) {
551 *phase_offset = 0;
552
553 return 0;
554 }
555
556 ref_phase = pin->phase_offset;
557
558 /* The DPLL being locked to a higher freq than the current ref
559 * the phase offset is modded to the period of the signal
560 * the dpll is locked to.
561 */
562 if (ZL3073X_DPLL_REF_IS_VALID(conn_ref) && conn_ref != ref) {
563 u32 conn_freq, ref_freq;
564
565 /* Get frequency of connected ref */
566 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, conn_ref,
567 &conn_freq);
568 if (rc)
569 return rc;
570
571 /* Get frequency of given ref */
572 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref,
573 &ref_freq);
574 if (rc)
575 return rc;
576
577 if (conn_freq > ref_freq) {
578 s64 conn_period, div_factor;
579
580 conn_period = div_s64(PSEC_PER_SEC, conn_freq);
581 div_factor = div64_s64(ref_phase, conn_period);
582 ref_phase -= conn_period * div_factor;
583 }
584 }
585
586 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER;
587
588 return rc;
589 }
590
591 static int
zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack)592 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
593 void *pin_priv,
594 const struct dpll_device *dpll,
595 void *dpll_priv,
596 s32 *phase_adjust,
597 struct netlink_ext_ack *extack)
598 {
599 struct zl3073x_dpll *zldpll = dpll_priv;
600 struct zl3073x_dev *zldev = zldpll->dev;
601 struct zl3073x_dpll_pin *pin = pin_priv;
602 s64 phase_comp;
603 u8 ref;
604 int rc;
605
606 guard(mutex)(&zldev->multiop_lock);
607
608 /* Read reference configuration */
609 ref = zl3073x_input_pin_ref_get(pin->id);
610 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
611 ZL_REG_REF_MB_MASK, BIT(ref));
612 if (rc)
613 return rc;
614
615 /* Read current phase offset compensation */
616 rc = zl3073x_read_u48(zldev, ZL_REG_REF_PHASE_OFFSET_COMP, &phase_comp);
617 if (rc)
618 return rc;
619
620 /* Perform sign extension for 48bit signed value */
621 phase_comp = sign_extend64(phase_comp, 47);
622
623 /* Reverse two's complement negation applied during set and convert
624 * to 32bit signed int
625 */
626 *phase_adjust = (s32)-phase_comp;
627
628 return rc;
629 }
630
631 static int
zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack)632 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin,
633 void *pin_priv,
634 const struct dpll_device *dpll,
635 void *dpll_priv,
636 s32 phase_adjust,
637 struct netlink_ext_ack *extack)
638 {
639 struct zl3073x_dpll *zldpll = dpll_priv;
640 struct zl3073x_dev *zldev = zldpll->dev;
641 struct zl3073x_dpll_pin *pin = pin_priv;
642 s64 phase_comp;
643 u8 ref;
644 int rc;
645
646 /* The value in the register is stored as two's complement negation
647 * of requested value.
648 */
649 phase_comp = -phase_adjust;
650
651 guard(mutex)(&zldev->multiop_lock);
652
653 /* Read reference configuration */
654 ref = zl3073x_input_pin_ref_get(pin->id);
655 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
656 ZL_REG_REF_MB_MASK, BIT(ref));
657 if (rc)
658 return rc;
659
660 /* Write the requested value into the compensation register */
661 rc = zl3073x_write_u48(zldev, ZL_REG_REF_PHASE_OFFSET_COMP, phase_comp);
662 if (rc)
663 return rc;
664
665 /* Commit reference configuration */
666 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR,
667 ZL_REG_REF_MB_MASK, BIT(ref));
668 }
669
670 /**
671 * zl3073x_dpll_ref_prio_get - get priority for given input pin
672 * @pin: pointer to pin
673 * @prio: place to store priority
674 *
675 * Reads current priority for the given input pin and stores the value
676 * to @prio.
677 *
678 * Return: 0 on success, <0 on error
679 */
680 static int
zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin * pin,u8 * prio)681 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio)
682 {
683 struct zl3073x_dpll *zldpll = pin->dpll;
684 struct zl3073x_dev *zldev = zldpll->dev;
685 u8 ref, ref_prio;
686 int rc;
687
688 guard(mutex)(&zldev->multiop_lock);
689
690 /* Read DPLL configuration */
691 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD,
692 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id));
693 if (rc)
694 return rc;
695
696 /* Read reference priority - one value for P&N pins (4 bits/pin) */
697 ref = zl3073x_input_pin_ref_get(pin->id);
698 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2),
699 &ref_prio);
700 if (rc)
701 return rc;
702
703 /* Select nibble according pin type */
704 if (zl3073x_dpll_is_p_pin(pin))
705 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio);
706 else
707 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio);
708
709 return rc;
710 }
711
712 /**
713 * zl3073x_dpll_ref_prio_set - set priority for given input pin
714 * @pin: pointer to pin
715 * @prio: place to store priority
716 *
717 * Sets priority for the given input pin.
718 *
719 * Return: 0 on success, <0 on error
720 */
721 static int
zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin * pin,u8 prio)722 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio)
723 {
724 struct zl3073x_dpll *zldpll = pin->dpll;
725 struct zl3073x_dev *zldev = zldpll->dev;
726 u8 ref, ref_prio;
727 int rc;
728
729 guard(mutex)(&zldev->multiop_lock);
730
731 /* Read DPLL configuration into mailbox */
732 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD,
733 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id));
734 if (rc)
735 return rc;
736
737 /* Read reference priority - one value shared between P&N pins */
738 ref = zl3073x_input_pin_ref_get(pin->id);
739 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio);
740 if (rc)
741 return rc;
742
743 /* Update nibble according pin type */
744 if (zl3073x_dpll_is_p_pin(pin)) {
745 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P;
746 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio);
747 } else {
748 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N;
749 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio);
750 }
751
752 /* Update reference priority */
753 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio);
754 if (rc)
755 return rc;
756
757 /* Commit configuration */
758 return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR,
759 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id));
760 }
761
762 /**
763 * zl3073x_dpll_ref_state_get - get status for given input pin
764 * @pin: pointer to pin
765 * @state: place to store status
766 *
767 * Checks current status for the given input pin and stores the value
768 * to @state.
769 *
770 * Return: 0 on success, <0 on error
771 */
772 static int
zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin * pin,enum dpll_pin_state * state)773 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin,
774 enum dpll_pin_state *state)
775 {
776 struct zl3073x_dpll *zldpll = pin->dpll;
777 struct zl3073x_dev *zldev = zldpll->dev;
778 u8 ref, ref_conn, status;
779 int rc;
780
781 ref = zl3073x_input_pin_ref_get(pin->id);
782
783 /* Get currently connected reference */
784 rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn);
785 if (rc)
786 return rc;
787
788 if (ref == ref_conn) {
789 *state = DPLL_PIN_STATE_CONNECTED;
790 return 0;
791 }
792
793 /* If the DPLL is running in automatic mode and the reference is
794 * selectable and its monitor does not report any error then report
795 * pin as selectable.
796 */
797 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO &&
798 pin->selectable) {
799 /* Read reference monitor status */
800 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref),
801 &status);
802 if (rc)
803 return rc;
804
805 /* If the monitor indicates errors report the reference
806 * as disconnected
807 */
808 if (status == ZL_REF_MON_STATUS_OK) {
809 *state = DPLL_PIN_STATE_SELECTABLE;
810 return 0;
811 }
812 }
813
814 /* Otherwise report the pin as disconnected */
815 *state = DPLL_PIN_STATE_DISCONNECTED;
816
817 return 0;
818 }
819
820 static int
zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)821 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin,
822 void *pin_priv,
823 const struct dpll_device *dpll,
824 void *dpll_priv,
825 enum dpll_pin_state *state,
826 struct netlink_ext_ack *extack)
827 {
828 struct zl3073x_dpll_pin *pin = pin_priv;
829
830 return zl3073x_dpll_ref_state_get(pin, state);
831 }
832
833 static int
zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack)834 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin,
835 void *pin_priv,
836 const struct dpll_device *dpll,
837 void *dpll_priv,
838 enum dpll_pin_state state,
839 struct netlink_ext_ack *extack)
840 {
841 struct zl3073x_dpll *zldpll = dpll_priv;
842 struct zl3073x_dpll_pin *pin = pin_priv;
843 u8 new_ref;
844 int rc;
845
846 switch (zldpll->refsel_mode) {
847 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK:
848 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN:
849 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER:
850 if (state == DPLL_PIN_STATE_CONNECTED) {
851 /* Choose the pin as new selected reference */
852 new_ref = zl3073x_input_pin_ref_get(pin->id);
853 } else if (state == DPLL_PIN_STATE_DISCONNECTED) {
854 /* No reference */
855 new_ref = ZL3073X_DPLL_REF_NONE;
856 } else {
857 NL_SET_ERR_MSG_MOD(extack,
858 "Invalid pin state for manual mode");
859 return -EINVAL;
860 }
861
862 rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref);
863 break;
864
865 case ZL_DPLL_MODE_REFSEL_MODE_AUTO:
866 if (state == DPLL_PIN_STATE_SELECTABLE) {
867 if (pin->selectable)
868 return 0; /* Pin is already selectable */
869
870 /* Restore pin priority in HW */
871 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio);
872 if (rc)
873 return rc;
874
875 /* Mark pin as selectable */
876 pin->selectable = true;
877 } else if (state == DPLL_PIN_STATE_DISCONNECTED) {
878 if (!pin->selectable)
879 return 0; /* Pin is already disconnected */
880
881 /* Set pin priority to none in HW */
882 rc = zl3073x_dpll_ref_prio_set(pin,
883 ZL_DPLL_REF_PRIO_NONE);
884 if (rc)
885 return rc;
886
887 /* Mark pin as non-selectable */
888 pin->selectable = false;
889 } else {
890 NL_SET_ERR_MSG(extack,
891 "Invalid pin state for automatic mode");
892 return -EINVAL;
893 }
894 break;
895
896 default:
897 /* In other modes we cannot change input reference */
898 NL_SET_ERR_MSG(extack,
899 "Pin state cannot be changed in current mode");
900 rc = -EOPNOTSUPP;
901 break;
902 }
903
904 return rc;
905 }
906
907 static int
zl3073x_dpll_input_pin_prio_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack)908 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv,
909 const struct dpll_device *dpll, void *dpll_priv,
910 u32 *prio, struct netlink_ext_ack *extack)
911 {
912 struct zl3073x_dpll_pin *pin = pin_priv;
913
914 *prio = pin->prio;
915
916 return 0;
917 }
918
919 static int
zl3073x_dpll_input_pin_prio_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack)920 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv,
921 const struct dpll_device *dpll, void *dpll_priv,
922 u32 prio, struct netlink_ext_ack *extack)
923 {
924 struct zl3073x_dpll_pin *pin = pin_priv;
925 int rc;
926
927 if (prio > ZL_DPLL_REF_PRIO_MAX)
928 return -EINVAL;
929
930 /* If the pin is selectable then update HW registers */
931 if (pin->selectable) {
932 rc = zl3073x_dpll_ref_prio_set(pin, prio);
933 if (rc)
934 return rc;
935 }
936
937 /* Save priority */
938 pin->prio = prio;
939
940 return 0;
941 }
942
943 static int
zl3073x_dpll_output_pin_esync_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack)944 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
945 void *pin_priv,
946 const struct dpll_device *dpll,
947 void *dpll_priv,
948 struct dpll_pin_esync *esync,
949 struct netlink_ext_ack *extack)
950 {
951 struct zl3073x_dpll *zldpll = dpll_priv;
952 struct zl3073x_dev *zldev = zldpll->dev;
953 struct zl3073x_dpll_pin *pin = pin_priv;
954 struct device *dev = zldev->dev;
955 u32 esync_period, esync_width;
956 u8 clock_type, synth;
957 u8 out, output_mode;
958 u32 output_div;
959 u32 synth_freq;
960 int rc;
961
962 out = zl3073x_output_pin_out_get(pin->id);
963
964 /* If N-division is enabled, esync is not supported. The register used
965 * for N-division is also used for the esync divider so both cannot
966 * be used.
967 */
968 switch (zl3073x_out_signal_format_get(zldev, out)) {
969 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
970 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
971 return -EOPNOTSUPP;
972 default:
973 break;
974 }
975
976 guard(mutex)(&zldev->multiop_lock);
977
978 /* Read output configuration into mailbox */
979 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
980 ZL_REG_OUTPUT_MB_MASK, BIT(out));
981 if (rc)
982 return rc;
983
984 /* Read output mode */
985 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode);
986 if (rc)
987 return rc;
988
989 /* Read output divisor */
990 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div);
991 if (rc)
992 return rc;
993
994 /* Check output divisor for zero */
995 if (!output_div) {
996 dev_err(dev, "Zero divisor for OUTPUT%u got from device\n",
997 out);
998 return -EINVAL;
999 }
1000
1001 /* Get synth attached to output pin */
1002 synth = zl3073x_out_synth_get(zldev, out);
1003
1004 /* Get synth frequency */
1005 synth_freq = zl3073x_synth_freq_get(zldev, synth);
1006
1007 clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, output_mode);
1008 if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) {
1009 /* No need to read esync data if it is not enabled */
1010 esync->freq = 0;
1011 esync->pulse = 0;
1012
1013 goto finish;
1014 }
1015
1016 /* Read esync period */
1017 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, &esync_period);
1018 if (rc)
1019 return rc;
1020
1021 /* Check esync divisor for zero */
1022 if (!esync_period) {
1023 dev_err(dev, "Zero esync divisor for OUTPUT%u got from device\n",
1024 out);
1025 return -EINVAL;
1026 }
1027
1028 /* Get esync pulse width in units of half synth cycles */
1029 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, &esync_width);
1030 if (rc)
1031 return rc;
1032
1033 /* Compute esync frequency */
1034 esync->freq = synth_freq / output_div / esync_period;
1035
1036 /* By comparing the esync_pulse_width to the half of the pulse width
1037 * the esync pulse percentage can be determined.
1038 * Note that half pulse width is in units of half synth cycles, which
1039 * is why it reduces down to be output_div.
1040 */
1041 esync->pulse = (50 * esync_width) / output_div;
1042
1043 finish:
1044 /* Set supported esync ranges if the pin supports esync control and
1045 * if the output frequency is > 1 Hz.
1046 */
1047 if (pin->esync_control && (synth_freq / output_div) > 1) {
1048 esync->range = esync_freq_ranges;
1049 esync->range_num = ARRAY_SIZE(esync_freq_ranges);
1050 } else {
1051 esync->range = NULL;
1052 esync->range_num = 0;
1053 }
1054
1055 return 0;
1056 }
1057
1058 static int
zl3073x_dpll_output_pin_esync_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack)1059 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin,
1060 void *pin_priv,
1061 const struct dpll_device *dpll,
1062 void *dpll_priv, u64 freq,
1063 struct netlink_ext_ack *extack)
1064 {
1065 u32 esync_period, esync_width, output_div;
1066 struct zl3073x_dpll *zldpll = dpll_priv;
1067 struct zl3073x_dev *zldev = zldpll->dev;
1068 struct zl3073x_dpll_pin *pin = pin_priv;
1069 u8 clock_type, out, output_mode, synth;
1070 u32 synth_freq;
1071 int rc;
1072
1073 out = zl3073x_output_pin_out_get(pin->id);
1074
1075 /* If N-division is enabled, esync is not supported. The register used
1076 * for N-division is also used for the esync divider so both cannot
1077 * be used.
1078 */
1079 switch (zl3073x_out_signal_format_get(zldev, out)) {
1080 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
1081 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
1082 return -EOPNOTSUPP;
1083 default:
1084 break;
1085 }
1086
1087 guard(mutex)(&zldev->multiop_lock);
1088
1089 /* Read output configuration into mailbox */
1090 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
1091 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1092 if (rc)
1093 return rc;
1094
1095 /* Read output mode */
1096 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode);
1097 if (rc)
1098 return rc;
1099
1100 /* Select clock type */
1101 if (freq)
1102 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC;
1103 else
1104 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL;
1105
1106 /* Update clock type in output mode */
1107 output_mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE;
1108 output_mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type);
1109 rc = zl3073x_write_u8(zldev, ZL_REG_OUTPUT_MODE, output_mode);
1110 if (rc)
1111 return rc;
1112
1113 /* If esync is being disabled just write mailbox and finish */
1114 if (!freq)
1115 goto write_mailbox;
1116
1117 /* Get synth attached to output pin */
1118 synth = zl3073x_out_synth_get(zldev, out);
1119
1120 /* Get synth frequency */
1121 synth_freq = zl3073x_synth_freq_get(zldev, synth);
1122
1123 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div);
1124 if (rc)
1125 return rc;
1126
1127 /* Check output divisor for zero */
1128 if (!output_div) {
1129 dev_err(zldev->dev,
1130 "Zero divisor for OUTPUT%u got from device\n", out);
1131 return -EINVAL;
1132 }
1133
1134 /* Compute and update esync period */
1135 esync_period = synth_freq / (u32)freq / output_div;
1136 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, esync_period);
1137 if (rc)
1138 return rc;
1139
1140 /* Half of the period in units of 1/2 synth cycle can be represented by
1141 * the output_div. To get the supported esync pulse width of 25% of the
1142 * period the output_div can just be divided by 2. Note that this
1143 * assumes that output_div is even, otherwise some resolution will be
1144 * lost.
1145 */
1146 esync_width = output_div / 2;
1147 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, esync_width);
1148 if (rc)
1149 return rc;
1150
1151 write_mailbox:
1152 /* Commit output configuration */
1153 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR,
1154 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1155 }
1156
1157 static int
zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)1158 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin,
1159 void *pin_priv,
1160 const struct dpll_device *dpll,
1161 void *dpll_priv, u64 *frequency,
1162 struct netlink_ext_ack *extack)
1163 {
1164 struct zl3073x_dpll *zldpll = dpll_priv;
1165 struct zl3073x_dev *zldev = zldpll->dev;
1166 struct zl3073x_dpll_pin *pin = pin_priv;
1167 struct device *dev = zldev->dev;
1168 u8 out, signal_format, synth;
1169 u32 output_div, synth_freq;
1170 int rc;
1171
1172 out = zl3073x_output_pin_out_get(pin->id);
1173 synth = zl3073x_out_synth_get(zldev, out);
1174 synth_freq = zl3073x_synth_freq_get(zldev, synth);
1175
1176 guard(mutex)(&zldev->multiop_lock);
1177
1178 /* Read output configuration into mailbox */
1179 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
1180 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1181 if (rc)
1182 return rc;
1183
1184 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div);
1185 if (rc)
1186 return rc;
1187
1188 /* Check output divisor for zero */
1189 if (!output_div) {
1190 dev_err(dev, "Zero divisor for output %u got from device\n",
1191 out);
1192 return -EINVAL;
1193 }
1194
1195 /* Read used signal format for the given output */
1196 signal_format = zl3073x_out_signal_format_get(zldev, out);
1197
1198 switch (signal_format) {
1199 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
1200 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
1201 /* In case of divided format we have to distiguish between
1202 * given output pin type.
1203 */
1204 if (zl3073x_dpll_is_p_pin(pin)) {
1205 /* For P-pin the resulting frequency is computed as
1206 * simple division of synth frequency and output
1207 * divisor.
1208 */
1209 *frequency = synth_freq / output_div;
1210 } else {
1211 /* For N-pin we have to divide additionally by
1212 * divisor stored in esync_period output mailbox
1213 * register that is used as N-pin divisor for these
1214 * modes.
1215 */
1216 u32 ndiv;
1217
1218 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD,
1219 &ndiv);
1220 if (rc)
1221 return rc;
1222
1223 /* Check N-pin divisor for zero */
1224 if (!ndiv) {
1225 dev_err(dev,
1226 "Zero N-pin divisor for output %u got from device\n",
1227 out);
1228 return -EINVAL;
1229 }
1230
1231 /* Compute final divisor for N-pin */
1232 *frequency = synth_freq / output_div / ndiv;
1233 }
1234 break;
1235 default:
1236 /* In other modes the resulting frequency is computed as
1237 * division of synth frequency and output divisor.
1238 */
1239 *frequency = synth_freq / output_div;
1240 break;
1241 }
1242
1243 return rc;
1244 }
1245
1246 static int
zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)1247 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin,
1248 void *pin_priv,
1249 const struct dpll_device *dpll,
1250 void *dpll_priv, u64 frequency,
1251 struct netlink_ext_ack *extack)
1252 {
1253 struct zl3073x_dpll *zldpll = dpll_priv;
1254 struct zl3073x_dev *zldev = zldpll->dev;
1255 struct zl3073x_dpll_pin *pin = pin_priv;
1256 struct device *dev = zldev->dev;
1257 u32 output_n_freq, output_p_freq;
1258 u8 out, signal_format, synth;
1259 u32 cur_div, new_div, ndiv;
1260 u32 synth_freq;
1261 int rc;
1262
1263 out = zl3073x_output_pin_out_get(pin->id);
1264 synth = zl3073x_out_synth_get(zldev, out);
1265 synth_freq = zl3073x_synth_freq_get(zldev, synth);
1266 new_div = synth_freq / (u32)frequency;
1267
1268 /* Get used signal format for the given output */
1269 signal_format = zl3073x_out_signal_format_get(zldev, out);
1270
1271 guard(mutex)(&zldev->multiop_lock);
1272
1273 /* Load output configuration */
1274 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
1275 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1276 if (rc)
1277 return rc;
1278
1279 /* Check signal format */
1280 if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV &&
1281 signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) {
1282 /* For non N-divided signal formats the frequency is computed
1283 * as division of synth frequency and output divisor.
1284 */
1285 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_DIV, new_div);
1286 if (rc)
1287 return rc;
1288
1289 /* For 50/50 duty cycle the divisor is equal to width */
1290 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_WIDTH, new_div);
1291 if (rc)
1292 return rc;
1293
1294 /* Commit output configuration */
1295 return zl3073x_mb_op(zldev,
1296 ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR,
1297 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1298 }
1299
1300 /* For N-divided signal format get current divisor */
1301 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &cur_div);
1302 if (rc)
1303 return rc;
1304
1305 /* Check output divisor for zero */
1306 if (!cur_div) {
1307 dev_err(dev, "Zero divisor for output %u got from device\n",
1308 out);
1309 return -EINVAL;
1310 }
1311
1312 /* Get N-pin divisor (shares the same register with esync */
1313 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, &ndiv);
1314 if (rc)
1315 return rc;
1316
1317 /* Check N-pin divisor for zero */
1318 if (!ndiv) {
1319 dev_err(dev,
1320 "Zero N-pin divisor for output %u got from device\n",
1321 out);
1322 return -EINVAL;
1323 }
1324
1325 /* Compute current output frequency for P-pin */
1326 output_p_freq = synth_freq / cur_div;
1327
1328 /* Compute current N-pin frequency */
1329 output_n_freq = output_p_freq / ndiv;
1330
1331 if (zl3073x_dpll_is_p_pin(pin)) {
1332 /* We are going to change output frequency for P-pin but
1333 * if the requested frequency is less than current N-pin
1334 * frequency then indicate a failure as we are not able
1335 * to compute N-pin divisor to keep its frequency unchanged.
1336 */
1337 if (frequency <= output_n_freq)
1338 return -EINVAL;
1339
1340 /* Update the output divisor */
1341 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_DIV, new_div);
1342 if (rc)
1343 return rc;
1344
1345 /* For 50/50 duty cycle the divisor is equal to width */
1346 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_WIDTH, new_div);
1347 if (rc)
1348 return rc;
1349
1350 /* Compute new divisor for N-pin */
1351 ndiv = (u32)frequency / output_n_freq;
1352 } else {
1353 /* We are going to change frequency of N-pin but if
1354 * the requested freq is greater or equal than freq of P-pin
1355 * in the output pair we cannot compute divisor for the N-pin.
1356 * In this case indicate a failure.
1357 */
1358 if (output_p_freq <= frequency)
1359 return -EINVAL;
1360
1361 /* Compute new divisor for N-pin */
1362 ndiv = output_p_freq / (u32)frequency;
1363 }
1364
1365 /* Update divisor for the N-pin */
1366 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, ndiv);
1367 if (rc)
1368 return rc;
1369
1370 /* For 50/50 duty cycle the divisor is equal to width */
1371 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, ndiv);
1372 if (rc)
1373 return rc;
1374
1375 /* Commit output configuration */
1376 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR,
1377 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1378 }
1379
1380 static int
zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack)1381 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
1382 void *pin_priv,
1383 const struct dpll_device *dpll,
1384 void *dpll_priv,
1385 s32 *phase_adjust,
1386 struct netlink_ext_ack *extack)
1387 {
1388 struct zl3073x_dpll *zldpll = dpll_priv;
1389 struct zl3073x_dev *zldev = zldpll->dev;
1390 struct zl3073x_dpll_pin *pin = pin_priv;
1391 u32 synth_freq;
1392 s32 phase_comp;
1393 u8 out, synth;
1394 int rc;
1395
1396 out = zl3073x_output_pin_out_get(pin->id);
1397 synth = zl3073x_out_synth_get(zldev, out);
1398 synth_freq = zl3073x_synth_freq_get(zldev, synth);
1399
1400 /* Check synth freq for zero */
1401 if (!synth_freq) {
1402 dev_err(zldev->dev, "Got zero synth frequency for output %u\n",
1403 out);
1404 return -EINVAL;
1405 }
1406
1407 guard(mutex)(&zldev->multiop_lock);
1408
1409 /* Read output configuration */
1410 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
1411 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1412 if (rc)
1413 return rc;
1414
1415 /* Read current output phase compensation */
1416 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, &phase_comp);
1417 if (rc)
1418 return rc;
1419
1420 /* Value in register is expressed in half synth clock cycles */
1421 phase_comp *= (int)div_u64(PSEC_PER_SEC, 2 * synth_freq);
1422
1423 /* Reverse two's complement negation applied during 'set' */
1424 *phase_adjust = -phase_comp;
1425
1426 return rc;
1427 }
1428
1429 static int
zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack)1430 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin,
1431 void *pin_priv,
1432 const struct dpll_device *dpll,
1433 void *dpll_priv,
1434 s32 phase_adjust,
1435 struct netlink_ext_ack *extack)
1436 {
1437 struct zl3073x_dpll *zldpll = dpll_priv;
1438 struct zl3073x_dev *zldev = zldpll->dev;
1439 struct zl3073x_dpll_pin *pin = pin_priv;
1440 int half_synth_cycle;
1441 u32 synth_freq;
1442 u8 out, synth;
1443 int rc;
1444
1445 /* Get attached synth */
1446 out = zl3073x_output_pin_out_get(pin->id);
1447 synth = zl3073x_out_synth_get(zldev, out);
1448
1449 /* Get synth's frequency */
1450 synth_freq = zl3073x_synth_freq_get(zldev, synth);
1451
1452 /* Value in register is expressed in half synth clock cycles so
1453 * the given phase adjustment a multiple of half synth clock.
1454 */
1455 half_synth_cycle = (int)div_u64(PSEC_PER_SEC, 2 * synth_freq);
1456
1457 if ((phase_adjust % half_synth_cycle) != 0) {
1458 NL_SET_ERR_MSG_FMT(extack,
1459 "Phase adjustment value has to be multiple of %d",
1460 half_synth_cycle);
1461 return -EINVAL;
1462 }
1463 phase_adjust /= half_synth_cycle;
1464
1465 /* The value in the register is stored as two's complement negation
1466 * of requested value.
1467 */
1468 phase_adjust = -phase_adjust;
1469
1470 guard(mutex)(&zldev->multiop_lock);
1471
1472 /* Read output configuration */
1473 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
1474 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1475 if (rc)
1476 return rc;
1477
1478 /* Write the requested value into the compensation register */
1479 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, phase_adjust);
1480 if (rc)
1481 return rc;
1482
1483 /* Update output configuration from mailbox */
1484 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR,
1485 ZL_REG_OUTPUT_MB_MASK, BIT(out));
1486 }
1487
1488 static int
zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)1489 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin,
1490 void *pin_priv,
1491 const struct dpll_device *dpll,
1492 void *dpll_priv,
1493 enum dpll_pin_state *state,
1494 struct netlink_ext_ack *extack)
1495 {
1496 /* If the output pin is registered then it is always connected */
1497 *state = DPLL_PIN_STATE_CONNECTED;
1498
1499 return 0;
1500 }
1501
1502 static int
zl3073x_dpll_lock_status_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack)1503 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv,
1504 enum dpll_lock_status *status,
1505 enum dpll_lock_status_error *status_error,
1506 struct netlink_ext_ack *extack)
1507 {
1508 struct zl3073x_dpll *zldpll = dpll_priv;
1509 struct zl3073x_dev *zldev = zldpll->dev;
1510 u8 mon_status, state;
1511 int rc;
1512
1513 switch (zldpll->refsel_mode) {
1514 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN:
1515 case ZL_DPLL_MODE_REFSEL_MODE_NCO:
1516 /* In FREERUN and NCO modes the DPLL is always unlocked */
1517 *status = DPLL_LOCK_STATUS_UNLOCKED;
1518
1519 return 0;
1520 default:
1521 break;
1522 }
1523
1524 /* Read DPLL monitor status */
1525 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id),
1526 &mon_status);
1527 if (rc)
1528 return rc;
1529 state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status);
1530
1531 switch (state) {
1532 case ZL_DPLL_MON_STATUS_STATE_LOCK:
1533 if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status))
1534 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ;
1535 else
1536 *status = DPLL_LOCK_STATUS_LOCKED;
1537 break;
1538 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER:
1539 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING:
1540 *status = DPLL_LOCK_STATUS_HOLDOVER;
1541 break;
1542 default:
1543 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n",
1544 mon_status);
1545 *status = DPLL_LOCK_STATUS_UNLOCKED;
1546 break;
1547 }
1548
1549 return 0;
1550 }
1551
1552 static int
zl3073x_dpll_mode_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode * mode,struct netlink_ext_ack * extack)1553 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv,
1554 enum dpll_mode *mode, struct netlink_ext_ack *extack)
1555 {
1556 struct zl3073x_dpll *zldpll = dpll_priv;
1557
1558 switch (zldpll->refsel_mode) {
1559 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN:
1560 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER:
1561 case ZL_DPLL_MODE_REFSEL_MODE_NCO:
1562 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK:
1563 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and
1564 * REFLOCK modes
1565 */
1566 *mode = DPLL_MODE_MANUAL;
1567 break;
1568 case ZL_DPLL_MODE_REFSEL_MODE_AUTO:
1569 /* Use AUTO for device AUTO mode */
1570 *mode = DPLL_MODE_AUTOMATIC;
1571 break;
1572 default:
1573 return -EINVAL;
1574 }
1575
1576 return 0;
1577 }
1578
1579 static int
zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device * dpll,void * dpll_priv,u32 * factor,struct netlink_ext_ack * extack)1580 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll,
1581 void *dpll_priv, u32 *factor,
1582 struct netlink_ext_ack *extack)
1583 {
1584 struct zl3073x_dpll *zldpll = dpll_priv;
1585
1586 *factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev);
1587
1588 return 0;
1589 }
1590
1591 static void
zl3073x_dpll_change_work(struct work_struct * work)1592 zl3073x_dpll_change_work(struct work_struct *work)
1593 {
1594 struct zl3073x_dpll *zldpll;
1595
1596 zldpll = container_of(work, struct zl3073x_dpll, change_work);
1597 dpll_device_change_ntf(zldpll->dpll_dev);
1598 }
1599
1600 static int
zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device * dpll,void * dpll_priv,u32 factor,struct netlink_ext_ack * extack)1601 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll,
1602 void *dpll_priv, u32 factor,
1603 struct netlink_ext_ack *extack)
1604 {
1605 struct zl3073x_dpll *item, *zldpll = dpll_priv;
1606 int rc;
1607
1608 if (factor > 15) {
1609 NL_SET_ERR_MSG_FMT(extack,
1610 "Phase offset average factor has to be from range <0,15>");
1611 return -EINVAL;
1612 }
1613
1614 rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor);
1615 if (rc) {
1616 NL_SET_ERR_MSG_FMT(extack,
1617 "Failed to set phase offset averaging factor");
1618 return rc;
1619 }
1620
1621 /* The averaging factor is common for all DPLL channels so after change
1622 * we have to send a notification for other DPLL devices.
1623 */
1624 list_for_each_entry(item, &zldpll->dev->dplls, list) {
1625 if (item != zldpll)
1626 schedule_work(&item->change_work);
1627 }
1628
1629 return 0;
1630 }
1631
1632 static int
zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state * state,struct netlink_ext_ack * extack)1633 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll,
1634 void *dpll_priv,
1635 enum dpll_feature_state *state,
1636 struct netlink_ext_ack *extack)
1637 {
1638 struct zl3073x_dpll *zldpll = dpll_priv;
1639
1640 if (zldpll->phase_monitor)
1641 *state = DPLL_FEATURE_STATE_ENABLE;
1642 else
1643 *state = DPLL_FEATURE_STATE_DISABLE;
1644
1645 return 0;
1646 }
1647
1648 static int
zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state state,struct netlink_ext_ack * extack)1649 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll,
1650 void *dpll_priv,
1651 enum dpll_feature_state state,
1652 struct netlink_ext_ack *extack)
1653 {
1654 struct zl3073x_dpll *zldpll = dpll_priv;
1655
1656 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE);
1657
1658 return 0;
1659 }
1660
1661 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = {
1662 .direction_get = zl3073x_dpll_pin_direction_get,
1663 .esync_get = zl3073x_dpll_input_pin_esync_get,
1664 .esync_set = zl3073x_dpll_input_pin_esync_set,
1665 .ffo_get = zl3073x_dpll_input_pin_ffo_get,
1666 .frequency_get = zl3073x_dpll_input_pin_frequency_get,
1667 .frequency_set = zl3073x_dpll_input_pin_frequency_set,
1668 .phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get,
1669 .phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get,
1670 .phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set,
1671 .prio_get = zl3073x_dpll_input_pin_prio_get,
1672 .prio_set = zl3073x_dpll_input_pin_prio_set,
1673 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get,
1674 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set,
1675 };
1676
1677 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = {
1678 .direction_get = zl3073x_dpll_pin_direction_get,
1679 .esync_get = zl3073x_dpll_output_pin_esync_get,
1680 .esync_set = zl3073x_dpll_output_pin_esync_set,
1681 .frequency_get = zl3073x_dpll_output_pin_frequency_get,
1682 .frequency_set = zl3073x_dpll_output_pin_frequency_set,
1683 .phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get,
1684 .phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set,
1685 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get,
1686 };
1687
1688 static const struct dpll_device_ops zl3073x_dpll_device_ops = {
1689 .lock_status_get = zl3073x_dpll_lock_status_get,
1690 .mode_get = zl3073x_dpll_mode_get,
1691 .phase_offset_avg_factor_get = zl3073x_dpll_phase_offset_avg_factor_get,
1692 .phase_offset_avg_factor_set = zl3073x_dpll_phase_offset_avg_factor_set,
1693 .phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get,
1694 .phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set,
1695 };
1696
1697 /**
1698 * zl3073x_dpll_pin_alloc - allocate DPLL pin
1699 * @zldpll: pointer to zl3073x_dpll
1700 * @dir: pin direction
1701 * @id: pin id
1702 *
1703 * Allocates and initializes zl3073x_dpll_pin structure for given
1704 * pin id and direction.
1705 *
1706 * Return: pointer to allocated structure on success, error pointer on error
1707 */
1708 static struct zl3073x_dpll_pin *
zl3073x_dpll_pin_alloc(struct zl3073x_dpll * zldpll,enum dpll_pin_direction dir,u8 id)1709 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir,
1710 u8 id)
1711 {
1712 struct zl3073x_dpll_pin *pin;
1713
1714 pin = kzalloc(sizeof(*pin), GFP_KERNEL);
1715 if (!pin)
1716 return ERR_PTR(-ENOMEM);
1717
1718 pin->dpll = zldpll;
1719 pin->dir = dir;
1720 pin->id = id;
1721
1722 return pin;
1723 }
1724
1725 /**
1726 * zl3073x_dpll_pin_free - deallocate DPLL pin
1727 * @pin: pin to free
1728 *
1729 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc.
1730 */
1731 static void
zl3073x_dpll_pin_free(struct zl3073x_dpll_pin * pin)1732 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin)
1733 {
1734 WARN(pin->dpll_pin, "DPLL pin is still registered\n");
1735
1736 kfree(pin);
1737 }
1738
1739 /**
1740 * zl3073x_dpll_pin_register - register DPLL pin
1741 * @pin: pointer to DPLL pin
1742 * @index: absolute pin index for registration
1743 *
1744 * Registers given DPLL pin into DPLL sub-system.
1745 *
1746 * Return: 0 on success, <0 on error
1747 */
1748 static int
zl3073x_dpll_pin_register(struct zl3073x_dpll_pin * pin,u32 index)1749 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index)
1750 {
1751 struct zl3073x_dpll *zldpll = pin->dpll;
1752 struct zl3073x_pin_props *props;
1753 const struct dpll_pin_ops *ops;
1754 int rc;
1755
1756 /* Get pin properties */
1757 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id);
1758 if (IS_ERR(props))
1759 return PTR_ERR(props);
1760
1761 /* Save package label & esync capability */
1762 strscpy(pin->label, props->package_label);
1763 pin->esync_control = props->esync_control;
1764
1765 if (zl3073x_dpll_is_input_pin(pin)) {
1766 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio);
1767 if (rc)
1768 goto err_prio_get;
1769
1770 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) {
1771 /* Clamp prio to max value & mark pin non-selectable */
1772 pin->prio = ZL_DPLL_REF_PRIO_MAX;
1773 pin->selectable = false;
1774 } else {
1775 /* Mark pin as selectable */
1776 pin->selectable = true;
1777 }
1778 }
1779
1780 /* Create or get existing DPLL pin */
1781 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE,
1782 &props->dpll_props);
1783 if (IS_ERR(pin->dpll_pin)) {
1784 rc = PTR_ERR(pin->dpll_pin);
1785 goto err_pin_get;
1786 }
1787
1788 if (zl3073x_dpll_is_input_pin(pin))
1789 ops = &zl3073x_dpll_input_pin_ops;
1790 else
1791 ops = &zl3073x_dpll_output_pin_ops;
1792
1793 /* Register the pin */
1794 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin);
1795 if (rc)
1796 goto err_register;
1797
1798 /* Free pin properties */
1799 zl3073x_pin_props_put(props);
1800
1801 return 0;
1802
1803 err_register:
1804 dpll_pin_put(pin->dpll_pin);
1805 err_prio_get:
1806 pin->dpll_pin = NULL;
1807 err_pin_get:
1808 zl3073x_pin_props_put(props);
1809
1810 return rc;
1811 }
1812
1813 /**
1814 * zl3073x_dpll_pin_unregister - unregister DPLL pin
1815 * @pin: pointer to DPLL pin
1816 *
1817 * Unregisters pin previously registered by @zl3073x_dpll_pin_register.
1818 */
1819 static void
zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin * pin)1820 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin)
1821 {
1822 struct zl3073x_dpll *zldpll = pin->dpll;
1823 const struct dpll_pin_ops *ops;
1824
1825 WARN(!pin->dpll_pin, "DPLL pin is not registered\n");
1826
1827 if (zl3073x_dpll_is_input_pin(pin))
1828 ops = &zl3073x_dpll_input_pin_ops;
1829 else
1830 ops = &zl3073x_dpll_output_pin_ops;
1831
1832 /* Unregister the pin */
1833 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin);
1834
1835 dpll_pin_put(pin->dpll_pin);
1836 pin->dpll_pin = NULL;
1837 }
1838
1839 /**
1840 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins
1841 * @zldpll: pointer to zl3073x_dpll structure
1842 *
1843 * Enumerates all DPLL pins registered to given DPLL device and
1844 * unregisters them.
1845 */
1846 static void
zl3073x_dpll_pins_unregister(struct zl3073x_dpll * zldpll)1847 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll)
1848 {
1849 struct zl3073x_dpll_pin *pin, *next;
1850
1851 list_for_each_entry_safe(pin, next, &zldpll->pins, list) {
1852 zl3073x_dpll_pin_unregister(pin);
1853 list_del(&pin->list);
1854 zl3073x_dpll_pin_free(pin);
1855 }
1856 }
1857
1858 /**
1859 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable
1860 * @zldpll: pointer to zl3073x_dpll structure
1861 * @dir: pin direction
1862 * @index: pin index
1863 *
1864 * Checks if the given pin can be registered to given DPLL. For both
1865 * directions the pin can be registered if it is enabled. In case of
1866 * differential signal type only P-pin is reported as registrable.
1867 * And additionally for the output pin, the pin can be registered only
1868 * if it is connected to synthesizer that is driven by given DPLL.
1869 *
1870 * Return: true if the pin is registrable, false if not
1871 */
1872 static bool
zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll * zldpll,enum dpll_pin_direction dir,u8 index)1873 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll,
1874 enum dpll_pin_direction dir, u8 index)
1875 {
1876 struct zl3073x_dev *zldev = zldpll->dev;
1877 bool is_diff, is_enabled;
1878 const char *name;
1879
1880 if (dir == DPLL_PIN_DIRECTION_INPUT) {
1881 u8 ref = zl3073x_input_pin_ref_get(index);
1882
1883 name = "REF";
1884
1885 /* Skip the pin if the DPLL is running in NCO mode */
1886 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO)
1887 return false;
1888
1889 is_diff = zl3073x_ref_is_diff(zldev, ref);
1890 is_enabled = zl3073x_ref_is_enabled(zldev, ref);
1891 } else {
1892 /* Output P&N pair shares single HW output */
1893 u8 out = zl3073x_output_pin_out_get(index);
1894
1895 name = "OUT";
1896
1897 /* Skip the pin if it is connected to different DPLL channel */
1898 if (zl3073x_out_dpll_get(zldev, out) != zldpll->id) {
1899 dev_dbg(zldev->dev,
1900 "%s%u is driven by different DPLL\n", name,
1901 out);
1902
1903 return false;
1904 }
1905
1906 is_diff = zl3073x_out_is_diff(zldev, out);
1907 is_enabled = zl3073x_output_pin_is_enabled(zldev, index);
1908 }
1909
1910 /* Skip N-pin if the corresponding input/output is differential */
1911 if (is_diff && zl3073x_is_n_pin(index)) {
1912 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n",
1913 name, index / 2);
1914
1915 return false;
1916 }
1917
1918 /* Skip the pin if it is disabled */
1919 if (!is_enabled) {
1920 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2,
1921 zl3073x_is_p_pin(index) ? 'P' : 'N');
1922
1923 return false;
1924 }
1925
1926 return true;
1927 }
1928
1929 /**
1930 * zl3073x_dpll_pins_register - register all registerable DPLL pins
1931 * @zldpll: pointer to zl3073x_dpll structure
1932 *
1933 * Enumerates all possible input/output pins and registers all of them
1934 * that are registrable.
1935 *
1936 * Return: 0 on success, <0 on error
1937 */
1938 static int
zl3073x_dpll_pins_register(struct zl3073x_dpll * zldpll)1939 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll)
1940 {
1941 struct zl3073x_dpll_pin *pin;
1942 enum dpll_pin_direction dir;
1943 u8 id, index;
1944 int rc;
1945
1946 /* Process input pins */
1947 for (index = 0; index < ZL3073X_NUM_PINS; index++) {
1948 /* First input pins and then output pins */
1949 if (index < ZL3073X_NUM_INPUT_PINS) {
1950 id = index;
1951 dir = DPLL_PIN_DIRECTION_INPUT;
1952 } else {
1953 id = index - ZL3073X_NUM_INPUT_PINS;
1954 dir = DPLL_PIN_DIRECTION_OUTPUT;
1955 }
1956
1957 /* Check if the pin registrable to this DPLL */
1958 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id))
1959 continue;
1960
1961 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id);
1962 if (IS_ERR(pin)) {
1963 rc = PTR_ERR(pin);
1964 goto error;
1965 }
1966
1967 rc = zl3073x_dpll_pin_register(pin, index);
1968 if (rc)
1969 goto error;
1970
1971 list_add(&pin->list, &zldpll->pins);
1972 }
1973
1974 return 0;
1975
1976 error:
1977 zl3073x_dpll_pins_unregister(zldpll);
1978
1979 return rc;
1980 }
1981
1982 /**
1983 * zl3073x_dpll_device_register - register DPLL device
1984 * @zldpll: pointer to zl3073x_dpll structure
1985 *
1986 * Registers given DPLL device into DPLL sub-system.
1987 *
1988 * Return: 0 on success, <0 on error
1989 */
1990 static int
zl3073x_dpll_device_register(struct zl3073x_dpll * zldpll)1991 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll)
1992 {
1993 struct zl3073x_dev *zldev = zldpll->dev;
1994 u8 dpll_mode_refsel;
1995 int rc;
1996
1997 /* Read DPLL mode and forcibly selected reference */
1998 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id),
1999 &dpll_mode_refsel);
2000 if (rc)
2001 return rc;
2002
2003 /* Extract mode and selected input reference */
2004 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE,
2005 dpll_mode_refsel);
2006 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF,
2007 dpll_mode_refsel);
2008
2009 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id,
2010 THIS_MODULE);
2011 if (IS_ERR(zldpll->dpll_dev)) {
2012 rc = PTR_ERR(zldpll->dpll_dev);
2013 zldpll->dpll_dev = NULL;
2014
2015 return rc;
2016 }
2017
2018 rc = dpll_device_register(zldpll->dpll_dev,
2019 zl3073x_prop_dpll_type_get(zldev, zldpll->id),
2020 &zl3073x_dpll_device_ops, zldpll);
2021 if (rc) {
2022 dpll_device_put(zldpll->dpll_dev);
2023 zldpll->dpll_dev = NULL;
2024 }
2025
2026 return rc;
2027 }
2028
2029 /**
2030 * zl3073x_dpll_device_unregister - unregister DPLL device
2031 * @zldpll: pointer to zl3073x_dpll structure
2032 *
2033 * Unregisters given DPLL device from DPLL sub-system previously registered
2034 * by @zl3073x_dpll_device_register.
2035 */
2036 static void
zl3073x_dpll_device_unregister(struct zl3073x_dpll * zldpll)2037 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll)
2038 {
2039 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n");
2040
2041 cancel_work_sync(&zldpll->change_work);
2042
2043 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops,
2044 zldpll);
2045 dpll_device_put(zldpll->dpll_dev);
2046 zldpll->dpll_dev = NULL;
2047 }
2048
2049 /**
2050 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change
2051 * @pin: pin to check
2052 *
2053 * Check for the change of DPLL to connected pin phase offset change.
2054 *
2055 * Return: true on phase offset change, false otherwise
2056 */
2057 static bool
zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin * pin)2058 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin)
2059 {
2060 struct zl3073x_dpll *zldpll = pin->dpll;
2061 struct zl3073x_dev *zldev = zldpll->dev;
2062 unsigned int reg;
2063 s64 phase_offset;
2064 u8 ref;
2065 int rc;
2066
2067 ref = zl3073x_input_pin_ref_get(pin->id);
2068
2069 /* Select register to read phase offset value depending on pin and
2070 * phase monitor state:
2071 * 1) For connected pin use dpll_phase_err_data register
2072 * 2) For other pins use appropriate ref_phase register if the phase
2073 * monitor feature is enabled and reference monitor does not
2074 * report signal errors for given input pin
2075 */
2076 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) {
2077 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id);
2078 } else if (zldpll->phase_monitor) {
2079 u8 status;
2080
2081 /* Get reference monitor status */
2082 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref),
2083 &status);
2084 if (rc) {
2085 dev_err(zldev->dev,
2086 "Failed to read %s refmon status: %pe\n",
2087 pin->label, ERR_PTR(rc));
2088
2089 return false;
2090 }
2091
2092 if (status != ZL_REF_MON_STATUS_OK)
2093 return false;
2094
2095 reg = ZL_REG_REF_PHASE(ref);
2096 } else {
2097 /* The pin is not connected or phase monitor disabled */
2098 return false;
2099 }
2100
2101 /* Read measured phase offset value */
2102 rc = zl3073x_read_u48(zldev, reg, &phase_offset);
2103 if (rc) {
2104 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n",
2105 ERR_PTR(rc));
2106
2107 return false;
2108 }
2109
2110 /* Convert to ps */
2111 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100);
2112
2113 /* Compare with previous value */
2114 if (phase_offset != pin->phase_offset) {
2115 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n",
2116 pin->label, pin->phase_offset, phase_offset);
2117 pin->phase_offset = phase_offset;
2118
2119 return true;
2120 }
2121
2122 return false;
2123 }
2124
2125 /**
2126 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change
2127 * @pin: pin to check
2128 *
2129 * Check for the given pin's fractional frequency change.
2130 *
2131 * Return: true on fractional frequency offset change, false otherwise
2132 */
2133 static bool
zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin * pin)2134 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin)
2135 {
2136 struct zl3073x_dpll *zldpll = pin->dpll;
2137 struct zl3073x_dev *zldev = zldpll->dev;
2138 u8 ref, status;
2139 s64 ffo;
2140 int rc;
2141
2142 /* Get reference monitor status */
2143 ref = zl3073x_input_pin_ref_get(pin->id);
2144 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), &status);
2145 if (rc) {
2146 dev_err(zldev->dev, "Failed to read %s refmon status: %pe\n",
2147 pin->label, ERR_PTR(rc));
2148
2149 return false;
2150 }
2151
2152 /* Do not report ffo changes if the reference monitor report errors */
2153 if (status != ZL_REF_MON_STATUS_OK)
2154 return false;
2155
2156 /* Get the latest measured ref's ffo */
2157 ffo = zl3073x_ref_ffo_get(zldev, ref);
2158
2159 /* Compare with previous value */
2160 if (pin->freq_offset != ffo) {
2161 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n",
2162 pin->label, pin->freq_offset, ffo);
2163 pin->freq_offset = ffo;
2164
2165 return true;
2166 }
2167
2168 return false;
2169 }
2170
2171 /**
2172 * zl3073x_dpll_changes_check - check for changes and send notifications
2173 * @zldpll: pointer to zl3073x_dpll structure
2174 *
2175 * Checks for changes on given DPLL device and its registered DPLL pins
2176 * and sends notifications about them.
2177 *
2178 * This function is periodically called from @zl3073x_dev_periodic_work.
2179 */
2180 void
zl3073x_dpll_changes_check(struct zl3073x_dpll * zldpll)2181 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll)
2182 {
2183 struct zl3073x_dev *zldev = zldpll->dev;
2184 enum dpll_lock_status lock_status;
2185 struct device *dev = zldev->dev;
2186 struct zl3073x_dpll_pin *pin;
2187 int rc;
2188
2189 zldpll->check_count++;
2190
2191 /* Get current lock status for the DPLL */
2192 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll,
2193 &lock_status, NULL, NULL);
2194 if (rc) {
2195 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n",
2196 zldpll->id, ERR_PTR(rc));
2197 return;
2198 }
2199
2200 /* If lock status was changed then notify DPLL core */
2201 if (zldpll->lock_status != lock_status) {
2202 zldpll->lock_status = lock_status;
2203 dpll_device_change_ntf(zldpll->dpll_dev);
2204 }
2205
2206 /* Input pin monitoring does make sense only in automatic
2207 * or forced reference modes.
2208 */
2209 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO &&
2210 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK)
2211 return;
2212
2213 /* Update phase offset latch registers for this DPLL if the phase
2214 * offset monitor feature is enabled.
2215 */
2216 if (zldpll->phase_monitor) {
2217 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id);
2218 if (rc) {
2219 dev_err(zldev->dev,
2220 "Failed to update phase offsets: %pe\n",
2221 ERR_PTR(rc));
2222 return;
2223 }
2224 }
2225
2226 list_for_each_entry(pin, &zldpll->pins, list) {
2227 enum dpll_pin_state state;
2228 bool pin_changed = false;
2229
2230 /* Output pins change checks are not necessary because output
2231 * states are constant.
2232 */
2233 if (!zl3073x_dpll_is_input_pin(pin))
2234 continue;
2235
2236 rc = zl3073x_dpll_ref_state_get(pin, &state);
2237 if (rc) {
2238 dev_err(dev,
2239 "Failed to get %s on DPLL%u state: %pe\n",
2240 pin->label, zldpll->id, ERR_PTR(rc));
2241 return;
2242 }
2243
2244 if (state != pin->pin_state) {
2245 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label,
2246 pin->pin_state, state);
2247 pin->pin_state = state;
2248 pin_changed = true;
2249 }
2250
2251 /* Check for phase offset and ffo change once per second */
2252 if (zldpll->check_count % 2 == 0) {
2253 if (zl3073x_dpll_pin_phase_offset_check(pin))
2254 pin_changed = true;
2255
2256 if (zl3073x_dpll_pin_ffo_check(pin))
2257 pin_changed = true;
2258 }
2259
2260 if (pin_changed)
2261 dpll_pin_change_ntf(pin->dpll_pin);
2262 }
2263 }
2264
2265 /**
2266 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments
2267 * @zldev: pointer to zl3073x device
2268 *
2269 * Performs initial fine phase adjustments needed per datasheet.
2270 *
2271 * Return: 0 on success, <0 on error
2272 */
2273 int
zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev * zldev)2274 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev)
2275 {
2276 int rc;
2277
2278 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f);
2279 if (rc)
2280 return rc;
2281
2282 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01);
2283 if (rc)
2284 return rc;
2285
2286 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff);
2287 if (rc)
2288 return rc;
2289
2290 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01);
2291 if (rc)
2292 return rc;
2293
2294 return rc;
2295 }
2296
2297 /**
2298 * zl3073x_dpll_alloc - allocate DPLL device
2299 * @zldev: pointer to zl3073x device
2300 * @ch: DPLL channel number
2301 *
2302 * Allocates DPLL device structure for given DPLL channel.
2303 *
2304 * Return: pointer to DPLL device on success, error pointer on error
2305 */
2306 struct zl3073x_dpll *
zl3073x_dpll_alloc(struct zl3073x_dev * zldev,u8 ch)2307 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch)
2308 {
2309 struct zl3073x_dpll *zldpll;
2310
2311 zldpll = kzalloc(sizeof(*zldpll), GFP_KERNEL);
2312 if (!zldpll)
2313 return ERR_PTR(-ENOMEM);
2314
2315 zldpll->dev = zldev;
2316 zldpll->id = ch;
2317 INIT_LIST_HEAD(&zldpll->pins);
2318 INIT_WORK(&zldpll->change_work, zl3073x_dpll_change_work);
2319
2320 return zldpll;
2321 }
2322
2323 /**
2324 * zl3073x_dpll_free - free DPLL device
2325 * @zldpll: pointer to zl3073x_dpll structure
2326 *
2327 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc.
2328 */
2329 void
zl3073x_dpll_free(struct zl3073x_dpll * zldpll)2330 zl3073x_dpll_free(struct zl3073x_dpll *zldpll)
2331 {
2332 WARN(zldpll->dpll_dev, "DPLL device is still registered\n");
2333
2334 kfree(zldpll);
2335 }
2336
2337 /**
2338 * zl3073x_dpll_register - register DPLL device and all its pins
2339 * @zldpll: pointer to zl3073x_dpll structure
2340 *
2341 * Registers given DPLL device and all its pins into DPLL sub-system.
2342 *
2343 * Return: 0 on success, <0 on error
2344 */
2345 int
zl3073x_dpll_register(struct zl3073x_dpll * zldpll)2346 zl3073x_dpll_register(struct zl3073x_dpll *zldpll)
2347 {
2348 int rc;
2349
2350 rc = zl3073x_dpll_device_register(zldpll);
2351 if (rc)
2352 return rc;
2353
2354 rc = zl3073x_dpll_pins_register(zldpll);
2355 if (rc) {
2356 zl3073x_dpll_device_unregister(zldpll);
2357 return rc;
2358 }
2359
2360 return 0;
2361 }
2362
2363 /**
2364 * zl3073x_dpll_unregister - unregister DPLL device and its pins
2365 * @zldpll: pointer to zl3073x_dpll structure
2366 *
2367 * Unregisters given DPLL device and all its pins from DPLL sub-system
2368 * previously registered by @zl3073x_dpll_register.
2369 */
2370 void
zl3073x_dpll_unregister(struct zl3073x_dpll * zldpll)2371 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll)
2372 {
2373 /* Unregister all pins and dpll */
2374 zl3073x_dpll_pins_unregister(zldpll);
2375 zl3073x_dpll_device_unregister(zldpll);
2376 }
2377