1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO controller in LSI ZEVIO SoCs.
4 *
5 * Author: Fabian Vogt <fabian@ritter-vogt.de>
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/platform_device.h>
13 #include <linux/property.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16
17 #include <linux/gpio/driver.h>
18
19 /*
20 * Memory layout:
21 * This chip has four gpio sections, each controls 8 GPIOs.
22 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
23 * Disclaimer: Reverse engineered!
24 * For more information refer to:
25 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
26 *
27 * 0x00-0x3F: Section 0
28 * +0x00: Masked interrupt status (read-only)
29 * +0x04: R: Interrupt status W: Reset interrupt status
30 * +0x08: R: Interrupt mask W: Mask interrupt
31 * +0x0C: W: Unmask interrupt (write-only)
32 * +0x10: Direction: I/O=1/0
33 * +0x14: Output
34 * +0x18: Input (read-only)
35 * +0x20: R: Level interrupt W: Set as level interrupt
36 * 0x40-0x7F: Section 1
37 * 0x80-0xBF: Section 2
38 * 0xC0-0xFF: Section 3
39 */
40
41 #define ZEVIO_GPIO_SECTION_SIZE 0x40
42
43 /* Offsets to various registers */
44 #define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
45 #define ZEVIO_GPIO_INT_STATUS 0x04
46 #define ZEVIO_GPIO_INT_UNMASK 0x08
47 #define ZEVIO_GPIO_INT_MASK 0x0C
48 #define ZEVIO_GPIO_DIRECTION 0x10
49 #define ZEVIO_GPIO_OUTPUT 0x14
50 #define ZEVIO_GPIO_INPUT 0x18
51 #define ZEVIO_GPIO_INT_STICKY 0x20
52
53 /* Bit number of GPIO in its section */
54 #define ZEVIO_GPIO_BIT(gpio) (gpio&7)
55
56 struct zevio_gpio {
57 struct gpio_chip chip;
58 spinlock_t lock;
59 void __iomem *regs;
60 };
61
zevio_gpio_port_get(struct zevio_gpio * c,unsigned pin,unsigned port_offset)62 static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
63 unsigned port_offset)
64 {
65 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
66 return readl(c->regs + section_offset + port_offset);
67 }
68
zevio_gpio_port_set(struct zevio_gpio * c,unsigned pin,unsigned port_offset,u32 val)69 static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
70 unsigned port_offset, u32 val)
71 {
72 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
73 writel(val, c->regs + section_offset + port_offset);
74 }
75
76 /* Functions for struct gpio_chip */
zevio_gpio_get(struct gpio_chip * chip,unsigned pin)77 static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
78 {
79 struct zevio_gpio *controller = gpiochip_get_data(chip);
80 u32 val, dir;
81
82 spin_lock(&controller->lock);
83 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
84 if (dir & BIT(ZEVIO_GPIO_BIT(pin)))
85 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
86 else
87 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
88 spin_unlock(&controller->lock);
89
90 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
91 }
92
zevio_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)93 static int zevio_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
94 {
95 struct zevio_gpio *controller = gpiochip_get_data(chip);
96 u32 val;
97
98 spin_lock(&controller->lock);
99 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
100 if (value)
101 val |= BIT(ZEVIO_GPIO_BIT(pin));
102 else
103 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
104
105 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
106 spin_unlock(&controller->lock);
107
108 return 0;
109 }
110
zevio_gpio_direction_input(struct gpio_chip * chip,unsigned pin)111 static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
112 {
113 struct zevio_gpio *controller = gpiochip_get_data(chip);
114 u32 val;
115
116 spin_lock(&controller->lock);
117
118 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
119 val |= BIT(ZEVIO_GPIO_BIT(pin));
120 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
121
122 spin_unlock(&controller->lock);
123
124 return 0;
125 }
126
zevio_gpio_direction_output(struct gpio_chip * chip,unsigned pin,int value)127 static int zevio_gpio_direction_output(struct gpio_chip *chip,
128 unsigned pin, int value)
129 {
130 struct zevio_gpio *controller = gpiochip_get_data(chip);
131 u32 val;
132
133 spin_lock(&controller->lock);
134 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
135 if (value)
136 val |= BIT(ZEVIO_GPIO_BIT(pin));
137 else
138 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
139
140 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
141 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
142 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
143 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
144
145 spin_unlock(&controller->lock);
146
147 return 0;
148 }
149
zevio_gpio_to_irq(struct gpio_chip * chip,unsigned pin)150 static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
151 {
152 /*
153 * TODO: Implement IRQs.
154 * Not implemented yet due to weird lockups
155 */
156
157 return -ENXIO;
158 }
159
160 static const struct gpio_chip zevio_gpio_chip = {
161 .direction_input = zevio_gpio_direction_input,
162 .direction_output = zevio_gpio_direction_output,
163 .set = zevio_gpio_set,
164 .get = zevio_gpio_get,
165 .to_irq = zevio_gpio_to_irq,
166 .base = 0,
167 .owner = THIS_MODULE,
168 .ngpio = 32,
169 };
170
171 /* Initialization */
zevio_gpio_probe(struct platform_device * pdev)172 static int zevio_gpio_probe(struct platform_device *pdev)
173 {
174 struct device *dev = &pdev->dev;
175 struct zevio_gpio *controller;
176 int status, i;
177
178 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
179 if (!controller)
180 return -ENOMEM;
181
182 /* Copy our reference */
183 controller->chip = zevio_gpio_chip;
184 controller->chip.parent = &pdev->dev;
185
186 controller->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev));
187 if (!controller->chip.label)
188 return -ENOMEM;
189
190 controller->regs = devm_platform_ioremap_resource(pdev, 0);
191 if (IS_ERR(controller->regs))
192 return dev_err_probe(&pdev->dev, PTR_ERR(controller->regs),
193 "failed to ioremap memory resource\n");
194
195 status = devm_gpiochip_add_data(&pdev->dev, &controller->chip, controller);
196 if (status) {
197 dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
198 return status;
199 }
200
201 spin_lock_init(&controller->lock);
202
203 /* Disable interrupts, they only cause errors */
204 for (i = 0; i < controller->chip.ngpio; i += 8)
205 zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
206
207 dev_dbg(controller->chip.parent, "ZEVIO GPIO controller set up!\n");
208
209 return 0;
210 }
211
212 static const struct of_device_id zevio_gpio_of_match[] = {
213 { .compatible = "lsi,zevio-gpio", },
214 { },
215 };
216
217 static struct platform_driver zevio_gpio_driver = {
218 .driver = {
219 .name = "gpio-zevio",
220 .of_match_table = zevio_gpio_of_match,
221 .suppress_bind_attrs = true,
222 },
223 .probe = zevio_gpio_probe,
224 };
225 builtin_platform_driver(zevio_gpio_driver);
226