1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Motorcomm 8511/8521/8531/8531S/8821 PHY driver. 4 * 5 * Author: Peter Geis <pgwipeout@gmail.com> 6 * Author: Frank <Frank.Sae@motor-comm.com> 7 */ 8 9 #include <linux/etherdevice.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/phy.h> 13 #include <linux/of.h> 14 15 #define PHY_ID_YT8511 0x0000010a 16 #define PHY_ID_YT8521 0x0000011a 17 #define PHY_ID_YT8531 0x4f51e91b 18 #define PHY_ID_YT8531S 0x4f51e91a 19 #define PHY_ID_YT8821 0x4f51ea19 20 /* YT8521/YT8531S/YT8821 Register Overview 21 * UTP Register space | FIBER Register space 22 * ------------------------------------------------------------ 23 * | UTP MII | FIBER MII | 24 * | UTP MMD | | 25 * | UTP Extended | FIBER Extended | 26 * ------------------------------------------------------------ 27 * | Common Extended | 28 * ------------------------------------------------------------ 29 */ 30 31 /* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */ 32 33 /* Specific Function Control Register */ 34 #define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10 35 36 /* 2b00 Manual MDI configuration 37 * 2b01 Manual MDIX configuration 38 * 2b10 Reserved 39 * 2b11 Enable automatic crossover for all modes *default* 40 */ 41 #define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5)) 42 #define YTPHY_SFCR_CROSSOVER_EN BIT(3) 43 #define YTPHY_SFCR_SQE_TEST_EN BIT(2) 44 #define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1) 45 #define YTPHY_SFCR_JABBER_DIS BIT(0) 46 47 /* Specific Status Register */ 48 #define YTPHY_SPECIFIC_STATUS_REG 0x11 49 #define YTPHY_SSR_SPEED_MASK ((0x3 << 14) | BIT(9)) 50 #define YTPHY_SSR_SPEED_10M ((0x0 << 14)) 51 #define YTPHY_SSR_SPEED_100M ((0x1 << 14)) 52 #define YTPHY_SSR_SPEED_1000M ((0x2 << 14)) 53 #define YTPHY_SSR_SPEED_10G ((0x3 << 14)) 54 #define YTPHY_SSR_SPEED_2500M ((0x0 << 14) | BIT(9)) 55 #define YTPHY_SSR_DUPLEX_OFFSET 13 56 #define YTPHY_SSR_DUPLEX BIT(13) 57 #define YTPHY_SSR_PAGE_RECEIVED BIT(12) 58 #define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11) 59 #define YTPHY_SSR_LINK BIT(10) 60 #define YTPHY_SSR_MDIX_CROSSOVER BIT(6) 61 #define YTPHY_SSR_DOWNGRADE BIT(5) 62 #define YTPHY_SSR_TRANSMIT_PAUSE BIT(3) 63 #define YTPHY_SSR_RECEIVE_PAUSE BIT(2) 64 #define YTPHY_SSR_POLARITY BIT(1) 65 #define YTPHY_SSR_JABBER BIT(0) 66 67 /* Interrupt enable Register */ 68 #define YTPHY_INTERRUPT_ENABLE_REG 0x12 69 #define YTPHY_IER_WOL BIT(6) 70 71 /* Interrupt Status Register */ 72 #define YTPHY_INTERRUPT_STATUS_REG 0x13 73 #define YTPHY_ISR_AUTONEG_ERR BIT(15) 74 #define YTPHY_ISR_SPEED_CHANGED BIT(14) 75 #define YTPHY_ISR_DUPLEX_CHANGED BIT(13) 76 #define YTPHY_ISR_PAGE_RECEIVED BIT(12) 77 #define YTPHY_ISR_LINK_FAILED BIT(11) 78 #define YTPHY_ISR_LINK_SUCCESSED BIT(10) 79 #define YTPHY_ISR_WOL BIT(6) 80 #define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5) 81 #define YTPHY_ISR_SERDES_LINK_FAILED BIT(3) 82 #define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2) 83 #define YTPHY_ISR_POLARITY_CHANGED BIT(1) 84 #define YTPHY_ISR_JABBER_HAPPENED BIT(0) 85 86 /* Speed Auto Downgrade Control Register */ 87 #define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14 88 #define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5) 89 90 /* If these bits are set to 3, the PHY attempts five times ( 3(set value) + 91 * additional 2) before downgrading, default 0x3 92 */ 93 #define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2) 94 95 /* Rx Error Counter Register */ 96 #define YTPHY_RX_ERROR_COUNTER_REG 0x15 97 98 /* Extended Register's Address Offset Register */ 99 #define YTPHY_PAGE_SELECT 0x1E 100 101 /* Extended Register's Data Register */ 102 #define YTPHY_PAGE_DATA 0x1F 103 104 /* FIBER Auto-Negotiation link partner ability */ 105 #define YTPHY_FLPA_PAUSE (0x3 << 7) 106 #define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7) 107 108 #define YT8511_PAGE_SELECT 0x1e 109 #define YT8511_PAGE 0x1f 110 #define YT8511_EXT_CLK_GATE 0x0c 111 #define YT8511_EXT_DELAY_DRIVE 0x0d 112 #define YT8511_EXT_SLEEP_CTRL 0x27 113 114 /* 2b00 25m from pll 115 * 2b01 25m from xtl *default* 116 * 2b10 62.m from pll 117 * 2b11 125m from pll 118 */ 119 #define YT8511_CLK_125M (BIT(2) | BIT(1)) 120 #define YT8511_PLLON_SLP BIT(14) 121 122 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */ 123 #define YT8511_DELAY_RX BIT(0) 124 125 /* TX Gig-E Delay is bits 7:4, default 0x5 126 * TX Fast-E Delay is bits 15:12, default 0xf 127 * Delay = 150ps * N - 250ps 128 * On = 2000ps, off = 50ps 129 */ 130 #define YT8511_DELAY_GE_TX_EN (0xf << 4) 131 #define YT8511_DELAY_GE_TX_DIS (0x2 << 4) 132 #define YT8511_DELAY_FE_TX_EN (0xf << 12) 133 #define YT8511_DELAY_FE_TX_DIS (0x2 << 12) 134 135 /* Extended register is different from MMD Register and MII Register. 136 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to 137 * operate extended register. 138 * Extended Register start 139 */ 140 141 /* Phy gmii clock gating Register */ 142 #define YT8521_CLOCK_GATING_REG 0xC 143 #define YT8521_CGR_RX_CLK_EN BIT(12) 144 145 #define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27 146 #define YT8521_ESC1R_SLEEP_SW BIT(15) 147 #define YT8521_ESC1R_PLLON_SLP BIT(14) 148 149 /* Phy fiber Link timer cfg2 Register */ 150 #define YT8521_LINK_TIMER_CFG2_REG 0xA5 151 #define YT8521_LTCR_EN_AUTOSEN BIT(15) 152 153 /* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers 154 * of yt8521 phy. There is no need to switch reg space when operating these 155 * registers. 156 */ 157 158 #define YT8521_REG_SPACE_SELECT_REG 0xA000 159 #define YT8521_RSSR_SPACE_MASK BIT(1) 160 #define YT8521_RSSR_FIBER_SPACE (0x1 << 1) 161 #define YT8521_RSSR_UTP_SPACE (0x0 << 1) 162 #define YT8521_RSSR_TO_BE_ARBITRATED (0xFF) 163 164 #define YT8521_CHIP_CONFIG_REG 0xA001 165 #define YT8521_CCR_SW_RST BIT(15) 166 #define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4) 167 #define YT8531_LDO_VOL_3V3 0x0 168 #define YT8531_LDO_VOL_1V8 0x2 169 170 /* 1b0 disable 1.9ns rxc clock delay *default* 171 * 1b1 enable 1.9ns rxc clock delay 172 */ 173 #define YT8521_CCR_RXC_DLY_EN BIT(8) 174 #define YT8521_CCR_RXC_DLY_1_900_NS 1900 175 176 #define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0)) 177 #define YT8521_CCR_MODE_UTP_TO_RGMII 0 178 #define YT8521_CCR_MODE_FIBER_TO_RGMII 1 179 #define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2 180 #define YT8521_CCR_MODE_UTP_TO_SGMII 3 181 #define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4 182 #define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5 183 #define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6 184 #define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7 185 186 /* 3 phy polling modes,poll mode combines utp and fiber mode*/ 187 #define YT8521_MODE_FIBER 0x1 188 #define YT8521_MODE_UTP 0x2 189 #define YT8521_MODE_POLL 0x3 190 191 #define YT8521_RGMII_CONFIG1_REG 0xA003 192 /* 1b0 use original tx_clk_rgmii *default* 193 * 1b1 use inverted tx_clk_rgmii. 194 */ 195 #define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14) 196 #define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10) 197 #define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) 198 #define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) 199 #define YT8521_RC1R_RGMII_0_000_NS 0 200 #define YT8521_RC1R_RGMII_0_150_NS 1 201 #define YT8521_RC1R_RGMII_0_300_NS 2 202 #define YT8521_RC1R_RGMII_0_450_NS 3 203 #define YT8521_RC1R_RGMII_0_600_NS 4 204 #define YT8521_RC1R_RGMII_0_750_NS 5 205 #define YT8521_RC1R_RGMII_0_900_NS 6 206 #define YT8521_RC1R_RGMII_1_050_NS 7 207 #define YT8521_RC1R_RGMII_1_200_NS 8 208 #define YT8521_RC1R_RGMII_1_350_NS 9 209 #define YT8521_RC1R_RGMII_1_500_NS 10 210 #define YT8521_RC1R_RGMII_1_650_NS 11 211 #define YT8521_RC1R_RGMII_1_800_NS 12 212 #define YT8521_RC1R_RGMII_1_950_NS 13 213 #define YT8521_RC1R_RGMII_2_100_NS 14 214 #define YT8521_RC1R_RGMII_2_250_NS 15 215 216 /* LED CONFIG */ 217 #define YT8521_MAX_LEDS 3 218 #define YT8521_LED0_CFG_REG 0xA00C 219 #define YT8521_LED1_CFG_REG 0xA00D 220 #define YT8521_LED2_CFG_REG 0xA00E 221 #define YT8521_LED_ACT_BLK_IND BIT(13) 222 #define YT8521_LED_FDX_ON_EN BIT(12) 223 #define YT8521_LED_HDX_ON_EN BIT(11) 224 #define YT8521_LED_TXACT_BLK_EN BIT(10) 225 #define YT8521_LED_RXACT_BLK_EN BIT(9) 226 #define YT8521_LED_1000_ON_EN BIT(6) 227 #define YT8521_LED_100_ON_EN BIT(5) 228 #define YT8521_LED_10_ON_EN BIT(4) 229 230 #define YTPHY_MISC_CONFIG_REG 0xA006 231 #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) 232 #define YTPHY_MCR_FIBER_1000BX (0x1 << 0) 233 #define YTPHY_MCR_FIBER_100FX (0x0 << 0) 234 235 /* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */ 236 #define YTPHY_WOL_MACADDR2_REG 0xA007 237 #define YTPHY_WOL_MACADDR1_REG 0xA008 238 #define YTPHY_WOL_MACADDR0_REG 0xA009 239 240 #define YTPHY_WOL_CONFIG_REG 0xA00A 241 #define YTPHY_WCR_INTR_SEL BIT(6) 242 #define YTPHY_WCR_ENABLE BIT(3) 243 244 /* 2b00 84ms 245 * 2b01 168ms *default* 246 * 2b10 336ms 247 * 2b11 672ms 248 */ 249 #define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1)) 250 #define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1)) 251 252 /* 1b0 Interrupt and WOL events is level triggered and active LOW *default* 253 * 1b1 Interrupt and WOL events is pulse triggered and active LOW 254 */ 255 #define YTPHY_WCR_TYPE_PULSE BIT(0) 256 257 #define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 258 #define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13) 259 #define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */ 260 #define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ 261 #define YT8531_RGMII_RX_DS_DEFAULT 0x3 262 263 #define YTPHY_SYNCE_CFG_REG 0xA012 264 #define YT8521_SCR_SYNCE_ENABLE BIT(5) 265 /* 1b0 output 25m clock 266 * 1b1 output 125m clock *default* 267 */ 268 #define YT8521_SCR_CLK_FRE_SEL_125M BIT(3) 269 #define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1) 270 #define YT8521_SCR_CLK_SRC_PLL_125M 0 271 #define YT8521_SCR_CLK_SRC_UTP_RX 1 272 #define YT8521_SCR_CLK_SRC_SDS_RX 2 273 #define YT8521_SCR_CLK_SRC_REF_25M 3 274 #define YT8531_SCR_SYNCE_ENABLE BIT(6) 275 /* 1b0 output 25m clock *default* 276 * 1b1 output 125m clock 277 */ 278 #define YT8531_SCR_CLK_FRE_SEL_125M BIT(4) 279 #define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1) 280 #define YT8531_SCR_CLK_SRC_PLL_125M 0 281 #define YT8531_SCR_CLK_SRC_UTP_RX 1 282 #define YT8531_SCR_CLK_SRC_SDS_RX 2 283 #define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 284 #define YT8531_SCR_CLK_SRC_REF_25M 4 285 #define YT8531_SCR_CLK_SRC_SSC_25M 5 286 287 #define YT8821_SDS_EXT_CSR_CTRL_REG 0x23 288 #define YT8821_SDS_EXT_CSR_VCO_LDO_EN BIT(15) 289 #define YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN BIT(8) 290 291 #define YT8821_UTP_EXT_PI_CTRL_REG 0x56 292 #define YT8821_UTP_EXT_PI_RST_N_FIFO BIT(5) 293 #define YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE BIT(4) 294 #define YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE BIT(3) 295 #define YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE BIT(2) 296 #define YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE BIT(1) 297 #define YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE BIT(0) 298 299 #define YT8821_UTP_EXT_VCT_CFG6_CTRL_REG 0x97 300 #define YT8821_UTP_EXT_FECHO_AMP_TH_HUGE GENMASK(15, 8) 301 302 #define YT8821_UTP_EXT_ECHO_CTRL_REG 0x336 303 #define YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000 GENMASK(14, 8) 304 305 #define YT8821_UTP_EXT_GAIN_CTRL_REG 0x340 306 #define YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000 GENMASK(6, 0) 307 308 #define YT8821_UTP_EXT_RPDN_CTRL_REG 0x34E 309 #define YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 BIT(15) 310 #define YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 BIT(7) 311 #define YT8821_UTP_EXT_RPDN_IPR_SHT_2500 GENMASK(6, 0) 312 313 #define YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG 0x36A 314 #define YT8821_UTP_EXT_TH_20DB_2500 GENMASK(15, 0) 315 316 #define YT8821_UTP_EXT_TRACE_CTRL_REG 0x372 317 #define YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 GENMASK(14, 8) 318 #define YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500 GENMASK(6, 0) 319 320 #define YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG 0x374 321 #define YT8821_UTP_EXT_ALPHA_SHT_2500 GENMASK(14, 8) 322 #define YT8821_UTP_EXT_IPR_LNG_2500 GENMASK(6, 0) 323 324 #define YT8821_UTP_EXT_PLL_CTRL_REG 0x450 325 #define YT8821_UTP_EXT_PLL_SPARE_CFG GENMASK(7, 0) 326 327 #define YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG 0x466 328 #define YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG GENMASK(14, 8) 329 #define YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG GENMASK(6, 0) 330 331 #define YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG 0x467 332 #define YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG GENMASK(14, 8) 333 #define YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG GENMASK(6, 0) 334 335 #define YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG 0x468 336 #define YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG GENMASK(14, 8) 337 #define YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG GENMASK(6, 0) 338 339 #define YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG 0x469 340 #define YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG GENMASK(14, 8) 341 #define YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG GENMASK(6, 0) 342 343 #define YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG 0x4B3 344 #define YT8821_UTP_EXT_MU_COARSE_FR_F_FFE GENMASK(14, 12) 345 #define YT8821_UTP_EXT_MU_COARSE_FR_F_FBE GENMASK(10, 8) 346 347 #define YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG 0x4B5 348 #define YT8821_UTP_EXT_MU_FINE_FR_F_FFE GENMASK(14, 12) 349 #define YT8821_UTP_EXT_MU_FINE_FR_F_FBE GENMASK(10, 8) 350 351 #define YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG 0x4D2 352 #define YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER GENMASK(7, 4) 353 #define YT8821_UTP_EXT_VGA_LPF1_CAP_2500 GENMASK(3, 0) 354 355 #define YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG 0x4D3 356 #define YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER GENMASK(7, 4) 357 #define YT8821_UTP_EXT_VGA_LPF2_CAP_2500 GENMASK(3, 0) 358 359 #define YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG 0x660 360 #define YT8821_UTP_EXT_NFR_TX_ABILITY BIT(3) 361 /* Extended Register end */ 362 363 #define YTPHY_DTS_OUTPUT_CLK_DIS 0 364 #define YTPHY_DTS_OUTPUT_CLK_25M 25000000 365 #define YTPHY_DTS_OUTPUT_CLK_125M 125000000 366 367 #define YT8821_CHIP_MODE_AUTO_BX2500_SGMII 0 368 #define YT8821_CHIP_MODE_FORCE_BX2500 1 369 370 struct yt8521_priv { 371 /* combo_advertising is used for case of YT8521 in combo mode, 372 * this means that yt8521 may work in utp or fiber mode which depends 373 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED). 374 */ 375 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising); 376 377 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/ 378 u8 polling_mode; 379 u8 strap_mode; /* 8 working modes */ 380 /* current reg page of yt8521 phy: 381 * YT8521_RSSR_UTP_SPACE 382 * YT8521_RSSR_FIBER_SPACE 383 * YT8521_RSSR_TO_BE_ARBITRATED 384 */ 385 u8 reg_page; 386 }; 387 388 /** 389 * ytphy_read_ext() - read a PHY's extended register 390 * @phydev: a pointer to a &struct phy_device 391 * @regnum: register number to read 392 * 393 * NOTE:The caller must have taken the MDIO bus lock. 394 * 395 * returns the value of regnum reg or negative error code 396 */ 397 static int ytphy_read_ext(struct phy_device *phydev, u16 regnum) 398 { 399 int ret; 400 401 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 402 if (ret < 0) 403 return ret; 404 405 return __phy_read(phydev, YTPHY_PAGE_DATA); 406 } 407 408 /** 409 * ytphy_read_ext_with_lock() - read a PHY's extended register 410 * @phydev: a pointer to a &struct phy_device 411 * @regnum: register number to read 412 * 413 * returns the value of regnum reg or negative error code 414 */ 415 static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum) 416 { 417 int ret; 418 419 phy_lock_mdio_bus(phydev); 420 ret = ytphy_read_ext(phydev, regnum); 421 phy_unlock_mdio_bus(phydev); 422 423 return ret; 424 } 425 426 /** 427 * ytphy_write_ext() - write a PHY's extended register 428 * @phydev: a pointer to a &struct phy_device 429 * @regnum: register number to write 430 * @val: value to write to @regnum 431 * 432 * NOTE:The caller must have taken the MDIO bus lock. 433 * 434 * returns 0 or negative error code 435 */ 436 static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val) 437 { 438 int ret; 439 440 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 441 if (ret < 0) 442 return ret; 443 444 return __phy_write(phydev, YTPHY_PAGE_DATA, val); 445 } 446 447 /** 448 * ytphy_write_ext_with_lock() - write a PHY's extended register 449 * @phydev: a pointer to a &struct phy_device 450 * @regnum: register number to write 451 * @val: value to write to @regnum 452 * 453 * returns 0 or negative error code 454 */ 455 static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum, 456 u16 val) 457 { 458 int ret; 459 460 phy_lock_mdio_bus(phydev); 461 ret = ytphy_write_ext(phydev, regnum, val); 462 phy_unlock_mdio_bus(phydev); 463 464 return ret; 465 } 466 467 /** 468 * ytphy_modify_ext() - bits modify a PHY's extended register 469 * @phydev: a pointer to a &struct phy_device 470 * @regnum: register number to write 471 * @mask: bit mask of bits to clear 472 * @set: bit mask of bits to set 473 * 474 * NOTE: Convenience function which allows a PHY's extended register to be 475 * modified as new register value = (old register value & ~mask) | set. 476 * The caller must have taken the MDIO bus lock. 477 * 478 * returns 0 or negative error code 479 */ 480 static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask, 481 u16 set) 482 { 483 int ret; 484 485 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 486 if (ret < 0) 487 return ret; 488 489 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set); 490 } 491 492 /** 493 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register 494 * @phydev: a pointer to a &struct phy_device 495 * @regnum: register number to write 496 * @mask: bit mask of bits to clear 497 * @set: bit mask of bits to set 498 * 499 * NOTE: Convenience function which allows a PHY's extended register to be 500 * modified as new register value = (old register value & ~mask) | set. 501 * 502 * returns 0 or negative error code 503 */ 504 static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum, 505 u16 mask, u16 set) 506 { 507 int ret; 508 509 phy_lock_mdio_bus(phydev); 510 ret = ytphy_modify_ext(phydev, regnum, mask, set); 511 phy_unlock_mdio_bus(phydev); 512 513 return ret; 514 } 515 516 /** 517 * ytphy_get_wol() - report whether wake-on-lan is enabled 518 * @phydev: a pointer to a &struct phy_device 519 * @wol: a pointer to a &struct ethtool_wolinfo 520 * 521 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg. 522 */ 523 static void ytphy_get_wol(struct phy_device *phydev, 524 struct ethtool_wolinfo *wol) 525 { 526 int wol_config; 527 528 wol->supported = WAKE_MAGIC; 529 wol->wolopts = 0; 530 531 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 532 if (wol_config < 0) 533 return; 534 535 if (wol_config & YTPHY_WCR_ENABLE) 536 wol->wolopts |= WAKE_MAGIC; 537 } 538 539 /** 540 * ytphy_set_wol() - turn wake-on-lan on or off 541 * @phydev: a pointer to a &struct phy_device 542 * @wol: a pointer to a &struct ethtool_wolinfo 543 * 544 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG 545 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The 546 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register. 547 * 548 * returns 0 or negative errno code 549 */ 550 static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 551 { 552 struct net_device *p_attached_dev; 553 const u16 mac_addr_reg[] = { 554 YTPHY_WOL_MACADDR2_REG, 555 YTPHY_WOL_MACADDR1_REG, 556 YTPHY_WOL_MACADDR0_REG, 557 }; 558 const u8 *mac_addr; 559 int old_page; 560 int ret = 0; 561 u16 mask; 562 u16 val; 563 u8 i; 564 565 if (wol->wolopts & WAKE_MAGIC) { 566 p_attached_dev = phydev->attached_dev; 567 if (!p_attached_dev) 568 return -ENODEV; 569 570 mac_addr = (const u8 *)p_attached_dev->dev_addr; 571 if (!is_valid_ether_addr(mac_addr)) 572 return -EINVAL; 573 574 /* lock mdio bus then switch to utp reg space */ 575 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 576 if (old_page < 0) 577 goto err_restore_page; 578 579 /* Store the device address for the magic packet */ 580 for (i = 0; i < 3; i++) { 581 ret = ytphy_write_ext(phydev, mac_addr_reg[i], 582 ((mac_addr[i * 2] << 8)) | 583 (mac_addr[i * 2 + 1])); 584 if (ret < 0) 585 goto err_restore_page; 586 } 587 588 /* Enable WOL feature */ 589 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 590 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 591 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 592 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val); 593 if (ret < 0) 594 goto err_restore_page; 595 596 /* Enable WOL interrupt */ 597 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 598 YTPHY_IER_WOL); 599 if (ret < 0) 600 goto err_restore_page; 601 602 } else { 603 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 604 if (old_page < 0) 605 goto err_restore_page; 606 607 /* Disable WOL feature */ 608 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 609 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0); 610 611 /* Disable WOL interrupt */ 612 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 613 YTPHY_IER_WOL, 0); 614 if (ret < 0) 615 goto err_restore_page; 616 } 617 618 err_restore_page: 619 return phy_restore_page(phydev, old_page, ret); 620 } 621 622 static int yt8531_set_wol(struct phy_device *phydev, 623 struct ethtool_wolinfo *wol) 624 { 625 const u16 mac_addr_reg[] = { 626 YTPHY_WOL_MACADDR2_REG, 627 YTPHY_WOL_MACADDR1_REG, 628 YTPHY_WOL_MACADDR0_REG, 629 }; 630 const u8 *mac_addr; 631 u16 mask, val; 632 int ret; 633 u8 i; 634 635 if (wol->wolopts & WAKE_MAGIC) { 636 mac_addr = phydev->attached_dev->dev_addr; 637 638 /* Store the device address for the magic packet */ 639 for (i = 0; i < 3; i++) { 640 ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i], 641 ((mac_addr[i * 2] << 8)) | 642 (mac_addr[i * 2 + 1])); 643 if (ret < 0) 644 return ret; 645 } 646 647 /* Enable WOL feature */ 648 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 649 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 650 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 651 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, 652 mask, val); 653 if (ret < 0) 654 return ret; 655 656 /* Enable WOL interrupt */ 657 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 658 YTPHY_IER_WOL); 659 if (ret < 0) 660 return ret; 661 } else { 662 /* Disable WOL feature */ 663 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 664 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, 665 mask, 0); 666 667 /* Disable WOL interrupt */ 668 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 669 YTPHY_IER_WOL, 0); 670 if (ret < 0) 671 return ret; 672 } 673 674 return 0; 675 } 676 677 static int yt8511_read_page(struct phy_device *phydev) 678 { 679 return __phy_read(phydev, YT8511_PAGE_SELECT); 680 }; 681 682 static int yt8511_write_page(struct phy_device *phydev, int page) 683 { 684 return __phy_write(phydev, YT8511_PAGE_SELECT, page); 685 }; 686 687 static int yt8511_config_init(struct phy_device *phydev) 688 { 689 int oldpage, ret = 0; 690 unsigned int ge, fe; 691 692 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE); 693 if (oldpage < 0) 694 goto err_restore_page; 695 696 /* set rgmii delay mode */ 697 switch (phydev->interface) { 698 case PHY_INTERFACE_MODE_RGMII: 699 ge = YT8511_DELAY_GE_TX_DIS; 700 fe = YT8511_DELAY_FE_TX_DIS; 701 break; 702 case PHY_INTERFACE_MODE_RGMII_RXID: 703 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS; 704 fe = YT8511_DELAY_FE_TX_DIS; 705 break; 706 case PHY_INTERFACE_MODE_RGMII_TXID: 707 ge = YT8511_DELAY_GE_TX_EN; 708 fe = YT8511_DELAY_FE_TX_EN; 709 break; 710 case PHY_INTERFACE_MODE_RGMII_ID: 711 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN; 712 fe = YT8511_DELAY_FE_TX_EN; 713 break; 714 default: /* do not support other modes */ 715 ret = -EOPNOTSUPP; 716 goto err_restore_page; 717 } 718 719 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge); 720 if (ret < 0) 721 goto err_restore_page; 722 723 /* set clock mode to 125mhz */ 724 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M); 725 if (ret < 0) 726 goto err_restore_page; 727 728 /* fast ethernet delay is in a separate page */ 729 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE); 730 if (ret < 0) 731 goto err_restore_page; 732 733 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe); 734 if (ret < 0) 735 goto err_restore_page; 736 737 /* leave pll enabled in sleep */ 738 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL); 739 if (ret < 0) 740 goto err_restore_page; 741 742 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP); 743 if (ret < 0) 744 goto err_restore_page; 745 746 err_restore_page: 747 return phy_restore_page(phydev, oldpage, ret); 748 } 749 750 /** 751 * yt8521_read_page() - read reg page 752 * @phydev: a pointer to a &struct phy_device 753 * 754 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/ 755 * YT8521_RSSR_UTP_SPACE) or negative errno code 756 */ 757 static int yt8521_read_page(struct phy_device *phydev) 758 { 759 int old_page; 760 761 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG); 762 if (old_page < 0) 763 return old_page; 764 765 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 766 return YT8521_RSSR_FIBER_SPACE; 767 768 return YT8521_RSSR_UTP_SPACE; 769 }; 770 771 /** 772 * yt8521_write_page() - write reg page 773 * @phydev: a pointer to a &struct phy_device 774 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write. 775 * 776 * returns 0 or negative errno code 777 */ 778 static int yt8521_write_page(struct phy_device *phydev, int page) 779 { 780 int mask = YT8521_RSSR_SPACE_MASK; 781 int set; 782 783 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 784 set = YT8521_RSSR_FIBER_SPACE; 785 else 786 set = YT8521_RSSR_UTP_SPACE; 787 788 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set); 789 }; 790 791 /** 792 * struct ytphy_cfg_reg_map - map a config value to a register value 793 * @cfg: value in device configuration 794 * @reg: value in the register 795 */ 796 struct ytphy_cfg_reg_map { 797 u32 cfg; 798 u32 reg; 799 }; 800 801 static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = { 802 /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */ 803 { 0, YT8521_RC1R_RGMII_0_000_NS }, 804 { 150, YT8521_RC1R_RGMII_0_150_NS }, 805 { 300, YT8521_RC1R_RGMII_0_300_NS }, 806 { 450, YT8521_RC1R_RGMII_0_450_NS }, 807 { 600, YT8521_RC1R_RGMII_0_600_NS }, 808 { 750, YT8521_RC1R_RGMII_0_750_NS }, 809 { 900, YT8521_RC1R_RGMII_0_900_NS }, 810 { 1050, YT8521_RC1R_RGMII_1_050_NS }, 811 { 1200, YT8521_RC1R_RGMII_1_200_NS }, 812 { 1350, YT8521_RC1R_RGMII_1_350_NS }, 813 { 1500, YT8521_RC1R_RGMII_1_500_NS }, 814 { 1650, YT8521_RC1R_RGMII_1_650_NS }, 815 { 1800, YT8521_RC1R_RGMII_1_800_NS }, 816 { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */ 817 { 2100, YT8521_RC1R_RGMII_2_100_NS }, 818 { 2250, YT8521_RC1R_RGMII_2_250_NS }, 819 820 /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */ 821 { 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS }, 822 { 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS }, 823 { 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS }, 824 { 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS }, 825 { 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS }, 826 { 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS }, 827 { 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS }, 828 { 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS }, 829 { 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS }, 830 { 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS }, 831 { 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS }, 832 { 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS }, 833 { 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS }, 834 { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS }, 835 { 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS }, 836 { 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS } 837 }; 838 839 static u32 ytphy_get_delay_reg_value(struct phy_device *phydev, 840 const char *prop_name, 841 const struct ytphy_cfg_reg_map *tbl, 842 int tb_size, 843 u16 *rxc_dly_en, 844 u32 dflt) 845 { 846 struct device_node *node = phydev->mdio.dev.of_node; 847 int tb_size_half = tb_size / 2; 848 u32 val; 849 int i; 850 851 if (of_property_read_u32(node, prop_name, &val)) 852 goto err_dts_val; 853 854 /* when rxc_dly_en is NULL, it is get the delay for tx, only half of 855 * tb_size is valid. 856 */ 857 if (!rxc_dly_en) 858 tb_size = tb_size_half; 859 860 for (i = 0; i < tb_size; i++) { 861 if (tbl[i].cfg == val) { 862 if (rxc_dly_en && i < tb_size_half) 863 *rxc_dly_en = 0; 864 return tbl[i].reg; 865 } 866 } 867 868 phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n", 869 val, prop_name, dflt); 870 871 err_dts_val: 872 /* when rxc_dly_en is not NULL, it is get the delay for rx. 873 * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps, 874 * so YT8521_CCR_RXC_DLY_EN should not be set. 875 */ 876 if (rxc_dly_en) 877 *rxc_dly_en = 0; 878 879 return dflt; 880 } 881 882 static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) 883 { 884 int tb_size = ARRAY_SIZE(ytphy_rgmii_delays); 885 u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN; 886 u32 rx_reg, tx_reg; 887 u16 mask, val = 0; 888 int ret; 889 890 rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps", 891 ytphy_rgmii_delays, tb_size, 892 &rxc_dly_en, 893 YT8521_RC1R_RGMII_1_950_NS); 894 tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps", 895 ytphy_rgmii_delays, tb_size, NULL, 896 YT8521_RC1R_RGMII_1_950_NS); 897 898 switch (phydev->interface) { 899 case PHY_INTERFACE_MODE_RGMII: 900 rxc_dly_en = 0; 901 break; 902 case PHY_INTERFACE_MODE_RGMII_RXID: 903 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg); 904 break; 905 case PHY_INTERFACE_MODE_RGMII_TXID: 906 rxc_dly_en = 0; 907 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); 908 break; 909 case PHY_INTERFACE_MODE_RGMII_ID: 910 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | 911 FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); 912 break; 913 case PHY_INTERFACE_MODE_GMII: 914 if (phydev->drv->phy_id != PHY_ID_YT8531S) 915 return -EOPNOTSUPP; 916 return 0; 917 default: /* do not support other modes */ 918 return -EOPNOTSUPP; 919 } 920 921 ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 922 YT8521_CCR_RXC_DLY_EN, rxc_dly_en); 923 if (ret < 0) 924 return ret; 925 926 /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */ 927 mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK; 928 return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); 929 } 930 931 static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev) 932 { 933 int ret; 934 935 phy_lock_mdio_bus(phydev); 936 ret = ytphy_rgmii_clk_delay_config(phydev); 937 phy_unlock_mdio_bus(phydev); 938 939 return ret; 940 } 941 942 /** 943 * struct ytphy_ldo_vol_map - map a current value to a register value 944 * @vol: ldo voltage 945 * @ds: value in the register 946 * @cur: value in device configuration 947 */ 948 struct ytphy_ldo_vol_map { 949 u32 vol; 950 u32 ds; 951 u32 cur; 952 }; 953 954 static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = { 955 {.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200}, 956 {.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100}, 957 {.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700}, 958 {.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910}, 959 {.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110}, 960 {.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600}, 961 {.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970}, 962 {.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350}, 963 {.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070}, 964 {.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080}, 965 {.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370}, 966 {.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680}, 967 {.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020}, 968 {.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450}, 969 {.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740}, 970 {.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140}, 971 }; 972 973 static u32 yt8531_get_ldo_vol(struct phy_device *phydev) 974 { 975 u32 val; 976 977 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 978 val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val); 979 980 return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8; 981 } 982 983 static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur) 984 { 985 u32 vol; 986 int i; 987 988 vol = yt8531_get_ldo_vol(phydev); 989 for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) { 990 if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur) 991 return yt8531_ldo_vol[i].ds; 992 } 993 994 return -EINVAL; 995 } 996 997 static int yt8531_set_ds(struct phy_device *phydev) 998 { 999 struct device_node *node = phydev->mdio.dev.of_node; 1000 u32 ds_field_low, ds_field_hi, val; 1001 int ret, ds; 1002 1003 /* set rgmii rx clk driver strength */ 1004 if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) { 1005 ds = yt8531_get_ds_map(phydev, val); 1006 if (ds < 0) 1007 return dev_err_probe(&phydev->mdio.dev, ds, 1008 "No matching current value was found.\n"); 1009 } else { 1010 ds = YT8531_RGMII_RX_DS_DEFAULT; 1011 } 1012 1013 ret = ytphy_modify_ext_with_lock(phydev, 1014 YTPHY_PAD_DRIVE_STRENGTH_REG, 1015 YT8531_RGMII_RXC_DS_MASK, 1016 FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds)); 1017 if (ret < 0) 1018 return ret; 1019 1020 /* set rgmii rx data driver strength */ 1021 if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) { 1022 ds = yt8531_get_ds_map(phydev, val); 1023 if (ds < 0) 1024 return dev_err_probe(&phydev->mdio.dev, ds, 1025 "No matching current value was found.\n"); 1026 } else { 1027 ds = YT8531_RGMII_RX_DS_DEFAULT; 1028 } 1029 1030 ds_field_hi = FIELD_GET(BIT(2), ds); 1031 ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi); 1032 1033 ds_field_low = FIELD_GET(GENMASK(1, 0), ds); 1034 ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low); 1035 1036 ret = ytphy_modify_ext_with_lock(phydev, 1037 YTPHY_PAD_DRIVE_STRENGTH_REG, 1038 YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK, 1039 ds_field_low | ds_field_hi); 1040 if (ret < 0) 1041 return ret; 1042 1043 return 0; 1044 } 1045 1046 /** 1047 * yt8521_probe() - read chip config then set suitable polling_mode 1048 * @phydev: a pointer to a &struct phy_device 1049 * 1050 * returns 0 or negative errno code 1051 */ 1052 static int yt8521_probe(struct phy_device *phydev) 1053 { 1054 struct device_node *node = phydev->mdio.dev.of_node; 1055 struct device *dev = &phydev->mdio.dev; 1056 struct yt8521_priv *priv; 1057 int chip_config; 1058 u16 mask, val; 1059 u32 freq; 1060 int ret; 1061 1062 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1063 if (!priv) 1064 return -ENOMEM; 1065 1066 phydev->priv = priv; 1067 1068 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 1069 if (chip_config < 0) 1070 return chip_config; 1071 1072 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK; 1073 switch (priv->strap_mode) { 1074 case YT8521_CCR_MODE_FIBER_TO_RGMII: 1075 case YT8521_CCR_MODE_SGPHY_TO_RGMAC: 1076 case YT8521_CCR_MODE_SGMAC_TO_RGPHY: 1077 priv->polling_mode = YT8521_MODE_FIBER; 1078 priv->reg_page = YT8521_RSSR_FIBER_SPACE; 1079 phydev->port = PORT_FIBRE; 1080 break; 1081 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII: 1082 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO: 1083 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE: 1084 priv->polling_mode = YT8521_MODE_POLL; 1085 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 1086 phydev->port = PORT_NONE; 1087 break; 1088 case YT8521_CCR_MODE_UTP_TO_SGMII: 1089 case YT8521_CCR_MODE_UTP_TO_RGMII: 1090 priv->polling_mode = YT8521_MODE_UTP; 1091 priv->reg_page = YT8521_RSSR_UTP_SPACE; 1092 phydev->port = PORT_TP; 1093 break; 1094 } 1095 /* set default reg space */ 1096 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1097 ret = ytphy_write_ext_with_lock(phydev, 1098 YT8521_REG_SPACE_SELECT_REG, 1099 priv->reg_page); 1100 if (ret < 0) 1101 return ret; 1102 } 1103 1104 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) 1105 freq = YTPHY_DTS_OUTPUT_CLK_DIS; 1106 1107 if (phydev->drv->phy_id == PHY_ID_YT8521) { 1108 switch (freq) { 1109 case YTPHY_DTS_OUTPUT_CLK_DIS: 1110 mask = YT8521_SCR_SYNCE_ENABLE; 1111 val = 0; 1112 break; 1113 case YTPHY_DTS_OUTPUT_CLK_25M: 1114 mask = YT8521_SCR_SYNCE_ENABLE | 1115 YT8521_SCR_CLK_SRC_MASK | 1116 YT8521_SCR_CLK_FRE_SEL_125M; 1117 val = YT8521_SCR_SYNCE_ENABLE | 1118 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, 1119 YT8521_SCR_CLK_SRC_REF_25M); 1120 break; 1121 case YTPHY_DTS_OUTPUT_CLK_125M: 1122 mask = YT8521_SCR_SYNCE_ENABLE | 1123 YT8521_SCR_CLK_SRC_MASK | 1124 YT8521_SCR_CLK_FRE_SEL_125M; 1125 val = YT8521_SCR_SYNCE_ENABLE | 1126 YT8521_SCR_CLK_FRE_SEL_125M | 1127 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, 1128 YT8521_SCR_CLK_SRC_PLL_125M); 1129 break; 1130 default: 1131 phydev_warn(phydev, "Freq err:%u\n", freq); 1132 return -EINVAL; 1133 } 1134 } else if (phydev->drv->phy_id == PHY_ID_YT8531S) { 1135 switch (freq) { 1136 case YTPHY_DTS_OUTPUT_CLK_DIS: 1137 mask = YT8531_SCR_SYNCE_ENABLE; 1138 val = 0; 1139 break; 1140 case YTPHY_DTS_OUTPUT_CLK_25M: 1141 mask = YT8531_SCR_SYNCE_ENABLE | 1142 YT8531_SCR_CLK_SRC_MASK | 1143 YT8531_SCR_CLK_FRE_SEL_125M; 1144 val = YT8531_SCR_SYNCE_ENABLE | 1145 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1146 YT8531_SCR_CLK_SRC_REF_25M); 1147 break; 1148 case YTPHY_DTS_OUTPUT_CLK_125M: 1149 mask = YT8531_SCR_SYNCE_ENABLE | 1150 YT8531_SCR_CLK_SRC_MASK | 1151 YT8531_SCR_CLK_FRE_SEL_125M; 1152 val = YT8531_SCR_SYNCE_ENABLE | 1153 YT8531_SCR_CLK_FRE_SEL_125M | 1154 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1155 YT8531_SCR_CLK_SRC_PLL_125M); 1156 break; 1157 default: 1158 phydev_warn(phydev, "Freq err:%u\n", freq); 1159 return -EINVAL; 1160 } 1161 } else { 1162 phydev_warn(phydev, "PHY id err\n"); 1163 return -EINVAL; 1164 } 1165 1166 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, 1167 val); 1168 } 1169 1170 static int yt8531_probe(struct phy_device *phydev) 1171 { 1172 struct device_node *node = phydev->mdio.dev.of_node; 1173 u16 mask, val; 1174 u32 freq; 1175 1176 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) 1177 freq = YTPHY_DTS_OUTPUT_CLK_DIS; 1178 1179 switch (freq) { 1180 case YTPHY_DTS_OUTPUT_CLK_DIS: 1181 mask = YT8531_SCR_SYNCE_ENABLE; 1182 val = 0; 1183 break; 1184 case YTPHY_DTS_OUTPUT_CLK_25M: 1185 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | 1186 YT8531_SCR_CLK_FRE_SEL_125M; 1187 val = YT8531_SCR_SYNCE_ENABLE | 1188 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1189 YT8531_SCR_CLK_SRC_REF_25M); 1190 break; 1191 case YTPHY_DTS_OUTPUT_CLK_125M: 1192 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | 1193 YT8531_SCR_CLK_FRE_SEL_125M; 1194 val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | 1195 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1196 YT8531_SCR_CLK_SRC_PLL_125M); 1197 break; 1198 default: 1199 phydev_warn(phydev, "Freq err:%u\n", freq); 1200 return -EINVAL; 1201 } 1202 1203 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, 1204 val); 1205 } 1206 1207 /** 1208 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp 1209 * @phydev: a pointer to a &struct phy_device 1210 * 1211 * NOTE:The caller must have taken the MDIO bus lock. 1212 * 1213 * returns 0 or negative errno code 1214 */ 1215 static int ytphy_utp_read_lpa(struct phy_device *phydev) 1216 { 1217 int lpa, lpagb; 1218 1219 if (phydev->autoneg == AUTONEG_ENABLE) { 1220 if (!phydev->autoneg_complete) { 1221 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 1222 0); 1223 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1224 return 0; 1225 } 1226 1227 if (phydev->is_gigabit_capable) { 1228 lpagb = __phy_read(phydev, MII_STAT1000); 1229 if (lpagb < 0) 1230 return lpagb; 1231 1232 if (lpagb & LPA_1000MSFAIL) { 1233 int adv = __phy_read(phydev, MII_CTRL1000); 1234 1235 if (adv < 0) 1236 return adv; 1237 1238 if (adv & CTL1000_ENABLE_MASTER) 1239 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); 1240 else 1241 phydev_err(phydev, "Master/Slave resolution failed\n"); 1242 return -ENOLINK; 1243 } 1244 1245 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 1246 lpagb); 1247 } 1248 1249 lpa = __phy_read(phydev, MII_LPA); 1250 if (lpa < 0) 1251 return lpa; 1252 1253 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa); 1254 } else { 1255 linkmode_zero(phydev->lp_advertising); 1256 } 1257 1258 return 0; 1259 } 1260 1261 /** 1262 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber 1263 * mode, adjust speed and duplex. 1264 * @phydev: a pointer to a &struct phy_device 1265 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG 1266 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode) 1267 * 1268 * NOTE:The caller must have taken the MDIO bus lock. 1269 * 1270 * returns 0 1271 */ 1272 static int yt8521_adjust_status(struct phy_device *phydev, int status, 1273 bool is_utp) 1274 { 1275 int speed_mode, duplex; 1276 int speed; 1277 int err; 1278 int lpa; 1279 1280 if (is_utp) 1281 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET; 1282 else 1283 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */ 1284 1285 speed_mode = status & YTPHY_SSR_SPEED_MASK; 1286 1287 switch (speed_mode) { 1288 case YTPHY_SSR_SPEED_10M: 1289 if (is_utp) 1290 speed = SPEED_10; 1291 else 1292 /* for fiber, it will never run here, default to 1293 * SPEED_UNKNOWN 1294 */ 1295 speed = SPEED_UNKNOWN; 1296 break; 1297 case YTPHY_SSR_SPEED_100M: 1298 speed = SPEED_100; 1299 break; 1300 case YTPHY_SSR_SPEED_1000M: 1301 speed = SPEED_1000; 1302 break; 1303 default: 1304 speed = SPEED_UNKNOWN; 1305 break; 1306 } 1307 1308 phydev->speed = speed; 1309 phydev->duplex = duplex; 1310 1311 if (is_utp) { 1312 err = ytphy_utp_read_lpa(phydev); 1313 if (err < 0) 1314 return err; 1315 1316 phy_resolve_aneg_pause(phydev); 1317 } else { 1318 lpa = __phy_read(phydev, MII_LPA); 1319 if (lpa < 0) 1320 return lpa; 1321 1322 /* only support 1000baseX Full */ 1323 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1324 phydev->lp_advertising, lpa & LPA_1000XFULL); 1325 1326 if (!(lpa & YTPHY_FLPA_PAUSE)) { 1327 phydev->pause = 0; 1328 phydev->asym_pause = 0; 1329 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) { 1330 phydev->pause = 1; 1331 phydev->asym_pause = 1; 1332 } else { 1333 phydev->pause = 1; 1334 phydev->asym_pause = 0; 1335 } 1336 } 1337 1338 return 0; 1339 } 1340 1341 /** 1342 * yt8521_read_status_paged() - determines the speed and duplex of one page 1343 * @phydev: a pointer to a &struct phy_device 1344 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 1345 * operate. 1346 * 1347 * returns 1 (utp or fiber link),0 (no link) or negative errno code 1348 */ 1349 static int yt8521_read_status_paged(struct phy_device *phydev, int page) 1350 { 1351 int fiber_latch_val; 1352 int fiber_curr_val; 1353 int old_page; 1354 int ret = 0; 1355 int status; 1356 int link; 1357 1358 linkmode_zero(phydev->lp_advertising); 1359 phydev->duplex = DUPLEX_UNKNOWN; 1360 phydev->speed = SPEED_UNKNOWN; 1361 phydev->asym_pause = 0; 1362 phydev->pause = 0; 1363 1364 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber 1365 * respectively. but for utp/fiber combo mode, reg space should be 1366 * arbitrated based on media priority. by default, utp takes 1367 * priority. reg space should be properly set before read 1368 * YTPHY_SPECIFIC_STATUS_REG. 1369 */ 1370 1371 page &= YT8521_RSSR_SPACE_MASK; 1372 old_page = phy_select_page(phydev, page); 1373 if (old_page < 0) 1374 goto err_restore_page; 1375 1376 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex 1377 * of the PHY is actually using. 1378 */ 1379 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 1380 if (ret < 0) 1381 goto err_restore_page; 1382 1383 status = ret; 1384 link = !!(status & YTPHY_SSR_LINK); 1385 1386 /* When PHY is in fiber mode, speed transferred from 1000Mbps to 1387 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so 1388 * we need check MII_BMSR to identify such case. 1389 */ 1390 if (page == YT8521_RSSR_FIBER_SPACE) { 1391 ret = __phy_read(phydev, MII_BMSR); 1392 if (ret < 0) 1393 goto err_restore_page; 1394 1395 fiber_latch_val = ret; 1396 ret = __phy_read(phydev, MII_BMSR); 1397 if (ret < 0) 1398 goto err_restore_page; 1399 1400 fiber_curr_val = ret; 1401 if (link && fiber_latch_val != fiber_curr_val) { 1402 link = 0; 1403 phydev_info(phydev, 1404 "%s, fiber link down detect, latch = %04x, curr = %04x\n", 1405 __func__, fiber_latch_val, fiber_curr_val); 1406 } 1407 } else { 1408 /* Read autonegotiation status */ 1409 ret = __phy_read(phydev, MII_BMSR); 1410 if (ret < 0) 1411 goto err_restore_page; 1412 1413 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0; 1414 } 1415 1416 if (link) { 1417 if (page == YT8521_RSSR_UTP_SPACE) 1418 yt8521_adjust_status(phydev, status, true); 1419 else 1420 yt8521_adjust_status(phydev, status, false); 1421 } 1422 return phy_restore_page(phydev, old_page, link); 1423 1424 err_restore_page: 1425 return phy_restore_page(phydev, old_page, ret); 1426 } 1427 1428 /** 1429 * yt8521_read_status() - determines the negotiated speed and duplex 1430 * @phydev: a pointer to a &struct phy_device 1431 * 1432 * returns 0 or negative errno code 1433 */ 1434 static int yt8521_read_status(struct phy_device *phydev) 1435 { 1436 struct yt8521_priv *priv = phydev->priv; 1437 int link_fiber = 0; 1438 int link_utp; 1439 int link; 1440 int ret; 1441 1442 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1443 link = yt8521_read_status_paged(phydev, priv->reg_page); 1444 if (link < 0) 1445 return link; 1446 } else { 1447 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is 1448 * needed. by default, utp is higher priority. 1449 */ 1450 1451 link_utp = yt8521_read_status_paged(phydev, 1452 YT8521_RSSR_UTP_SPACE); 1453 if (link_utp < 0) 1454 return link_utp; 1455 1456 if (!link_utp) { 1457 link_fiber = yt8521_read_status_paged(phydev, 1458 YT8521_RSSR_FIBER_SPACE); 1459 if (link_fiber < 0) 1460 return link_fiber; 1461 } 1462 1463 link = link_utp || link_fiber; 1464 } 1465 1466 if (link) { 1467 if (phydev->link == 0) { 1468 /* arbitrate reg space based on linkup media type. */ 1469 if (priv->polling_mode == YT8521_MODE_POLL && 1470 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 1471 if (link_fiber) 1472 priv->reg_page = 1473 YT8521_RSSR_FIBER_SPACE; 1474 else 1475 priv->reg_page = YT8521_RSSR_UTP_SPACE; 1476 1477 ret = ytphy_write_ext_with_lock(phydev, 1478 YT8521_REG_SPACE_SELECT_REG, 1479 priv->reg_page); 1480 if (ret < 0) 1481 return ret; 1482 1483 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP; 1484 1485 phydev_info(phydev, "%s, link up, media: %s\n", 1486 __func__, 1487 (phydev->port == PORT_TP) ? 1488 "UTP" : "Fiber"); 1489 } 1490 } 1491 phydev->link = 1; 1492 } else { 1493 if (phydev->link == 1) { 1494 phydev_info(phydev, "%s, link down, media: %s\n", 1495 __func__, (phydev->port == PORT_TP) ? 1496 "UTP" : "Fiber"); 1497 1498 /* When in YT8521_MODE_POLL mode, need prepare for next 1499 * arbitration. 1500 */ 1501 if (priv->polling_mode == YT8521_MODE_POLL) { 1502 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 1503 phydev->port = PORT_NONE; 1504 } 1505 } 1506 1507 phydev->link = 0; 1508 } 1509 1510 return 0; 1511 } 1512 1513 /** 1514 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page 1515 * @phydev: the phy_device struct 1516 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate 1517 * @mask: bit mask of bits to clear 1518 * @set: bit mask of bits to set 1519 * 1520 * NOTE: Convenience function which allows a PHY's BMCR register to be 1521 * modified as new register value = (old register value & ~mask) | set. 1522 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1523 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1524 * If it is reset, it will wait for completion. 1525 * 1526 * returns 0 or negative errno code 1527 */ 1528 static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page, 1529 u16 mask, u16 set) 1530 { 1531 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */ 1532 int old_page; 1533 int ret = 0; 1534 1535 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 1536 if (old_page < 0) 1537 goto err_restore_page; 1538 1539 ret = __phy_modify(phydev, MII_BMCR, mask, set); 1540 if (ret < 0) 1541 goto err_restore_page; 1542 1543 /* If it is reset, need to wait for the reset to complete */ 1544 if (set == BMCR_RESET) { 1545 while (max_cnt--) { 1546 usleep_range(1000, 1100); 1547 ret = __phy_read(phydev, MII_BMCR); 1548 if (ret < 0) 1549 goto err_restore_page; 1550 1551 if (!(ret & BMCR_RESET)) 1552 return phy_restore_page(phydev, old_page, 0); 1553 } 1554 } 1555 1556 err_restore_page: 1557 return phy_restore_page(phydev, old_page, ret); 1558 } 1559 1560 /** 1561 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register 1562 * @phydev: the phy_device struct 1563 * @mask: bit mask of bits to clear 1564 * @set: bit mask of bits to set 1565 * 1566 * NOTE: Convenience function which allows a PHY's BMCR register to be 1567 * modified as new register value = (old register value & ~mask) | set. 1568 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1569 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1570 * 1571 * returns 0 or negative errno code 1572 */ 1573 static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask, 1574 u16 set) 1575 { 1576 struct yt8521_priv *priv = phydev->priv; 1577 int ret; 1578 1579 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1580 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask, 1581 set); 1582 if (ret < 0) 1583 return ret; 1584 } else { 1585 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, 1586 mask, set); 1587 if (ret < 0) 1588 return ret; 1589 1590 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, 1591 mask, set); 1592 if (ret < 0) 1593 return ret; 1594 } 1595 return 0; 1596 } 1597 1598 /** 1599 * yt8521_soft_reset() - called to issue a PHY software reset 1600 * @phydev: a pointer to a &struct phy_device 1601 * 1602 * returns 0 or negative errno code 1603 */ 1604 static int yt8521_soft_reset(struct phy_device *phydev) 1605 { 1606 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET); 1607 } 1608 1609 /** 1610 * yt8521_suspend() - suspend the hardware 1611 * @phydev: a pointer to a &struct phy_device 1612 * 1613 * returns 0 or negative errno code 1614 */ 1615 static int yt8521_suspend(struct phy_device *phydev) 1616 { 1617 int wol_config; 1618 1619 /* YTPHY_WOL_CONFIG_REG is common ext reg */ 1620 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1621 if (wol_config < 0) 1622 return wol_config; 1623 1624 /* if wol enable, do nothing */ 1625 if (wol_config & YTPHY_WCR_ENABLE) 1626 return 0; 1627 1628 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); 1629 } 1630 1631 /** 1632 * yt8521_resume() - resume the hardware 1633 * @phydev: a pointer to a &struct phy_device 1634 * 1635 * returns 0 or negative errno code 1636 */ 1637 static int yt8521_resume(struct phy_device *phydev) 1638 { 1639 int ret; 1640 int wol_config; 1641 1642 /* disable auto sleep */ 1643 ret = ytphy_modify_ext_with_lock(phydev, 1644 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1645 YT8521_ESC1R_SLEEP_SW, 0); 1646 if (ret < 0) 1647 return ret; 1648 1649 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1650 if (wol_config < 0) 1651 return wol_config; 1652 1653 /* if wol enable, do nothing */ 1654 if (wol_config & YTPHY_WCR_ENABLE) 1655 return 0; 1656 1657 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); 1658 } 1659 1660 /** 1661 * yt8521_config_init() - called to initialize the PHY 1662 * @phydev: a pointer to a &struct phy_device 1663 * 1664 * returns 0 or negative errno code 1665 */ 1666 static int yt8521_config_init(struct phy_device *phydev) 1667 { 1668 struct device_node *node = phydev->mdio.dev.of_node; 1669 int old_page; 1670 int ret = 0; 1671 1672 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 1673 if (old_page < 0) 1674 goto err_restore_page; 1675 1676 /* set rgmii delay mode */ 1677 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) { 1678 ret = ytphy_rgmii_clk_delay_config(phydev); 1679 if (ret < 0) 1680 goto err_restore_page; 1681 } 1682 1683 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { 1684 /* disable auto sleep */ 1685 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, 1686 YT8521_ESC1R_SLEEP_SW, 0); 1687 if (ret < 0) 1688 goto err_restore_page; 1689 } 1690 1691 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { 1692 /* enable RXC clock when no wire plug */ 1693 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, 1694 YT8521_CGR_RX_CLK_EN, 0); 1695 if (ret < 0) 1696 goto err_restore_page; 1697 } 1698 err_restore_page: 1699 return phy_restore_page(phydev, old_page, ret); 1700 } 1701 1702 static const unsigned long supported_trgs = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1703 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1704 BIT(TRIGGER_NETDEV_LINK) | 1705 BIT(TRIGGER_NETDEV_LINK_10) | 1706 BIT(TRIGGER_NETDEV_LINK_100) | 1707 BIT(TRIGGER_NETDEV_LINK_1000) | 1708 BIT(TRIGGER_NETDEV_RX) | 1709 BIT(TRIGGER_NETDEV_TX)); 1710 1711 static int yt8521_led_hw_is_supported(struct phy_device *phydev, u8 index, 1712 unsigned long rules) 1713 { 1714 if (index >= YT8521_MAX_LEDS) 1715 return -EINVAL; 1716 1717 /* All combinations of the supported triggers are allowed */ 1718 if (rules & ~supported_trgs) 1719 return -EOPNOTSUPP; 1720 1721 return 0; 1722 } 1723 1724 static int yt8521_led_hw_control_set(struct phy_device *phydev, u8 index, 1725 unsigned long rules) 1726 { 1727 u16 val = 0; 1728 1729 if (index >= YT8521_MAX_LEDS) 1730 return -EINVAL; 1731 1732 if (test_bit(TRIGGER_NETDEV_LINK, &rules)) { 1733 val |= YT8521_LED_10_ON_EN; 1734 val |= YT8521_LED_100_ON_EN; 1735 val |= YT8521_LED_1000_ON_EN; 1736 } 1737 1738 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 1739 val |= YT8521_LED_10_ON_EN; 1740 1741 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 1742 val |= YT8521_LED_100_ON_EN; 1743 1744 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 1745 val |= YT8521_LED_1000_ON_EN; 1746 1747 if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) 1748 val |= YT8521_LED_FDX_ON_EN; 1749 1750 if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) 1751 val |= YT8521_LED_HDX_ON_EN; 1752 1753 if (test_bit(TRIGGER_NETDEV_TX, &rules) || 1754 test_bit(TRIGGER_NETDEV_RX, &rules)) 1755 val |= YT8521_LED_ACT_BLK_IND; 1756 1757 if (test_bit(TRIGGER_NETDEV_TX, &rules)) 1758 val |= YT8521_LED_TXACT_BLK_EN; 1759 1760 if (test_bit(TRIGGER_NETDEV_RX, &rules)) 1761 val |= YT8521_LED_RXACT_BLK_EN; 1762 1763 return ytphy_write_ext(phydev, YT8521_LED0_CFG_REG + index, val); 1764 } 1765 1766 static int yt8521_led_hw_control_get(struct phy_device *phydev, u8 index, 1767 unsigned long *rules) 1768 { 1769 int val; 1770 1771 if (index >= YT8521_MAX_LEDS) 1772 return -EINVAL; 1773 1774 val = ytphy_read_ext(phydev, YT8521_LED0_CFG_REG + index); 1775 if (val < 0) 1776 return val; 1777 1778 if (val & YT8521_LED_TXACT_BLK_EN || val & YT8521_LED_ACT_BLK_IND) 1779 __set_bit(TRIGGER_NETDEV_TX, rules); 1780 1781 if (val & YT8521_LED_RXACT_BLK_EN || val & YT8521_LED_ACT_BLK_IND) 1782 __set_bit(TRIGGER_NETDEV_RX, rules); 1783 1784 if (val & YT8521_LED_FDX_ON_EN) 1785 __set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); 1786 1787 if (val & YT8521_LED_HDX_ON_EN) 1788 __set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); 1789 1790 if (val & YT8521_LED_1000_ON_EN) 1791 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1792 1793 if (val & YT8521_LED_100_ON_EN) 1794 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1795 1796 if (val & YT8521_LED_10_ON_EN) 1797 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1798 1799 return 0; 1800 } 1801 1802 static int yt8531_config_init(struct phy_device *phydev) 1803 { 1804 struct device_node *node = phydev->mdio.dev.of_node; 1805 int ret; 1806 1807 ret = ytphy_rgmii_clk_delay_config_with_lock(phydev); 1808 if (ret < 0) 1809 return ret; 1810 1811 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { 1812 /* disable auto sleep */ 1813 ret = ytphy_modify_ext_with_lock(phydev, 1814 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1815 YT8521_ESC1R_SLEEP_SW, 0); 1816 if (ret < 0) 1817 return ret; 1818 } 1819 1820 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { 1821 /* enable RXC clock when no wire plug */ 1822 ret = ytphy_modify_ext_with_lock(phydev, 1823 YT8521_CLOCK_GATING_REG, 1824 YT8521_CGR_RX_CLK_EN, 0); 1825 if (ret < 0) 1826 return ret; 1827 } 1828 1829 ret = yt8531_set_ds(phydev); 1830 if (ret < 0) 1831 return ret; 1832 1833 return 0; 1834 } 1835 1836 /** 1837 * yt8531_link_change_notify() - Adjust the tx clock direction according to 1838 * the current speed and dts config. 1839 * @phydev: a pointer to a &struct phy_device 1840 * 1841 * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please 1842 * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not 1843 * JH7110. 1844 */ 1845 static void yt8531_link_change_notify(struct phy_device *phydev) 1846 { 1847 struct device_node *node = phydev->mdio.dev.of_node; 1848 bool tx_clk_1000_inverted = false; 1849 bool tx_clk_100_inverted = false; 1850 bool tx_clk_10_inverted = false; 1851 bool tx_clk_adj_enabled = false; 1852 u16 val = 0; 1853 int ret; 1854 1855 if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled")) 1856 tx_clk_adj_enabled = true; 1857 1858 if (!tx_clk_adj_enabled) 1859 return; 1860 1861 if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted")) 1862 tx_clk_10_inverted = true; 1863 if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted")) 1864 tx_clk_100_inverted = true; 1865 if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted")) 1866 tx_clk_1000_inverted = true; 1867 1868 if (phydev->speed < 0) 1869 return; 1870 1871 switch (phydev->speed) { 1872 case SPEED_1000: 1873 if (tx_clk_1000_inverted) 1874 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1875 break; 1876 case SPEED_100: 1877 if (tx_clk_100_inverted) 1878 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1879 break; 1880 case SPEED_10: 1881 if (tx_clk_10_inverted) 1882 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1883 break; 1884 default: 1885 return; 1886 } 1887 1888 ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG, 1889 YT8521_RC1R_TX_CLK_SEL_INVERTED, val); 1890 if (ret < 0) 1891 phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret); 1892 } 1893 1894 /** 1895 * yt8521_prepare_fiber_features() - A small helper function that setup 1896 * fiber's features. 1897 * @phydev: a pointer to a &struct phy_device 1898 * @dst: a pointer to store fiber's features 1899 */ 1900 static void yt8521_prepare_fiber_features(struct phy_device *phydev, 1901 unsigned long *dst) 1902 { 1903 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst); 1904 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst); 1905 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst); 1906 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst); 1907 } 1908 1909 /** 1910 * yt8521_fiber_setup_forced - configures/forces speed from @phydev 1911 * @phydev: target phy_device struct 1912 * 1913 * NOTE:The caller must have taken the MDIO bus lock. 1914 * 1915 * returns 0 or negative errno code 1916 */ 1917 static int yt8521_fiber_setup_forced(struct phy_device *phydev) 1918 { 1919 u16 val; 1920 int ret; 1921 1922 if (phydev->speed == SPEED_1000) 1923 val = YTPHY_MCR_FIBER_1000BX; 1924 else if (phydev->speed == SPEED_100) 1925 val = YTPHY_MCR_FIBER_100FX; 1926 else 1927 return -EINVAL; 1928 1929 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 1930 if (ret < 0) 1931 return ret; 1932 1933 /* disable Fiber auto sensing */ 1934 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 1935 YT8521_LTCR_EN_AUTOSEN, 0); 1936 if (ret < 0) 1937 return ret; 1938 1939 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG, 1940 YTPHY_MCR_FIBER_SPEED_MASK, val); 1941 if (ret < 0) 1942 return ret; 1943 1944 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 1945 YT8521_CCR_SW_RST, 0); 1946 } 1947 1948 /** 1949 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation 1950 * @phydev: target phy_device struct 1951 * @restart: whether aneg restart is requested 1952 * 1953 * NOTE:The caller must have taken the MDIO bus lock. 1954 * 1955 * returns 0 or negative errno code 1956 */ 1957 static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart) 1958 { 1959 int ret; 1960 1961 if (!restart) { 1962 /* Advertisement hasn't changed, but maybe aneg was never on to 1963 * begin with? Or maybe phy was isolated? 1964 */ 1965 ret = __phy_read(phydev, MII_BMCR); 1966 if (ret < 0) 1967 return ret; 1968 1969 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE)) 1970 restart = true; 1971 } 1972 /* Enable and Restart Autonegotiation 1973 * Don't isolate the PHY if we're negotiating 1974 */ 1975 if (restart) 1976 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, 1977 BMCR_ANENABLE | BMCR_ANRESTART); 1978 1979 return 0; 1980 } 1981 1982 /** 1983 * yt8521_fiber_config_aneg - restart auto-negotiation or write 1984 * YTPHY_MISC_CONFIG_REG. 1985 * @phydev: target phy_device struct 1986 * 1987 * NOTE:The caller must have taken the MDIO bus lock. 1988 * 1989 * returns 0 or negative errno code 1990 */ 1991 static int yt8521_fiber_config_aneg(struct phy_device *phydev) 1992 { 1993 int err, changed = 0; 1994 int bmcr; 1995 u16 adv; 1996 1997 if (phydev->autoneg != AUTONEG_ENABLE) 1998 return yt8521_fiber_setup_forced(phydev); 1999 2000 /* enable Fiber auto sensing */ 2001 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 2002 0, YT8521_LTCR_EN_AUTOSEN); 2003 if (err < 0) 2004 return err; 2005 2006 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 2007 YT8521_CCR_SW_RST, 0); 2008 if (err < 0) 2009 return err; 2010 2011 bmcr = __phy_read(phydev, MII_BMCR); 2012 if (bmcr < 0) 2013 return bmcr; 2014 2015 /* When it is coming from fiber forced mode, add bmcr power down 2016 * and power up to let aneg work fine. 2017 */ 2018 if (!(bmcr & BMCR_ANENABLE)) { 2019 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 2020 usleep_range(1000, 1100); 2021 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 2022 } 2023 2024 adv = linkmode_adv_to_mii_adv_x(phydev->advertising, 2025 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 2026 2027 /* Setup fiber advertisement */ 2028 err = __phy_modify_changed(phydev, MII_ADVERTISE, 2029 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL | 2030 ADVERTISE_1000XPAUSE | 2031 ADVERTISE_1000XPSE_ASYM, 2032 adv); 2033 if (err < 0) 2034 return err; 2035 2036 if (err > 0) 2037 changed = 1; 2038 2039 return ytphy_check_and_restart_aneg(phydev, changed); 2040 } 2041 2042 /** 2043 * ytphy_setup_master_slave 2044 * @phydev: target phy_device struct 2045 * 2046 * NOTE: The caller must have taken the MDIO bus lock. 2047 * 2048 * returns 0 or negative errno code 2049 */ 2050 static int ytphy_setup_master_slave(struct phy_device *phydev) 2051 { 2052 u16 ctl = 0; 2053 2054 if (!phydev->is_gigabit_capable) 2055 return 0; 2056 2057 switch (phydev->master_slave_set) { 2058 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 2059 ctl |= CTL1000_PREFER_MASTER; 2060 break; 2061 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 2062 break; 2063 case MASTER_SLAVE_CFG_MASTER_FORCE: 2064 ctl |= CTL1000_AS_MASTER; 2065 fallthrough; 2066 case MASTER_SLAVE_CFG_SLAVE_FORCE: 2067 ctl |= CTL1000_ENABLE_MASTER; 2068 break; 2069 case MASTER_SLAVE_CFG_UNKNOWN: 2070 case MASTER_SLAVE_CFG_UNSUPPORTED: 2071 return 0; 2072 default: 2073 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 2074 return -EOPNOTSUPP; 2075 } 2076 2077 return __phy_modify_changed(phydev, MII_CTRL1000, 2078 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER | 2079 CTL1000_PREFER_MASTER), ctl); 2080 } 2081 2082 /** 2083 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters 2084 * @phydev: target phy_device struct 2085 * 2086 * NOTE: Writes MII_ADVERTISE with the appropriate values, 2087 * after sanitizing the values to make sure we only advertise 2088 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement 2089 * hasn't changed, and > 0 if it has changed. 2090 * The caller must have taken the MDIO bus lock. 2091 * 2092 * returns 0 or negative errno code 2093 */ 2094 static int ytphy_utp_config_advert(struct phy_device *phydev) 2095 { 2096 int err, bmsr, changed = 0; 2097 u32 adv; 2098 2099 /* Only allow advertising what this PHY supports */ 2100 linkmode_and(phydev->advertising, phydev->advertising, 2101 phydev->supported); 2102 2103 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 2104 2105 /* Setup standard advertisement */ 2106 err = __phy_modify_changed(phydev, MII_ADVERTISE, 2107 ADVERTISE_ALL | ADVERTISE_100BASE4 | 2108 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 2109 adv); 2110 if (err < 0) 2111 return err; 2112 if (err > 0) 2113 changed = 1; 2114 2115 bmsr = __phy_read(phydev, MII_BMSR); 2116 if (bmsr < 0) 2117 return bmsr; 2118 2119 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all 2120 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a 2121 * logical 1. 2122 */ 2123 if (!(bmsr & BMSR_ESTATEN)) 2124 return changed; 2125 2126 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 2127 2128 err = __phy_modify_changed(phydev, MII_CTRL1000, 2129 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 2130 adv); 2131 if (err < 0) 2132 return err; 2133 if (err > 0) 2134 changed = 1; 2135 2136 return changed; 2137 } 2138 2139 /** 2140 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR 2141 * @phydev: target phy_device struct 2142 * @changed: whether autoneg is requested 2143 * 2144 * NOTE: If auto-negotiation is enabled, we configure the 2145 * advertising, and then restart auto-negotiation. If it is not 2146 * enabled, then we write the BMCR. 2147 * The caller must have taken the MDIO bus lock. 2148 * 2149 * returns 0 or negative errno code 2150 */ 2151 static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed) 2152 { 2153 int err; 2154 u16 ctl; 2155 2156 err = ytphy_setup_master_slave(phydev); 2157 if (err < 0) 2158 return err; 2159 else if (err) 2160 changed = true; 2161 2162 if (phydev->autoneg != AUTONEG_ENABLE) { 2163 /* configures/forces speed/duplex from @phydev */ 2164 2165 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex); 2166 2167 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK | 2168 BMCR_ISOLATE | BMCR_PDOWN), ctl); 2169 } 2170 2171 err = ytphy_utp_config_advert(phydev); 2172 if (err < 0) /* error */ 2173 return err; 2174 else if (err) 2175 changed = true; 2176 2177 return ytphy_check_and_restart_aneg(phydev, changed); 2178 } 2179 2180 /** 2181 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg 2182 * of one page 2183 * @phydev: a pointer to a &struct phy_device 2184 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2185 * operate. 2186 * 2187 * returns 0 or negative errno code 2188 */ 2189 static int yt8521_config_aneg_paged(struct phy_device *phydev, int page) 2190 { 2191 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported); 2192 struct yt8521_priv *priv = phydev->priv; 2193 int old_page; 2194 int ret = 0; 2195 2196 page &= YT8521_RSSR_SPACE_MASK; 2197 2198 old_page = phy_select_page(phydev, page); 2199 if (old_page < 0) 2200 goto err_restore_page; 2201 2202 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 2203 * phydev->advertising should be updated. 2204 */ 2205 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 2206 linkmode_zero(fiber_supported); 2207 yt8521_prepare_fiber_features(phydev, fiber_supported); 2208 2209 /* prepare fiber_supported, then setup advertising. */ 2210 if (page == YT8521_RSSR_FIBER_SPACE) { 2211 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2212 fiber_supported); 2213 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2214 fiber_supported); 2215 linkmode_and(phydev->advertising, 2216 priv->combo_advertising, fiber_supported); 2217 } else { 2218 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */ 2219 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2220 fiber_supported); 2221 linkmode_andnot(phydev->advertising, 2222 priv->combo_advertising, 2223 fiber_supported); 2224 } 2225 } 2226 2227 if (page == YT8521_RSSR_FIBER_SPACE) 2228 ret = yt8521_fiber_config_aneg(phydev); 2229 else 2230 ret = ytphy_utp_config_aneg(phydev, false); 2231 2232 err_restore_page: 2233 return phy_restore_page(phydev, old_page, ret); 2234 } 2235 2236 /** 2237 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged 2238 * @phydev: a pointer to a &struct phy_device 2239 * 2240 * returns 0 or negative errno code 2241 */ 2242 static int yt8521_config_aneg(struct phy_device *phydev) 2243 { 2244 struct yt8521_priv *priv = phydev->priv; 2245 int ret; 2246 2247 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2248 ret = yt8521_config_aneg_paged(phydev, priv->reg_page); 2249 if (ret < 0) 2250 return ret; 2251 } else { 2252 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 2253 * phydev->advertising need to be saved at first run. 2254 * Because it contains the advertising which supported by both 2255 * mac and yt8521(utp and fiber). 2256 */ 2257 if (linkmode_empty(priv->combo_advertising)) { 2258 linkmode_copy(priv->combo_advertising, 2259 phydev->advertising); 2260 } 2261 2262 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE); 2263 if (ret < 0) 2264 return ret; 2265 2266 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE); 2267 if (ret < 0) 2268 return ret; 2269 2270 /* we don't known which will be link, so restore 2271 * phydev->advertising as default value. 2272 */ 2273 linkmode_copy(phydev->advertising, priv->combo_advertising); 2274 } 2275 return 0; 2276 } 2277 2278 /** 2279 * yt8521_aneg_done_paged() - determines the auto negotiation result of one 2280 * page. 2281 * @phydev: a pointer to a &struct phy_device 2282 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2283 * operate. 2284 * 2285 * returns 0(no link)or 1(fiber or utp link) or negative errno code 2286 */ 2287 static int yt8521_aneg_done_paged(struct phy_device *phydev, int page) 2288 { 2289 int old_page; 2290 int ret = 0; 2291 int link; 2292 2293 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 2294 if (old_page < 0) 2295 goto err_restore_page; 2296 2297 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 2298 if (ret < 0) 2299 goto err_restore_page; 2300 2301 link = !!(ret & YTPHY_SSR_LINK); 2302 ret = link; 2303 2304 err_restore_page: 2305 return phy_restore_page(phydev, old_page, ret); 2306 } 2307 2308 /** 2309 * yt8521_aneg_done() - determines the auto negotiation result 2310 * @phydev: a pointer to a &struct phy_device 2311 * 2312 * returns 0(no link)or 1(fiber or utp link) or negative errno code 2313 */ 2314 static int yt8521_aneg_done(struct phy_device *phydev) 2315 { 2316 struct yt8521_priv *priv = phydev->priv; 2317 int link_fiber = 0; 2318 int link_utp; 2319 int link; 2320 2321 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2322 link = yt8521_aneg_done_paged(phydev, priv->reg_page); 2323 } else { 2324 link_utp = yt8521_aneg_done_paged(phydev, 2325 YT8521_RSSR_UTP_SPACE); 2326 if (link_utp < 0) 2327 return link_utp; 2328 2329 if (!link_utp) { 2330 link_fiber = yt8521_aneg_done_paged(phydev, 2331 YT8521_RSSR_FIBER_SPACE); 2332 if (link_fiber < 0) 2333 return link_fiber; 2334 } 2335 link = link_fiber || link_utp; 2336 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n", 2337 __func__, link_fiber, link_utp); 2338 } 2339 2340 return link; 2341 } 2342 2343 /** 2344 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers 2345 * @phydev: target phy_device struct 2346 * 2347 * NOTE: Reads the PHY's abilities and populates 2348 * phydev->supported accordingly. 2349 * The caller must have taken the MDIO bus lock. 2350 * 2351 * returns 0 or negative errno code 2352 */ 2353 static int ytphy_utp_read_abilities(struct phy_device *phydev) 2354 { 2355 int val; 2356 2357 linkmode_set_bit_array(phy_basic_ports_array, 2358 ARRAY_SIZE(phy_basic_ports_array), 2359 phydev->supported); 2360 2361 val = __phy_read(phydev, MII_BMSR); 2362 if (val < 0) 2363 return val; 2364 2365 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported, 2366 val & BMSR_ANEGCAPABLE); 2367 2368 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported, 2369 val & BMSR_100FULL); 2370 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported, 2371 val & BMSR_100HALF); 2372 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported, 2373 val & BMSR_10FULL); 2374 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported, 2375 val & BMSR_10HALF); 2376 2377 if (val & BMSR_ESTATEN) { 2378 val = __phy_read(phydev, MII_ESTATUS); 2379 if (val < 0) 2380 return val; 2381 2382 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2383 phydev->supported, val & ESTATUS_1000_TFULL); 2384 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 2385 phydev->supported, val & ESTATUS_1000_THALF); 2386 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2387 phydev->supported, val & ESTATUS_1000_XFULL); 2388 } 2389 2390 return 0; 2391 } 2392 2393 /** 2394 * yt8521_get_features_paged() - read supported link modes for one page 2395 * @phydev: a pointer to a &struct phy_device 2396 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2397 * operate. 2398 * 2399 * returns 0 or negative errno code 2400 */ 2401 static int yt8521_get_features_paged(struct phy_device *phydev, int page) 2402 { 2403 int old_page; 2404 int ret = 0; 2405 2406 page &= YT8521_RSSR_SPACE_MASK; 2407 old_page = phy_select_page(phydev, page); 2408 if (old_page < 0) 2409 goto err_restore_page; 2410 2411 if (page == YT8521_RSSR_FIBER_SPACE) { 2412 linkmode_zero(phydev->supported); 2413 yt8521_prepare_fiber_features(phydev, phydev->supported); 2414 } else { 2415 ret = ytphy_utp_read_abilities(phydev); 2416 if (ret < 0) 2417 goto err_restore_page; 2418 } 2419 2420 err_restore_page: 2421 return phy_restore_page(phydev, old_page, ret); 2422 } 2423 2424 /** 2425 * yt8521_get_features - switch reg space then call yt8521_get_features_paged 2426 * @phydev: target phy_device struct 2427 * 2428 * returns 0 or negative errno code 2429 */ 2430 static int yt8521_get_features(struct phy_device *phydev) 2431 { 2432 struct yt8521_priv *priv = phydev->priv; 2433 int ret; 2434 2435 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2436 ret = yt8521_get_features_paged(phydev, priv->reg_page); 2437 } else { 2438 ret = yt8521_get_features_paged(phydev, 2439 YT8521_RSSR_UTP_SPACE); 2440 if (ret < 0) 2441 return ret; 2442 2443 /* add fiber's features to phydev->supported */ 2444 yt8521_prepare_fiber_features(phydev, phydev->supported); 2445 } 2446 return ret; 2447 } 2448 2449 /** 2450 * yt8821_get_features - read mmd register to get 2.5G capability 2451 * @phydev: target phy_device struct 2452 * 2453 * Returns: 0 or negative errno code 2454 */ 2455 static int yt8821_get_features(struct phy_device *phydev) 2456 { 2457 int ret; 2458 2459 ret = genphy_c45_pma_read_ext_abilities(phydev); 2460 if (ret < 0) 2461 return ret; 2462 2463 return genphy_read_abilities(phydev); 2464 } 2465 2466 /** 2467 * yt8821_get_rate_matching - read register to get phy chip mode 2468 * @phydev: target phy_device struct 2469 * @iface: PHY data interface type 2470 * 2471 * Returns: rate matching type or negative errno code 2472 */ 2473 static int yt8821_get_rate_matching(struct phy_device *phydev, 2474 phy_interface_t iface) 2475 { 2476 int val; 2477 2478 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 2479 if (val < 0) 2480 return val; 2481 2482 if (FIELD_GET(YT8521_CCR_MODE_SEL_MASK, val) == 2483 YT8821_CHIP_MODE_FORCE_BX2500) 2484 return RATE_MATCH_PAUSE; 2485 2486 return RATE_MATCH_NONE; 2487 } 2488 2489 /** 2490 * yt8821_aneg_done() - determines the auto negotiation result 2491 * @phydev: a pointer to a &struct phy_device 2492 * 2493 * Returns: 0(no link)or 1(utp link) or negative errno code 2494 */ 2495 static int yt8821_aneg_done(struct phy_device *phydev) 2496 { 2497 return yt8521_aneg_done_paged(phydev, YT8521_RSSR_UTP_SPACE); 2498 } 2499 2500 /** 2501 * yt8821_serdes_init() - serdes init 2502 * @phydev: a pointer to a &struct phy_device 2503 * 2504 * Returns: 0 or negative errno code 2505 */ 2506 static int yt8821_serdes_init(struct phy_device *phydev) 2507 { 2508 int old_page; 2509 int ret = 0; 2510 u16 mask; 2511 u16 set; 2512 2513 old_page = phy_select_page(phydev, YT8521_RSSR_FIBER_SPACE); 2514 if (old_page < 0) { 2515 phydev_err(phydev, "Failed to select page: %d\n", 2516 old_page); 2517 goto err_restore_page; 2518 } 2519 2520 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 2521 if (ret < 0) 2522 goto err_restore_page; 2523 2524 mask = YT8821_SDS_EXT_CSR_VCO_LDO_EN | 2525 YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN; 2526 set = YT8821_SDS_EXT_CSR_VCO_LDO_EN; 2527 ret = ytphy_modify_ext(phydev, YT8821_SDS_EXT_CSR_CTRL_REG, mask, 2528 set); 2529 2530 err_restore_page: 2531 return phy_restore_page(phydev, old_page, ret); 2532 } 2533 2534 /** 2535 * yt8821_utp_init() - utp init 2536 * @phydev: a pointer to a &struct phy_device 2537 * 2538 * Returns: 0 or negative errno code 2539 */ 2540 static int yt8821_utp_init(struct phy_device *phydev) 2541 { 2542 int old_page; 2543 int ret = 0; 2544 u16 mask; 2545 u16 save; 2546 u16 set; 2547 2548 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 2549 if (old_page < 0) { 2550 phydev_err(phydev, "Failed to select page: %d\n", 2551 old_page); 2552 goto err_restore_page; 2553 } 2554 2555 mask = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 | 2556 YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 | 2557 YT8821_UTP_EXT_RPDN_IPR_SHT_2500; 2558 set = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 | 2559 YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500; 2560 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_RPDN_CTRL_REG, 2561 mask, set); 2562 if (ret < 0) 2563 goto err_restore_page; 2564 2565 mask = YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER | 2566 YT8821_UTP_EXT_VGA_LPF1_CAP_2500; 2567 ret = ytphy_modify_ext(phydev, 2568 YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG, 2569 mask, 0); 2570 if (ret < 0) 2571 goto err_restore_page; 2572 2573 mask = YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER | 2574 YT8821_UTP_EXT_VGA_LPF2_CAP_2500; 2575 ret = ytphy_modify_ext(phydev, 2576 YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG, 2577 mask, 0); 2578 if (ret < 0) 2579 goto err_restore_page; 2580 2581 mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 | 2582 YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500; 2583 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500, 0x5a) | 2584 FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500, 0x3c); 2585 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_TRACE_CTRL_REG, 2586 mask, set); 2587 if (ret < 0) 2588 goto err_restore_page; 2589 2590 mask = YT8821_UTP_EXT_IPR_LNG_2500; 2591 set = FIELD_PREP(YT8821_UTP_EXT_IPR_LNG_2500, 0x6c); 2592 ret = ytphy_modify_ext(phydev, 2593 YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG, 2594 mask, set); 2595 if (ret < 0) 2596 goto err_restore_page; 2597 2598 mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000; 2599 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000, 0x2a); 2600 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_ECHO_CTRL_REG, 2601 mask, set); 2602 if (ret < 0) 2603 goto err_restore_page; 2604 2605 mask = YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000; 2606 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000, 0x22); 2607 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_GAIN_CTRL_REG, 2608 mask, set); 2609 if (ret < 0) 2610 goto err_restore_page; 2611 2612 mask = YT8821_UTP_EXT_TH_20DB_2500; 2613 set = FIELD_PREP(YT8821_UTP_EXT_TH_20DB_2500, 0x8000); 2614 ret = ytphy_modify_ext(phydev, 2615 YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG, 2616 mask, set); 2617 if (ret < 0) 2618 goto err_restore_page; 2619 2620 mask = YT8821_UTP_EXT_MU_COARSE_FR_F_FFE | 2621 YT8821_UTP_EXT_MU_COARSE_FR_F_FBE; 2622 set = FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FFE, 0x7) | 2623 FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FBE, 0x7); 2624 ret = ytphy_modify_ext(phydev, 2625 YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG, 2626 mask, set); 2627 if (ret < 0) 2628 goto err_restore_page; 2629 2630 mask = YT8821_UTP_EXT_MU_FINE_FR_F_FFE | 2631 YT8821_UTP_EXT_MU_FINE_FR_F_FBE; 2632 set = FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FFE, 0x2) | 2633 FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FBE, 0x2); 2634 ret = ytphy_modify_ext(phydev, 2635 YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG, 2636 mask, set); 2637 if (ret < 0) 2638 goto err_restore_page; 2639 2640 /* save YT8821_UTP_EXT_PI_CTRL_REG's val for use later */ 2641 ret = ytphy_read_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG); 2642 if (ret < 0) 2643 goto err_restore_page; 2644 2645 save = ret; 2646 2647 mask = YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE | 2648 YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE | 2649 YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE | 2650 YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE | 2651 YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE; 2652 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, 2653 mask, 0); 2654 if (ret < 0) 2655 goto err_restore_page; 2656 2657 /* restore YT8821_UTP_EXT_PI_CTRL_REG's val */ 2658 ret = ytphy_write_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, save); 2659 if (ret < 0) 2660 goto err_restore_page; 2661 2662 mask = YT8821_UTP_EXT_FECHO_AMP_TH_HUGE; 2663 set = FIELD_PREP(YT8821_UTP_EXT_FECHO_AMP_TH_HUGE, 0x38); 2664 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_VCT_CFG6_CTRL_REG, 2665 mask, set); 2666 if (ret < 0) 2667 goto err_restore_page; 2668 2669 mask = YT8821_UTP_EXT_NFR_TX_ABILITY; 2670 set = YT8821_UTP_EXT_NFR_TX_ABILITY; 2671 ret = ytphy_modify_ext(phydev, 2672 YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG, 2673 mask, set); 2674 if (ret < 0) 2675 goto err_restore_page; 2676 2677 mask = YT8821_UTP_EXT_PLL_SPARE_CFG; 2678 set = FIELD_PREP(YT8821_UTP_EXT_PLL_SPARE_CFG, 0xe9); 2679 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PLL_CTRL_REG, 2680 mask, set); 2681 if (ret < 0) 2682 goto err_restore_page; 2683 2684 mask = YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG | 2685 YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG; 2686 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG, 0x64) | 2687 FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG, 0x64); 2688 ret = ytphy_modify_ext(phydev, 2689 YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG, 2690 mask, set); 2691 if (ret < 0) 2692 goto err_restore_page; 2693 2694 mask = YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG | 2695 YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG; 2696 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG, 0x64) | 2697 FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG, 0x64); 2698 ret = ytphy_modify_ext(phydev, 2699 YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG, 2700 mask, set); 2701 if (ret < 0) 2702 goto err_restore_page; 2703 2704 mask = YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG | 2705 YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG; 2706 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG, 0x64) | 2707 FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG, 0x64); 2708 ret = ytphy_modify_ext(phydev, 2709 YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG, 2710 mask, set); 2711 if (ret < 0) 2712 goto err_restore_page; 2713 2714 mask = YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG | 2715 YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG; 2716 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG, 0x64) | 2717 FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG, 0x64); 2718 ret = ytphy_modify_ext(phydev, 2719 YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG, 2720 mask, set); 2721 2722 err_restore_page: 2723 return phy_restore_page(phydev, old_page, ret); 2724 } 2725 2726 /** 2727 * yt8821_auto_sleep_config() - phy auto sleep config 2728 * @phydev: a pointer to a &struct phy_device 2729 * @enable: true enable auto sleep, false disable auto sleep 2730 * 2731 * Returns: 0 or negative errno code 2732 */ 2733 static int yt8821_auto_sleep_config(struct phy_device *phydev, 2734 bool enable) 2735 { 2736 int old_page; 2737 int ret = 0; 2738 2739 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 2740 if (old_page < 0) { 2741 phydev_err(phydev, "Failed to select page: %d\n", 2742 old_page); 2743 goto err_restore_page; 2744 } 2745 2746 ret = ytphy_modify_ext(phydev, 2747 YT8521_EXTREG_SLEEP_CONTROL1_REG, 2748 YT8521_ESC1R_SLEEP_SW, 2749 enable ? 1 : 0); 2750 2751 err_restore_page: 2752 return phy_restore_page(phydev, old_page, ret); 2753 } 2754 2755 /** 2756 * yt8821_soft_reset() - soft reset utp and serdes 2757 * @phydev: a pointer to a &struct phy_device 2758 * 2759 * Returns: 0 or negative errno code 2760 */ 2761 static int yt8821_soft_reset(struct phy_device *phydev) 2762 { 2763 return ytphy_modify_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG, 2764 YT8521_CCR_SW_RST, 0); 2765 } 2766 2767 /** 2768 * yt8821_config_init() - phy initializatioin 2769 * @phydev: a pointer to a &struct phy_device 2770 * 2771 * Returns: 0 or negative errno code 2772 */ 2773 static int yt8821_config_init(struct phy_device *phydev) 2774 { 2775 u8 mode = YT8821_CHIP_MODE_AUTO_BX2500_SGMII; 2776 int ret; 2777 u16 set; 2778 2779 if (phydev->interface == PHY_INTERFACE_MODE_2500BASEX) 2780 mode = YT8821_CHIP_MODE_FORCE_BX2500; 2781 2782 set = FIELD_PREP(YT8521_CCR_MODE_SEL_MASK, mode); 2783 ret = ytphy_modify_ext_with_lock(phydev, 2784 YT8521_CHIP_CONFIG_REG, 2785 YT8521_CCR_MODE_SEL_MASK, 2786 set); 2787 if (ret < 0) 2788 return ret; 2789 2790 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2791 phydev->possible_interfaces); 2792 2793 if (mode == YT8821_CHIP_MODE_AUTO_BX2500_SGMII) { 2794 __set_bit(PHY_INTERFACE_MODE_SGMII, 2795 phydev->possible_interfaces); 2796 2797 phydev->rate_matching = RATE_MATCH_NONE; 2798 } else if (mode == YT8821_CHIP_MODE_FORCE_BX2500) { 2799 phydev->rate_matching = RATE_MATCH_PAUSE; 2800 } 2801 2802 ret = yt8821_serdes_init(phydev); 2803 if (ret < 0) 2804 return ret; 2805 2806 ret = yt8821_utp_init(phydev); 2807 if (ret < 0) 2808 return ret; 2809 2810 /* disable auto sleep */ 2811 ret = yt8821_auto_sleep_config(phydev, false); 2812 if (ret < 0) 2813 return ret; 2814 2815 /* soft reset */ 2816 return yt8821_soft_reset(phydev); 2817 } 2818 2819 /** 2820 * yt8821_adjust_status() - update speed and duplex to phydev 2821 * @phydev: a pointer to a &struct phy_device 2822 * @val: read from YTPHY_SPECIFIC_STATUS_REG 2823 */ 2824 static void yt8821_adjust_status(struct phy_device *phydev, int val) 2825 { 2826 int speed, duplex; 2827 int speed_mode; 2828 2829 duplex = FIELD_GET(YTPHY_SSR_DUPLEX, val); 2830 speed_mode = val & YTPHY_SSR_SPEED_MASK; 2831 switch (speed_mode) { 2832 case YTPHY_SSR_SPEED_10M: 2833 speed = SPEED_10; 2834 break; 2835 case YTPHY_SSR_SPEED_100M: 2836 speed = SPEED_100; 2837 break; 2838 case YTPHY_SSR_SPEED_1000M: 2839 speed = SPEED_1000; 2840 break; 2841 case YTPHY_SSR_SPEED_2500M: 2842 speed = SPEED_2500; 2843 break; 2844 default: 2845 speed = SPEED_UNKNOWN; 2846 break; 2847 } 2848 2849 phydev->speed = speed; 2850 phydev->duplex = duplex; 2851 } 2852 2853 /** 2854 * yt8821_update_interface() - update interface per current speed 2855 * @phydev: a pointer to a &struct phy_device 2856 */ 2857 static void yt8821_update_interface(struct phy_device *phydev) 2858 { 2859 if (!phydev->link) 2860 return; 2861 2862 switch (phydev->speed) { 2863 case SPEED_2500: 2864 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 2865 break; 2866 case SPEED_1000: 2867 case SPEED_100: 2868 case SPEED_10: 2869 phydev->interface = PHY_INTERFACE_MODE_SGMII; 2870 break; 2871 default: 2872 phydev_warn(phydev, "phy speed err :%d\n", phydev->speed); 2873 break; 2874 } 2875 } 2876 2877 /** 2878 * yt8821_read_status() - determines the negotiated speed and duplex 2879 * @phydev: a pointer to a &struct phy_device 2880 * 2881 * Returns: 0 or negative errno code 2882 */ 2883 static int yt8821_read_status(struct phy_device *phydev) 2884 { 2885 int link; 2886 int ret; 2887 int val; 2888 2889 ret = ytphy_write_ext_with_lock(phydev, 2890 YT8521_REG_SPACE_SELECT_REG, 2891 YT8521_RSSR_UTP_SPACE); 2892 if (ret < 0) 2893 return ret; 2894 2895 ret = genphy_read_status(phydev); 2896 if (ret < 0) 2897 return ret; 2898 2899 if (phydev->autoneg_complete) { 2900 ret = genphy_c45_read_lpa(phydev); 2901 if (ret < 0) 2902 return ret; 2903 } 2904 2905 ret = phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 2906 if (ret < 0) 2907 return ret; 2908 2909 val = ret; 2910 2911 link = val & YTPHY_SSR_LINK; 2912 if (link) 2913 yt8821_adjust_status(phydev, val); 2914 2915 if (link) { 2916 if (phydev->link == 0) 2917 phydev_dbg(phydev, 2918 "%s, phy addr: %d, link up\n", 2919 __func__, phydev->mdio.addr); 2920 phydev->link = 1; 2921 } else { 2922 if (phydev->link == 1) 2923 phydev_dbg(phydev, 2924 "%s, phy addr: %d, link down\n", 2925 __func__, phydev->mdio.addr); 2926 phydev->link = 0; 2927 } 2928 2929 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 2930 if (val < 0) 2931 return val; 2932 2933 if (FIELD_GET(YT8521_CCR_MODE_SEL_MASK, val) == 2934 YT8821_CHIP_MODE_AUTO_BX2500_SGMII) 2935 yt8821_update_interface(phydev); 2936 2937 return 0; 2938 } 2939 2940 /** 2941 * yt8821_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register 2942 * @phydev: the phy_device struct 2943 * @mask: bit mask of bits to clear 2944 * @set: bit mask of bits to set 2945 * 2946 * NOTE: Convenience function which allows a PHY's BMCR register to be 2947 * modified as new register value = (old register value & ~mask) | set. 2948 * 2949 * Returns: 0 or negative errno code 2950 */ 2951 static int yt8821_modify_utp_fiber_bmcr(struct phy_device *phydev, 2952 u16 mask, u16 set) 2953 { 2954 int ret; 2955 2956 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, 2957 mask, set); 2958 if (ret < 0) 2959 return ret; 2960 2961 return yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, 2962 mask, set); 2963 } 2964 2965 /** 2966 * yt8821_suspend() - suspend the hardware 2967 * @phydev: a pointer to a &struct phy_device 2968 * 2969 * Returns: 0 or negative errno code 2970 */ 2971 static int yt8821_suspend(struct phy_device *phydev) 2972 { 2973 int wol_config; 2974 2975 wol_config = ytphy_read_ext_with_lock(phydev, 2976 YTPHY_WOL_CONFIG_REG); 2977 if (wol_config < 0) 2978 return wol_config; 2979 2980 /* if wol enable, do nothing */ 2981 if (wol_config & YTPHY_WCR_ENABLE) 2982 return 0; 2983 2984 return yt8821_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); 2985 } 2986 2987 /** 2988 * yt8821_resume() - resume the hardware 2989 * @phydev: a pointer to a &struct phy_device 2990 * 2991 * Returns: 0 or negative errno code 2992 */ 2993 static int yt8821_resume(struct phy_device *phydev) 2994 { 2995 int wol_config; 2996 int ret; 2997 2998 /* disable auto sleep */ 2999 ret = yt8821_auto_sleep_config(phydev, false); 3000 if (ret < 0) 3001 return ret; 3002 3003 wol_config = ytphy_read_ext_with_lock(phydev, 3004 YTPHY_WOL_CONFIG_REG); 3005 if (wol_config < 0) 3006 return wol_config; 3007 3008 /* if wol enable, do nothing */ 3009 if (wol_config & YTPHY_WCR_ENABLE) 3010 return 0; 3011 3012 return yt8821_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); 3013 } 3014 3015 static struct phy_driver motorcomm_phy_drvs[] = { 3016 { 3017 PHY_ID_MATCH_EXACT(PHY_ID_YT8511), 3018 .name = "YT8511 Gigabit Ethernet", 3019 .config_init = yt8511_config_init, 3020 .suspend = genphy_suspend, 3021 .resume = genphy_resume, 3022 .read_page = yt8511_read_page, 3023 .write_page = yt8511_write_page, 3024 }, 3025 { 3026 PHY_ID_MATCH_EXACT(PHY_ID_YT8521), 3027 .name = "YT8521 Gigabit Ethernet", 3028 .get_features = yt8521_get_features, 3029 .probe = yt8521_probe, 3030 .read_page = yt8521_read_page, 3031 .write_page = yt8521_write_page, 3032 .get_wol = ytphy_get_wol, 3033 .set_wol = ytphy_set_wol, 3034 .config_aneg = yt8521_config_aneg, 3035 .aneg_done = yt8521_aneg_done, 3036 .config_init = yt8521_config_init, 3037 .read_status = yt8521_read_status, 3038 .soft_reset = yt8521_soft_reset, 3039 .suspend = yt8521_suspend, 3040 .resume = yt8521_resume, 3041 .led_hw_is_supported = yt8521_led_hw_is_supported, 3042 .led_hw_control_set = yt8521_led_hw_control_set, 3043 .led_hw_control_get = yt8521_led_hw_control_get, 3044 }, 3045 { 3046 PHY_ID_MATCH_EXACT(PHY_ID_YT8531), 3047 .name = "YT8531 Gigabit Ethernet", 3048 .probe = yt8531_probe, 3049 .config_init = yt8531_config_init, 3050 .suspend = genphy_suspend, 3051 .resume = genphy_resume, 3052 .get_wol = ytphy_get_wol, 3053 .set_wol = yt8531_set_wol, 3054 .link_change_notify = yt8531_link_change_notify, 3055 .led_hw_is_supported = yt8521_led_hw_is_supported, 3056 .led_hw_control_set = yt8521_led_hw_control_set, 3057 .led_hw_control_get = yt8521_led_hw_control_get, 3058 }, 3059 { 3060 PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), 3061 .name = "YT8531S Gigabit Ethernet", 3062 .get_features = yt8521_get_features, 3063 .probe = yt8521_probe, 3064 .read_page = yt8521_read_page, 3065 .write_page = yt8521_write_page, 3066 .get_wol = ytphy_get_wol, 3067 .set_wol = ytphy_set_wol, 3068 .config_aneg = yt8521_config_aneg, 3069 .aneg_done = yt8521_aneg_done, 3070 .config_init = yt8521_config_init, 3071 .read_status = yt8521_read_status, 3072 .soft_reset = yt8521_soft_reset, 3073 .suspend = yt8521_suspend, 3074 .resume = yt8521_resume, 3075 }, 3076 { 3077 PHY_ID_MATCH_EXACT(PHY_ID_YT8821), 3078 .name = "YT8821 2.5Gbps PHY", 3079 .get_features = yt8821_get_features, 3080 .read_page = yt8521_read_page, 3081 .write_page = yt8521_write_page, 3082 .get_wol = ytphy_get_wol, 3083 .set_wol = ytphy_set_wol, 3084 .config_aneg = genphy_config_aneg, 3085 .aneg_done = yt8821_aneg_done, 3086 .config_init = yt8821_config_init, 3087 .get_rate_matching = yt8821_get_rate_matching, 3088 .read_status = yt8821_read_status, 3089 .soft_reset = yt8821_soft_reset, 3090 .suspend = yt8821_suspend, 3091 .resume = yt8821_resume, 3092 }, 3093 }; 3094 3095 module_phy_driver(motorcomm_phy_drvs); 3096 3097 MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S/8821 PHY driver"); 3098 MODULE_AUTHOR("Peter Geis"); 3099 MODULE_AUTHOR("Frank"); 3100 MODULE_LICENSE("GPL"); 3101 3102 static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { 3103 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, 3104 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) }, 3105 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, 3106 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) }, 3107 { PHY_ID_MATCH_EXACT(PHY_ID_YT8821) }, 3108 { /* sentinel */ } 3109 }; 3110 3111 MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); 3112