1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // peb2466.c -- Infineon PEB2466 ALSA SoC driver 4 // 5 // Copyright 2023 CS GROUP France 6 // 7 // Author: Herve Codina <herve.codina@bootlin.com> 8 9 #include <linux/unaligned.h> 10 #include <linux/clk.h> 11 #include <linux/firmware.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/slab.h> 17 #include <linux/spi/spi.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 #include <sound/tlv.h> 21 22 #define PEB2466_NB_CHANNEL 4 23 24 struct peb2466_lookup { 25 u8 (*table)[4]; 26 unsigned int count; 27 }; 28 29 #define PEB2466_TLV_SIZE ARRAY_SIZE(((unsigned int[]){TLV_DB_SCALE_ITEM(0, 0, 0)})) 30 31 struct peb2466_lkup_ctrl { 32 int reg; 33 unsigned int index; 34 const struct peb2466_lookup *lookup; 35 unsigned int tlv_array[PEB2466_TLV_SIZE]; 36 }; 37 38 struct peb2466 { 39 struct spi_device *spi; 40 struct clk *mclk; 41 struct gpio_desc *reset_gpio; 42 u8 spi_tx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */ 43 u8 spi_rx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */ 44 struct regmap *regmap; 45 struct { 46 struct peb2466_lookup ax_lookup; 47 struct peb2466_lookup ar_lookup; 48 struct peb2466_lkup_ctrl ax_lkup_ctrl; 49 struct peb2466_lkup_ctrl ar_lkup_ctrl; 50 unsigned int tg1_freq_item; 51 unsigned int tg2_freq_item; 52 } ch[PEB2466_NB_CHANNEL]; 53 int max_chan_playback; 54 int max_chan_capture; 55 struct { 56 struct gpio_chip gpio_chip; 57 struct mutex lock; 58 struct { 59 unsigned int xr0; 60 unsigned int xr1; 61 unsigned int xr2; 62 unsigned int xr3; 63 } cache; 64 } gpio; 65 }; 66 67 #define PEB2466_CMD_R (1 << 5) 68 #define PEB2466_CMD_W (0 << 5) 69 70 #define PEB2466_CMD_MASK 0x18 71 #define PEB2466_CMD_XOP 0x18 /* XOP is 0bxxx11xxx */ 72 #define PEB2466_CMD_SOP 0x10 /* SOP is 0bxxx10xxx */ 73 #define PEB2466_CMD_COP 0x00 /* COP is 0bxxx0xxxx, handle 0bxxx00xxx */ 74 #define PEB2466_CMD_COP1 0x08 /* COP is 0bxxx0xxxx, handle 0bxxx01xxx */ 75 76 #define PEB2466_MAKE_XOP(_lsel) (PEB2466_CMD_XOP | (_lsel)) 77 #define PEB2466_MAKE_SOP(_ad, _lsel) (PEB2466_CMD_SOP | ((_ad) << 6) | (_lsel)) 78 #define PEB2466_MAKE_COP(_ad, _code) (PEB2466_CMD_COP | ((_ad) << 6) | (_code)) 79 80 #define PEB2466_CR0(_ch) PEB2466_MAKE_SOP(_ch, 0x0) 81 #define PEB2466_CR0_TH (1 << 7) 82 #define PEB2466_CR0_IMR1 (1 << 6) 83 #define PEB2466_CR0_FRX (1 << 5) 84 #define PEB2466_CR0_FRR (1 << 4) 85 #define PEB2466_CR0_AX (1 << 3) 86 #define PEB2466_CR0_AR (1 << 2) 87 #define PEB2466_CR0_THSEL_MASK (0x3 << 0) 88 #define PEB2466_CR0_THSEL(_set) ((_set) << 0) 89 90 #define PEB2466_CR1(_ch) PEB2466_MAKE_SOP(_ch, 0x1) 91 #define PEB2466_CR1_ETG2 (1 << 7) 92 #define PEB2466_CR1_ETG1 (1 << 6) 93 #define PEB2466_CR1_PTG2 (1 << 5) 94 #define PEB2466_CR1_PTG1 (1 << 4) 95 #define PEB2466_CR1_LAW_MASK (1 << 3) 96 #define PEB2466_CR1_LAW_ALAW (0 << 3) 97 #define PEB2466_CR1_LAW_MULAW (1 << 3) 98 #define PEB2466_CR1_PU (1 << 0) 99 100 #define PEB2466_CR2(_ch) PEB2466_MAKE_SOP(_ch, 0x2) 101 #define PEB2466_CR3(_ch) PEB2466_MAKE_SOP(_ch, 0x3) 102 #define PEB2466_CR4(_ch) PEB2466_MAKE_SOP(_ch, 0x4) 103 #define PEB2466_CR5(_ch) PEB2466_MAKE_SOP(_ch, 0x5) 104 105 #define PEB2466_XR0 PEB2466_MAKE_XOP(0x0) 106 #define PEB2466_XR1 PEB2466_MAKE_XOP(0x1) 107 #define PEB2466_XR2 PEB2466_MAKE_XOP(0x2) 108 #define PEB2466_XR3 PEB2466_MAKE_XOP(0x3) 109 #define PEB2466_XR4 PEB2466_MAKE_XOP(0x4) 110 #define PEB2466_XR5 PEB2466_MAKE_XOP(0x5) 111 #define PEB2466_XR5_MCLK_1536 (0x0 << 6) 112 #define PEB2466_XR5_MCLK_2048 (0x1 << 6) 113 #define PEB2466_XR5_MCLK_4096 (0x2 << 6) 114 #define PEB2466_XR5_MCLK_8192 (0x3 << 6) 115 116 #define PEB2466_XR6 PEB2466_MAKE_XOP(0x6) 117 #define PEB2466_XR6_PCM_OFFSET(_off) ((_off) << 0) 118 119 #define PEB2466_XR7 PEB2466_MAKE_XOP(0x7) 120 121 #define PEB2466_TH_FILTER_P1(_ch) PEB2466_MAKE_COP(_ch, 0x0) 122 #define PEB2466_TH_FILTER_P2(_ch) PEB2466_MAKE_COP(_ch, 0x1) 123 #define PEB2466_TH_FILTER_P3(_ch) PEB2466_MAKE_COP(_ch, 0x2) 124 #define PEB2466_IMR1_FILTER_P1(_ch) PEB2466_MAKE_COP(_ch, 0x4) 125 #define PEB2466_IMR1_FILTER_P2(_ch) PEB2466_MAKE_COP(_ch, 0x5) 126 #define PEB2466_FRX_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x6) 127 #define PEB2466_FRR_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x7) 128 #define PEB2466_AX_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x8) 129 #define PEB2466_AR_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x9) 130 #define PEB2466_TG1(_ch) PEB2466_MAKE_COP(_ch, 0xc) 131 #define PEB2466_TG2(_ch) PEB2466_MAKE_COP(_ch, 0xd) 132 133 static int peb2466_write_byte(struct peb2466 *peb2466, u8 cmd, u8 val) 134 { 135 struct spi_transfer xfer = { 136 .tx_buf = &peb2466->spi_tx_buf, 137 .len = 2, 138 }; 139 140 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W; 141 peb2466->spi_tx_buf[1] = val; 142 143 dev_dbg(&peb2466->spi->dev, "write byte (cmd %02x) %02x\n", 144 peb2466->spi_tx_buf[0], peb2466->spi_tx_buf[1]); 145 146 return spi_sync_transfer(peb2466->spi, &xfer, 1); 147 } 148 149 static int peb2466_read_byte(struct peb2466 *peb2466, u8 cmd, u8 *val) 150 { 151 struct spi_transfer xfer = { 152 .tx_buf = &peb2466->spi_tx_buf, 153 .rx_buf = &peb2466->spi_rx_buf, 154 .len = 3, 155 }; 156 int ret; 157 158 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_R; 159 160 ret = spi_sync_transfer(peb2466->spi, &xfer, 1); 161 if (ret) 162 return ret; 163 164 if (peb2466->spi_rx_buf[1] != 0x81) { 165 dev_err(&peb2466->spi->dev, 166 "spi xfer rd (cmd %02x) invalid ident byte (0x%02x)\n", 167 peb2466->spi_tx_buf[0], peb2466->spi_rx_buf[1]); 168 return -EILSEQ; 169 } 170 171 *val = peb2466->spi_rx_buf[2]; 172 173 dev_dbg(&peb2466->spi->dev, "read byte (cmd %02x) %02x\n", 174 peb2466->spi_tx_buf[0], *val); 175 176 return 0; 177 } 178 179 static int peb2466_write_buf(struct peb2466 *peb2466, u8 cmd, const u8 *buf, unsigned int len) 180 { 181 struct spi_transfer xfer = { 182 .tx_buf = &peb2466->spi_tx_buf, 183 .len = len + 1, 184 }; 185 186 if (len > 8) 187 return -EINVAL; 188 189 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W; 190 memcpy(&peb2466->spi_tx_buf[1], buf, len); 191 192 dev_dbg(&peb2466->spi->dev, "write buf (cmd %02x, %u) %*ph\n", 193 peb2466->spi_tx_buf[0], len, len, &peb2466->spi_tx_buf[1]); 194 195 return spi_sync_transfer(peb2466->spi, &xfer, 1); 196 } 197 198 static int peb2466_reg_write(void *context, unsigned int reg, unsigned int val) 199 { 200 struct peb2466 *peb2466 = context; 201 int ret; 202 203 /* 204 * Only XOP and SOP commands can be handled as registers. 205 * COP commands are handled using direct peb2466_write_buf() calls. 206 */ 207 switch (reg & PEB2466_CMD_MASK) { 208 case PEB2466_CMD_XOP: 209 case PEB2466_CMD_SOP: 210 ret = peb2466_write_byte(peb2466, reg, val); 211 break; 212 default: 213 dev_err(&peb2466->spi->dev, "Not a XOP or SOP command\n"); 214 ret = -EINVAL; 215 break; 216 } 217 return ret; 218 } 219 220 static int peb2466_reg_read(void *context, unsigned int reg, unsigned int *val) 221 { 222 struct peb2466 *peb2466 = context; 223 int ret; 224 u8 tmp; 225 226 /* Only XOP and SOP commands can be handled as registers */ 227 switch (reg & PEB2466_CMD_MASK) { 228 case PEB2466_CMD_XOP: 229 case PEB2466_CMD_SOP: 230 ret = peb2466_read_byte(peb2466, reg, &tmp); 231 if (!ret) 232 *val = tmp; 233 break; 234 default: 235 dev_err(&peb2466->spi->dev, "Not a XOP or SOP command\n"); 236 ret = -EINVAL; 237 break; 238 } 239 return ret; 240 } 241 242 static const struct regmap_config peb2466_regmap_config = { 243 .reg_bits = 8, 244 .val_bits = 8, 245 .max_register = 0xFF, 246 .reg_write = peb2466_reg_write, 247 .reg_read = peb2466_reg_read, 248 .cache_type = REGCACHE_NONE, 249 }; 250 251 static int peb2466_lkup_ctrl_info(struct snd_kcontrol *kcontrol, 252 struct snd_ctl_elem_info *uinfo) 253 { 254 struct peb2466_lkup_ctrl *lkup_ctrl = 255 (struct peb2466_lkup_ctrl *)kcontrol->private_value; 256 257 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 258 uinfo->count = 1; 259 uinfo->value.integer.min = 0; 260 uinfo->value.integer.max = lkup_ctrl->lookup->count - 1; 261 return 0; 262 } 263 264 static int peb2466_lkup_ctrl_get(struct snd_kcontrol *kcontrol, 265 struct snd_ctl_elem_value *ucontrol) 266 { 267 struct peb2466_lkup_ctrl *lkup_ctrl = 268 (struct peb2466_lkup_ctrl *)kcontrol->private_value; 269 270 ucontrol->value.integer.value[0] = lkup_ctrl->index; 271 return 0; 272 } 273 274 static int peb2466_lkup_ctrl_put(struct snd_kcontrol *kcontrol, 275 struct snd_ctl_elem_value *ucontrol) 276 { 277 struct peb2466_lkup_ctrl *lkup_ctrl = 278 (struct peb2466_lkup_ctrl *)kcontrol->private_value; 279 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 280 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 281 unsigned int index; 282 int ret; 283 284 index = ucontrol->value.integer.value[0]; 285 if (index >= lkup_ctrl->lookup->count) 286 return -EINVAL; 287 288 if (index == lkup_ctrl->index) 289 return 0; 290 291 ret = peb2466_write_buf(peb2466, lkup_ctrl->reg, 292 lkup_ctrl->lookup->table[index], 4); 293 if (ret) 294 return ret; 295 296 lkup_ctrl->index = index; 297 return 1; /* The value changed */ 298 } 299 300 static int peb2466_add_lkup_ctrl(struct snd_soc_component *component, 301 struct peb2466_lkup_ctrl *lkup_ctrl, 302 const char *name, int min_val, int step) 303 { 304 DECLARE_TLV_DB_SCALE(tlv_array, min_val, step, 0); 305 struct snd_kcontrol_new control = {0}; 306 307 BUILD_BUG_ON(sizeof(lkup_ctrl->tlv_array) < sizeof(tlv_array)); 308 memcpy(lkup_ctrl->tlv_array, tlv_array, sizeof(tlv_array)); 309 310 control.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 311 control.name = name; 312 control.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 313 SNDRV_CTL_ELEM_ACCESS_READWRITE; 314 control.tlv.p = lkup_ctrl->tlv_array; 315 control.info = peb2466_lkup_ctrl_info; 316 control.get = peb2466_lkup_ctrl_get; 317 control.put = peb2466_lkup_ctrl_put; 318 control.private_value = (unsigned long)lkup_ctrl; 319 320 return snd_soc_add_component_controls(component, &control, 1); 321 } 322 323 enum peb2466_tone_freq { 324 PEB2466_TONE_697HZ, 325 PEB2466_TONE_800HZ, 326 PEB2466_TONE_950HZ, 327 PEB2466_TONE_1000HZ, 328 PEB2466_TONE_1008HZ, 329 PEB2466_TONE_2000HZ, 330 }; 331 332 static const u8 peb2466_tone_lookup[][4] = { 333 [PEB2466_TONE_697HZ] = {0x0a, 0x33, 0x5a, 0x2c}, 334 [PEB2466_TONE_800HZ] = {0x12, 0xD6, 0x5a, 0xc0}, 335 [PEB2466_TONE_950HZ] = {0x1c, 0xf0, 0x5c, 0xc0}, 336 [PEB2466_TONE_1000HZ] = {0}, /* lookup value not used for 1000Hz */ 337 [PEB2466_TONE_1008HZ] = {0x1a, 0xae, 0x57, 0x70}, 338 [PEB2466_TONE_2000HZ] = {0x00, 0x80, 0x50, 0x09}, 339 }; 340 341 static const char * const peb2466_tone_freq_txt[] = { 342 [PEB2466_TONE_697HZ] = "697Hz", 343 [PEB2466_TONE_800HZ] = "800Hz", 344 [PEB2466_TONE_950HZ] = "950Hz", 345 [PEB2466_TONE_1000HZ] = "1000Hz", 346 [PEB2466_TONE_1008HZ] = "1008Hz", 347 [PEB2466_TONE_2000HZ] = "2000Hz" 348 }; 349 350 static const struct soc_enum peb2466_tg_freq[][2] = { 351 [0] = { 352 SOC_ENUM_SINGLE(PEB2466_TG1(0), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 353 peb2466_tone_freq_txt), 354 SOC_ENUM_SINGLE(PEB2466_TG2(0), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 355 peb2466_tone_freq_txt) 356 }, 357 [1] = { 358 SOC_ENUM_SINGLE(PEB2466_TG1(1), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 359 peb2466_tone_freq_txt), 360 SOC_ENUM_SINGLE(PEB2466_TG2(1), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 361 peb2466_tone_freq_txt) 362 }, 363 [2] = { 364 SOC_ENUM_SINGLE(PEB2466_TG1(2), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 365 peb2466_tone_freq_txt), 366 SOC_ENUM_SINGLE(PEB2466_TG2(2), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 367 peb2466_tone_freq_txt) 368 }, 369 [3] = { 370 SOC_ENUM_SINGLE(PEB2466_TG1(3), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 371 peb2466_tone_freq_txt), 372 SOC_ENUM_SINGLE(PEB2466_TG2(3), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 373 peb2466_tone_freq_txt) 374 } 375 }; 376 377 static int peb2466_tg_freq_get(struct snd_kcontrol *kcontrol, 378 struct snd_ctl_elem_value *ucontrol) 379 { 380 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 381 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 382 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 383 384 switch (e->reg) { 385 case PEB2466_TG1(0): 386 ucontrol->value.enumerated.item[0] = peb2466->ch[0].tg1_freq_item; 387 break; 388 case PEB2466_TG2(0): 389 ucontrol->value.enumerated.item[0] = peb2466->ch[0].tg2_freq_item; 390 break; 391 case PEB2466_TG1(1): 392 ucontrol->value.enumerated.item[0] = peb2466->ch[1].tg1_freq_item; 393 break; 394 case PEB2466_TG2(1): 395 ucontrol->value.enumerated.item[0] = peb2466->ch[1].tg2_freq_item; 396 break; 397 case PEB2466_TG1(2): 398 ucontrol->value.enumerated.item[0] = peb2466->ch[2].tg1_freq_item; 399 break; 400 case PEB2466_TG2(2): 401 ucontrol->value.enumerated.item[0] = peb2466->ch[2].tg2_freq_item; 402 break; 403 case PEB2466_TG1(3): 404 ucontrol->value.enumerated.item[0] = peb2466->ch[3].tg1_freq_item; 405 break; 406 case PEB2466_TG2(3): 407 ucontrol->value.enumerated.item[0] = peb2466->ch[3].tg2_freq_item; 408 break; 409 default: 410 return -EINVAL; 411 } 412 return 0; 413 } 414 415 static int peb2466_tg_freq_put(struct snd_kcontrol *kcontrol, 416 struct snd_ctl_elem_value *ucontrol) 417 { 418 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 419 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 420 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 421 unsigned int *tg_freq_item; 422 u8 cr1_reg, cr1_mask; 423 unsigned int index; 424 int ret; 425 426 index = ucontrol->value.enumerated.item[0]; 427 428 if (index >= ARRAY_SIZE(peb2466_tone_lookup)) 429 return -EINVAL; 430 431 switch (e->reg) { 432 case PEB2466_TG1(0): 433 tg_freq_item = &peb2466->ch[0].tg1_freq_item; 434 cr1_reg = PEB2466_CR1(0); 435 cr1_mask = PEB2466_CR1_PTG1; 436 break; 437 case PEB2466_TG2(0): 438 tg_freq_item = &peb2466->ch[0].tg2_freq_item; 439 cr1_reg = PEB2466_CR1(0); 440 cr1_mask = PEB2466_CR1_PTG2; 441 break; 442 case PEB2466_TG1(1): 443 tg_freq_item = &peb2466->ch[1].tg1_freq_item; 444 cr1_reg = PEB2466_CR1(1); 445 cr1_mask = PEB2466_CR1_PTG1; 446 break; 447 case PEB2466_TG2(1): 448 tg_freq_item = &peb2466->ch[1].tg2_freq_item; 449 cr1_reg = PEB2466_CR1(1); 450 cr1_mask = PEB2466_CR1_PTG2; 451 break; 452 case PEB2466_TG1(2): 453 tg_freq_item = &peb2466->ch[2].tg1_freq_item; 454 cr1_reg = PEB2466_CR1(2); 455 cr1_mask = PEB2466_CR1_PTG1; 456 break; 457 case PEB2466_TG2(2): 458 tg_freq_item = &peb2466->ch[2].tg2_freq_item; 459 cr1_reg = PEB2466_CR1(2); 460 cr1_mask = PEB2466_CR1_PTG2; 461 break; 462 case PEB2466_TG1(3): 463 tg_freq_item = &peb2466->ch[3].tg1_freq_item; 464 cr1_reg = PEB2466_CR1(3); 465 cr1_mask = PEB2466_CR1_PTG1; 466 break; 467 case PEB2466_TG2(3): 468 tg_freq_item = &peb2466->ch[3].tg2_freq_item; 469 cr1_reg = PEB2466_CR1(3); 470 cr1_mask = PEB2466_CR1_PTG2; 471 break; 472 default: 473 return -EINVAL; 474 } 475 476 if (index == *tg_freq_item) 477 return 0; 478 479 if (index == PEB2466_TONE_1000HZ) { 480 ret = regmap_update_bits(peb2466->regmap, cr1_reg, cr1_mask, 0); 481 if (ret) 482 return ret; 483 } else { 484 ret = peb2466_write_buf(peb2466, e->reg, peb2466_tone_lookup[index], 4); 485 if (ret) 486 return ret; 487 ret = regmap_update_bits(peb2466->regmap, cr1_reg, cr1_mask, cr1_mask); 488 if (ret) 489 return ret; 490 } 491 492 *tg_freq_item = index; 493 return 1; /* The value changed */ 494 } 495 496 static const struct snd_kcontrol_new peb2466_ch0_out_mix_controls[] = { 497 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(0), 6, 1, 0), 498 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(0), 7, 1, 0), 499 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(0), 0, 1, 0) 500 }; 501 502 static const struct snd_kcontrol_new peb2466_ch1_out_mix_controls[] = { 503 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(1), 6, 1, 0), 504 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(1), 7, 1, 0), 505 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(1), 0, 1, 0) 506 }; 507 508 static const struct snd_kcontrol_new peb2466_ch2_out_mix_controls[] = { 509 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(2), 6, 1, 0), 510 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(2), 7, 1, 0), 511 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(2), 0, 1, 0) 512 }; 513 514 static const struct snd_kcontrol_new peb2466_ch3_out_mix_controls[] = { 515 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(3), 6, 1, 0), 516 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(3), 7, 1, 0), 517 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(3), 0, 1, 0) 518 }; 519 520 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(peb2466_gain_p_tlv, -600, 0); 521 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(peb2466_gain_c_tlv, 0, 600); 522 523 static const struct snd_kcontrol_new peb2466_controls[] = { 524 /* Attenuators */ 525 SOC_SINGLE_TLV("DAC0 -6dB Playback Volume", PEB2466_CR3(0), 2, 1, 1, peb2466_gain_p_tlv), 526 SOC_SINGLE_TLV("DAC1 -6dB Playback Volume", PEB2466_CR3(1), 2, 1, 1, peb2466_gain_p_tlv), 527 SOC_SINGLE_TLV("DAC2 -6dB Playback Volume", PEB2466_CR3(2), 2, 1, 1, peb2466_gain_p_tlv), 528 SOC_SINGLE_TLV("DAC3 -6dB Playback Volume", PEB2466_CR3(3), 2, 1, 1, peb2466_gain_p_tlv), 529 530 /* Amplifiers */ 531 SOC_SINGLE_TLV("ADC0 +6dB Capture Volume", PEB2466_CR3(0), 3, 1, 0, peb2466_gain_c_tlv), 532 SOC_SINGLE_TLV("ADC1 +6dB Capture Volume", PEB2466_CR3(1), 3, 1, 0, peb2466_gain_c_tlv), 533 SOC_SINGLE_TLV("ADC2 +6dB Capture Volume", PEB2466_CR3(2), 3, 1, 0, peb2466_gain_c_tlv), 534 SOC_SINGLE_TLV("ADC3 +6dB Capture Volume", PEB2466_CR3(3), 3, 1, 0, peb2466_gain_c_tlv), 535 536 /* Tone generators */ 537 SOC_ENUM_EXT("DAC0 TG1 Freq", peb2466_tg_freq[0][0], 538 peb2466_tg_freq_get, peb2466_tg_freq_put), 539 SOC_ENUM_EXT("DAC1 TG1 Freq", peb2466_tg_freq[1][0], 540 peb2466_tg_freq_get, peb2466_tg_freq_put), 541 SOC_ENUM_EXT("DAC2 TG1 Freq", peb2466_tg_freq[2][0], 542 peb2466_tg_freq_get, peb2466_tg_freq_put), 543 SOC_ENUM_EXT("DAC3 TG1 Freq", peb2466_tg_freq[3][0], 544 peb2466_tg_freq_get, peb2466_tg_freq_put), 545 546 SOC_ENUM_EXT("DAC0 TG2 Freq", peb2466_tg_freq[0][1], 547 peb2466_tg_freq_get, peb2466_tg_freq_put), 548 SOC_ENUM_EXT("DAC1 TG2 Freq", peb2466_tg_freq[1][1], 549 peb2466_tg_freq_get, peb2466_tg_freq_put), 550 SOC_ENUM_EXT("DAC2 TG2 Freq", peb2466_tg_freq[2][1], 551 peb2466_tg_freq_get, peb2466_tg_freq_put), 552 SOC_ENUM_EXT("DAC3 TG2 Freq", peb2466_tg_freq[3][1], 553 peb2466_tg_freq_get, peb2466_tg_freq_put), 554 }; 555 556 static const struct snd_soc_dapm_widget peb2466_dapm_widgets[] = { 557 SND_SOC_DAPM_SUPPLY("CH0 PWR", PEB2466_CR1(0), 0, 0, NULL, 0), 558 SND_SOC_DAPM_SUPPLY("CH1 PWR", PEB2466_CR1(1), 0, 0, NULL, 0), 559 SND_SOC_DAPM_SUPPLY("CH2 PWR", PEB2466_CR1(2), 0, 0, NULL, 0), 560 SND_SOC_DAPM_SUPPLY("CH3 PWR", PEB2466_CR1(3), 0, 0, NULL, 0), 561 562 SND_SOC_DAPM_DAC("CH0 DIN", "Playback", SND_SOC_NOPM, 0, 0), 563 SND_SOC_DAPM_DAC("CH1 DIN", "Playback", SND_SOC_NOPM, 0, 0), 564 SND_SOC_DAPM_DAC("CH2 DIN", "Playback", SND_SOC_NOPM, 0, 0), 565 SND_SOC_DAPM_DAC("CH3 DIN", "Playback", SND_SOC_NOPM, 0, 0), 566 567 SND_SOC_DAPM_SIGGEN("CH0 TG1"), 568 SND_SOC_DAPM_SIGGEN("CH1 TG1"), 569 SND_SOC_DAPM_SIGGEN("CH2 TG1"), 570 SND_SOC_DAPM_SIGGEN("CH3 TG1"), 571 572 SND_SOC_DAPM_SIGGEN("CH0 TG2"), 573 SND_SOC_DAPM_SIGGEN("CH1 TG2"), 574 SND_SOC_DAPM_SIGGEN("CH2 TG2"), 575 SND_SOC_DAPM_SIGGEN("CH3 TG2"), 576 577 SND_SOC_DAPM_MIXER("DAC0 Mixer", SND_SOC_NOPM, 0, 0, 578 peb2466_ch0_out_mix_controls, 579 ARRAY_SIZE(peb2466_ch0_out_mix_controls)), 580 SND_SOC_DAPM_MIXER("DAC1 Mixer", SND_SOC_NOPM, 0, 0, 581 peb2466_ch1_out_mix_controls, 582 ARRAY_SIZE(peb2466_ch1_out_mix_controls)), 583 SND_SOC_DAPM_MIXER("DAC2 Mixer", SND_SOC_NOPM, 0, 0, 584 peb2466_ch2_out_mix_controls, 585 ARRAY_SIZE(peb2466_ch2_out_mix_controls)), 586 SND_SOC_DAPM_MIXER("DAC3 Mixer", SND_SOC_NOPM, 0, 0, 587 peb2466_ch3_out_mix_controls, 588 ARRAY_SIZE(peb2466_ch3_out_mix_controls)), 589 590 SND_SOC_DAPM_PGA("DAC0 PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 591 SND_SOC_DAPM_PGA("DAC1 PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 592 SND_SOC_DAPM_PGA("DAC2 PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 593 SND_SOC_DAPM_PGA("DAC3 PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 594 595 SND_SOC_DAPM_OUTPUT("OUT0"), 596 SND_SOC_DAPM_OUTPUT("OUT1"), 597 SND_SOC_DAPM_OUTPUT("OUT2"), 598 SND_SOC_DAPM_OUTPUT("OUT3"), 599 600 SND_SOC_DAPM_INPUT("IN0"), 601 SND_SOC_DAPM_INPUT("IN1"), 602 SND_SOC_DAPM_INPUT("IN2"), 603 SND_SOC_DAPM_INPUT("IN3"), 604 605 SND_SOC_DAPM_DAC("ADC0", "Capture", SND_SOC_NOPM, 0, 0), 606 SND_SOC_DAPM_DAC("ADC1", "Capture", SND_SOC_NOPM, 0, 0), 607 SND_SOC_DAPM_DAC("ADC2", "Capture", SND_SOC_NOPM, 0, 0), 608 SND_SOC_DAPM_DAC("ADC3", "Capture", SND_SOC_NOPM, 0, 0), 609 }; 610 611 static const struct snd_soc_dapm_route peb2466_dapm_routes[] = { 612 { "CH0 DIN", NULL, "CH0 PWR" }, 613 { "CH1 DIN", NULL, "CH1 PWR" }, 614 { "CH2 DIN", NULL, "CH2 PWR" }, 615 { "CH3 DIN", NULL, "CH3 PWR" }, 616 617 { "CH0 TG1", NULL, "CH0 PWR" }, 618 { "CH1 TG1", NULL, "CH1 PWR" }, 619 { "CH2 TG1", NULL, "CH2 PWR" }, 620 { "CH3 TG1", NULL, "CH3 PWR" }, 621 622 { "CH0 TG2", NULL, "CH0 PWR" }, 623 { "CH1 TG2", NULL, "CH1 PWR" }, 624 { "CH2 TG2", NULL, "CH2 PWR" }, 625 { "CH3 TG2", NULL, "CH3 PWR" }, 626 627 { "DAC0 Mixer", "TG1 Switch", "CH0 TG1" }, 628 { "DAC0 Mixer", "TG2 Switch", "CH0 TG2" }, 629 { "DAC0 Mixer", "Voice Switch", "CH0 DIN" }, 630 { "DAC0 Mixer", NULL, "CH0 DIN" }, 631 632 { "DAC1 Mixer", "TG1 Switch", "CH1 TG1" }, 633 { "DAC1 Mixer", "TG2 Switch", "CH1 TG2" }, 634 { "DAC1 Mixer", "Voice Switch", "CH1 DIN" }, 635 { "DAC1 Mixer", NULL, "CH1 DIN" }, 636 637 { "DAC2 Mixer", "TG1 Switch", "CH2 TG1" }, 638 { "DAC2 Mixer", "TG2 Switch", "CH2 TG2" }, 639 { "DAC2 Mixer", "Voice Switch", "CH2 DIN" }, 640 { "DAC2 Mixer", NULL, "CH2 DIN" }, 641 642 { "DAC3 Mixer", "TG1 Switch", "CH3 TG1" }, 643 { "DAC3 Mixer", "TG2 Switch", "CH3 TG2" }, 644 { "DAC3 Mixer", "Voice Switch", "CH3 DIN" }, 645 { "DAC3 Mixer", NULL, "CH3 DIN" }, 646 647 { "DAC0 PGA", NULL, "DAC0 Mixer" }, 648 { "DAC1 PGA", NULL, "DAC1 Mixer" }, 649 { "DAC2 PGA", NULL, "DAC2 Mixer" }, 650 { "DAC3 PGA", NULL, "DAC3 Mixer" }, 651 652 { "OUT0", NULL, "DAC0 PGA" }, 653 { "OUT1", NULL, "DAC1 PGA" }, 654 { "OUT2", NULL, "DAC2 PGA" }, 655 { "OUT3", NULL, "DAC3 PGA" }, 656 657 { "ADC0", NULL, "IN0" }, 658 { "ADC1", NULL, "IN1" }, 659 { "ADC2", NULL, "IN2" }, 660 { "ADC3", NULL, "IN3" }, 661 662 { "ADC0", NULL, "CH0 PWR" }, 663 { "ADC1", NULL, "CH1 PWR" }, 664 { "ADC2", NULL, "CH2 PWR" }, 665 { "ADC3", NULL, "CH3 PWR" }, 666 }; 667 668 static int peb2466_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 669 unsigned int rx_mask, int slots, int width) 670 { 671 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component); 672 unsigned int chan; 673 unsigned int mask; 674 u8 slot; 675 int ret; 676 677 switch (width) { 678 case 0: 679 /* Not set -> default 8 */ 680 case 8: 681 break; 682 default: 683 dev_err(dai->dev, "tdm slot width %d not supported\n", width); 684 return -EINVAL; 685 } 686 687 mask = tx_mask; 688 slot = 0; 689 chan = 0; 690 while (mask && chan < PEB2466_NB_CHANNEL) { 691 if (mask & 0x1) { 692 ret = regmap_write(peb2466->regmap, PEB2466_CR5(chan), slot); 693 if (ret) { 694 dev_err(dai->dev, "chan %d set tx tdm slot failed (%d)\n", 695 chan, ret); 696 return ret; 697 } 698 chan++; 699 } 700 mask >>= 1; 701 slot++; 702 } 703 if (mask) { 704 dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n", 705 tx_mask, PEB2466_NB_CHANNEL); 706 return -EINVAL; 707 } 708 peb2466->max_chan_playback = chan; 709 710 mask = rx_mask; 711 slot = 0; 712 chan = 0; 713 while (mask && chan < PEB2466_NB_CHANNEL) { 714 if (mask & 0x1) { 715 ret = regmap_write(peb2466->regmap, PEB2466_CR4(chan), slot); 716 if (ret) { 717 dev_err(dai->dev, "chan %d set rx tdm slot failed (%d)\n", 718 chan, ret); 719 return ret; 720 } 721 chan++; 722 } 723 mask >>= 1; 724 slot++; 725 } 726 if (mask) { 727 dev_err(dai->dev, "too much rx slots defined (mask = 0x%x) support max %d\n", 728 rx_mask, PEB2466_NB_CHANNEL); 729 return -EINVAL; 730 } 731 peb2466->max_chan_capture = chan; 732 733 return 0; 734 } 735 736 static int peb2466_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 737 { 738 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component); 739 u8 xr6; 740 741 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 742 case SND_SOC_DAIFMT_DSP_A: 743 xr6 = PEB2466_XR6_PCM_OFFSET(1); 744 break; 745 case SND_SOC_DAIFMT_DSP_B: 746 xr6 = PEB2466_XR6_PCM_OFFSET(0); 747 break; 748 default: 749 dev_err(dai->dev, "Unsupported format 0x%x\n", 750 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 751 return -EINVAL; 752 } 753 return regmap_write(peb2466->regmap, PEB2466_XR6, xr6); 754 } 755 756 static int peb2466_dai_hw_params(struct snd_pcm_substream *substream, 757 struct snd_pcm_hw_params *params, 758 struct snd_soc_dai *dai) 759 { 760 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component); 761 unsigned int ch; 762 int ret; 763 u8 cr1; 764 765 switch (params_format(params)) { 766 case SNDRV_PCM_FORMAT_MU_LAW: 767 cr1 = PEB2466_CR1_LAW_MULAW; 768 break; 769 case SNDRV_PCM_FORMAT_A_LAW: 770 cr1 = PEB2466_CR1_LAW_ALAW; 771 break; 772 default: 773 dev_err(&peb2466->spi->dev, "Unsupported format 0x%x\n", 774 params_format(params)); 775 return -EINVAL; 776 } 777 778 for (ch = 0; ch < PEB2466_NB_CHANNEL; ch++) { 779 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR1(ch), 780 PEB2466_CR1_LAW_MASK, cr1); 781 if (ret) 782 return ret; 783 } 784 785 return 0; 786 } 787 788 static const unsigned int peb2466_sample_bits[] = {8}; 789 790 static struct snd_pcm_hw_constraint_list peb2466_sample_bits_constr = { 791 .list = peb2466_sample_bits, 792 .count = ARRAY_SIZE(peb2466_sample_bits), 793 }; 794 795 static int peb2466_dai_startup(struct snd_pcm_substream *substream, 796 struct snd_soc_dai *dai) 797 { 798 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component); 799 unsigned int max_ch; 800 int ret; 801 802 max_ch = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 803 peb2466->max_chan_playback : peb2466->max_chan_capture; 804 805 /* 806 * Disable stream support (min = 0, max = 0) if no timeslots were 807 * configured. 808 */ 809 ret = snd_pcm_hw_constraint_minmax(substream->runtime, 810 SNDRV_PCM_HW_PARAM_CHANNELS, 811 max_ch ? 1 : 0, max_ch); 812 if (ret < 0) 813 return ret; 814 815 return snd_pcm_hw_constraint_list(substream->runtime, 0, 816 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 817 &peb2466_sample_bits_constr); 818 } 819 820 static const u64 peb2466_dai_formats = 821 SND_SOC_POSSIBLE_DAIFMT_DSP_A | 822 SND_SOC_POSSIBLE_DAIFMT_DSP_B; 823 824 static const struct snd_soc_dai_ops peb2466_dai_ops = { 825 .startup = peb2466_dai_startup, 826 .hw_params = peb2466_dai_hw_params, 827 .set_tdm_slot = peb2466_dai_set_tdm_slot, 828 .set_fmt = peb2466_dai_set_fmt, 829 .auto_selectable_formats = &peb2466_dai_formats, 830 .num_auto_selectable_formats = 1, 831 }; 832 833 static struct snd_soc_dai_driver peb2466_dai_driver = { 834 .name = "peb2466", 835 .playback = { 836 .stream_name = "Playback", 837 .channels_min = 1, 838 .channels_max = PEB2466_NB_CHANNEL, 839 .rates = SNDRV_PCM_RATE_8000, 840 .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, 841 }, 842 .capture = { 843 .stream_name = "Capture", 844 .channels_min = 1, 845 .channels_max = PEB2466_NB_CHANNEL, 846 .rates = SNDRV_PCM_RATE_8000, 847 .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, 848 }, 849 .ops = &peb2466_dai_ops, 850 }; 851 852 static int peb2466_reset_audio(struct peb2466 *peb2466) 853 { 854 static const struct reg_sequence reg_reset[] = { 855 { .reg = PEB2466_XR6, .def = 0x00 }, 856 857 { .reg = PEB2466_CR5(0), .def = 0x00 }, 858 { .reg = PEB2466_CR4(0), .def = 0x00 }, 859 { .reg = PEB2466_CR3(0), .def = 0x00 }, 860 { .reg = PEB2466_CR2(0), .def = 0x00 }, 861 { .reg = PEB2466_CR1(0), .def = 0x00 }, 862 { .reg = PEB2466_CR0(0), .def = PEB2466_CR0_IMR1 }, 863 864 { .reg = PEB2466_CR5(1), .def = 0x00 }, 865 { .reg = PEB2466_CR4(1), .def = 0x00 }, 866 { .reg = PEB2466_CR3(1), .def = 0x00 }, 867 { .reg = PEB2466_CR2(1), .def = 0x00 }, 868 { .reg = PEB2466_CR1(1), .def = 0x00 }, 869 { .reg = PEB2466_CR0(1), .def = PEB2466_CR0_IMR1 }, 870 871 { .reg = PEB2466_CR5(2), .def = 0x00 }, 872 { .reg = PEB2466_CR4(2), .def = 0x00 }, 873 { .reg = PEB2466_CR3(2), .def = 0x00 }, 874 { .reg = PEB2466_CR2(2), .def = 0x00 }, 875 { .reg = PEB2466_CR1(2), .def = 0x00 }, 876 { .reg = PEB2466_CR0(2), .def = PEB2466_CR0_IMR1 }, 877 878 { .reg = PEB2466_CR5(3), .def = 0x00 }, 879 { .reg = PEB2466_CR4(3), .def = 0x00 }, 880 { .reg = PEB2466_CR3(3), .def = 0x00 }, 881 { .reg = PEB2466_CR2(3), .def = 0x00 }, 882 { .reg = PEB2466_CR1(3), .def = 0x00 }, 883 { .reg = PEB2466_CR0(3), .def = PEB2466_CR0_IMR1 }, 884 }; 885 static const u8 imr1_p1[8] = {0x00, 0x90, 0x09, 0x00, 0x90, 0x09, 0x00, 0x00}; 886 static const u8 imr1_p2[8] = {0x7F, 0xFF, 0x00, 0x00, 0x90, 0x14, 0x40, 0x08}; 887 static const u8 zero[8] = {0}; 888 int ret; 889 int i; 890 891 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 892 peb2466->ch[i].tg1_freq_item = PEB2466_TONE_1000HZ; 893 peb2466->ch[i].tg2_freq_item = PEB2466_TONE_1000HZ; 894 895 /* 896 * Even if not used, disabling IM/R1 filter is not recommended. 897 * Instead, we must configure it with default coefficients and 898 * enable it. 899 * The filter will be enabled right after (in the following 900 * regmap_multi_reg_write() call). 901 */ 902 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P1(i), imr1_p1, 8); 903 if (ret) 904 return ret; 905 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P2(i), imr1_p2, 8); 906 if (ret) 907 return ret; 908 909 /* Set all other filters coefficients to zero */ 910 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P1(i), zero, 8); 911 if (ret) 912 return ret; 913 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P2(i), zero, 8); 914 if (ret) 915 return ret; 916 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P3(i), zero, 8); 917 if (ret) 918 return ret; 919 ret = peb2466_write_buf(peb2466, PEB2466_FRX_FILTER(i), zero, 8); 920 if (ret) 921 return ret; 922 ret = peb2466_write_buf(peb2466, PEB2466_FRR_FILTER(i), zero, 8); 923 if (ret) 924 return ret; 925 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), zero, 4); 926 if (ret) 927 return ret; 928 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), zero, 4); 929 if (ret) 930 return ret; 931 } 932 933 return regmap_multi_reg_write(peb2466->regmap, reg_reset, ARRAY_SIZE(reg_reset)); 934 } 935 936 static int peb2466_fw_parse_thfilter(struct snd_soc_component *component, 937 u16 tag, u32 lng, const u8 *data) 938 { 939 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 940 u8 mask; 941 int ret; 942 int i; 943 944 dev_info(component->dev, "fw TH filter: mask %x, %*phN\n", *data, 945 lng - 1, data + 1); 946 947 /* 948 * TH_FILTER TLV data: 949 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 950 * - @1 8 bytes: TH-Filter coefficients part1 951 * - @9 8 bytes: TH-Filter coefficients part2 952 * - @17 8 bytes: TH-Filter coefficients part3 953 */ 954 mask = *data; 955 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 956 if (!(mask & (1 << i))) 957 continue; 958 959 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 960 PEB2466_CR0_TH, 0); 961 if (ret) 962 return ret; 963 964 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P1(i), data + 1, 8); 965 if (ret) 966 return ret; 967 968 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P2(i), data + 9, 8); 969 if (ret) 970 return ret; 971 972 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P3(i), data + 17, 8); 973 if (ret) 974 return ret; 975 976 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 977 PEB2466_CR0_TH | PEB2466_CR0_THSEL_MASK, 978 PEB2466_CR0_TH | PEB2466_CR0_THSEL(i)); 979 if (ret) 980 return ret; 981 } 982 return 0; 983 } 984 985 static int peb2466_fw_parse_imr1filter(struct snd_soc_component *component, 986 u16 tag, u32 lng, const u8 *data) 987 { 988 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 989 u8 mask; 990 int ret; 991 int i; 992 993 dev_info(component->dev, "fw IM/R1 filter: mask %x, %*phN\n", *data, 994 lng - 1, data + 1); 995 996 /* 997 * IMR1_FILTER TLV data: 998 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 999 * - @1 8 bytes: IM/R1-Filter coefficients part1 1000 * - @9 8 bytes: IM/R1-Filter coefficients part2 1001 */ 1002 mask = *data; 1003 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1004 if (!(mask & (1 << i))) 1005 continue; 1006 1007 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1008 PEB2466_CR0_IMR1, 0); 1009 if (ret) 1010 return ret; 1011 1012 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P1(i), data + 1, 8); 1013 if (ret) 1014 return ret; 1015 1016 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P2(i), data + 9, 8); 1017 if (ret) 1018 return ret; 1019 1020 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1021 PEB2466_CR0_IMR1, PEB2466_CR0_IMR1); 1022 if (ret) 1023 return ret; 1024 } 1025 return 0; 1026 } 1027 1028 static int peb2466_fw_parse_frxfilter(struct snd_soc_component *component, 1029 u16 tag, u32 lng, const u8 *data) 1030 { 1031 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1032 u8 mask; 1033 int ret; 1034 int i; 1035 1036 dev_info(component->dev, "fw FRX filter: mask %x, %*phN\n", *data, 1037 lng - 1, data + 1); 1038 1039 /* 1040 * FRX_FILTER TLV data: 1041 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1042 * - @1 8 bytes: FRX-Filter coefficients 1043 */ 1044 mask = *data; 1045 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1046 if (!(mask & (1 << i))) 1047 continue; 1048 1049 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1050 PEB2466_CR0_FRX, 0); 1051 if (ret) 1052 return ret; 1053 1054 ret = peb2466_write_buf(peb2466, PEB2466_FRX_FILTER(i), data + 1, 8); 1055 if (ret) 1056 return ret; 1057 1058 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1059 PEB2466_CR0_FRX, PEB2466_CR0_FRX); 1060 if (ret) 1061 return ret; 1062 } 1063 return 0; 1064 } 1065 1066 static int peb2466_fw_parse_frrfilter(struct snd_soc_component *component, 1067 u16 tag, u32 lng, const u8 *data) 1068 { 1069 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1070 u8 mask; 1071 int ret; 1072 int i; 1073 1074 dev_info(component->dev, "fw FRR filter: mask %x, %*phN\n", *data, 1075 lng - 1, data + 1); 1076 1077 /* 1078 * FRR_FILTER TLV data: 1079 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1080 * - @1 8 bytes: FRR-Filter coefficients 1081 */ 1082 mask = *data; 1083 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1084 if (!(mask & (1 << i))) 1085 continue; 1086 1087 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1088 PEB2466_CR0_FRR, 0); 1089 if (ret) 1090 return ret; 1091 1092 ret = peb2466_write_buf(peb2466, PEB2466_FRR_FILTER(i), data + 1, 8); 1093 if (ret) 1094 return ret; 1095 1096 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1097 PEB2466_CR0_FRR, PEB2466_CR0_FRR); 1098 if (ret) 1099 return ret; 1100 } 1101 return 0; 1102 } 1103 1104 static int peb2466_fw_parse_axfilter(struct snd_soc_component *component, 1105 u16 tag, u32 lng, const u8 *data) 1106 { 1107 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1108 u8 mask; 1109 int ret; 1110 int i; 1111 1112 dev_info(component->dev, "fw AX filter: mask %x, %*phN\n", *data, 1113 lng - 1, data + 1); 1114 1115 /* 1116 * AX_FILTER TLV data: 1117 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1118 * - @1 4 bytes: AX-Filter coefficients 1119 */ 1120 mask = *data; 1121 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1122 if (!(mask & (1 << i))) 1123 continue; 1124 1125 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1126 PEB2466_CR0_AX, 0); 1127 if (ret) 1128 return ret; 1129 1130 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), data + 1, 4); 1131 if (ret) 1132 return ret; 1133 1134 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1135 PEB2466_CR0_AX, PEB2466_CR0_AX); 1136 if (ret) 1137 return ret; 1138 } 1139 return 0; 1140 } 1141 1142 static int peb2466_fw_parse_arfilter(struct snd_soc_component *component, 1143 u16 tag, u32 lng, const u8 *data) 1144 { 1145 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1146 u8 mask; 1147 int ret; 1148 int i; 1149 1150 dev_info(component->dev, "fw AR filter: mask %x, %*phN\n", *data, 1151 lng - 1, data + 1); 1152 1153 /* 1154 * AR_FILTER TLV data: 1155 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1156 * - @1 4 bytes: AR-Filter coefficients 1157 */ 1158 mask = *data; 1159 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1160 if (!(mask & (1 << i))) 1161 continue; 1162 1163 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1164 PEB2466_CR0_AR, 0); 1165 if (ret) 1166 return ret; 1167 1168 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), data + 1, 4); 1169 if (ret) 1170 return ret; 1171 1172 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1173 PEB2466_CR0_AR, PEB2466_CR0_AR); 1174 if (ret) 1175 return ret; 1176 } 1177 return 0; 1178 } 1179 1180 static const char * const peb2466_ax_ctrl_names[] = { 1181 "ADC0 Capture Volume", 1182 "ADC1 Capture Volume", 1183 "ADC2 Capture Volume", 1184 "ADC3 Capture Volume", 1185 }; 1186 1187 static int peb2466_fw_parse_axtable(struct snd_soc_component *component, 1188 u16 tag, u32 lng, const u8 *data) 1189 { 1190 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1191 struct peb2466_lkup_ctrl *lkup_ctrl; 1192 struct peb2466_lookup *lookup; 1193 u8 (*table)[4]; 1194 u32 table_size; 1195 u32 init_index; 1196 s32 min_val; 1197 s32 step; 1198 u8 mask; 1199 int ret; 1200 int i; 1201 1202 /* 1203 * AX_TABLE TLV data: 1204 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1205 * - @1 32bits signed: Min table value in centi dB (MinVal) 1206 * ie -300 means -3.0 dB 1207 * - @5 32bits signed: Step from on item to other item in centi dB (Step) 1208 * ie 25 means 0.25 dB) 1209 * - @9 32bits unsigned: Item index in the table to use for the initial 1210 * value 1211 * - @13 N*4 bytes: Table composed of 4 bytes items. 1212 * Each item correspond to an AX filter value. 1213 * 1214 * The conversion from raw value item in the table to/from the value in 1215 * dB is: Raw value at index i <-> (MinVal + i * Step) in centi dB. 1216 */ 1217 1218 /* Check Lng and extract the table size. */ 1219 if (lng < 13 || ((lng - 13) % 4)) { 1220 dev_err(component->dev, "fw AX table lng %u invalid\n", lng); 1221 return -EINVAL; 1222 } 1223 table_size = lng - 13; 1224 1225 min_val = get_unaligned_be32(data + 1); 1226 step = get_unaligned_be32(data + 5); 1227 init_index = get_unaligned_be32(data + 9); 1228 if (init_index >= (table_size / 4)) { 1229 dev_err(component->dev, "fw AX table index %u out of table[%u]\n", 1230 init_index, table_size / 4); 1231 return -EINVAL; 1232 } 1233 1234 dev_info(component->dev, 1235 "fw AX table: mask %x, min %d, step %d, %u items, tbl[%u] %*phN\n", 1236 *data, min_val, step, table_size / 4, init_index, 1237 4, data + 13 + (init_index * 4)); 1238 1239 BUILD_BUG_ON(sizeof(*table) != 4); 1240 table = devm_kzalloc(&peb2466->spi->dev, table_size, GFP_KERNEL); 1241 if (!table) 1242 return -ENOMEM; 1243 memcpy(table, data + 13, table_size); 1244 1245 mask = *data; 1246 BUILD_BUG_ON(ARRAY_SIZE(peb2466_ax_ctrl_names) != ARRAY_SIZE(peb2466->ch)); 1247 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1248 if (!(mask & (1 << i))) 1249 continue; 1250 1251 lookup = &peb2466->ch[i].ax_lookup; 1252 lookup->table = table; 1253 lookup->count = table_size / 4; 1254 1255 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1256 PEB2466_CR0_AX, 0); 1257 if (ret) 1258 return ret; 1259 1260 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), 1261 lookup->table[init_index], 4); 1262 if (ret) 1263 return ret; 1264 1265 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1266 PEB2466_CR0_AX, PEB2466_CR0_AX); 1267 if (ret) 1268 return ret; 1269 1270 lkup_ctrl = &peb2466->ch[i].ax_lkup_ctrl; 1271 lkup_ctrl->lookup = lookup; 1272 lkup_ctrl->reg = PEB2466_AX_FILTER(i); 1273 lkup_ctrl->index = init_index; 1274 1275 ret = peb2466_add_lkup_ctrl(component, lkup_ctrl, 1276 peb2466_ax_ctrl_names[i], 1277 min_val, step); 1278 if (ret) 1279 return ret; 1280 } 1281 return 0; 1282 } 1283 1284 static const char * const peb2466_ar_ctrl_names[] = { 1285 "DAC0 Playback Volume", 1286 "DAC1 Playback Volume", 1287 "DAC2 Playback Volume", 1288 "DAC3 Playback Volume", 1289 }; 1290 1291 static int peb2466_fw_parse_artable(struct snd_soc_component *component, 1292 u16 tag, u32 lng, const u8 *data) 1293 { 1294 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1295 struct peb2466_lkup_ctrl *lkup_ctrl; 1296 struct peb2466_lookup *lookup; 1297 u8 (*table)[4]; 1298 u32 table_size; 1299 u32 init_index; 1300 s32 min_val; 1301 s32 step; 1302 u8 mask; 1303 int ret; 1304 int i; 1305 1306 /* 1307 * AR_TABLE TLV data: 1308 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1309 * - @1 32bits signed: Min table value in centi dB (MinVal) 1310 * ie -300 means -3.0 dB 1311 * - @5 32bits signed: Step from on item to other item in centi dB (Step) 1312 * ie 25 means 0.25 dB) 1313 * - @9 32bits unsigned: Item index in the table to use for the initial 1314 * value 1315 * - @13 N*4 bytes: Table composed of 4 bytes items. 1316 * Each item correspond to an AR filter value. 1317 * 1318 * The conversion from raw value item in the table to/from the value in 1319 * dB is: Raw value at index i <-> (MinVal + i * Step) in centi dB. 1320 */ 1321 1322 /* Check Lng and extract the table size. */ 1323 if (lng < 13 || ((lng - 13) % 4)) { 1324 dev_err(component->dev, "fw AR table lng %u invalid\n", lng); 1325 return -EINVAL; 1326 } 1327 table_size = lng - 13; 1328 1329 min_val = get_unaligned_be32(data + 1); 1330 step = get_unaligned_be32(data + 5); 1331 init_index = get_unaligned_be32(data + 9); 1332 if (init_index >= (table_size / 4)) { 1333 dev_err(component->dev, "fw AR table index %u out of table[%u]\n", 1334 init_index, table_size / 4); 1335 return -EINVAL; 1336 } 1337 1338 dev_info(component->dev, 1339 "fw AR table: mask %x, min %d, step %d, %u items, tbl[%u] %*phN\n", 1340 *data, min_val, step, table_size / 4, init_index, 1341 4, data + 13 + (init_index * 4)); 1342 1343 BUILD_BUG_ON(sizeof(*table) != 4); 1344 table = devm_kzalloc(&peb2466->spi->dev, table_size, GFP_KERNEL); 1345 if (!table) 1346 return -ENOMEM; 1347 memcpy(table, data + 13, table_size); 1348 1349 mask = *data; 1350 BUILD_BUG_ON(ARRAY_SIZE(peb2466_ar_ctrl_names) != ARRAY_SIZE(peb2466->ch)); 1351 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1352 if (!(mask & (1 << i))) 1353 continue; 1354 1355 lookup = &peb2466->ch[i].ar_lookup; 1356 lookup->table = table; 1357 lookup->count = table_size / 4; 1358 1359 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1360 PEB2466_CR0_AR, 0); 1361 if (ret) 1362 return ret; 1363 1364 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), 1365 lookup->table[init_index], 4); 1366 if (ret) 1367 return ret; 1368 1369 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1370 PEB2466_CR0_AR, PEB2466_CR0_AR); 1371 if (ret) 1372 return ret; 1373 1374 lkup_ctrl = &peb2466->ch[i].ar_lkup_ctrl; 1375 lkup_ctrl->lookup = lookup; 1376 lkup_ctrl->reg = PEB2466_AR_FILTER(i); 1377 lkup_ctrl->index = init_index; 1378 1379 ret = peb2466_add_lkup_ctrl(component, lkup_ctrl, 1380 peb2466_ar_ctrl_names[i], 1381 min_val, step); 1382 if (ret) 1383 return ret; 1384 } 1385 return 0; 1386 } 1387 1388 struct peb2466_fw_tag_def { 1389 u16 tag; 1390 u32 lng_min; 1391 u32 lng_max; 1392 int (*parse)(struct snd_soc_component *component, 1393 u16 tag, u32 lng, const u8 *data); 1394 }; 1395 1396 #define PEB2466_TAG_DEF_LNG_EQ(__tag, __lng, __parse) { \ 1397 .tag = __tag, \ 1398 .lng_min = __lng, \ 1399 .lng_max = __lng, \ 1400 .parse = __parse, \ 1401 } 1402 1403 #define PEB2466_TAG_DEF_LNG_MIN(__tag, __lng_min, __parse) { \ 1404 .tag = __tag, \ 1405 .lng_min = __lng_min, \ 1406 .lng_max = U32_MAX, \ 1407 .parse = __parse, \ 1408 } 1409 1410 static const struct peb2466_fw_tag_def peb2466_fw_tag_defs[] = { 1411 /* TH FILTER */ 1412 PEB2466_TAG_DEF_LNG_EQ(0x0001, 1 + 3 * 8, peb2466_fw_parse_thfilter), 1413 /* IMR1 FILTER */ 1414 PEB2466_TAG_DEF_LNG_EQ(0x0002, 1 + 2 * 8, peb2466_fw_parse_imr1filter), 1415 /* FRX FILTER */ 1416 PEB2466_TAG_DEF_LNG_EQ(0x0003, 1 + 8, peb2466_fw_parse_frxfilter), 1417 /* FRR FILTER */ 1418 PEB2466_TAG_DEF_LNG_EQ(0x0004, 1 + 8, peb2466_fw_parse_frrfilter), 1419 /* AX FILTER */ 1420 PEB2466_TAG_DEF_LNG_EQ(0x0005, 1 + 4, peb2466_fw_parse_axfilter), 1421 /* AR FILTER */ 1422 PEB2466_TAG_DEF_LNG_EQ(0x0006, 1 + 4, peb2466_fw_parse_arfilter), 1423 /* AX TABLE */ 1424 PEB2466_TAG_DEF_LNG_MIN(0x0105, 1 + 3 * 4, peb2466_fw_parse_axtable), 1425 /* AR TABLE */ 1426 PEB2466_TAG_DEF_LNG_MIN(0x0106, 1 + 3 * 4, peb2466_fw_parse_artable), 1427 }; 1428 1429 static const struct peb2466_fw_tag_def *peb2466_fw_get_tag_def(u16 tag) 1430 { 1431 int i; 1432 1433 for (i = 0; i < ARRAY_SIZE(peb2466_fw_tag_defs); i++) { 1434 if (peb2466_fw_tag_defs[i].tag == tag) 1435 return &peb2466_fw_tag_defs[i]; 1436 } 1437 return NULL; 1438 } 1439 1440 static int peb2466_fw_parse(struct snd_soc_component *component, 1441 const u8 *data, size_t size) 1442 { 1443 const struct peb2466_fw_tag_def *tag_def; 1444 size_t left; 1445 const u8 *buf; 1446 u16 val16; 1447 u16 tag; 1448 u32 lng; 1449 int ret; 1450 1451 /* 1452 * Coefficients firmware binary structure (16bits and 32bits are 1453 * big-endian values). 1454 * 1455 * @0, 16bits: Magic (0x2466) 1456 * @2, 16bits: Version (0x0100 for version 1.0) 1457 * @4, 2+4+N bytes: TLV block 1458 * @4+(2+4+N) bytes: Next TLV block 1459 * ... 1460 * 1461 * Detail of a TLV block: 1462 * @0, 16bits: Tag 1463 * @2, 32bits: Lng 1464 * @6, lng bytes: Data 1465 * 1466 * The detail the Data for a given TLV Tag is provided in the related 1467 * parser. 1468 */ 1469 1470 left = size; 1471 buf = data; 1472 1473 if (left < 4) { 1474 dev_err(component->dev, "fw size %zu, exp at least 4\n", left); 1475 return -EINVAL; 1476 } 1477 1478 /* Check magic */ 1479 val16 = get_unaligned_be16(buf); 1480 if (val16 != 0x2466) { 1481 dev_err(component->dev, "fw magic 0x%04x exp 0x2466\n", val16); 1482 return -EINVAL; 1483 } 1484 buf += 2; 1485 left -= 2; 1486 1487 /* Check version */ 1488 val16 = get_unaligned_be16(buf); 1489 if (val16 != 0x0100) { 1490 dev_err(component->dev, "fw magic 0x%04x exp 0x0100\n", val16); 1491 return -EINVAL; 1492 } 1493 buf += 2; 1494 left -= 2; 1495 1496 while (left) { 1497 if (left < 6) { 1498 dev_err(component->dev, "fw %td/%zu left %zu, exp at least 6\n", 1499 buf - data, size, left); 1500 return -EINVAL; 1501 } 1502 /* Check tag and lng */ 1503 tag = get_unaligned_be16(buf); 1504 lng = get_unaligned_be32(buf + 2); 1505 tag_def = peb2466_fw_get_tag_def(tag); 1506 if (!tag_def) { 1507 dev_err(component->dev, "fw %td/%zu tag 0x%04x unknown\n", 1508 buf - data, size, tag); 1509 return -EINVAL; 1510 } 1511 if (lng < tag_def->lng_min || lng > tag_def->lng_max) { 1512 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u, exp [%u;%u]\n", 1513 buf - data, size, tag, lng, tag_def->lng_min, tag_def->lng_max); 1514 return -EINVAL; 1515 } 1516 buf += 6; 1517 left -= 6; 1518 if (left < lng) { 1519 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u, left %zu\n", 1520 buf - data, size, tag, lng, left); 1521 return -EINVAL; 1522 } 1523 1524 /* TLV block is valid -> parse the data part */ 1525 ret = tag_def->parse(component, tag, lng, buf); 1526 if (ret) { 1527 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u parse failed\n", 1528 buf - data, size, tag, lng); 1529 return ret; 1530 } 1531 1532 buf += lng; 1533 left -= lng; 1534 } 1535 return 0; 1536 } 1537 1538 static int peb2466_load_coeffs(struct snd_soc_component *component, const char *fw_name) 1539 { 1540 const struct firmware *fw; 1541 int ret; 1542 1543 ret = request_firmware(&fw, fw_name, component->dev); 1544 if (ret) 1545 return ret; 1546 1547 ret = peb2466_fw_parse(component, fw->data, fw->size); 1548 release_firmware(fw); 1549 1550 return ret; 1551 } 1552 1553 static int peb2466_component_probe(struct snd_soc_component *component) 1554 { 1555 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1556 const char *firmware_name; 1557 int ret; 1558 1559 /* reset peb2466 audio part */ 1560 ret = peb2466_reset_audio(peb2466); 1561 if (ret) 1562 return ret; 1563 1564 ret = of_property_read_string(peb2466->spi->dev.of_node, 1565 "firmware-name", &firmware_name); 1566 if (ret) 1567 return (ret == -EINVAL) ? 0 : ret; 1568 1569 return peb2466_load_coeffs(component, firmware_name); 1570 } 1571 1572 static const struct snd_soc_component_driver peb2466_component_driver = { 1573 .probe = peb2466_component_probe, 1574 .controls = peb2466_controls, 1575 .num_controls = ARRAY_SIZE(peb2466_controls), 1576 .dapm_widgets = peb2466_dapm_widgets, 1577 .num_dapm_widgets = ARRAY_SIZE(peb2466_dapm_widgets), 1578 .dapm_routes = peb2466_dapm_routes, 1579 .num_dapm_routes = ARRAY_SIZE(peb2466_dapm_routes), 1580 .endianness = 1, 1581 }; 1582 1583 /* 1584 * The mapping used for the relationship between the gpio offset and the 1585 * physical pin is the following: 1586 * 1587 * offset pin 1588 * 0 SI1_0 1589 * 1 SI1_1 1590 * 2 SI2_0 1591 * 3 SI2_1 1592 * 4 SI3_0 1593 * 5 SI3_1 1594 * 6 SI4_0 1595 * 7 SI4_1 1596 * 8 SO1_0 1597 * 9 SO1_1 1598 * 10 SO2_0 1599 * 11 SO2_1 1600 * 12 SO3_0 1601 * 13 SO3_1 1602 * 14 SO4_0 1603 * 15 SO4_1 1604 * 16 SB1_0 1605 * 17 SB1_1 1606 * 18 SB2_0 1607 * 19 SB2_1 1608 * 20 SB3_0 1609 * 21 SB3_1 1610 * 22 SB4_0 1611 * 23 SB4_1 1612 * 24 SB1_2 1613 * 25 SB2_2 1614 * 26 SB3_2 1615 * 27 SB4_2 1616 */ 1617 1618 static int peb2466_chip_gpio_offset_to_data_regmask(unsigned int offset, 1619 unsigned int *xr_reg, 1620 unsigned int *mask) 1621 { 1622 if (offset < 16) { 1623 /* 1624 * SIx_{0,1} and SOx_{0,1} 1625 * Read accesses read SIx_{0,1} values 1626 * Write accesses write SOx_{0,1} values 1627 */ 1628 *xr_reg = PEB2466_XR0; 1629 *mask = (1 << (offset % 8)); 1630 return 0; 1631 } 1632 if (offset < 24) { 1633 /* SBx_{0,1} */ 1634 *xr_reg = PEB2466_XR1; 1635 *mask = (1 << (offset - 16)); 1636 return 0; 1637 } 1638 if (offset < 28) { 1639 /* SBx_2 */ 1640 *xr_reg = PEB2466_XR3; 1641 *mask = (1 << (offset - 24 + 4)); 1642 return 0; 1643 } 1644 return -EINVAL; 1645 } 1646 1647 static int peb2466_chip_gpio_offset_to_dir_regmask(unsigned int offset, 1648 unsigned int *xr_reg, 1649 unsigned int *mask) 1650 { 1651 if (offset < 16) { 1652 /* Direction cannot be changed for these GPIOs */ 1653 return -EINVAL; 1654 } 1655 if (offset < 24) { 1656 *xr_reg = PEB2466_XR2; 1657 *mask = (1 << (offset - 16)); 1658 return 0; 1659 } 1660 if (offset < 28) { 1661 *xr_reg = PEB2466_XR3; 1662 *mask = (1 << (offset - 24)); 1663 return 0; 1664 } 1665 return -EINVAL; 1666 } 1667 1668 static unsigned int *peb2466_chip_gpio_get_cache(struct peb2466 *peb2466, 1669 unsigned int xr_reg) 1670 { 1671 unsigned int *cache; 1672 1673 switch (xr_reg) { 1674 case PEB2466_XR0: 1675 cache = &peb2466->gpio.cache.xr0; 1676 break; 1677 case PEB2466_XR1: 1678 cache = &peb2466->gpio.cache.xr1; 1679 break; 1680 case PEB2466_XR2: 1681 cache = &peb2466->gpio.cache.xr2; 1682 break; 1683 case PEB2466_XR3: 1684 cache = &peb2466->gpio.cache.xr3; 1685 break; 1686 default: 1687 cache = NULL; 1688 break; 1689 } 1690 return cache; 1691 } 1692 1693 static int peb2466_chip_gpio_update_bits(struct peb2466 *peb2466, unsigned int xr_reg, 1694 unsigned int mask, unsigned int val) 1695 { 1696 unsigned int tmp; 1697 unsigned int *cache; 1698 int ret; 1699 1700 /* 1701 * Read and write accesses use different peb2466 internal signals (input 1702 * signals on reads and output signals on writes). regmap_update_bits 1703 * cannot be used to read/modify/write the value. 1704 * So, a specific cache value is used. 1705 */ 1706 1707 mutex_lock(&peb2466->gpio.lock); 1708 1709 cache = peb2466_chip_gpio_get_cache(peb2466, xr_reg); 1710 if (!cache) { 1711 ret = -EINVAL; 1712 goto end; 1713 } 1714 1715 tmp = *cache; 1716 tmp &= ~mask; 1717 tmp |= val; 1718 1719 ret = regmap_write(peb2466->regmap, xr_reg, tmp); 1720 if (ret) 1721 goto end; 1722 1723 *cache = tmp; 1724 ret = 0; 1725 1726 end: 1727 mutex_unlock(&peb2466->gpio.lock); 1728 return ret; 1729 } 1730 1731 static int peb2466_chip_gpio_set(struct gpio_chip *c, unsigned int offset, 1732 int val) 1733 { 1734 struct peb2466 *peb2466 = gpiochip_get_data(c); 1735 unsigned int xr_reg; 1736 unsigned int mask; 1737 int ret; 1738 1739 if (offset < 8) { 1740 /* 1741 * SIx_{0,1} signals cannot be set and writing the related 1742 * register will change the SOx_{0,1} signals 1743 */ 1744 dev_warn(&peb2466->spi->dev, "cannot set gpio %d (read-only)\n", 1745 offset); 1746 return -EINVAL; 1747 } 1748 1749 ret = peb2466_chip_gpio_offset_to_data_regmask(offset, &xr_reg, &mask); 1750 if (ret) { 1751 dev_err(&peb2466->spi->dev, "cannot set gpio %d (%d)\n", 1752 offset, ret); 1753 return ret; 1754 } 1755 1756 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, val ? mask : 0); 1757 if (ret) { 1758 dev_err(&peb2466->spi->dev, "set gpio %d (0x%x, 0x%x) failed (%d)\n", 1759 offset, xr_reg, mask, ret); 1760 } 1761 1762 return ret; 1763 } 1764 1765 static int peb2466_chip_gpio_get(struct gpio_chip *c, unsigned int offset) 1766 { 1767 struct peb2466 *peb2466 = gpiochip_get_data(c); 1768 bool use_cache = false; 1769 unsigned int *cache; 1770 unsigned int xr_reg; 1771 unsigned int mask; 1772 unsigned int val; 1773 int ret; 1774 1775 if (offset >= 8 && offset < 16) { 1776 /* 1777 * SOx_{0,1} signals cannot be read. Reading the related 1778 * register will read the SIx_{0,1} signals. 1779 * Use the cache to get value; 1780 */ 1781 use_cache = true; 1782 } 1783 1784 ret = peb2466_chip_gpio_offset_to_data_regmask(offset, &xr_reg, &mask); 1785 if (ret) { 1786 dev_err(&peb2466->spi->dev, "cannot get gpio %d (%d)\n", 1787 offset, ret); 1788 return -EINVAL; 1789 } 1790 1791 if (use_cache) { 1792 cache = peb2466_chip_gpio_get_cache(peb2466, xr_reg); 1793 if (!cache) 1794 return -EINVAL; 1795 val = *cache; 1796 } else { 1797 ret = regmap_read(peb2466->regmap, xr_reg, &val); 1798 if (ret) { 1799 dev_err(&peb2466->spi->dev, "get gpio %d (0x%x, 0x%x) failed (%d)\n", 1800 offset, xr_reg, mask, ret); 1801 return ret; 1802 } 1803 } 1804 1805 return !!(val & mask); 1806 } 1807 1808 static int peb2466_chip_get_direction(struct gpio_chip *c, unsigned int offset) 1809 { 1810 struct peb2466 *peb2466 = gpiochip_get_data(c); 1811 unsigned int xr_reg; 1812 unsigned int mask; 1813 unsigned int val; 1814 int ret; 1815 1816 if (offset < 8) { 1817 /* SIx_{0,1} */ 1818 return GPIO_LINE_DIRECTION_IN; 1819 } 1820 if (offset < 16) { 1821 /* SOx_{0,1} */ 1822 return GPIO_LINE_DIRECTION_OUT; 1823 } 1824 1825 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask); 1826 if (ret) { 1827 dev_err(&peb2466->spi->dev, "cannot get gpio %d direction (%d)\n", 1828 offset, ret); 1829 return ret; 1830 } 1831 1832 ret = regmap_read(peb2466->regmap, xr_reg, &val); 1833 if (ret) { 1834 dev_err(&peb2466->spi->dev, "get dir gpio %d (0x%x, 0x%x) failed (%d)\n", 1835 offset, xr_reg, mask, ret); 1836 return ret; 1837 } 1838 1839 return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1840 } 1841 1842 static int peb2466_chip_direction_input(struct gpio_chip *c, unsigned int offset) 1843 { 1844 struct peb2466 *peb2466 = gpiochip_get_data(c); 1845 unsigned int xr_reg; 1846 unsigned int mask; 1847 int ret; 1848 1849 if (offset < 8) { 1850 /* SIx_{0,1} */ 1851 return 0; 1852 } 1853 if (offset < 16) { 1854 /* SOx_{0,1} */ 1855 return -EINVAL; 1856 } 1857 1858 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask); 1859 if (ret) { 1860 dev_err(&peb2466->spi->dev, "cannot set gpio %d direction (%d)\n", 1861 offset, ret); 1862 return ret; 1863 } 1864 1865 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, 0); 1866 if (ret) { 1867 dev_err(&peb2466->spi->dev, "Set dir in gpio %d (0x%x, 0x%x) failed (%d)\n", 1868 offset, xr_reg, mask, ret); 1869 return ret; 1870 } 1871 1872 return 0; 1873 } 1874 1875 static int peb2466_chip_direction_output(struct gpio_chip *c, unsigned int offset, int val) 1876 { 1877 struct peb2466 *peb2466 = gpiochip_get_data(c); 1878 unsigned int xr_reg; 1879 unsigned int mask; 1880 int ret; 1881 1882 if (offset < 8) { 1883 /* SIx_{0,1} */ 1884 return -EINVAL; 1885 } 1886 1887 ret = peb2466_chip_gpio_set(c, offset, val); 1888 if (ret) 1889 return ret; 1890 1891 if (offset < 16) { 1892 /* SOx_{0,1} */ 1893 return 0; 1894 } 1895 1896 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask); 1897 if (ret) { 1898 dev_err(&peb2466->spi->dev, "cannot set gpio %d direction (%d)\n", 1899 offset, ret); 1900 return ret; 1901 } 1902 1903 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, mask); 1904 if (ret) { 1905 dev_err(&peb2466->spi->dev, "Set dir in gpio %d (0x%x, 0x%x) failed (%d)\n", 1906 offset, xr_reg, mask, ret); 1907 return ret; 1908 } 1909 1910 return 0; 1911 } 1912 1913 static int peb2466_reset_gpio(struct peb2466 *peb2466) 1914 { 1915 static const struct reg_sequence reg_reset[] = { 1916 /* Output pins at 0, input/output pins as input */ 1917 { .reg = PEB2466_XR0, .def = 0 }, 1918 { .reg = PEB2466_XR1, .def = 0 }, 1919 { .reg = PEB2466_XR2, .def = 0 }, 1920 { .reg = PEB2466_XR3, .def = 0 }, 1921 }; 1922 1923 peb2466->gpio.cache.xr0 = 0; 1924 peb2466->gpio.cache.xr1 = 0; 1925 peb2466->gpio.cache.xr2 = 0; 1926 peb2466->gpio.cache.xr3 = 0; 1927 1928 return regmap_multi_reg_write(peb2466->regmap, reg_reset, ARRAY_SIZE(reg_reset)); 1929 } 1930 1931 static int peb2466_gpio_init(struct peb2466 *peb2466) 1932 { 1933 int ret; 1934 1935 mutex_init(&peb2466->gpio.lock); 1936 1937 ret = peb2466_reset_gpio(peb2466); 1938 if (ret) 1939 return ret; 1940 1941 peb2466->gpio.gpio_chip.owner = THIS_MODULE; 1942 peb2466->gpio.gpio_chip.label = dev_name(&peb2466->spi->dev); 1943 peb2466->gpio.gpio_chip.parent = &peb2466->spi->dev; 1944 peb2466->gpio.gpio_chip.base = -1; 1945 peb2466->gpio.gpio_chip.ngpio = 28; 1946 peb2466->gpio.gpio_chip.get_direction = peb2466_chip_get_direction; 1947 peb2466->gpio.gpio_chip.direction_input = peb2466_chip_direction_input; 1948 peb2466->gpio.gpio_chip.direction_output = peb2466_chip_direction_output; 1949 peb2466->gpio.gpio_chip.get = peb2466_chip_gpio_get; 1950 peb2466->gpio.gpio_chip.set = peb2466_chip_gpio_set; 1951 peb2466->gpio.gpio_chip.can_sleep = true; 1952 1953 return devm_gpiochip_add_data(&peb2466->spi->dev, &peb2466->gpio.gpio_chip, 1954 peb2466); 1955 } 1956 1957 static int peb2466_spi_probe(struct spi_device *spi) 1958 { 1959 struct peb2466 *peb2466; 1960 unsigned long mclk_rate; 1961 int ret; 1962 u8 xr5; 1963 1964 spi->bits_per_word = 8; 1965 ret = spi_setup(spi); 1966 if (ret < 0) 1967 return ret; 1968 1969 peb2466 = devm_kzalloc(&spi->dev, sizeof(*peb2466), GFP_KERNEL); 1970 if (!peb2466) 1971 return -ENOMEM; 1972 1973 peb2466->spi = spi; 1974 1975 peb2466->regmap = devm_regmap_init(&peb2466->spi->dev, NULL, peb2466, 1976 &peb2466_regmap_config); 1977 if (IS_ERR(peb2466->regmap)) 1978 return PTR_ERR(peb2466->regmap); 1979 1980 peb2466->reset_gpio = devm_gpiod_get_optional(&peb2466->spi->dev, 1981 "reset", GPIOD_OUT_LOW); 1982 if (IS_ERR(peb2466->reset_gpio)) 1983 return PTR_ERR(peb2466->reset_gpio); 1984 1985 peb2466->mclk = devm_clk_get_enabled(&peb2466->spi->dev, "mclk"); 1986 if (IS_ERR(peb2466->mclk)) 1987 return PTR_ERR(peb2466->mclk); 1988 1989 if (peb2466->reset_gpio) { 1990 gpiod_set_value_cansleep(peb2466->reset_gpio, 1); 1991 udelay(4); 1992 gpiod_set_value_cansleep(peb2466->reset_gpio, 0); 1993 udelay(4); 1994 } 1995 1996 spi_set_drvdata(spi, peb2466); 1997 1998 mclk_rate = clk_get_rate(peb2466->mclk); 1999 switch (mclk_rate) { 2000 case 1536000: 2001 xr5 = PEB2466_XR5_MCLK_1536; 2002 break; 2003 case 2048000: 2004 xr5 = PEB2466_XR5_MCLK_2048; 2005 break; 2006 case 4096000: 2007 xr5 = PEB2466_XR5_MCLK_4096; 2008 break; 2009 case 8192000: 2010 xr5 = PEB2466_XR5_MCLK_8192; 2011 break; 2012 default: 2013 dev_err(&peb2466->spi->dev, "Unsupported clock rate %lu\n", 2014 mclk_rate); 2015 ret = -EINVAL; 2016 goto failed; 2017 } 2018 ret = regmap_write(peb2466->regmap, PEB2466_XR5, xr5); 2019 if (ret) { 2020 dev_err(&peb2466->spi->dev, "Setting MCLK failed (%d)\n", ret); 2021 goto failed; 2022 } 2023 2024 ret = devm_snd_soc_register_component(&spi->dev, &peb2466_component_driver, 2025 &peb2466_dai_driver, 1); 2026 if (ret) 2027 goto failed; 2028 2029 if (IS_ENABLED(CONFIG_GPIOLIB)) { 2030 ret = peb2466_gpio_init(peb2466); 2031 if (ret) 2032 goto failed; 2033 } 2034 2035 return 0; 2036 2037 failed: 2038 return ret; 2039 } 2040 2041 static const struct of_device_id peb2466_of_match[] = { 2042 { .compatible = "infineon,peb2466", }, 2043 { } 2044 }; 2045 MODULE_DEVICE_TABLE(of, peb2466_of_match); 2046 2047 static const struct spi_device_id peb2466_id_table[] = { 2048 { "peb2466", 0 }, 2049 { } 2050 }; 2051 MODULE_DEVICE_TABLE(spi, peb2466_id_table); 2052 2053 static struct spi_driver peb2466_spi_driver = { 2054 .driver = { 2055 .name = "peb2466", 2056 .of_match_table = peb2466_of_match, 2057 }, 2058 .id_table = peb2466_id_table, 2059 .probe = peb2466_spi_probe, 2060 }; 2061 2062 module_spi_driver(peb2466_spi_driver); 2063 2064 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>"); 2065 MODULE_DESCRIPTION("PEB2466 ALSA SoC driver"); 2066 MODULE_LICENSE("GPL"); 2067