1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // peb2466.c -- Infineon PEB2466 ALSA SoC driver 4 // 5 // Copyright 2023 CS GROUP France 6 // 7 // Author: Herve Codina <herve.codina@bootlin.com> 8 9 #include <linux/cleanup.h> 10 #include <linux/unaligned.h> 11 #include <linux/clk.h> 12 #include <linux/firmware.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/slab.h> 18 #include <linux/spi/spi.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #define PEB2466_NB_CHANNEL 4 24 25 struct peb2466_lookup { 26 u8 (*table)[4]; 27 unsigned int count; 28 }; 29 30 #define PEB2466_TLV_SIZE ARRAY_SIZE(((unsigned int[]){TLV_DB_SCALE_ITEM(0, 0, 0)})) 31 32 struct peb2466_lkup_ctrl { 33 int reg; 34 unsigned int index; 35 const struct peb2466_lookup *lookup; 36 unsigned int tlv_array[PEB2466_TLV_SIZE]; 37 }; 38 39 struct peb2466 { 40 struct spi_device *spi; 41 struct clk *mclk; 42 struct gpio_desc *reset_gpio; 43 u8 spi_tx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */ 44 u8 spi_rx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */ 45 struct regmap *regmap; 46 struct { 47 struct peb2466_lookup ax_lookup; 48 struct peb2466_lookup ar_lookup; 49 struct peb2466_lkup_ctrl ax_lkup_ctrl; 50 struct peb2466_lkup_ctrl ar_lkup_ctrl; 51 unsigned int tg1_freq_item; 52 unsigned int tg2_freq_item; 53 } ch[PEB2466_NB_CHANNEL]; 54 int max_chan_playback; 55 int max_chan_capture; 56 struct { 57 struct gpio_chip gpio_chip; 58 struct mutex lock; 59 struct { 60 unsigned int xr0; 61 unsigned int xr1; 62 unsigned int xr2; 63 unsigned int xr3; 64 } cache; 65 } gpio; 66 }; 67 68 #define PEB2466_CMD_R (1 << 5) 69 #define PEB2466_CMD_W (0 << 5) 70 71 #define PEB2466_CMD_MASK 0x18 72 #define PEB2466_CMD_XOP 0x18 /* XOP is 0bxxx11xxx */ 73 #define PEB2466_CMD_SOP 0x10 /* SOP is 0bxxx10xxx */ 74 #define PEB2466_CMD_COP 0x00 /* COP is 0bxxx0xxxx, handle 0bxxx00xxx */ 75 #define PEB2466_CMD_COP1 0x08 /* COP is 0bxxx0xxxx, handle 0bxxx01xxx */ 76 77 #define PEB2466_MAKE_XOP(_lsel) (PEB2466_CMD_XOP | (_lsel)) 78 #define PEB2466_MAKE_SOP(_ad, _lsel) (PEB2466_CMD_SOP | ((_ad) << 6) | (_lsel)) 79 #define PEB2466_MAKE_COP(_ad, _code) (PEB2466_CMD_COP | ((_ad) << 6) | (_code)) 80 81 #define PEB2466_CR0(_ch) PEB2466_MAKE_SOP(_ch, 0x0) 82 #define PEB2466_CR0_TH (1 << 7) 83 #define PEB2466_CR0_IMR1 (1 << 6) 84 #define PEB2466_CR0_FRX (1 << 5) 85 #define PEB2466_CR0_FRR (1 << 4) 86 #define PEB2466_CR0_AX (1 << 3) 87 #define PEB2466_CR0_AR (1 << 2) 88 #define PEB2466_CR0_THSEL_MASK (0x3 << 0) 89 #define PEB2466_CR0_THSEL(_set) ((_set) << 0) 90 91 #define PEB2466_CR1(_ch) PEB2466_MAKE_SOP(_ch, 0x1) 92 #define PEB2466_CR1_ETG2 (1 << 7) 93 #define PEB2466_CR1_ETG1 (1 << 6) 94 #define PEB2466_CR1_PTG2 (1 << 5) 95 #define PEB2466_CR1_PTG1 (1 << 4) 96 #define PEB2466_CR1_LAW_MASK (1 << 3) 97 #define PEB2466_CR1_LAW_ALAW (0 << 3) 98 #define PEB2466_CR1_LAW_MULAW (1 << 3) 99 #define PEB2466_CR1_PU (1 << 0) 100 101 #define PEB2466_CR2(_ch) PEB2466_MAKE_SOP(_ch, 0x2) 102 #define PEB2466_CR3(_ch) PEB2466_MAKE_SOP(_ch, 0x3) 103 #define PEB2466_CR4(_ch) PEB2466_MAKE_SOP(_ch, 0x4) 104 #define PEB2466_CR5(_ch) PEB2466_MAKE_SOP(_ch, 0x5) 105 106 #define PEB2466_XR0 PEB2466_MAKE_XOP(0x0) 107 #define PEB2466_XR1 PEB2466_MAKE_XOP(0x1) 108 #define PEB2466_XR2 PEB2466_MAKE_XOP(0x2) 109 #define PEB2466_XR3 PEB2466_MAKE_XOP(0x3) 110 #define PEB2466_XR4 PEB2466_MAKE_XOP(0x4) 111 #define PEB2466_XR5 PEB2466_MAKE_XOP(0x5) 112 #define PEB2466_XR5_MCLK_1536 (0x0 << 6) 113 #define PEB2466_XR5_MCLK_2048 (0x1 << 6) 114 #define PEB2466_XR5_MCLK_4096 (0x2 << 6) 115 #define PEB2466_XR5_MCLK_8192 (0x3 << 6) 116 117 #define PEB2466_XR6 PEB2466_MAKE_XOP(0x6) 118 #define PEB2466_XR6_PCM_OFFSET(_off) ((_off) << 0) 119 120 #define PEB2466_XR7 PEB2466_MAKE_XOP(0x7) 121 122 #define PEB2466_TH_FILTER_P1(_ch) PEB2466_MAKE_COP(_ch, 0x0) 123 #define PEB2466_TH_FILTER_P2(_ch) PEB2466_MAKE_COP(_ch, 0x1) 124 #define PEB2466_TH_FILTER_P3(_ch) PEB2466_MAKE_COP(_ch, 0x2) 125 #define PEB2466_IMR1_FILTER_P1(_ch) PEB2466_MAKE_COP(_ch, 0x4) 126 #define PEB2466_IMR1_FILTER_P2(_ch) PEB2466_MAKE_COP(_ch, 0x5) 127 #define PEB2466_FRX_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x6) 128 #define PEB2466_FRR_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x7) 129 #define PEB2466_AX_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x8) 130 #define PEB2466_AR_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x9) 131 #define PEB2466_TG1(_ch) PEB2466_MAKE_COP(_ch, 0xc) 132 #define PEB2466_TG2(_ch) PEB2466_MAKE_COP(_ch, 0xd) 133 134 static int peb2466_write_byte(struct peb2466 *peb2466, u8 cmd, u8 val) 135 { 136 struct spi_transfer xfer = { 137 .tx_buf = &peb2466->spi_tx_buf, 138 .len = 2, 139 }; 140 141 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W; 142 peb2466->spi_tx_buf[1] = val; 143 144 dev_dbg(&peb2466->spi->dev, "write byte (cmd %02x) %02x\n", 145 peb2466->spi_tx_buf[0], peb2466->spi_tx_buf[1]); 146 147 return spi_sync_transfer(peb2466->spi, &xfer, 1); 148 } 149 150 static int peb2466_read_byte(struct peb2466 *peb2466, u8 cmd, u8 *val) 151 { 152 struct spi_transfer xfer = { 153 .tx_buf = &peb2466->spi_tx_buf, 154 .rx_buf = &peb2466->spi_rx_buf, 155 .len = 3, 156 }; 157 int ret; 158 159 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_R; 160 161 ret = spi_sync_transfer(peb2466->spi, &xfer, 1); 162 if (ret) 163 return ret; 164 165 if (peb2466->spi_rx_buf[1] != 0x81) { 166 dev_err(&peb2466->spi->dev, 167 "spi xfer rd (cmd %02x) invalid ident byte (0x%02x)\n", 168 peb2466->spi_tx_buf[0], peb2466->spi_rx_buf[1]); 169 return -EILSEQ; 170 } 171 172 *val = peb2466->spi_rx_buf[2]; 173 174 dev_dbg(&peb2466->spi->dev, "read byte (cmd %02x) %02x\n", 175 peb2466->spi_tx_buf[0], *val); 176 177 return 0; 178 } 179 180 static int peb2466_write_buf(struct peb2466 *peb2466, u8 cmd, const u8 *buf, unsigned int len) 181 { 182 struct spi_transfer xfer = { 183 .tx_buf = &peb2466->spi_tx_buf, 184 .len = len + 1, 185 }; 186 187 if (len > 8) 188 return -EINVAL; 189 190 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W; 191 memcpy(&peb2466->spi_tx_buf[1], buf, len); 192 193 dev_dbg(&peb2466->spi->dev, "write buf (cmd %02x, %u) %*ph\n", 194 peb2466->spi_tx_buf[0], len, len, &peb2466->spi_tx_buf[1]); 195 196 return spi_sync_transfer(peb2466->spi, &xfer, 1); 197 } 198 199 static int peb2466_reg_write(void *context, unsigned int reg, unsigned int val) 200 { 201 struct peb2466 *peb2466 = context; 202 int ret; 203 204 /* 205 * Only XOP and SOP commands can be handled as registers. 206 * COP commands are handled using direct peb2466_write_buf() calls. 207 */ 208 switch (reg & PEB2466_CMD_MASK) { 209 case PEB2466_CMD_XOP: 210 case PEB2466_CMD_SOP: 211 ret = peb2466_write_byte(peb2466, reg, val); 212 break; 213 default: 214 dev_err(&peb2466->spi->dev, "Not a XOP or SOP command\n"); 215 ret = -EINVAL; 216 break; 217 } 218 return ret; 219 } 220 221 static int peb2466_reg_read(void *context, unsigned int reg, unsigned int *val) 222 { 223 struct peb2466 *peb2466 = context; 224 int ret; 225 u8 tmp; 226 227 /* Only XOP and SOP commands can be handled as registers */ 228 switch (reg & PEB2466_CMD_MASK) { 229 case PEB2466_CMD_XOP: 230 case PEB2466_CMD_SOP: 231 ret = peb2466_read_byte(peb2466, reg, &tmp); 232 if (!ret) 233 *val = tmp; 234 break; 235 default: 236 dev_err(&peb2466->spi->dev, "Not a XOP or SOP command\n"); 237 ret = -EINVAL; 238 break; 239 } 240 return ret; 241 } 242 243 static const struct regmap_config peb2466_regmap_config = { 244 .reg_bits = 8, 245 .val_bits = 8, 246 .max_register = 0xFF, 247 .reg_write = peb2466_reg_write, 248 .reg_read = peb2466_reg_read, 249 .cache_type = REGCACHE_NONE, 250 }; 251 252 static int peb2466_lkup_ctrl_info(struct snd_kcontrol *kcontrol, 253 struct snd_ctl_elem_info *uinfo) 254 { 255 struct peb2466_lkup_ctrl *lkup_ctrl = 256 (struct peb2466_lkup_ctrl *)kcontrol->private_value; 257 258 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 259 uinfo->count = 1; 260 uinfo->value.integer.min = 0; 261 uinfo->value.integer.max = lkup_ctrl->lookup->count - 1; 262 return 0; 263 } 264 265 static int peb2466_lkup_ctrl_get(struct snd_kcontrol *kcontrol, 266 struct snd_ctl_elem_value *ucontrol) 267 { 268 struct peb2466_lkup_ctrl *lkup_ctrl = 269 (struct peb2466_lkup_ctrl *)kcontrol->private_value; 270 271 ucontrol->value.integer.value[0] = lkup_ctrl->index; 272 return 0; 273 } 274 275 static int peb2466_lkup_ctrl_put(struct snd_kcontrol *kcontrol, 276 struct snd_ctl_elem_value *ucontrol) 277 { 278 struct peb2466_lkup_ctrl *lkup_ctrl = 279 (struct peb2466_lkup_ctrl *)kcontrol->private_value; 280 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 281 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 282 unsigned int index; 283 int ret; 284 285 index = ucontrol->value.integer.value[0]; 286 if (index >= lkup_ctrl->lookup->count) 287 return -EINVAL; 288 289 if (index == lkup_ctrl->index) 290 return 0; 291 292 ret = peb2466_write_buf(peb2466, lkup_ctrl->reg, 293 lkup_ctrl->lookup->table[index], 4); 294 if (ret) 295 return ret; 296 297 lkup_ctrl->index = index; 298 return 1; /* The value changed */ 299 } 300 301 static int peb2466_add_lkup_ctrl(struct snd_soc_component *component, 302 struct peb2466_lkup_ctrl *lkup_ctrl, 303 const char *name, int min_val, int step) 304 { 305 DECLARE_TLV_DB_SCALE(tlv_array, min_val, step, 0); 306 struct snd_kcontrol_new control = {0}; 307 308 BUILD_BUG_ON(sizeof(lkup_ctrl->tlv_array) < sizeof(tlv_array)); 309 memcpy(lkup_ctrl->tlv_array, tlv_array, sizeof(tlv_array)); 310 311 control.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 312 control.name = name; 313 control.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 314 SNDRV_CTL_ELEM_ACCESS_READWRITE; 315 control.tlv.p = lkup_ctrl->tlv_array; 316 control.info = peb2466_lkup_ctrl_info; 317 control.get = peb2466_lkup_ctrl_get; 318 control.put = peb2466_lkup_ctrl_put; 319 control.private_value = (unsigned long)lkup_ctrl; 320 321 return snd_soc_add_component_controls(component, &control, 1); 322 } 323 324 enum peb2466_tone_freq { 325 PEB2466_TONE_697HZ, 326 PEB2466_TONE_800HZ, 327 PEB2466_TONE_950HZ, 328 PEB2466_TONE_1000HZ, 329 PEB2466_TONE_1008HZ, 330 PEB2466_TONE_2000HZ, 331 }; 332 333 static const u8 peb2466_tone_lookup[][4] = { 334 [PEB2466_TONE_697HZ] = {0x0a, 0x33, 0x5a, 0x2c}, 335 [PEB2466_TONE_800HZ] = {0x12, 0xD6, 0x5a, 0xc0}, 336 [PEB2466_TONE_950HZ] = {0x1c, 0xf0, 0x5c, 0xc0}, 337 [PEB2466_TONE_1000HZ] = {0}, /* lookup value not used for 1000Hz */ 338 [PEB2466_TONE_1008HZ] = {0x1a, 0xae, 0x57, 0x70}, 339 [PEB2466_TONE_2000HZ] = {0x00, 0x80, 0x50, 0x09}, 340 }; 341 342 static const char * const peb2466_tone_freq_txt[] = { 343 [PEB2466_TONE_697HZ] = "697Hz", 344 [PEB2466_TONE_800HZ] = "800Hz", 345 [PEB2466_TONE_950HZ] = "950Hz", 346 [PEB2466_TONE_1000HZ] = "1000Hz", 347 [PEB2466_TONE_1008HZ] = "1008Hz", 348 [PEB2466_TONE_2000HZ] = "2000Hz" 349 }; 350 351 static const struct soc_enum peb2466_tg_freq[][2] = { 352 [0] = { 353 SOC_ENUM_SINGLE(PEB2466_TG1(0), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 354 peb2466_tone_freq_txt), 355 SOC_ENUM_SINGLE(PEB2466_TG2(0), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 356 peb2466_tone_freq_txt) 357 }, 358 [1] = { 359 SOC_ENUM_SINGLE(PEB2466_TG1(1), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 360 peb2466_tone_freq_txt), 361 SOC_ENUM_SINGLE(PEB2466_TG2(1), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 362 peb2466_tone_freq_txt) 363 }, 364 [2] = { 365 SOC_ENUM_SINGLE(PEB2466_TG1(2), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 366 peb2466_tone_freq_txt), 367 SOC_ENUM_SINGLE(PEB2466_TG2(2), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 368 peb2466_tone_freq_txt) 369 }, 370 [3] = { 371 SOC_ENUM_SINGLE(PEB2466_TG1(3), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 372 peb2466_tone_freq_txt), 373 SOC_ENUM_SINGLE(PEB2466_TG2(3), 0, ARRAY_SIZE(peb2466_tone_freq_txt), 374 peb2466_tone_freq_txt) 375 } 376 }; 377 378 static int peb2466_tg_freq_get(struct snd_kcontrol *kcontrol, 379 struct snd_ctl_elem_value *ucontrol) 380 { 381 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 382 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 383 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 384 385 switch (e->reg) { 386 case PEB2466_TG1(0): 387 ucontrol->value.enumerated.item[0] = peb2466->ch[0].tg1_freq_item; 388 break; 389 case PEB2466_TG2(0): 390 ucontrol->value.enumerated.item[0] = peb2466->ch[0].tg2_freq_item; 391 break; 392 case PEB2466_TG1(1): 393 ucontrol->value.enumerated.item[0] = peb2466->ch[1].tg1_freq_item; 394 break; 395 case PEB2466_TG2(1): 396 ucontrol->value.enumerated.item[0] = peb2466->ch[1].tg2_freq_item; 397 break; 398 case PEB2466_TG1(2): 399 ucontrol->value.enumerated.item[0] = peb2466->ch[2].tg1_freq_item; 400 break; 401 case PEB2466_TG2(2): 402 ucontrol->value.enumerated.item[0] = peb2466->ch[2].tg2_freq_item; 403 break; 404 case PEB2466_TG1(3): 405 ucontrol->value.enumerated.item[0] = peb2466->ch[3].tg1_freq_item; 406 break; 407 case PEB2466_TG2(3): 408 ucontrol->value.enumerated.item[0] = peb2466->ch[3].tg2_freq_item; 409 break; 410 default: 411 return -EINVAL; 412 } 413 return 0; 414 } 415 416 static int peb2466_tg_freq_put(struct snd_kcontrol *kcontrol, 417 struct snd_ctl_elem_value *ucontrol) 418 { 419 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 420 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 421 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 422 unsigned int *tg_freq_item; 423 u8 cr1_reg, cr1_mask; 424 unsigned int index; 425 int ret; 426 427 index = ucontrol->value.enumerated.item[0]; 428 429 if (index >= ARRAY_SIZE(peb2466_tone_lookup)) 430 return -EINVAL; 431 432 switch (e->reg) { 433 case PEB2466_TG1(0): 434 tg_freq_item = &peb2466->ch[0].tg1_freq_item; 435 cr1_reg = PEB2466_CR1(0); 436 cr1_mask = PEB2466_CR1_PTG1; 437 break; 438 case PEB2466_TG2(0): 439 tg_freq_item = &peb2466->ch[0].tg2_freq_item; 440 cr1_reg = PEB2466_CR1(0); 441 cr1_mask = PEB2466_CR1_PTG2; 442 break; 443 case PEB2466_TG1(1): 444 tg_freq_item = &peb2466->ch[1].tg1_freq_item; 445 cr1_reg = PEB2466_CR1(1); 446 cr1_mask = PEB2466_CR1_PTG1; 447 break; 448 case PEB2466_TG2(1): 449 tg_freq_item = &peb2466->ch[1].tg2_freq_item; 450 cr1_reg = PEB2466_CR1(1); 451 cr1_mask = PEB2466_CR1_PTG2; 452 break; 453 case PEB2466_TG1(2): 454 tg_freq_item = &peb2466->ch[2].tg1_freq_item; 455 cr1_reg = PEB2466_CR1(2); 456 cr1_mask = PEB2466_CR1_PTG1; 457 break; 458 case PEB2466_TG2(2): 459 tg_freq_item = &peb2466->ch[2].tg2_freq_item; 460 cr1_reg = PEB2466_CR1(2); 461 cr1_mask = PEB2466_CR1_PTG2; 462 break; 463 case PEB2466_TG1(3): 464 tg_freq_item = &peb2466->ch[3].tg1_freq_item; 465 cr1_reg = PEB2466_CR1(3); 466 cr1_mask = PEB2466_CR1_PTG1; 467 break; 468 case PEB2466_TG2(3): 469 tg_freq_item = &peb2466->ch[3].tg2_freq_item; 470 cr1_reg = PEB2466_CR1(3); 471 cr1_mask = PEB2466_CR1_PTG2; 472 break; 473 default: 474 return -EINVAL; 475 } 476 477 if (index == *tg_freq_item) 478 return 0; 479 480 if (index == PEB2466_TONE_1000HZ) { 481 ret = regmap_update_bits(peb2466->regmap, cr1_reg, cr1_mask, 0); 482 if (ret) 483 return ret; 484 } else { 485 ret = peb2466_write_buf(peb2466, e->reg, peb2466_tone_lookup[index], 4); 486 if (ret) 487 return ret; 488 ret = regmap_update_bits(peb2466->regmap, cr1_reg, cr1_mask, cr1_mask); 489 if (ret) 490 return ret; 491 } 492 493 *tg_freq_item = index; 494 return 1; /* The value changed */ 495 } 496 497 static const struct snd_kcontrol_new peb2466_ch0_out_mix_controls[] = { 498 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(0), 6, 1, 0), 499 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(0), 7, 1, 0), 500 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(0), 0, 1, 0) 501 }; 502 503 static const struct snd_kcontrol_new peb2466_ch1_out_mix_controls[] = { 504 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(1), 6, 1, 0), 505 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(1), 7, 1, 0), 506 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(1), 0, 1, 0) 507 }; 508 509 static const struct snd_kcontrol_new peb2466_ch2_out_mix_controls[] = { 510 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(2), 6, 1, 0), 511 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(2), 7, 1, 0), 512 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(2), 0, 1, 0) 513 }; 514 515 static const struct snd_kcontrol_new peb2466_ch3_out_mix_controls[] = { 516 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(3), 6, 1, 0), 517 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(3), 7, 1, 0), 518 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(3), 0, 1, 0) 519 }; 520 521 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(peb2466_gain_p_tlv, -600, 0); 522 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(peb2466_gain_c_tlv, 0, 600); 523 524 static const struct snd_kcontrol_new peb2466_controls[] = { 525 /* Attenuators */ 526 SOC_SINGLE_TLV("DAC0 -6dB Playback Volume", PEB2466_CR3(0), 2, 1, 1, peb2466_gain_p_tlv), 527 SOC_SINGLE_TLV("DAC1 -6dB Playback Volume", PEB2466_CR3(1), 2, 1, 1, peb2466_gain_p_tlv), 528 SOC_SINGLE_TLV("DAC2 -6dB Playback Volume", PEB2466_CR3(2), 2, 1, 1, peb2466_gain_p_tlv), 529 SOC_SINGLE_TLV("DAC3 -6dB Playback Volume", PEB2466_CR3(3), 2, 1, 1, peb2466_gain_p_tlv), 530 531 /* Amplifiers */ 532 SOC_SINGLE_TLV("ADC0 +6dB Capture Volume", PEB2466_CR3(0), 3, 1, 0, peb2466_gain_c_tlv), 533 SOC_SINGLE_TLV("ADC1 +6dB Capture Volume", PEB2466_CR3(1), 3, 1, 0, peb2466_gain_c_tlv), 534 SOC_SINGLE_TLV("ADC2 +6dB Capture Volume", PEB2466_CR3(2), 3, 1, 0, peb2466_gain_c_tlv), 535 SOC_SINGLE_TLV("ADC3 +6dB Capture Volume", PEB2466_CR3(3), 3, 1, 0, peb2466_gain_c_tlv), 536 537 /* Tone generators */ 538 SOC_ENUM_EXT("DAC0 TG1 Freq", peb2466_tg_freq[0][0], 539 peb2466_tg_freq_get, peb2466_tg_freq_put), 540 SOC_ENUM_EXT("DAC1 TG1 Freq", peb2466_tg_freq[1][0], 541 peb2466_tg_freq_get, peb2466_tg_freq_put), 542 SOC_ENUM_EXT("DAC2 TG1 Freq", peb2466_tg_freq[2][0], 543 peb2466_tg_freq_get, peb2466_tg_freq_put), 544 SOC_ENUM_EXT("DAC3 TG1 Freq", peb2466_tg_freq[3][0], 545 peb2466_tg_freq_get, peb2466_tg_freq_put), 546 547 SOC_ENUM_EXT("DAC0 TG2 Freq", peb2466_tg_freq[0][1], 548 peb2466_tg_freq_get, peb2466_tg_freq_put), 549 SOC_ENUM_EXT("DAC1 TG2 Freq", peb2466_tg_freq[1][1], 550 peb2466_tg_freq_get, peb2466_tg_freq_put), 551 SOC_ENUM_EXT("DAC2 TG2 Freq", peb2466_tg_freq[2][1], 552 peb2466_tg_freq_get, peb2466_tg_freq_put), 553 SOC_ENUM_EXT("DAC3 TG2 Freq", peb2466_tg_freq[3][1], 554 peb2466_tg_freq_get, peb2466_tg_freq_put), 555 }; 556 557 static const struct snd_soc_dapm_widget peb2466_dapm_widgets[] = { 558 SND_SOC_DAPM_SUPPLY("CH0 PWR", PEB2466_CR1(0), 0, 0, NULL, 0), 559 SND_SOC_DAPM_SUPPLY("CH1 PWR", PEB2466_CR1(1), 0, 0, NULL, 0), 560 SND_SOC_DAPM_SUPPLY("CH2 PWR", PEB2466_CR1(2), 0, 0, NULL, 0), 561 SND_SOC_DAPM_SUPPLY("CH3 PWR", PEB2466_CR1(3), 0, 0, NULL, 0), 562 563 SND_SOC_DAPM_DAC("CH0 DIN", "Playback", SND_SOC_NOPM, 0, 0), 564 SND_SOC_DAPM_DAC("CH1 DIN", "Playback", SND_SOC_NOPM, 0, 0), 565 SND_SOC_DAPM_DAC("CH2 DIN", "Playback", SND_SOC_NOPM, 0, 0), 566 SND_SOC_DAPM_DAC("CH3 DIN", "Playback", SND_SOC_NOPM, 0, 0), 567 568 SND_SOC_DAPM_SIGGEN("CH0 TG1"), 569 SND_SOC_DAPM_SIGGEN("CH1 TG1"), 570 SND_SOC_DAPM_SIGGEN("CH2 TG1"), 571 SND_SOC_DAPM_SIGGEN("CH3 TG1"), 572 573 SND_SOC_DAPM_SIGGEN("CH0 TG2"), 574 SND_SOC_DAPM_SIGGEN("CH1 TG2"), 575 SND_SOC_DAPM_SIGGEN("CH2 TG2"), 576 SND_SOC_DAPM_SIGGEN("CH3 TG2"), 577 578 SND_SOC_DAPM_MIXER("DAC0 Mixer", SND_SOC_NOPM, 0, 0, 579 peb2466_ch0_out_mix_controls, 580 ARRAY_SIZE(peb2466_ch0_out_mix_controls)), 581 SND_SOC_DAPM_MIXER("DAC1 Mixer", SND_SOC_NOPM, 0, 0, 582 peb2466_ch1_out_mix_controls, 583 ARRAY_SIZE(peb2466_ch1_out_mix_controls)), 584 SND_SOC_DAPM_MIXER("DAC2 Mixer", SND_SOC_NOPM, 0, 0, 585 peb2466_ch2_out_mix_controls, 586 ARRAY_SIZE(peb2466_ch2_out_mix_controls)), 587 SND_SOC_DAPM_MIXER("DAC3 Mixer", SND_SOC_NOPM, 0, 0, 588 peb2466_ch3_out_mix_controls, 589 ARRAY_SIZE(peb2466_ch3_out_mix_controls)), 590 591 SND_SOC_DAPM_PGA("DAC0 PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 592 SND_SOC_DAPM_PGA("DAC1 PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 593 SND_SOC_DAPM_PGA("DAC2 PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 594 SND_SOC_DAPM_PGA("DAC3 PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 595 596 SND_SOC_DAPM_OUTPUT("OUT0"), 597 SND_SOC_DAPM_OUTPUT("OUT1"), 598 SND_SOC_DAPM_OUTPUT("OUT2"), 599 SND_SOC_DAPM_OUTPUT("OUT3"), 600 601 SND_SOC_DAPM_INPUT("IN0"), 602 SND_SOC_DAPM_INPUT("IN1"), 603 SND_SOC_DAPM_INPUT("IN2"), 604 SND_SOC_DAPM_INPUT("IN3"), 605 606 SND_SOC_DAPM_DAC("ADC0", "Capture", SND_SOC_NOPM, 0, 0), 607 SND_SOC_DAPM_DAC("ADC1", "Capture", SND_SOC_NOPM, 0, 0), 608 SND_SOC_DAPM_DAC("ADC2", "Capture", SND_SOC_NOPM, 0, 0), 609 SND_SOC_DAPM_DAC("ADC3", "Capture", SND_SOC_NOPM, 0, 0), 610 }; 611 612 static const struct snd_soc_dapm_route peb2466_dapm_routes[] = { 613 { "CH0 DIN", NULL, "CH0 PWR" }, 614 { "CH1 DIN", NULL, "CH1 PWR" }, 615 { "CH2 DIN", NULL, "CH2 PWR" }, 616 { "CH3 DIN", NULL, "CH3 PWR" }, 617 618 { "CH0 TG1", NULL, "CH0 PWR" }, 619 { "CH1 TG1", NULL, "CH1 PWR" }, 620 { "CH2 TG1", NULL, "CH2 PWR" }, 621 { "CH3 TG1", NULL, "CH3 PWR" }, 622 623 { "CH0 TG2", NULL, "CH0 PWR" }, 624 { "CH1 TG2", NULL, "CH1 PWR" }, 625 { "CH2 TG2", NULL, "CH2 PWR" }, 626 { "CH3 TG2", NULL, "CH3 PWR" }, 627 628 { "DAC0 Mixer", "TG1 Switch", "CH0 TG1" }, 629 { "DAC0 Mixer", "TG2 Switch", "CH0 TG2" }, 630 { "DAC0 Mixer", "Voice Switch", "CH0 DIN" }, 631 { "DAC0 Mixer", NULL, "CH0 DIN" }, 632 633 { "DAC1 Mixer", "TG1 Switch", "CH1 TG1" }, 634 { "DAC1 Mixer", "TG2 Switch", "CH1 TG2" }, 635 { "DAC1 Mixer", "Voice Switch", "CH1 DIN" }, 636 { "DAC1 Mixer", NULL, "CH1 DIN" }, 637 638 { "DAC2 Mixer", "TG1 Switch", "CH2 TG1" }, 639 { "DAC2 Mixer", "TG2 Switch", "CH2 TG2" }, 640 { "DAC2 Mixer", "Voice Switch", "CH2 DIN" }, 641 { "DAC2 Mixer", NULL, "CH2 DIN" }, 642 643 { "DAC3 Mixer", "TG1 Switch", "CH3 TG1" }, 644 { "DAC3 Mixer", "TG2 Switch", "CH3 TG2" }, 645 { "DAC3 Mixer", "Voice Switch", "CH3 DIN" }, 646 { "DAC3 Mixer", NULL, "CH3 DIN" }, 647 648 { "DAC0 PGA", NULL, "DAC0 Mixer" }, 649 { "DAC1 PGA", NULL, "DAC1 Mixer" }, 650 { "DAC2 PGA", NULL, "DAC2 Mixer" }, 651 { "DAC3 PGA", NULL, "DAC3 Mixer" }, 652 653 { "OUT0", NULL, "DAC0 PGA" }, 654 { "OUT1", NULL, "DAC1 PGA" }, 655 { "OUT2", NULL, "DAC2 PGA" }, 656 { "OUT3", NULL, "DAC3 PGA" }, 657 658 { "ADC0", NULL, "IN0" }, 659 { "ADC1", NULL, "IN1" }, 660 { "ADC2", NULL, "IN2" }, 661 { "ADC3", NULL, "IN3" }, 662 663 { "ADC0", NULL, "CH0 PWR" }, 664 { "ADC1", NULL, "CH1 PWR" }, 665 { "ADC2", NULL, "CH2 PWR" }, 666 { "ADC3", NULL, "CH3 PWR" }, 667 }; 668 669 static int peb2466_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 670 unsigned int rx_mask, int slots, int width) 671 { 672 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component); 673 unsigned int chan; 674 unsigned int mask; 675 u8 slot; 676 int ret; 677 678 switch (width) { 679 case 0: 680 /* Not set -> default 8 */ 681 case 8: 682 break; 683 default: 684 dev_err(dai->dev, "tdm slot width %d not supported\n", width); 685 return -EINVAL; 686 } 687 688 mask = tx_mask; 689 slot = 0; 690 chan = 0; 691 while (mask && chan < PEB2466_NB_CHANNEL) { 692 if (mask & 0x1) { 693 ret = regmap_write(peb2466->regmap, PEB2466_CR5(chan), slot); 694 if (ret) { 695 dev_err(dai->dev, "chan %d set tx tdm slot failed (%d)\n", 696 chan, ret); 697 return ret; 698 } 699 chan++; 700 } 701 mask >>= 1; 702 slot++; 703 } 704 if (mask) { 705 dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n", 706 tx_mask, PEB2466_NB_CHANNEL); 707 return -EINVAL; 708 } 709 peb2466->max_chan_playback = chan; 710 711 mask = rx_mask; 712 slot = 0; 713 chan = 0; 714 while (mask && chan < PEB2466_NB_CHANNEL) { 715 if (mask & 0x1) { 716 ret = regmap_write(peb2466->regmap, PEB2466_CR4(chan), slot); 717 if (ret) { 718 dev_err(dai->dev, "chan %d set rx tdm slot failed (%d)\n", 719 chan, ret); 720 return ret; 721 } 722 chan++; 723 } 724 mask >>= 1; 725 slot++; 726 } 727 if (mask) { 728 dev_err(dai->dev, "too much rx slots defined (mask = 0x%x) support max %d\n", 729 rx_mask, PEB2466_NB_CHANNEL); 730 return -EINVAL; 731 } 732 peb2466->max_chan_capture = chan; 733 734 return 0; 735 } 736 737 static int peb2466_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 738 { 739 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component); 740 u8 xr6; 741 742 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 743 case SND_SOC_DAIFMT_DSP_A: 744 xr6 = PEB2466_XR6_PCM_OFFSET(1); 745 break; 746 case SND_SOC_DAIFMT_DSP_B: 747 xr6 = PEB2466_XR6_PCM_OFFSET(0); 748 break; 749 default: 750 dev_err(dai->dev, "Unsupported format 0x%x\n", 751 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 752 return -EINVAL; 753 } 754 return regmap_write(peb2466->regmap, PEB2466_XR6, xr6); 755 } 756 757 static int peb2466_dai_hw_params(struct snd_pcm_substream *substream, 758 struct snd_pcm_hw_params *params, 759 struct snd_soc_dai *dai) 760 { 761 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component); 762 unsigned int ch; 763 int ret; 764 u8 cr1; 765 766 switch (params_format(params)) { 767 case SNDRV_PCM_FORMAT_MU_LAW: 768 cr1 = PEB2466_CR1_LAW_MULAW; 769 break; 770 case SNDRV_PCM_FORMAT_A_LAW: 771 cr1 = PEB2466_CR1_LAW_ALAW; 772 break; 773 default: 774 dev_err(&peb2466->spi->dev, "Unsupported format 0x%x\n", 775 params_format(params)); 776 return -EINVAL; 777 } 778 779 for (ch = 0; ch < PEB2466_NB_CHANNEL; ch++) { 780 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR1(ch), 781 PEB2466_CR1_LAW_MASK, cr1); 782 if (ret) 783 return ret; 784 } 785 786 return 0; 787 } 788 789 static const unsigned int peb2466_sample_bits[] = {8}; 790 791 static struct snd_pcm_hw_constraint_list peb2466_sample_bits_constr = { 792 .list = peb2466_sample_bits, 793 .count = ARRAY_SIZE(peb2466_sample_bits), 794 }; 795 796 static int peb2466_dai_startup(struct snd_pcm_substream *substream, 797 struct snd_soc_dai *dai) 798 { 799 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component); 800 unsigned int max_ch; 801 int ret; 802 803 max_ch = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 804 peb2466->max_chan_playback : peb2466->max_chan_capture; 805 806 /* 807 * Disable stream support (min = 0, max = 0) if no timeslots were 808 * configured. 809 */ 810 ret = snd_pcm_hw_constraint_minmax(substream->runtime, 811 SNDRV_PCM_HW_PARAM_CHANNELS, 812 max_ch ? 1 : 0, max_ch); 813 if (ret < 0) 814 return ret; 815 816 return snd_pcm_hw_constraint_list(substream->runtime, 0, 817 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 818 &peb2466_sample_bits_constr); 819 } 820 821 static const u64 peb2466_dai_formats = 822 SND_SOC_POSSIBLE_DAIFMT_DSP_A | 823 SND_SOC_POSSIBLE_DAIFMT_DSP_B; 824 825 static const struct snd_soc_dai_ops peb2466_dai_ops = { 826 .startup = peb2466_dai_startup, 827 .hw_params = peb2466_dai_hw_params, 828 .set_tdm_slot = peb2466_dai_set_tdm_slot, 829 .set_fmt = peb2466_dai_set_fmt, 830 .auto_selectable_formats = &peb2466_dai_formats, 831 .num_auto_selectable_formats = 1, 832 }; 833 834 static struct snd_soc_dai_driver peb2466_dai_driver = { 835 .name = "peb2466", 836 .playback = { 837 .stream_name = "Playback", 838 .channels_min = 1, 839 .channels_max = PEB2466_NB_CHANNEL, 840 .rates = SNDRV_PCM_RATE_8000, 841 .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, 842 }, 843 .capture = { 844 .stream_name = "Capture", 845 .channels_min = 1, 846 .channels_max = PEB2466_NB_CHANNEL, 847 .rates = SNDRV_PCM_RATE_8000, 848 .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, 849 }, 850 .ops = &peb2466_dai_ops, 851 }; 852 853 static int peb2466_reset_audio(struct peb2466 *peb2466) 854 { 855 static const struct reg_sequence reg_reset[] = { 856 { .reg = PEB2466_XR6, .def = 0x00 }, 857 858 { .reg = PEB2466_CR5(0), .def = 0x00 }, 859 { .reg = PEB2466_CR4(0), .def = 0x00 }, 860 { .reg = PEB2466_CR3(0), .def = 0x00 }, 861 { .reg = PEB2466_CR2(0), .def = 0x00 }, 862 { .reg = PEB2466_CR1(0), .def = 0x00 }, 863 { .reg = PEB2466_CR0(0), .def = PEB2466_CR0_IMR1 }, 864 865 { .reg = PEB2466_CR5(1), .def = 0x00 }, 866 { .reg = PEB2466_CR4(1), .def = 0x00 }, 867 { .reg = PEB2466_CR3(1), .def = 0x00 }, 868 { .reg = PEB2466_CR2(1), .def = 0x00 }, 869 { .reg = PEB2466_CR1(1), .def = 0x00 }, 870 { .reg = PEB2466_CR0(1), .def = PEB2466_CR0_IMR1 }, 871 872 { .reg = PEB2466_CR5(2), .def = 0x00 }, 873 { .reg = PEB2466_CR4(2), .def = 0x00 }, 874 { .reg = PEB2466_CR3(2), .def = 0x00 }, 875 { .reg = PEB2466_CR2(2), .def = 0x00 }, 876 { .reg = PEB2466_CR1(2), .def = 0x00 }, 877 { .reg = PEB2466_CR0(2), .def = PEB2466_CR0_IMR1 }, 878 879 { .reg = PEB2466_CR5(3), .def = 0x00 }, 880 { .reg = PEB2466_CR4(3), .def = 0x00 }, 881 { .reg = PEB2466_CR3(3), .def = 0x00 }, 882 { .reg = PEB2466_CR2(3), .def = 0x00 }, 883 { .reg = PEB2466_CR1(3), .def = 0x00 }, 884 { .reg = PEB2466_CR0(3), .def = PEB2466_CR0_IMR1 }, 885 }; 886 static const u8 imr1_p1[8] = {0x00, 0x90, 0x09, 0x00, 0x90, 0x09, 0x00, 0x00}; 887 static const u8 imr1_p2[8] = {0x7F, 0xFF, 0x00, 0x00, 0x90, 0x14, 0x40, 0x08}; 888 static const u8 zero[8] = {0}; 889 int ret; 890 int i; 891 892 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 893 peb2466->ch[i].tg1_freq_item = PEB2466_TONE_1000HZ; 894 peb2466->ch[i].tg2_freq_item = PEB2466_TONE_1000HZ; 895 896 /* 897 * Even if not used, disabling IM/R1 filter is not recommended. 898 * Instead, we must configure it with default coefficients and 899 * enable it. 900 * The filter will be enabled right after (in the following 901 * regmap_multi_reg_write() call). 902 */ 903 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P1(i), imr1_p1, 8); 904 if (ret) 905 return ret; 906 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P2(i), imr1_p2, 8); 907 if (ret) 908 return ret; 909 910 /* Set all other filters coefficients to zero */ 911 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P1(i), zero, 8); 912 if (ret) 913 return ret; 914 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P2(i), zero, 8); 915 if (ret) 916 return ret; 917 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P3(i), zero, 8); 918 if (ret) 919 return ret; 920 ret = peb2466_write_buf(peb2466, PEB2466_FRX_FILTER(i), zero, 8); 921 if (ret) 922 return ret; 923 ret = peb2466_write_buf(peb2466, PEB2466_FRR_FILTER(i), zero, 8); 924 if (ret) 925 return ret; 926 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), zero, 4); 927 if (ret) 928 return ret; 929 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), zero, 4); 930 if (ret) 931 return ret; 932 } 933 934 return regmap_multi_reg_write(peb2466->regmap, reg_reset, ARRAY_SIZE(reg_reset)); 935 } 936 937 static int peb2466_fw_parse_thfilter(struct snd_soc_component *component, 938 u16 tag, u32 lng, const u8 *data) 939 { 940 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 941 u8 mask; 942 int ret; 943 int i; 944 945 dev_info(component->dev, "fw TH filter: mask %x, %*phN\n", *data, 946 lng - 1, data + 1); 947 948 /* 949 * TH_FILTER TLV data: 950 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 951 * - @1 8 bytes: TH-Filter coefficients part1 952 * - @9 8 bytes: TH-Filter coefficients part2 953 * - @17 8 bytes: TH-Filter coefficients part3 954 */ 955 mask = *data; 956 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 957 if (!(mask & (1 << i))) 958 continue; 959 960 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 961 PEB2466_CR0_TH, 0); 962 if (ret) 963 return ret; 964 965 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P1(i), data + 1, 8); 966 if (ret) 967 return ret; 968 969 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P2(i), data + 9, 8); 970 if (ret) 971 return ret; 972 973 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P3(i), data + 17, 8); 974 if (ret) 975 return ret; 976 977 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 978 PEB2466_CR0_TH | PEB2466_CR0_THSEL_MASK, 979 PEB2466_CR0_TH | PEB2466_CR0_THSEL(i)); 980 if (ret) 981 return ret; 982 } 983 return 0; 984 } 985 986 static int peb2466_fw_parse_imr1filter(struct snd_soc_component *component, 987 u16 tag, u32 lng, const u8 *data) 988 { 989 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 990 u8 mask; 991 int ret; 992 int i; 993 994 dev_info(component->dev, "fw IM/R1 filter: mask %x, %*phN\n", *data, 995 lng - 1, data + 1); 996 997 /* 998 * IMR1_FILTER TLV data: 999 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1000 * - @1 8 bytes: IM/R1-Filter coefficients part1 1001 * - @9 8 bytes: IM/R1-Filter coefficients part2 1002 */ 1003 mask = *data; 1004 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1005 if (!(mask & (1 << i))) 1006 continue; 1007 1008 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1009 PEB2466_CR0_IMR1, 0); 1010 if (ret) 1011 return ret; 1012 1013 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P1(i), data + 1, 8); 1014 if (ret) 1015 return ret; 1016 1017 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P2(i), data + 9, 8); 1018 if (ret) 1019 return ret; 1020 1021 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1022 PEB2466_CR0_IMR1, PEB2466_CR0_IMR1); 1023 if (ret) 1024 return ret; 1025 } 1026 return 0; 1027 } 1028 1029 static int peb2466_fw_parse_frxfilter(struct snd_soc_component *component, 1030 u16 tag, u32 lng, const u8 *data) 1031 { 1032 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1033 u8 mask; 1034 int ret; 1035 int i; 1036 1037 dev_info(component->dev, "fw FRX filter: mask %x, %*phN\n", *data, 1038 lng - 1, data + 1); 1039 1040 /* 1041 * FRX_FILTER TLV data: 1042 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1043 * - @1 8 bytes: FRX-Filter coefficients 1044 */ 1045 mask = *data; 1046 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1047 if (!(mask & (1 << i))) 1048 continue; 1049 1050 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1051 PEB2466_CR0_FRX, 0); 1052 if (ret) 1053 return ret; 1054 1055 ret = peb2466_write_buf(peb2466, PEB2466_FRX_FILTER(i), data + 1, 8); 1056 if (ret) 1057 return ret; 1058 1059 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1060 PEB2466_CR0_FRX, PEB2466_CR0_FRX); 1061 if (ret) 1062 return ret; 1063 } 1064 return 0; 1065 } 1066 1067 static int peb2466_fw_parse_frrfilter(struct snd_soc_component *component, 1068 u16 tag, u32 lng, const u8 *data) 1069 { 1070 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1071 u8 mask; 1072 int ret; 1073 int i; 1074 1075 dev_info(component->dev, "fw FRR filter: mask %x, %*phN\n", *data, 1076 lng - 1, data + 1); 1077 1078 /* 1079 * FRR_FILTER TLV data: 1080 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1081 * - @1 8 bytes: FRR-Filter coefficients 1082 */ 1083 mask = *data; 1084 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1085 if (!(mask & (1 << i))) 1086 continue; 1087 1088 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1089 PEB2466_CR0_FRR, 0); 1090 if (ret) 1091 return ret; 1092 1093 ret = peb2466_write_buf(peb2466, PEB2466_FRR_FILTER(i), data + 1, 8); 1094 if (ret) 1095 return ret; 1096 1097 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1098 PEB2466_CR0_FRR, PEB2466_CR0_FRR); 1099 if (ret) 1100 return ret; 1101 } 1102 return 0; 1103 } 1104 1105 static int peb2466_fw_parse_axfilter(struct snd_soc_component *component, 1106 u16 tag, u32 lng, const u8 *data) 1107 { 1108 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1109 u8 mask; 1110 int ret; 1111 int i; 1112 1113 dev_info(component->dev, "fw AX filter: mask %x, %*phN\n", *data, 1114 lng - 1, data + 1); 1115 1116 /* 1117 * AX_FILTER TLV data: 1118 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1119 * - @1 4 bytes: AX-Filter coefficients 1120 */ 1121 mask = *data; 1122 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1123 if (!(mask & (1 << i))) 1124 continue; 1125 1126 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1127 PEB2466_CR0_AX, 0); 1128 if (ret) 1129 return ret; 1130 1131 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), data + 1, 4); 1132 if (ret) 1133 return ret; 1134 1135 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1136 PEB2466_CR0_AX, PEB2466_CR0_AX); 1137 if (ret) 1138 return ret; 1139 } 1140 return 0; 1141 } 1142 1143 static int peb2466_fw_parse_arfilter(struct snd_soc_component *component, 1144 u16 tag, u32 lng, const u8 *data) 1145 { 1146 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1147 u8 mask; 1148 int ret; 1149 int i; 1150 1151 dev_info(component->dev, "fw AR filter: mask %x, %*phN\n", *data, 1152 lng - 1, data + 1); 1153 1154 /* 1155 * AR_FILTER TLV data: 1156 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1157 * - @1 4 bytes: AR-Filter coefficients 1158 */ 1159 mask = *data; 1160 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1161 if (!(mask & (1 << i))) 1162 continue; 1163 1164 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1165 PEB2466_CR0_AR, 0); 1166 if (ret) 1167 return ret; 1168 1169 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), data + 1, 4); 1170 if (ret) 1171 return ret; 1172 1173 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1174 PEB2466_CR0_AR, PEB2466_CR0_AR); 1175 if (ret) 1176 return ret; 1177 } 1178 return 0; 1179 } 1180 1181 static const char * const peb2466_ax_ctrl_names[] = { 1182 "ADC0 Capture Volume", 1183 "ADC1 Capture Volume", 1184 "ADC2 Capture Volume", 1185 "ADC3 Capture Volume", 1186 }; 1187 1188 static int peb2466_fw_parse_axtable(struct snd_soc_component *component, 1189 u16 tag, u32 lng, const u8 *data) 1190 { 1191 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1192 struct peb2466_lkup_ctrl *lkup_ctrl; 1193 struct peb2466_lookup *lookup; 1194 u8 (*table)[4]; 1195 u32 table_size; 1196 u32 init_index; 1197 s32 min_val; 1198 s32 step; 1199 u8 mask; 1200 int ret; 1201 int i; 1202 1203 /* 1204 * AX_TABLE TLV data: 1205 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1206 * - @1 32bits signed: Min table value in centi dB (MinVal) 1207 * ie -300 means -3.0 dB 1208 * - @5 32bits signed: Step from on item to other item in centi dB (Step) 1209 * ie 25 means 0.25 dB) 1210 * - @9 32bits unsigned: Item index in the table to use for the initial 1211 * value 1212 * - @13 N*4 bytes: Table composed of 4 bytes items. 1213 * Each item correspond to an AX filter value. 1214 * 1215 * The conversion from raw value item in the table to/from the value in 1216 * dB is: Raw value at index i <-> (MinVal + i * Step) in centi dB. 1217 */ 1218 1219 /* Check Lng and extract the table size. */ 1220 if (lng < 13 || ((lng - 13) % 4)) { 1221 dev_err(component->dev, "fw AX table lng %u invalid\n", lng); 1222 return -EINVAL; 1223 } 1224 table_size = lng - 13; 1225 1226 min_val = get_unaligned_be32(data + 1); 1227 step = get_unaligned_be32(data + 5); 1228 init_index = get_unaligned_be32(data + 9); 1229 if (init_index >= (table_size / 4)) { 1230 dev_err(component->dev, "fw AX table index %u out of table[%u]\n", 1231 init_index, table_size / 4); 1232 return -EINVAL; 1233 } 1234 1235 dev_info(component->dev, 1236 "fw AX table: mask %x, min %d, step %d, %u items, tbl[%u] %*phN\n", 1237 *data, min_val, step, table_size / 4, init_index, 1238 4, data + 13 + (init_index * 4)); 1239 1240 BUILD_BUG_ON(sizeof(*table) != 4); 1241 table = devm_kzalloc(&peb2466->spi->dev, table_size, GFP_KERNEL); 1242 if (!table) 1243 return -ENOMEM; 1244 memcpy(table, data + 13, table_size); 1245 1246 mask = *data; 1247 BUILD_BUG_ON(ARRAY_SIZE(peb2466_ax_ctrl_names) != ARRAY_SIZE(peb2466->ch)); 1248 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1249 if (!(mask & (1 << i))) 1250 continue; 1251 1252 lookup = &peb2466->ch[i].ax_lookup; 1253 lookup->table = table; 1254 lookup->count = table_size / 4; 1255 1256 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1257 PEB2466_CR0_AX, 0); 1258 if (ret) 1259 return ret; 1260 1261 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), 1262 lookup->table[init_index], 4); 1263 if (ret) 1264 return ret; 1265 1266 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1267 PEB2466_CR0_AX, PEB2466_CR0_AX); 1268 if (ret) 1269 return ret; 1270 1271 lkup_ctrl = &peb2466->ch[i].ax_lkup_ctrl; 1272 lkup_ctrl->lookup = lookup; 1273 lkup_ctrl->reg = PEB2466_AX_FILTER(i); 1274 lkup_ctrl->index = init_index; 1275 1276 ret = peb2466_add_lkup_ctrl(component, lkup_ctrl, 1277 peb2466_ax_ctrl_names[i], 1278 min_val, step); 1279 if (ret) 1280 return ret; 1281 } 1282 return 0; 1283 } 1284 1285 static const char * const peb2466_ar_ctrl_names[] = { 1286 "DAC0 Playback Volume", 1287 "DAC1 Playback Volume", 1288 "DAC2 Playback Volume", 1289 "DAC3 Playback Volume", 1290 }; 1291 1292 static int peb2466_fw_parse_artable(struct snd_soc_component *component, 1293 u16 tag, u32 lng, const u8 *data) 1294 { 1295 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1296 struct peb2466_lkup_ctrl *lkup_ctrl; 1297 struct peb2466_lookup *lookup; 1298 u8 (*table)[4]; 1299 u32 table_size; 1300 u32 init_index; 1301 s32 min_val; 1302 s32 step; 1303 u8 mask; 1304 int ret; 1305 int i; 1306 1307 /* 1308 * AR_TABLE TLV data: 1309 * - @0 1 byte: Chan mask (bit set means related channel is concerned) 1310 * - @1 32bits signed: Min table value in centi dB (MinVal) 1311 * ie -300 means -3.0 dB 1312 * - @5 32bits signed: Step from on item to other item in centi dB (Step) 1313 * ie 25 means 0.25 dB) 1314 * - @9 32bits unsigned: Item index in the table to use for the initial 1315 * value 1316 * - @13 N*4 bytes: Table composed of 4 bytes items. 1317 * Each item correspond to an AR filter value. 1318 * 1319 * The conversion from raw value item in the table to/from the value in 1320 * dB is: Raw value at index i <-> (MinVal + i * Step) in centi dB. 1321 */ 1322 1323 /* Check Lng and extract the table size. */ 1324 if (lng < 13 || ((lng - 13) % 4)) { 1325 dev_err(component->dev, "fw AR table lng %u invalid\n", lng); 1326 return -EINVAL; 1327 } 1328 table_size = lng - 13; 1329 1330 min_val = get_unaligned_be32(data + 1); 1331 step = get_unaligned_be32(data + 5); 1332 init_index = get_unaligned_be32(data + 9); 1333 if (init_index >= (table_size / 4)) { 1334 dev_err(component->dev, "fw AR table index %u out of table[%u]\n", 1335 init_index, table_size / 4); 1336 return -EINVAL; 1337 } 1338 1339 dev_info(component->dev, 1340 "fw AR table: mask %x, min %d, step %d, %u items, tbl[%u] %*phN\n", 1341 *data, min_val, step, table_size / 4, init_index, 1342 4, data + 13 + (init_index * 4)); 1343 1344 BUILD_BUG_ON(sizeof(*table) != 4); 1345 table = devm_kzalloc(&peb2466->spi->dev, table_size, GFP_KERNEL); 1346 if (!table) 1347 return -ENOMEM; 1348 memcpy(table, data + 13, table_size); 1349 1350 mask = *data; 1351 BUILD_BUG_ON(ARRAY_SIZE(peb2466_ar_ctrl_names) != ARRAY_SIZE(peb2466->ch)); 1352 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) { 1353 if (!(mask & (1 << i))) 1354 continue; 1355 1356 lookup = &peb2466->ch[i].ar_lookup; 1357 lookup->table = table; 1358 lookup->count = table_size / 4; 1359 1360 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1361 PEB2466_CR0_AR, 0); 1362 if (ret) 1363 return ret; 1364 1365 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), 1366 lookup->table[init_index], 4); 1367 if (ret) 1368 return ret; 1369 1370 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i), 1371 PEB2466_CR0_AR, PEB2466_CR0_AR); 1372 if (ret) 1373 return ret; 1374 1375 lkup_ctrl = &peb2466->ch[i].ar_lkup_ctrl; 1376 lkup_ctrl->lookup = lookup; 1377 lkup_ctrl->reg = PEB2466_AR_FILTER(i); 1378 lkup_ctrl->index = init_index; 1379 1380 ret = peb2466_add_lkup_ctrl(component, lkup_ctrl, 1381 peb2466_ar_ctrl_names[i], 1382 min_val, step); 1383 if (ret) 1384 return ret; 1385 } 1386 return 0; 1387 } 1388 1389 struct peb2466_fw_tag_def { 1390 u16 tag; 1391 u32 lng_min; 1392 u32 lng_max; 1393 int (*parse)(struct snd_soc_component *component, 1394 u16 tag, u32 lng, const u8 *data); 1395 }; 1396 1397 #define PEB2466_TAG_DEF_LNG_EQ(__tag, __lng, __parse) { \ 1398 .tag = __tag, \ 1399 .lng_min = __lng, \ 1400 .lng_max = __lng, \ 1401 .parse = __parse, \ 1402 } 1403 1404 #define PEB2466_TAG_DEF_LNG_MIN(__tag, __lng_min, __parse) { \ 1405 .tag = __tag, \ 1406 .lng_min = __lng_min, \ 1407 .lng_max = U32_MAX, \ 1408 .parse = __parse, \ 1409 } 1410 1411 static const struct peb2466_fw_tag_def peb2466_fw_tag_defs[] = { 1412 /* TH FILTER */ 1413 PEB2466_TAG_DEF_LNG_EQ(0x0001, 1 + 3 * 8, peb2466_fw_parse_thfilter), 1414 /* IMR1 FILTER */ 1415 PEB2466_TAG_DEF_LNG_EQ(0x0002, 1 + 2 * 8, peb2466_fw_parse_imr1filter), 1416 /* FRX FILTER */ 1417 PEB2466_TAG_DEF_LNG_EQ(0x0003, 1 + 8, peb2466_fw_parse_frxfilter), 1418 /* FRR FILTER */ 1419 PEB2466_TAG_DEF_LNG_EQ(0x0004, 1 + 8, peb2466_fw_parse_frrfilter), 1420 /* AX FILTER */ 1421 PEB2466_TAG_DEF_LNG_EQ(0x0005, 1 + 4, peb2466_fw_parse_axfilter), 1422 /* AR FILTER */ 1423 PEB2466_TAG_DEF_LNG_EQ(0x0006, 1 + 4, peb2466_fw_parse_arfilter), 1424 /* AX TABLE */ 1425 PEB2466_TAG_DEF_LNG_MIN(0x0105, 1 + 3 * 4, peb2466_fw_parse_axtable), 1426 /* AR TABLE */ 1427 PEB2466_TAG_DEF_LNG_MIN(0x0106, 1 + 3 * 4, peb2466_fw_parse_artable), 1428 }; 1429 1430 static const struct peb2466_fw_tag_def *peb2466_fw_get_tag_def(u16 tag) 1431 { 1432 int i; 1433 1434 for (i = 0; i < ARRAY_SIZE(peb2466_fw_tag_defs); i++) { 1435 if (peb2466_fw_tag_defs[i].tag == tag) 1436 return &peb2466_fw_tag_defs[i]; 1437 } 1438 return NULL; 1439 } 1440 1441 static int peb2466_fw_parse(struct snd_soc_component *component, 1442 const u8 *data, size_t size) 1443 { 1444 const struct peb2466_fw_tag_def *tag_def; 1445 size_t left; 1446 const u8 *buf; 1447 u16 val16; 1448 u16 tag; 1449 u32 lng; 1450 int ret; 1451 1452 /* 1453 * Coefficients firmware binary structure (16bits and 32bits are 1454 * big-endian values). 1455 * 1456 * @0, 16bits: Magic (0x2466) 1457 * @2, 16bits: Version (0x0100 for version 1.0) 1458 * @4, 2+4+N bytes: TLV block 1459 * @4+(2+4+N) bytes: Next TLV block 1460 * ... 1461 * 1462 * Detail of a TLV block: 1463 * @0, 16bits: Tag 1464 * @2, 32bits: Lng 1465 * @6, lng bytes: Data 1466 * 1467 * The detail the Data for a given TLV Tag is provided in the related 1468 * parser. 1469 */ 1470 1471 left = size; 1472 buf = data; 1473 1474 if (left < 4) { 1475 dev_err(component->dev, "fw size %zu, exp at least 4\n", left); 1476 return -EINVAL; 1477 } 1478 1479 /* Check magic */ 1480 val16 = get_unaligned_be16(buf); 1481 if (val16 != 0x2466) { 1482 dev_err(component->dev, "fw magic 0x%04x exp 0x2466\n", val16); 1483 return -EINVAL; 1484 } 1485 buf += 2; 1486 left -= 2; 1487 1488 /* Check version */ 1489 val16 = get_unaligned_be16(buf); 1490 if (val16 != 0x0100) { 1491 dev_err(component->dev, "fw magic 0x%04x exp 0x0100\n", val16); 1492 return -EINVAL; 1493 } 1494 buf += 2; 1495 left -= 2; 1496 1497 while (left) { 1498 if (left < 6) { 1499 dev_err(component->dev, "fw %td/%zu left %zu, exp at least 6\n", 1500 buf - data, size, left); 1501 return -EINVAL; 1502 } 1503 /* Check tag and lng */ 1504 tag = get_unaligned_be16(buf); 1505 lng = get_unaligned_be32(buf + 2); 1506 tag_def = peb2466_fw_get_tag_def(tag); 1507 if (!tag_def) { 1508 dev_err(component->dev, "fw %td/%zu tag 0x%04x unknown\n", 1509 buf - data, size, tag); 1510 return -EINVAL; 1511 } 1512 if (lng < tag_def->lng_min || lng > tag_def->lng_max) { 1513 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u, exp [%u;%u]\n", 1514 buf - data, size, tag, lng, tag_def->lng_min, tag_def->lng_max); 1515 return -EINVAL; 1516 } 1517 buf += 6; 1518 left -= 6; 1519 if (left < lng) { 1520 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u, left %zu\n", 1521 buf - data, size, tag, lng, left); 1522 return -EINVAL; 1523 } 1524 1525 /* TLV block is valid -> parse the data part */ 1526 ret = tag_def->parse(component, tag, lng, buf); 1527 if (ret) { 1528 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u parse failed\n", 1529 buf - data, size, tag, lng); 1530 return ret; 1531 } 1532 1533 buf += lng; 1534 left -= lng; 1535 } 1536 return 0; 1537 } 1538 1539 static int peb2466_load_coeffs(struct snd_soc_component *component, const char *fw_name) 1540 { 1541 const struct firmware *fw __free(firmware) = NULL; 1542 int ret; 1543 1544 ret = request_firmware(&fw, fw_name, component->dev); 1545 if (ret) 1546 return ret; 1547 1548 return peb2466_fw_parse(component, fw->data, fw->size); 1549 } 1550 1551 static int peb2466_component_probe(struct snd_soc_component *component) 1552 { 1553 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component); 1554 const char *firmware_name; 1555 int ret; 1556 1557 /* reset peb2466 audio part */ 1558 ret = peb2466_reset_audio(peb2466); 1559 if (ret) 1560 return ret; 1561 1562 ret = of_property_read_string(peb2466->spi->dev.of_node, 1563 "firmware-name", &firmware_name); 1564 if (ret) 1565 return (ret == -EINVAL) ? 0 : ret; 1566 1567 return peb2466_load_coeffs(component, firmware_name); 1568 } 1569 1570 static const struct snd_soc_component_driver peb2466_component_driver = { 1571 .probe = peb2466_component_probe, 1572 .controls = peb2466_controls, 1573 .num_controls = ARRAY_SIZE(peb2466_controls), 1574 .dapm_widgets = peb2466_dapm_widgets, 1575 .num_dapm_widgets = ARRAY_SIZE(peb2466_dapm_widgets), 1576 .dapm_routes = peb2466_dapm_routes, 1577 .num_dapm_routes = ARRAY_SIZE(peb2466_dapm_routes), 1578 .endianness = 1, 1579 }; 1580 1581 /* 1582 * The mapping used for the relationship between the gpio offset and the 1583 * physical pin is the following: 1584 * 1585 * offset pin 1586 * 0 SI1_0 1587 * 1 SI1_1 1588 * 2 SI2_0 1589 * 3 SI2_1 1590 * 4 SI3_0 1591 * 5 SI3_1 1592 * 6 SI4_0 1593 * 7 SI4_1 1594 * 8 SO1_0 1595 * 9 SO1_1 1596 * 10 SO2_0 1597 * 11 SO2_1 1598 * 12 SO3_0 1599 * 13 SO3_1 1600 * 14 SO4_0 1601 * 15 SO4_1 1602 * 16 SB1_0 1603 * 17 SB1_1 1604 * 18 SB2_0 1605 * 19 SB2_1 1606 * 20 SB3_0 1607 * 21 SB3_1 1608 * 22 SB4_0 1609 * 23 SB4_1 1610 * 24 SB1_2 1611 * 25 SB2_2 1612 * 26 SB3_2 1613 * 27 SB4_2 1614 */ 1615 1616 static int peb2466_chip_gpio_offset_to_data_regmask(unsigned int offset, 1617 unsigned int *xr_reg, 1618 unsigned int *mask) 1619 { 1620 if (offset < 16) { 1621 /* 1622 * SIx_{0,1} and SOx_{0,1} 1623 * Read accesses read SIx_{0,1} values 1624 * Write accesses write SOx_{0,1} values 1625 */ 1626 *xr_reg = PEB2466_XR0; 1627 *mask = (1 << (offset % 8)); 1628 return 0; 1629 } 1630 if (offset < 24) { 1631 /* SBx_{0,1} */ 1632 *xr_reg = PEB2466_XR1; 1633 *mask = (1 << (offset - 16)); 1634 return 0; 1635 } 1636 if (offset < 28) { 1637 /* SBx_2 */ 1638 *xr_reg = PEB2466_XR3; 1639 *mask = (1 << (offset - 24 + 4)); 1640 return 0; 1641 } 1642 return -EINVAL; 1643 } 1644 1645 static int peb2466_chip_gpio_offset_to_dir_regmask(unsigned int offset, 1646 unsigned int *xr_reg, 1647 unsigned int *mask) 1648 { 1649 if (offset < 16) { 1650 /* Direction cannot be changed for these GPIOs */ 1651 return -EINVAL; 1652 } 1653 if (offset < 24) { 1654 *xr_reg = PEB2466_XR2; 1655 *mask = (1 << (offset - 16)); 1656 return 0; 1657 } 1658 if (offset < 28) { 1659 *xr_reg = PEB2466_XR3; 1660 *mask = (1 << (offset - 24)); 1661 return 0; 1662 } 1663 return -EINVAL; 1664 } 1665 1666 static unsigned int *peb2466_chip_gpio_get_cache(struct peb2466 *peb2466, 1667 unsigned int xr_reg) 1668 { 1669 unsigned int *cache; 1670 1671 switch (xr_reg) { 1672 case PEB2466_XR0: 1673 cache = &peb2466->gpio.cache.xr0; 1674 break; 1675 case PEB2466_XR1: 1676 cache = &peb2466->gpio.cache.xr1; 1677 break; 1678 case PEB2466_XR2: 1679 cache = &peb2466->gpio.cache.xr2; 1680 break; 1681 case PEB2466_XR3: 1682 cache = &peb2466->gpio.cache.xr3; 1683 break; 1684 default: 1685 cache = NULL; 1686 break; 1687 } 1688 return cache; 1689 } 1690 1691 static int peb2466_chip_gpio_update_bits(struct peb2466 *peb2466, unsigned int xr_reg, 1692 unsigned int mask, unsigned int val) 1693 { 1694 unsigned int tmp; 1695 unsigned int *cache; 1696 int ret; 1697 1698 /* 1699 * Read and write accesses use different peb2466 internal signals (input 1700 * signals on reads and output signals on writes). regmap_update_bits 1701 * cannot be used to read/modify/write the value. 1702 * So, a specific cache value is used. 1703 */ 1704 1705 guard(mutex)(&peb2466->gpio.lock); 1706 1707 cache = peb2466_chip_gpio_get_cache(peb2466, xr_reg); 1708 if (!cache) 1709 return -EINVAL; 1710 1711 tmp = *cache; 1712 tmp &= ~mask; 1713 tmp |= val; 1714 1715 ret = regmap_write(peb2466->regmap, xr_reg, tmp); 1716 if (ret) 1717 return ret; 1718 1719 *cache = tmp; 1720 1721 return 0; 1722 } 1723 1724 static int peb2466_chip_gpio_set(struct gpio_chip *c, unsigned int offset, 1725 int val) 1726 { 1727 struct peb2466 *peb2466 = gpiochip_get_data(c); 1728 unsigned int xr_reg; 1729 unsigned int mask; 1730 int ret; 1731 1732 if (offset < 8) { 1733 /* 1734 * SIx_{0,1} signals cannot be set and writing the related 1735 * register will change the SOx_{0,1} signals 1736 */ 1737 dev_warn(&peb2466->spi->dev, "cannot set gpio %d (read-only)\n", 1738 offset); 1739 return -EINVAL; 1740 } 1741 1742 ret = peb2466_chip_gpio_offset_to_data_regmask(offset, &xr_reg, &mask); 1743 if (ret) { 1744 dev_err(&peb2466->spi->dev, "cannot set gpio %d (%d)\n", 1745 offset, ret); 1746 return ret; 1747 } 1748 1749 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, val ? mask : 0); 1750 if (ret) { 1751 dev_err(&peb2466->spi->dev, "set gpio %d (0x%x, 0x%x) failed (%d)\n", 1752 offset, xr_reg, mask, ret); 1753 } 1754 1755 return ret; 1756 } 1757 1758 static int peb2466_chip_gpio_get(struct gpio_chip *c, unsigned int offset) 1759 { 1760 struct peb2466 *peb2466 = gpiochip_get_data(c); 1761 bool use_cache = false; 1762 unsigned int *cache; 1763 unsigned int xr_reg; 1764 unsigned int mask; 1765 unsigned int val; 1766 int ret; 1767 1768 if (offset >= 8 && offset < 16) { 1769 /* 1770 * SOx_{0,1} signals cannot be read. Reading the related 1771 * register will read the SIx_{0,1} signals. 1772 * Use the cache to get value; 1773 */ 1774 use_cache = true; 1775 } 1776 1777 ret = peb2466_chip_gpio_offset_to_data_regmask(offset, &xr_reg, &mask); 1778 if (ret) { 1779 dev_err(&peb2466->spi->dev, "cannot get gpio %d (%d)\n", 1780 offset, ret); 1781 return -EINVAL; 1782 } 1783 1784 if (use_cache) { 1785 cache = peb2466_chip_gpio_get_cache(peb2466, xr_reg); 1786 if (!cache) 1787 return -EINVAL; 1788 val = *cache; 1789 } else { 1790 ret = regmap_read(peb2466->regmap, xr_reg, &val); 1791 if (ret) { 1792 dev_err(&peb2466->spi->dev, "get gpio %d (0x%x, 0x%x) failed (%d)\n", 1793 offset, xr_reg, mask, ret); 1794 return ret; 1795 } 1796 } 1797 1798 return !!(val & mask); 1799 } 1800 1801 static int peb2466_chip_get_direction(struct gpio_chip *c, unsigned int offset) 1802 { 1803 struct peb2466 *peb2466 = gpiochip_get_data(c); 1804 unsigned int xr_reg; 1805 unsigned int mask; 1806 unsigned int val; 1807 int ret; 1808 1809 if (offset < 8) { 1810 /* SIx_{0,1} */ 1811 return GPIO_LINE_DIRECTION_IN; 1812 } 1813 if (offset < 16) { 1814 /* SOx_{0,1} */ 1815 return GPIO_LINE_DIRECTION_OUT; 1816 } 1817 1818 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask); 1819 if (ret) { 1820 dev_err(&peb2466->spi->dev, "cannot get gpio %d direction (%d)\n", 1821 offset, ret); 1822 return ret; 1823 } 1824 1825 ret = regmap_read(peb2466->regmap, xr_reg, &val); 1826 if (ret) { 1827 dev_err(&peb2466->spi->dev, "get dir gpio %d (0x%x, 0x%x) failed (%d)\n", 1828 offset, xr_reg, mask, ret); 1829 return ret; 1830 } 1831 1832 return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1833 } 1834 1835 static int peb2466_chip_direction_input(struct gpio_chip *c, unsigned int offset) 1836 { 1837 struct peb2466 *peb2466 = gpiochip_get_data(c); 1838 unsigned int xr_reg; 1839 unsigned int mask; 1840 int ret; 1841 1842 if (offset < 8) { 1843 /* SIx_{0,1} */ 1844 return 0; 1845 } 1846 if (offset < 16) { 1847 /* SOx_{0,1} */ 1848 return -EINVAL; 1849 } 1850 1851 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask); 1852 if (ret) { 1853 dev_err(&peb2466->spi->dev, "cannot set gpio %d direction (%d)\n", 1854 offset, ret); 1855 return ret; 1856 } 1857 1858 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, 0); 1859 if (ret) { 1860 dev_err(&peb2466->spi->dev, "Set dir in gpio %d (0x%x, 0x%x) failed (%d)\n", 1861 offset, xr_reg, mask, ret); 1862 return ret; 1863 } 1864 1865 return 0; 1866 } 1867 1868 static int peb2466_chip_direction_output(struct gpio_chip *c, unsigned int offset, int val) 1869 { 1870 struct peb2466 *peb2466 = gpiochip_get_data(c); 1871 unsigned int xr_reg; 1872 unsigned int mask; 1873 int ret; 1874 1875 if (offset < 8) { 1876 /* SIx_{0,1} */ 1877 return -EINVAL; 1878 } 1879 1880 ret = peb2466_chip_gpio_set(c, offset, val); 1881 if (ret) 1882 return ret; 1883 1884 if (offset < 16) { 1885 /* SOx_{0,1} */ 1886 return 0; 1887 } 1888 1889 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask); 1890 if (ret) { 1891 dev_err(&peb2466->spi->dev, "cannot set gpio %d direction (%d)\n", 1892 offset, ret); 1893 return ret; 1894 } 1895 1896 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, mask); 1897 if (ret) { 1898 dev_err(&peb2466->spi->dev, "Set dir in gpio %d (0x%x, 0x%x) failed (%d)\n", 1899 offset, xr_reg, mask, ret); 1900 return ret; 1901 } 1902 1903 return 0; 1904 } 1905 1906 static int peb2466_reset_gpio(struct peb2466 *peb2466) 1907 { 1908 static const struct reg_sequence reg_reset[] = { 1909 /* Output pins at 0, input/output pins as input */ 1910 { .reg = PEB2466_XR0, .def = 0 }, 1911 { .reg = PEB2466_XR1, .def = 0 }, 1912 { .reg = PEB2466_XR2, .def = 0 }, 1913 { .reg = PEB2466_XR3, .def = 0 }, 1914 }; 1915 1916 peb2466->gpio.cache.xr0 = 0; 1917 peb2466->gpio.cache.xr1 = 0; 1918 peb2466->gpio.cache.xr2 = 0; 1919 peb2466->gpio.cache.xr3 = 0; 1920 1921 return regmap_multi_reg_write(peb2466->regmap, reg_reset, ARRAY_SIZE(reg_reset)); 1922 } 1923 1924 static int peb2466_gpio_init(struct peb2466 *peb2466) 1925 { 1926 int ret; 1927 1928 mutex_init(&peb2466->gpio.lock); 1929 1930 ret = peb2466_reset_gpio(peb2466); 1931 if (ret) 1932 return ret; 1933 1934 peb2466->gpio.gpio_chip.owner = THIS_MODULE; 1935 peb2466->gpio.gpio_chip.label = dev_name(&peb2466->spi->dev); 1936 peb2466->gpio.gpio_chip.parent = &peb2466->spi->dev; 1937 peb2466->gpio.gpio_chip.base = -1; 1938 peb2466->gpio.gpio_chip.ngpio = 28; 1939 peb2466->gpio.gpio_chip.get_direction = peb2466_chip_get_direction; 1940 peb2466->gpio.gpio_chip.direction_input = peb2466_chip_direction_input; 1941 peb2466->gpio.gpio_chip.direction_output = peb2466_chip_direction_output; 1942 peb2466->gpio.gpio_chip.get = peb2466_chip_gpio_get; 1943 peb2466->gpio.gpio_chip.set = peb2466_chip_gpio_set; 1944 peb2466->gpio.gpio_chip.can_sleep = true; 1945 1946 return devm_gpiochip_add_data(&peb2466->spi->dev, &peb2466->gpio.gpio_chip, 1947 peb2466); 1948 } 1949 1950 static int peb2466_spi_probe(struct spi_device *spi) 1951 { 1952 struct peb2466 *peb2466; 1953 unsigned long mclk_rate; 1954 int ret; 1955 u8 xr5; 1956 1957 spi->bits_per_word = 8; 1958 ret = spi_setup(spi); 1959 if (ret < 0) 1960 return ret; 1961 1962 peb2466 = devm_kzalloc(&spi->dev, sizeof(*peb2466), GFP_KERNEL); 1963 if (!peb2466) 1964 return -ENOMEM; 1965 1966 peb2466->spi = spi; 1967 1968 peb2466->regmap = devm_regmap_init(&peb2466->spi->dev, NULL, peb2466, 1969 &peb2466_regmap_config); 1970 if (IS_ERR(peb2466->regmap)) 1971 return PTR_ERR(peb2466->regmap); 1972 1973 peb2466->reset_gpio = devm_gpiod_get_optional(&peb2466->spi->dev, 1974 "reset", GPIOD_OUT_LOW); 1975 if (IS_ERR(peb2466->reset_gpio)) 1976 return PTR_ERR(peb2466->reset_gpio); 1977 1978 peb2466->mclk = devm_clk_get_enabled(&peb2466->spi->dev, "mclk"); 1979 if (IS_ERR(peb2466->mclk)) 1980 return PTR_ERR(peb2466->mclk); 1981 1982 if (peb2466->reset_gpio) { 1983 gpiod_set_value_cansleep(peb2466->reset_gpio, 1); 1984 udelay(4); 1985 gpiod_set_value_cansleep(peb2466->reset_gpio, 0); 1986 udelay(4); 1987 } 1988 1989 spi_set_drvdata(spi, peb2466); 1990 1991 mclk_rate = clk_get_rate(peb2466->mclk); 1992 switch (mclk_rate) { 1993 case 1536000: 1994 xr5 = PEB2466_XR5_MCLK_1536; 1995 break; 1996 case 2048000: 1997 xr5 = PEB2466_XR5_MCLK_2048; 1998 break; 1999 case 4096000: 2000 xr5 = PEB2466_XR5_MCLK_4096; 2001 break; 2002 case 8192000: 2003 xr5 = PEB2466_XR5_MCLK_8192; 2004 break; 2005 default: 2006 dev_err(&peb2466->spi->dev, "Unsupported clock rate %lu\n", 2007 mclk_rate); 2008 ret = -EINVAL; 2009 goto failed; 2010 } 2011 ret = regmap_write(peb2466->regmap, PEB2466_XR5, xr5); 2012 if (ret) { 2013 dev_err(&peb2466->spi->dev, "Setting MCLK failed (%d)\n", ret); 2014 goto failed; 2015 } 2016 2017 ret = devm_snd_soc_register_component(&spi->dev, &peb2466_component_driver, 2018 &peb2466_dai_driver, 1); 2019 if (ret) 2020 goto failed; 2021 2022 if (IS_ENABLED(CONFIG_GPIOLIB)) { 2023 ret = peb2466_gpio_init(peb2466); 2024 if (ret) 2025 goto failed; 2026 } 2027 2028 return 0; 2029 2030 failed: 2031 return ret; 2032 } 2033 2034 static const struct of_device_id peb2466_of_match[] = { 2035 { .compatible = "infineon,peb2466", }, 2036 { } 2037 }; 2038 MODULE_DEVICE_TABLE(of, peb2466_of_match); 2039 2040 static const struct spi_device_id peb2466_id_table[] = { 2041 { "peb2466", 0 }, 2042 { } 2043 }; 2044 MODULE_DEVICE_TABLE(spi, peb2466_id_table); 2045 2046 static struct spi_driver peb2466_spi_driver = { 2047 .driver = { 2048 .name = "peb2466", 2049 .of_match_table = peb2466_of_match, 2050 }, 2051 .id_table = peb2466_id_table, 2052 .probe = peb2466_spi_probe, 2053 }; 2054 2055 module_spi_driver(peb2466_spi_driver); 2056 2057 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>"); 2058 MODULE_DESCRIPTION("PEB2466 ALSA SoC driver"); 2059 MODULE_LICENSE("GPL"); 2060