1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/pcs/pcs-xpcs.h> 12 #include <linux/mdio.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 #include <linux/property.h> 16 17 #include "pcs-xpcs.h" 18 19 #define phylink_pcs_to_xpcs(pl_pcs) \ 20 container_of((pl_pcs), struct dw_xpcs, pcs) 21 22 static const int xpcs_usxgmii_features[] = { 23 ETHTOOL_LINK_MODE_Pause_BIT, 24 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 25 ETHTOOL_LINK_MODE_Autoneg_BIT, 26 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 27 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 28 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 29 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 30 __ETHTOOL_LINK_MODE_MASK_NBITS, 31 }; 32 33 static const int xpcs_10gkr_features[] = { 34 ETHTOOL_LINK_MODE_Pause_BIT, 35 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 36 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 37 __ETHTOOL_LINK_MODE_MASK_NBITS, 38 }; 39 40 static const int xpcs_25gbaser_features[] = { 41 ETHTOOL_LINK_MODE_MII_BIT, 42 ETHTOOL_LINK_MODE_Pause_BIT, 43 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 44 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 45 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 46 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 47 __ETHTOOL_LINK_MODE_MASK_NBITS, 48 }; 49 50 static const int xpcs_xlgmii_features[] = { 51 ETHTOOL_LINK_MODE_Pause_BIT, 52 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 53 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 54 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 55 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 56 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 57 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 58 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 59 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 60 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 61 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 62 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 63 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 64 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 65 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 66 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 67 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 68 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 69 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 70 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 71 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 72 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 73 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 74 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 75 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 76 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 77 __ETHTOOL_LINK_MODE_MASK_NBITS, 78 }; 79 80 static const int xpcs_50gbaser_features[] = { 81 ETHTOOL_LINK_MODE_MII_BIT, 82 ETHTOOL_LINK_MODE_Pause_BIT, 83 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 84 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 85 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 86 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 87 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 88 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 89 __ETHTOOL_LINK_MODE_MASK_NBITS, 90 }; 91 92 static const int xpcs_50gbaser2_features[] = { 93 ETHTOOL_LINK_MODE_MII_BIT, 94 ETHTOOL_LINK_MODE_Pause_BIT, 95 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 96 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 97 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 98 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 99 __ETHTOOL_LINK_MODE_MASK_NBITS, 100 }; 101 102 static const int xpcs_100gbasep_features[] = { 103 ETHTOOL_LINK_MODE_MII_BIT, 104 ETHTOOL_LINK_MODE_Pause_BIT, 105 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 106 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 107 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 108 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 109 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 110 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 111 __ETHTOOL_LINK_MODE_MASK_NBITS, 112 }; 113 114 static const int xpcs_10gbaser_features[] = { 115 ETHTOOL_LINK_MODE_Pause_BIT, 116 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 117 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 118 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 119 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 120 ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 121 __ETHTOOL_LINK_MODE_MASK_NBITS, 122 }; 123 124 static const int xpcs_sgmii_features[] = { 125 ETHTOOL_LINK_MODE_Pause_BIT, 126 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 127 ETHTOOL_LINK_MODE_Autoneg_BIT, 128 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 129 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 130 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 131 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 132 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 133 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 134 __ETHTOOL_LINK_MODE_MASK_NBITS, 135 }; 136 137 static const int xpcs_1000basex_features[] = { 138 ETHTOOL_LINK_MODE_Pause_BIT, 139 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 140 ETHTOOL_LINK_MODE_Autoneg_BIT, 141 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 142 __ETHTOOL_LINK_MODE_MASK_NBITS, 143 }; 144 145 static const int xpcs_2500basex_features[] = { 146 ETHTOOL_LINK_MODE_Pause_BIT, 147 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 148 ETHTOOL_LINK_MODE_Autoneg_BIT, 149 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 150 ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 151 __ETHTOOL_LINK_MODE_MASK_NBITS, 152 }; 153 154 struct dw_xpcs_compat { 155 phy_interface_t interface; 156 const int *supported; 157 int an_mode; 158 int (*pma_config)(struct dw_xpcs *xpcs); 159 }; 160 161 struct dw_xpcs_desc { 162 u32 id; 163 u32 mask; 164 const struct dw_xpcs_compat *compat; 165 }; 166 167 static const struct dw_xpcs_compat * 168 xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface) 169 { 170 const struct dw_xpcs_compat *compat; 171 172 for (compat = xpcs->desc->compat; compat->supported; compat++) 173 if (compat->interface == interface) 174 return compat; 175 176 return NULL; 177 } 178 179 struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs) 180 { 181 return &xpcs->pcs; 182 } 183 EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs); 184 185 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 186 { 187 const struct dw_xpcs_compat *compat; 188 189 compat = xpcs_find_compat(xpcs, interface); 190 if (!compat) 191 return -ENODEV; 192 193 return compat->an_mode; 194 } 195 EXPORT_SYMBOL_GPL(xpcs_get_an_mode); 196 197 static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat, 198 enum ethtool_link_mode_bit_indices linkmode) 199 { 200 int i; 201 202 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 203 if (compat->supported[i] == linkmode) 204 return true; 205 206 return false; 207 } 208 209 #define xpcs_linkmode_supported(compat, mode) \ 210 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT) 211 212 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) 213 { 214 return mdiodev_c45_read(xpcs->mdiodev, dev, reg); 215 } 216 217 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) 218 { 219 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); 220 } 221 222 int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) 223 { 224 return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); 225 } 226 227 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 228 u16 mask, u16 set) 229 { 230 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); 231 } 232 233 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) 234 { 235 return xpcs_read(xpcs, dev, DW_VENDOR | reg); 236 } 237 238 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, 239 u16 val) 240 { 241 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 242 } 243 244 static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask, 245 u16 set) 246 { 247 return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set); 248 } 249 250 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) 251 { 252 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 253 } 254 255 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) 256 { 257 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 258 } 259 260 static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val) 261 { 262 return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); 263 } 264 265 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) 266 { 267 int ret, val; 268 269 ret = read_poll_timeout(xpcs_read, val, 270 val < 0 || !(val & BMCR_RESET), 271 50000, 600000, true, xpcs, dev, MII_BMCR); 272 if (val < 0) 273 ret = val; 274 275 return ret; 276 } 277 278 static int xpcs_soft_reset(struct dw_xpcs *xpcs, 279 const struct dw_xpcs_compat *compat) 280 { 281 int ret, dev; 282 283 switch (compat->an_mode) { 284 case DW_AN_C73: 285 case DW_10GBASER: 286 dev = MDIO_MMD_PCS; 287 break; 288 case DW_AN_C37_SGMII: 289 case DW_2500BASEX: 290 case DW_AN_C37_1000BASEX: 291 dev = MDIO_MMD_VEND2; 292 break; 293 default: 294 return -EINVAL; 295 } 296 297 ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET); 298 if (ret < 0) 299 return ret; 300 301 return xpcs_poll_reset(xpcs, dev); 302 } 303 304 #define xpcs_warn(__xpcs, __state, __args...) \ 305 ({ \ 306 if ((__state)->link) \ 307 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ 308 }) 309 310 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, 311 struct phylink_link_state *state, 312 u16 pcs_stat1) 313 { 314 int ret; 315 316 if (pcs_stat1 & MDIO_STAT1_FAULT) { 317 xpcs_warn(xpcs, state, "Link fault condition detected!\n"); 318 return -EFAULT; 319 } 320 321 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 322 if (ret < 0) 323 return ret; 324 325 if (ret & MDIO_STAT2_RXFAULT) 326 xpcs_warn(xpcs, state, "Receiver fault detected!\n"); 327 if (ret & MDIO_STAT2_TXFAULT) 328 xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); 329 330 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 331 if (ret < 0) 332 return ret; 333 334 if (ret & DW_RXFIFO_ERR) { 335 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); 336 return -EFAULT; 337 } 338 339 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 340 if (ret < 0) 341 return ret; 342 343 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) 344 xpcs_warn(xpcs, state, "Link is not locked!\n"); 345 346 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 347 if (ret < 0) 348 return ret; 349 350 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { 351 xpcs_warn(xpcs, state, "Link has errors!\n"); 352 return -EFAULT; 353 } 354 355 return 0; 356 } 357 358 static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) 359 { 360 int ret, speed_sel; 361 362 switch (speed) { 363 case SPEED_10: 364 speed_sel = DW_USXGMII_10; 365 break; 366 case SPEED_100: 367 speed_sel = DW_USXGMII_100; 368 break; 369 case SPEED_1000: 370 speed_sel = DW_USXGMII_1000; 371 break; 372 case SPEED_2500: 373 speed_sel = DW_USXGMII_2500; 374 break; 375 case SPEED_5000: 376 speed_sel = DW_USXGMII_5000; 377 break; 378 case SPEED_10000: 379 speed_sel = DW_USXGMII_10000; 380 break; 381 default: 382 /* Nothing to do here */ 383 return; 384 } 385 386 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); 387 if (ret < 0) 388 goto out; 389 390 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK, 391 speed_sel | DW_USXGMII_FULL); 392 if (ret < 0) 393 goto out; 394 395 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, 396 DW_USXGMII_RST); 397 if (ret < 0) 398 goto out; 399 400 return; 401 402 out: 403 dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n", 404 __func__, ERR_PTR(ret)); 405 } 406 407 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 408 const struct dw_xpcs_compat *compat) 409 { 410 int ret, adv; 411 412 /* By default, in USXGMII mode XPCS operates at 10G baud and 413 * replicates data to achieve lower speeds. Hereby, in this 414 * default configuration we need to advertise all supported 415 * modes and not only the ones we want to use. 416 */ 417 418 /* SR_AN_ADV3 */ 419 adv = 0; 420 if (xpcs_linkmode_supported(compat, 2500baseX_Full)) 421 adv |= DW_C73_2500KX; 422 423 /* TODO: 5000baseKR */ 424 425 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); 426 if (ret < 0) 427 return ret; 428 429 /* SR_AN_ADV2 */ 430 adv = 0; 431 if (xpcs_linkmode_supported(compat, 1000baseKX_Full)) 432 adv |= DW_C73_1000KX; 433 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full)) 434 adv |= DW_C73_10000KX4; 435 if (xpcs_linkmode_supported(compat, 10000baseKR_Full)) 436 adv |= DW_C73_10000KR; 437 438 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); 439 if (ret < 0) 440 return ret; 441 442 /* SR_AN_ADV1 */ 443 adv = DW_C73_AN_ADV_SF; 444 if (xpcs_linkmode_supported(compat, Pause)) 445 adv |= DW_C73_PAUSE; 446 if (xpcs_linkmode_supported(compat, Asym_Pause)) 447 adv |= DW_C73_ASYM_PAUSE; 448 449 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); 450 } 451 452 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 453 const struct dw_xpcs_compat *compat) 454 { 455 int ret; 456 457 ret = _xpcs_config_aneg_c73(xpcs, compat); 458 if (ret < 0) 459 return ret; 460 461 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, 462 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART, 463 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 464 } 465 466 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, 467 struct phylink_link_state *state, 468 const struct dw_xpcs_compat *compat, u16 an_stat1) 469 { 470 int ret; 471 472 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) { 473 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); 474 if (ret < 0) 475 return ret; 476 477 /* Check if Aneg outcome is valid */ 478 if (!(ret & DW_C73_AN_ADV_SF)) { 479 xpcs_config_aneg_c73(xpcs, compat); 480 return 0; 481 } 482 483 return 1; 484 } 485 486 return 0; 487 } 488 489 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs, 490 struct phylink_link_state *state, u16 an_stat1) 491 { 492 u16 lpa[3]; 493 int i, ret; 494 495 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) { 496 phylink_clear(state->lp_advertising, Autoneg); 497 return 0; 498 } 499 500 phylink_set(state->lp_advertising, Autoneg); 501 502 /* Read Clause 73 link partner advertisement */ 503 for (i = ARRAY_SIZE(lpa); --i >= 0; ) { 504 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); 505 if (ret < 0) 506 return ret; 507 508 lpa[i] = ret; 509 } 510 511 mii_c73_mod_linkmode(state->lp_advertising, lpa); 512 513 return 0; 514 } 515 516 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs, 517 struct phylink_link_state *state) 518 { 519 unsigned long *adv = state->advertising; 520 int speed = SPEED_UNKNOWN; 521 int bit; 522 523 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { 524 int new_speed = SPEED_UNKNOWN; 525 526 switch (bit) { 527 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 528 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 529 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 530 new_speed = SPEED_25000; 531 break; 532 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 533 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 534 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 535 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 536 new_speed = SPEED_40000; 537 break; 538 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: 539 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: 540 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: 541 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 542 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 543 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 544 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 545 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: 546 new_speed = SPEED_50000; 547 break; 548 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 549 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 550 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 551 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 552 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: 553 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: 554 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: 555 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: 556 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: 557 new_speed = SPEED_100000; 558 break; 559 default: 560 continue; 561 } 562 563 if (new_speed > speed) 564 speed = new_speed; 565 } 566 567 return speed; 568 } 569 570 static int xpcs_c45_read_pcs_speed(struct dw_xpcs *xpcs, 571 struct phylink_link_state *state) 572 { 573 int pcs_ctrl1; 574 575 pcs_ctrl1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL1); 576 if (pcs_ctrl1 < 0) 577 return pcs_ctrl1; 578 579 switch (pcs_ctrl1 & MDIO_CTRL1_SPEEDSEL) { 580 case MDIO_PCS_CTRL1_SPEED25G: 581 state->speed = SPEED_25000; 582 break; 583 case MDIO_PCS_CTRL1_SPEED50G: 584 state->speed = SPEED_50000; 585 break; 586 case MDIO_PCS_CTRL1_SPEED100G: 587 state->speed = SPEED_100000; 588 break; 589 default: 590 state->speed = SPEED_UNKNOWN; 591 break; 592 } 593 594 return 0; 595 } 596 597 static int xpcs_resolve_pma(struct dw_xpcs *xpcs, 598 struct phylink_link_state *state) 599 { 600 int pmd_rxdet, err = 0; 601 602 /* The Meta Platforms FBNIC PMD will go into a training state for 603 * about 4 seconds when the link first comes up. During this time the 604 * PCS link will bounce. To avoid reporting link up too soon we include 605 * the PMD state provided by the driver. 606 */ 607 if (xpcs->info.pma == MP_FBNIC_XPCS_PMA_100G_ID) { 608 pmd_rxdet = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_PMA_RXDET); 609 if (pmd_rxdet < 0) { 610 state->link = false; 611 return pmd_rxdet; 612 } 613 614 /* Verify Rx lanes are trained before reporting link up */ 615 if (!(pmd_rxdet & MDIO_PMD_RXDET_GLOBAL)) { 616 state->link = false; 617 return 0; 618 } 619 } 620 621 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 622 state->duplex = DUPLEX_FULL; 623 624 switch (state->interface) { 625 case PHY_INTERFACE_MODE_10GKR: 626 state->speed = SPEED_10000; 627 break; 628 case PHY_INTERFACE_MODE_XLGMII: 629 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); 630 break; 631 case PHY_INTERFACE_MODE_100GBASEP: 632 case PHY_INTERFACE_MODE_LAUI: 633 case PHY_INTERFACE_MODE_50GBASER: 634 case PHY_INTERFACE_MODE_25GBASER: 635 err = xpcs_c45_read_pcs_speed(xpcs, state); 636 break; 637 default: 638 state->speed = SPEED_UNKNOWN; 639 break; 640 } 641 642 return err; 643 } 644 645 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, 646 const struct phylink_link_state *state) 647 { 648 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, }; 649 const struct dw_xpcs_compat *compat; 650 struct dw_xpcs *xpcs; 651 int i; 652 653 xpcs = phylink_pcs_to_xpcs(pcs); 654 compat = xpcs_find_compat(xpcs, state->interface); 655 if (!compat) 656 return -EINVAL; 657 658 /* Populate the supported link modes for this PHY interface type. 659 * FIXME: what about the port modes and autoneg bit? This masks 660 * all those away. 661 */ 662 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 663 set_bit(compat->supported[i], xpcs_supported); 664 665 linkmode_and(supported, supported, xpcs_supported); 666 667 return 0; 668 } 669 670 static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, 671 phy_interface_t interface) 672 { 673 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 674 const struct dw_xpcs_compat *compat; 675 676 compat = xpcs_find_compat(xpcs, interface); 677 if (!compat) 678 return 0; 679 680 switch (compat->an_mode) { 681 case DW_AN_C73: 682 return LINK_INBAND_ENABLE; 683 684 case DW_AN_C37_SGMII: 685 case DW_AN_C37_1000BASEX: 686 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 687 688 case DW_10GBASER: 689 case DW_2500BASEX: 690 return LINK_INBAND_DISABLE; 691 692 default: 693 return 0; 694 } 695 } 696 697 static void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) 698 { 699 const struct dw_xpcs_compat *compat; 700 701 for (compat = xpcs->desc->compat; compat->supported; compat++) 702 __set_bit(compat->interface, interfaces); 703 } 704 705 static int xpcs_switch_interface_mode(struct dw_xpcs *xpcs, 706 phy_interface_t interface) 707 { 708 int ret = 0; 709 710 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 711 ret = txgbe_xpcs_switch_mode(xpcs, interface); 712 } else if (xpcs->interface != interface) { 713 if (interface == PHY_INTERFACE_MODE_SGMII) 714 xpcs->need_reset = true; 715 xpcs->interface = interface; 716 } 717 718 return ret; 719 } 720 721 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) 722 { 723 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 724 const struct dw_xpcs_compat *compat; 725 int ret; 726 727 ret = xpcs_switch_interface_mode(xpcs, interface); 728 if (ret) 729 dev_err(&xpcs->mdiodev->dev, "switch interface failed: %pe\n", 730 ERR_PTR(ret)); 731 732 if (!xpcs->need_reset) 733 return; 734 735 compat = xpcs_find_compat(xpcs, interface); 736 if (!compat) { 737 dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n", 738 phy_modes(interface)); 739 return; 740 } 741 742 ret = xpcs_soft_reset(xpcs, compat); 743 if (ret) 744 dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n", 745 ERR_PTR(ret)); 746 747 xpcs->need_reset = false; 748 } 749 750 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, 751 unsigned int neg_mode) 752 { 753 int ret, mdio_ctrl, tx_conf; 754 u16 mask, val; 755 756 /* For AN for C37 SGMII mode, the settings are :- 757 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case 758 it is already enabled) 759 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) 760 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) 761 * DW xPCS used with DW EQoS MAC is always MAC side SGMII. 762 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic 763 * speed/duplex mode change by HW after SGMII AN complete) 764 * 5) VR_MII_AN_INTR_STS = 0x0 (Clear CL37 AN complete status) 765 * 6) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) 766 * VR_MII_MMD_CTRL Bit(9) [AN_RESTART] = 1b (Restart SGMII AN) 767 * 768 * Note that VR_MII_MMD_CTRL is MII_BMCR. 769 * 770 * Note: Since it is MAC side SGMII, there is no need to set 771 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from 772 * PHY about the link state change after C28 AN is completed 773 * between PHY and Link Partner. There is also no need to 774 * trigger AN restart for MAC-side SGMII on most devices. 775 * 776 * Note: While the DesignWare databook states that AN restart is 777 * not needed for MAC side SGMII, some implementations (e.g. 778 * Rockchip RK3568) exhibit a timing quirk when integrated with 779 * phylink and do not restart AN automatically when the link 780 * comes back up. An explicit AN restart is required on those 781 * parts to recover the link after a disconnect. 782 */ 783 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 784 if (mdio_ctrl < 0) 785 return mdio_ctrl; 786 787 if (mdio_ctrl & BMCR_ANENABLE) { 788 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 789 mdio_ctrl & ~BMCR_ANENABLE); 790 if (ret < 0) 791 return ret; 792 } 793 794 mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK; 795 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 796 DW_VR_MII_PCS_MODE_C37_SGMII); 797 798 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 799 mask |= DW_VR_MII_AN_CTRL_8BIT; 800 val |= DW_VR_MII_AN_CTRL_8BIT; 801 /* Hardware requires it to be PHY side SGMII */ 802 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; 803 } else { 804 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; 805 } 806 807 val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 808 809 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 810 if (ret < 0) 811 return ret; 812 813 val = 0; 814 mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 815 816 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 817 val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 818 819 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 820 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 821 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 822 } 823 824 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); 825 if (ret < 0) 826 return ret; 827 828 /* Clear CL37 AN complete status */ 829 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 830 if (ret < 0) 831 return ret; 832 833 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 834 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 835 mdio_ctrl | BMCR_ANENABLE | BMCR_ANRESTART); 836 837 return ret; 838 } 839 840 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, 841 unsigned int neg_mode, 842 const unsigned long *advertising) 843 { 844 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; 845 int ret, mdio_ctrl, adv; 846 bool changed = 0; 847 u16 mask, val; 848 849 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must 850 * be disabled first:- 851 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b 852 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37) 853 * 854 * Note that VR_MII_MMD_CTRL is MII_BMCR. 855 */ 856 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 857 if (mdio_ctrl < 0) 858 return mdio_ctrl; 859 860 if (mdio_ctrl & BMCR_ANENABLE) { 861 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 862 mdio_ctrl & ~BMCR_ANENABLE); 863 if (ret < 0) 864 return ret; 865 } 866 867 mask = DW_VR_MII_PCS_MODE_MASK; 868 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 869 DW_VR_MII_PCS_MODE_C37_1000BASEX); 870 871 if (!xpcs->pcs.poll) { 872 mask |= DW_VR_MII_AN_INTR_EN; 873 val |= DW_VR_MII_AN_INTR_EN; 874 } 875 876 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 877 if (ret < 0) 878 return ret; 879 880 /* Check for advertising changes and update the C45 MII ADV 881 * register accordingly. 882 */ 883 adv = phylink_mii_c22_pcs_encode_advertisement(interface, 884 advertising); 885 if (adv >= 0) { 886 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, 887 MII_ADVERTISE, 0xffff, adv); 888 if (ret < 0) 889 return ret; 890 891 changed = ret; 892 } 893 894 /* Clear CL37 AN complete status */ 895 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 896 if (ret < 0) 897 return ret; 898 899 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 900 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 901 mdio_ctrl | BMCR_ANENABLE); 902 if (ret < 0) 903 return ret; 904 } 905 906 return changed; 907 } 908 909 static int xpcs_config_2500basex(struct dw_xpcs *xpcs) 910 { 911 int ret; 912 913 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, 914 DW_VR_MII_DIG_CTRL1_2G5_EN | 915 DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW, 916 DW_VR_MII_DIG_CTRL1_2G5_EN); 917 if (ret < 0) 918 return ret; 919 920 return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, 921 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100, 922 BMCR_SPEED1000); 923 } 924 925 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, 926 const unsigned long *advertising, 927 unsigned int neg_mode) 928 { 929 const struct dw_xpcs_compat *compat; 930 int ret; 931 932 compat = xpcs_find_compat(xpcs, interface); 933 if (!compat) 934 return -ENODEV; 935 936 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 937 /* Wangxun devices need backplane CL37 AN enabled for 938 * SGMII and 1000base-X 939 */ 940 if (interface == PHY_INTERFACE_MODE_SGMII || 941 interface == PHY_INTERFACE_MODE_1000BASEX) 942 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, 943 DW_CL37_BP | DW_EN_VSMMD1); 944 } 945 946 switch (compat->an_mode) { 947 case DW_10GBASER: 948 break; 949 case DW_AN_C73: 950 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 951 ret = xpcs_config_aneg_c73(xpcs, compat); 952 if (ret) 953 return ret; 954 } 955 break; 956 case DW_AN_C37_SGMII: 957 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode); 958 if (ret) 959 return ret; 960 break; 961 case DW_AN_C37_1000BASEX: 962 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode, 963 advertising); 964 if (ret) 965 return ret; 966 break; 967 case DW_2500BASEX: 968 ret = xpcs_config_2500basex(xpcs); 969 if (ret) 970 return ret; 971 break; 972 default: 973 return -EINVAL; 974 } 975 976 if (compat->pma_config) { 977 ret = compat->pma_config(xpcs); 978 if (ret) 979 return ret; 980 } 981 982 return 0; 983 } 984 985 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 986 phy_interface_t interface, 987 const unsigned long *advertising, 988 bool permit_pause_to_mac) 989 { 990 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 991 992 return xpcs_do_config(xpcs, interface, advertising, neg_mode); 993 } 994 995 static int xpcs_get_state_c73(struct dw_xpcs *xpcs, 996 struct phylink_link_state *state, 997 const struct dw_xpcs_compat *compat) 998 { 999 bool an_enabled; 1000 int pcs_stat1; 1001 int an_stat1; 1002 int ret; 1003 1004 /* The link status bit is latching-low, so it is important to 1005 * avoid unnecessary re-reads of this register to avoid missing 1006 * a link-down event. 1007 */ 1008 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 1009 if (pcs_stat1 < 0) { 1010 state->link = false; 1011 return pcs_stat1; 1012 } 1013 1014 /* Link needs to be read first ... */ 1015 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS); 1016 1017 /* ... and then we check the faults. */ 1018 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1); 1019 if (ret) { 1020 ret = xpcs_soft_reset(xpcs, compat); 1021 if (ret) 1022 return ret; 1023 1024 state->link = 0; 1025 1026 return xpcs_do_config(xpcs, state->interface, NULL, 1027 PHYLINK_PCS_NEG_INBAND_ENABLED); 1028 } 1029 1030 /* There is no point doing anything else if the link is down. */ 1031 if (!state->link) 1032 return 0; 1033 1034 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1035 state->advertising); 1036 if (an_enabled) { 1037 /* The link status bit is latching-low, so it is important to 1038 * avoid unnecessary re-reads of this register to avoid missing 1039 * a link-down event. 1040 */ 1041 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 1042 if (an_stat1 < 0) { 1043 state->link = false; 1044 return an_stat1; 1045 } 1046 1047 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat, 1048 an_stat1); 1049 if (!state->an_complete) { 1050 state->link = false; 1051 return 0; 1052 } 1053 1054 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1); 1055 if (ret < 0) { 1056 state->link = false; 1057 return ret; 1058 } 1059 1060 phylink_resolve_c73(state); 1061 } else { 1062 ret = xpcs_resolve_pma(xpcs, state); 1063 } 1064 1065 return ret; 1066 } 1067 1068 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, 1069 struct phylink_link_state *state) 1070 { 1071 int ret; 1072 1073 /* Reset link_state */ 1074 state->link = false; 1075 state->an_complete = false; 1076 state->speed = SPEED_UNKNOWN; 1077 state->duplex = DUPLEX_UNKNOWN; 1078 state->pause = 0; 1079 1080 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link 1081 * status, speed and duplex. 1082 */ 1083 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 1084 if (ret < 0) 1085 return ret; 1086 1087 state->an_complete = ret & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR; 1088 1089 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { 1090 int speed_value; 1091 1092 state->link = true; 1093 1094 speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret); 1095 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 1096 state->speed = SPEED_1000; 1097 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) 1098 state->speed = SPEED_100; 1099 else 1100 state->speed = SPEED_10; 1101 1102 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) 1103 state->duplex = DUPLEX_FULL; 1104 else 1105 state->duplex = DUPLEX_HALF; 1106 1107 return 0; 1108 } 1109 1110 if (state->an_complete) { 1111 /* Clear AN complete status or interrupt */ 1112 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 1113 if (ret < 0) 1114 return ret; 1115 1116 /* Initiate the next round of AN */ 1117 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART, 1118 BMCR_ANRESTART); 1119 if (ret < 0) 1120 return ret; 1121 } 1122 1123 return 0; 1124 } 1125 1126 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, 1127 unsigned int neg_mode, 1128 struct phylink_link_state *state) 1129 { 1130 int lpa, bmsr; 1131 1132 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1133 state->advertising)) { 1134 /* Reset link state */ 1135 state->link = false; 1136 1137 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); 1138 if (lpa < 0 || lpa & LPA_RFAULT) 1139 return lpa; 1140 1141 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1142 if (bmsr < 0) 1143 return bmsr; 1144 1145 /* Clear AN complete interrupt */ 1146 if (!xpcs->pcs.poll) { 1147 int an_intr; 1148 1149 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 1150 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 1151 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR; 1152 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr); 1153 } 1154 } 1155 1156 phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa); 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, 1163 struct phylink_link_state *state) 1164 { 1165 int ret; 1166 1167 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1168 if (ret < 0) { 1169 state->link = 0; 1170 return ret; 1171 } 1172 1173 state->link = !!(ret & BMSR_LSTATUS); 1174 if (!state->link) 1175 return 0; 1176 1177 state->speed = SPEED_2500; 1178 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX; 1179 state->duplex = DUPLEX_FULL; 1180 1181 return 0; 1182 } 1183 1184 static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 1185 struct phylink_link_state *state) 1186 { 1187 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1188 const struct dw_xpcs_compat *compat; 1189 int ret; 1190 1191 compat = xpcs_find_compat(xpcs, state->interface); 1192 if (!compat) 1193 return; 1194 1195 switch (compat->an_mode) { 1196 case DW_10GBASER: 1197 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state); 1198 break; 1199 case DW_AN_C73: 1200 ret = xpcs_get_state_c73(xpcs, state, compat); 1201 if (ret) 1202 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1203 "xpcs_get_state_c73", ERR_PTR(ret)); 1204 break; 1205 case DW_AN_C37_SGMII: 1206 ret = xpcs_get_state_c37_sgmii(xpcs, state); 1207 if (ret) 1208 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1209 "xpcs_get_state_c37_sgmii", ERR_PTR(ret)); 1210 break; 1211 case DW_AN_C37_1000BASEX: 1212 ret = xpcs_get_state_c37_1000basex(xpcs, neg_mode, state); 1213 if (ret) 1214 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1215 "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); 1216 break; 1217 case DW_2500BASEX: 1218 ret = xpcs_get_state_2500basex(xpcs, state); 1219 if (ret) 1220 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1221 "xpcs_get_state_2500basex", ERR_PTR(ret)); 1222 break; 1223 default: 1224 return; 1225 } 1226 } 1227 1228 static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, 1229 unsigned int neg_mode, 1230 phy_interface_t interface, 1231 int speed, int duplex) 1232 { 1233 int ret; 1234 1235 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 1236 return; 1237 1238 if (interface == PHY_INTERFACE_MODE_1000BASEX) { 1239 if (speed != SPEED_1000) { 1240 dev_err(&xpcs->mdiodev->dev, 1241 "%s: speed %dMbps not supported\n", 1242 __func__, speed); 1243 return; 1244 } 1245 1246 if (duplex != DUPLEX_FULL) 1247 dev_err(&xpcs->mdiodev->dev, 1248 "%s: half duplex not supported\n", 1249 __func__); 1250 } 1251 1252 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 1253 mii_bmcr_encode_fixed(speed, duplex)); 1254 if (ret) 1255 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", 1256 __func__, ERR_PTR(ret)); 1257 } 1258 1259 static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 1260 phy_interface_t interface, int speed, int duplex) 1261 { 1262 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1263 1264 switch (interface) { 1265 case PHY_INTERFACE_MODE_USXGMII: 1266 xpcs_link_up_usxgmii(xpcs, speed); 1267 break; 1268 1269 case PHY_INTERFACE_MODE_SGMII: 1270 case PHY_INTERFACE_MODE_1000BASEX: 1271 xpcs_link_up_sgmii_1000basex(xpcs, neg_mode, interface, speed, 1272 duplex); 1273 break; 1274 1275 default: 1276 break; 1277 } 1278 } 1279 1280 static void xpcs_an_restart(struct phylink_pcs *pcs) 1281 { 1282 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1283 1284 xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART, 1285 BMCR_ANRESTART); 1286 } 1287 1288 static int xpcs_config_eee(struct dw_xpcs *xpcs, bool enable) 1289 { 1290 u16 mask, val; 1291 int ret; 1292 1293 mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 1294 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 1295 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 1296 DW_VR_MII_EEE_MULT_FACT_100NS; 1297 1298 if (enable) 1299 val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 1300 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 1301 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 1302 FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, 1303 xpcs->eee_mult_fact); 1304 else 1305 val = 0; 1306 1307 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask, 1308 val); 1309 if (ret < 0) 1310 return ret; 1311 1312 return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, 1313 DW_VR_MII_EEE_TRN_LPI, 1314 enable ? DW_VR_MII_EEE_TRN_LPI : 0); 1315 } 1316 1317 static void xpcs_disable_eee(struct phylink_pcs *pcs) 1318 { 1319 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1320 1321 xpcs_config_eee(xpcs, false); 1322 } 1323 1324 static void xpcs_enable_eee(struct phylink_pcs *pcs) 1325 { 1326 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1327 1328 xpcs_config_eee(xpcs, true); 1329 } 1330 1331 /** 1332 * xpcs_config_eee_mult_fact() - set the EEE clock multiplying factor 1333 * @xpcs: pointer to a &struct dw_xpcs instance 1334 * @mult_fact: the multiplying factor 1335 * 1336 * Configure the EEE clock multiplying factor. This value should be such that 1337 * clk_eee_time_period * (mult_fact + 1) is within the range 80 to 120ns. 1338 */ 1339 void xpcs_config_eee_mult_fact(struct dw_xpcs *xpcs, u8 mult_fact) 1340 { 1341 xpcs->eee_mult_fact = mult_fact; 1342 } 1343 EXPORT_SYMBOL_GPL(xpcs_config_eee_mult_fact); 1344 1345 static int xpcs_read_ids(struct dw_xpcs *xpcs) 1346 { 1347 int ret; 1348 u32 id; 1349 1350 /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication 1351 * failed indicating that device couldn't be reached. 1352 */ 1353 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 1354 if (ret < 0) 1355 return -ENODEV; 1356 1357 id = ret << 16; 1358 1359 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); 1360 if (ret < 0) 1361 return ret; 1362 1363 id |= ret; 1364 1365 /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73 1366 * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37 1367 * PCS in MII MMD 31. 1368 */ 1369 if (!id || id == 0xffffffff) { 1370 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); 1371 if (ret < 0) 1372 return ret; 1373 1374 id = ret << 16; 1375 1376 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); 1377 if (ret < 0) 1378 return ret; 1379 1380 id |= ret; 1381 } 1382 1383 /* Set the PCS ID if it hasn't been pre-initialized */ 1384 if (xpcs->info.pcs == DW_XPCS_ID_NATIVE) 1385 xpcs->info.pcs = id; 1386 1387 /* Find out PMA/PMD ID from MMD 1 device ID registers */ 1388 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1); 1389 if (ret < 0) 1390 return ret; 1391 1392 id = ret << 16; 1393 1394 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2); 1395 if (ret < 0) 1396 return ret; 1397 1398 /* For now we only record the OUI for the PMAPMD, we may want to 1399 * add the model number at some point in the future. 1400 */ 1401 id |= ret & MDIO_DEVID2_OUI; 1402 1403 /* Set the PMA ID if it hasn't been pre-initialized */ 1404 if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE) 1405 xpcs->info.pma = id; 1406 1407 return 0; 1408 } 1409 1410 static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { 1411 { 1412 .interface = PHY_INTERFACE_MODE_USXGMII, 1413 .supported = xpcs_usxgmii_features, 1414 .an_mode = DW_AN_C73, 1415 }, { 1416 .interface = PHY_INTERFACE_MODE_10GKR, 1417 .supported = xpcs_10gkr_features, 1418 .an_mode = DW_AN_C73, 1419 }, { 1420 .interface = PHY_INTERFACE_MODE_25GBASER, 1421 .supported = xpcs_25gbaser_features, 1422 .an_mode = DW_AN_C73, 1423 }, { 1424 .interface = PHY_INTERFACE_MODE_XLGMII, 1425 .supported = xpcs_xlgmii_features, 1426 .an_mode = DW_AN_C73, 1427 }, { 1428 .interface = PHY_INTERFACE_MODE_50GBASER, 1429 .supported = xpcs_50gbaser_features, 1430 .an_mode = DW_AN_C73, 1431 }, { 1432 .interface = PHY_INTERFACE_MODE_LAUI, 1433 .supported = xpcs_50gbaser2_features, 1434 .an_mode = DW_AN_C73, 1435 }, { 1436 .interface = PHY_INTERFACE_MODE_100GBASEP, 1437 .supported = xpcs_100gbasep_features, 1438 .an_mode = DW_AN_C73, 1439 }, { 1440 .interface = PHY_INTERFACE_MODE_10GBASER, 1441 .supported = xpcs_10gbaser_features, 1442 .an_mode = DW_10GBASER, 1443 }, { 1444 .interface = PHY_INTERFACE_MODE_SGMII, 1445 .supported = xpcs_sgmii_features, 1446 .an_mode = DW_AN_C37_SGMII, 1447 }, { 1448 .interface = PHY_INTERFACE_MODE_1000BASEX, 1449 .supported = xpcs_1000basex_features, 1450 .an_mode = DW_AN_C37_1000BASEX, 1451 }, { 1452 .interface = PHY_INTERFACE_MODE_2500BASEX, 1453 .supported = xpcs_2500basex_features, 1454 .an_mode = DW_2500BASEX, 1455 }, { 1456 } 1457 }; 1458 1459 static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = { 1460 { 1461 .interface = PHY_INTERFACE_MODE_SGMII, 1462 .supported = xpcs_sgmii_features, 1463 .an_mode = DW_AN_C37_SGMII, 1464 .pma_config = nxp_sja1105_sgmii_pma_config, 1465 }, { 1466 } 1467 }; 1468 1469 static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = { 1470 { 1471 .interface = PHY_INTERFACE_MODE_SGMII, 1472 .supported = xpcs_sgmii_features, 1473 .an_mode = DW_AN_C37_SGMII, 1474 .pma_config = nxp_sja1110_sgmii_pma_config, 1475 }, { 1476 .interface = PHY_INTERFACE_MODE_2500BASEX, 1477 .supported = xpcs_2500basex_features, 1478 .an_mode = DW_2500BASEX, 1479 .pma_config = nxp_sja1110_2500basex_pma_config, 1480 }, { 1481 } 1482 }; 1483 1484 static const struct dw_xpcs_desc xpcs_desc_list[] = { 1485 { 1486 .id = DW_XPCS_ID, 1487 .mask = DW_XPCS_ID_MASK, 1488 .compat = synopsys_xpcs_compat, 1489 }, { 1490 .id = NXP_SJA1105_XPCS_ID, 1491 .mask = DW_XPCS_ID_MASK, 1492 .compat = nxp_sja1105_xpcs_compat, 1493 }, { 1494 .id = NXP_SJA1110_XPCS_ID, 1495 .mask = DW_XPCS_ID_MASK, 1496 .compat = nxp_sja1110_xpcs_compat, 1497 }, 1498 }; 1499 1500 static const struct phylink_pcs_ops xpcs_phylink_ops = { 1501 .pcs_validate = xpcs_validate, 1502 .pcs_inband_caps = xpcs_inband_caps, 1503 .pcs_pre_config = xpcs_pre_config, 1504 .pcs_config = xpcs_config, 1505 .pcs_get_state = xpcs_get_state, 1506 .pcs_an_restart = xpcs_an_restart, 1507 .pcs_link_up = xpcs_link_up, 1508 .pcs_disable_eee = xpcs_disable_eee, 1509 .pcs_enable_eee = xpcs_enable_eee, 1510 }; 1511 1512 static int xpcs_identify(struct dw_xpcs *xpcs) 1513 { 1514 int i, ret; 1515 1516 ret = xpcs_read_ids(xpcs); 1517 if (ret < 0) 1518 return ret; 1519 1520 for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) { 1521 const struct dw_xpcs_desc *entry = &xpcs_desc_list[i]; 1522 1523 if ((xpcs->info.pcs & entry->mask) == entry->id) { 1524 xpcs->desc = entry; 1525 return 0; 1526 } 1527 } 1528 1529 return -ENODEV; 1530 } 1531 1532 static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) 1533 { 1534 struct dw_xpcs *xpcs; 1535 1536 xpcs = kzalloc_obj(*xpcs); 1537 if (!xpcs) 1538 return ERR_PTR(-ENOMEM); 1539 1540 mdio_device_get(mdiodev); 1541 xpcs->mdiodev = mdiodev; 1542 xpcs->pcs.ops = &xpcs_phylink_ops; 1543 xpcs->pcs.poll = true; 1544 1545 return xpcs; 1546 } 1547 1548 static void xpcs_free_data(struct dw_xpcs *xpcs) 1549 { 1550 mdio_device_put(xpcs->mdiodev); 1551 kfree(xpcs); 1552 } 1553 1554 static int xpcs_init_clks(struct dw_xpcs *xpcs) 1555 { 1556 static const char *ids[DW_XPCS_NUM_CLKS] = { 1557 [DW_XPCS_CORE_CLK] = "core", 1558 [DW_XPCS_PAD_CLK] = "pad", 1559 }; 1560 struct device *dev = &xpcs->mdiodev->dev; 1561 int ret, i; 1562 1563 for (i = 0; i < DW_XPCS_NUM_CLKS; ++i) 1564 xpcs->clks[i].id = ids[i]; 1565 1566 ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks); 1567 if (ret) 1568 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1569 1570 ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks); 1571 if (ret) { 1572 clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks); 1573 return dev_err_probe(dev, ret, "Failed to enable clocks\n"); 1574 } 1575 1576 return 0; 1577 } 1578 1579 static void xpcs_clear_clks(struct dw_xpcs *xpcs) 1580 { 1581 clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks); 1582 1583 clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks); 1584 } 1585 1586 static int xpcs_init_id(struct dw_xpcs *xpcs) 1587 { 1588 const struct dw_xpcs_info *info; 1589 1590 info = dev_get_platdata(&xpcs->mdiodev->dev); 1591 if (!info) { 1592 xpcs->info.pcs = DW_XPCS_ID_NATIVE; 1593 xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE; 1594 } else { 1595 xpcs->info = *info; 1596 } 1597 1598 return xpcs_identify(xpcs); 1599 } 1600 1601 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) 1602 { 1603 struct dw_xpcs *xpcs; 1604 int ret; 1605 1606 xpcs = xpcs_create_data(mdiodev); 1607 if (IS_ERR(xpcs)) 1608 return xpcs; 1609 1610 ret = xpcs_init_clks(xpcs); 1611 if (ret) 1612 goto out_free_data; 1613 1614 ret = xpcs_init_id(xpcs); 1615 if (ret) 1616 goto out_clear_clks; 1617 1618 xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); 1619 1620 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID || 1621 xpcs->info.pma == MP_FBNIC_XPCS_PMA_100G_ID) 1622 xpcs->pcs.poll = false; 1623 else 1624 xpcs->need_reset = true; 1625 1626 return xpcs; 1627 1628 out_clear_clks: 1629 xpcs_clear_clks(xpcs); 1630 1631 out_free_data: 1632 xpcs_free_data(xpcs); 1633 1634 return ERR_PTR(ret); 1635 } 1636 1637 /** 1638 * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr 1639 * @bus: pointer to the MDIO-bus descriptor for the device to be looked at 1640 * @addr: device MDIO-bus ID 1641 * 1642 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1643 * the PCS device couldn't be found on the bus and other negative errno related 1644 * to the data allocation and MDIO-bus communications. 1645 */ 1646 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) 1647 { 1648 struct mdio_device *mdiodev; 1649 struct dw_xpcs *xpcs; 1650 1651 mdiodev = mdio_device_create(bus, addr); 1652 if (IS_ERR(mdiodev)) 1653 return ERR_CAST(mdiodev); 1654 1655 xpcs = xpcs_create(mdiodev); 1656 1657 /* xpcs_create() has taken a refcount on the mdiodev if it was 1658 * successful. If xpcs_create() fails, this will free the mdio 1659 * device here. In any case, we don't need to hold our reference 1660 * anymore, and putting it here will allow mdio_device_put() in 1661 * xpcs_destroy() to automatically free the mdio device. 1662 */ 1663 mdio_device_put(mdiodev); 1664 1665 return xpcs; 1666 } 1667 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); 1668 1669 struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr) 1670 { 1671 struct dw_xpcs *xpcs; 1672 1673 xpcs = xpcs_create_mdiodev(bus, addr); 1674 if (IS_ERR(xpcs)) 1675 return ERR_CAST(xpcs); 1676 1677 return &xpcs->pcs; 1678 } 1679 EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev); 1680 1681 /** 1682 * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode 1683 * @fwnode: fwnode handle poining to the DW XPCS device 1684 * 1685 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1686 * the fwnode device is unavailable or the PCS device couldn't be found on the 1687 * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found, 1688 * other negative errno related to the data allocations and MDIO-bus 1689 * communications. 1690 */ 1691 struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode) 1692 { 1693 struct mdio_device *mdiodev; 1694 struct dw_xpcs *xpcs; 1695 1696 if (!fwnode_device_is_available(fwnode)) 1697 return ERR_PTR(-ENODEV); 1698 1699 mdiodev = fwnode_mdio_find_device(fwnode); 1700 if (!mdiodev) 1701 return ERR_PTR(-EPROBE_DEFER); 1702 1703 xpcs = xpcs_create(mdiodev); 1704 1705 /* xpcs_create() has taken a refcount on the mdiodev if it was 1706 * successful. If xpcs_create() fails, this will free the mdio 1707 * device here. In any case, we don't need to hold our reference 1708 * anymore, and putting it here will allow mdio_device_put() in 1709 * xpcs_destroy() to automatically free the mdio device. 1710 */ 1711 mdio_device_put(mdiodev); 1712 1713 return xpcs; 1714 } 1715 EXPORT_SYMBOL_GPL(xpcs_create_fwnode); 1716 1717 void xpcs_destroy(struct dw_xpcs *xpcs) 1718 { 1719 if (!xpcs) 1720 return; 1721 1722 xpcs_clear_clks(xpcs); 1723 1724 xpcs_free_data(xpcs); 1725 } 1726 EXPORT_SYMBOL_GPL(xpcs_destroy); 1727 1728 void xpcs_destroy_pcs(struct phylink_pcs *pcs) 1729 { 1730 xpcs_destroy(phylink_pcs_to_xpcs(pcs)); 1731 } 1732 EXPORT_SYMBOL_GPL(xpcs_destroy_pcs); 1733 1734 MODULE_DESCRIPTION("Synopsys DesignWare XPCS library"); 1735 MODULE_LICENSE("GPL v2"); 1736