1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
16 #include <linux/suspend.h>
17
18 #include "xhci.h"
19 #include "xhci-trace.h"
20 #include "xhci-pci.h"
21
22 #define SSIC_PORT_NUM 2
23 #define SSIC_PORT_CFG2 0x880c
24 #define SSIC_PORT_CFG2_OFFSET 0x30
25 #define PROG_DONE (1 << 30)
26 #define SSIC_PORT_UNUSED (1 << 31)
27 #define SPARSE_DISABLE_BIT 17
28 #define SPARSE_CNTL_ENABLE 0xC12C
29
30 /* Device for a quirk */
31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
36
37 #define PCI_VENDOR_ID_ETRON 0x1b6f
38 #define PCI_DEVICE_ID_ETRON_EJ168 0x7023
39 #define PCI_DEVICE_ID_ETRON_EJ188 0x7052
40
41 #define PCI_DEVICE_ID_VIA_VL805 0x3483
42
43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
44 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
45 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
46 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
47 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
48 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
49 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
50 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
51 #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8
52 #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0
53 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
54 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
55 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI 0xa0ed
56 #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af
57 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
58 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed
59
60 #define PCI_VENDOR_ID_PHYTIUM 0x1db7
61 #define PCI_DEVICE_ID_PHYTIUM_XHCI 0xdc27
62
63 /* Thunderbolt */
64 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
65 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
66 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
67 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
68 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
69 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
70 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
71 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
72 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
73
74 #define PCI_DEVICE_ID_AMD_ARIEL_TYPEC_XHCI 0x13ed
75 #define PCI_DEVICE_ID_AMD_ARIEL_TYPEA_XHCI 0x13ee
76 #define PCI_DEVICE_ID_AMD_STARSHIP_XHCI 0x148c
77 #define PCI_DEVICE_ID_AMD_FIREFLIGHT_15D4_XHCI 0x15d4
78 #define PCI_DEVICE_ID_AMD_FIREFLIGHT_15D5_XHCI 0x15d5
79 #define PCI_DEVICE_ID_AMD_RAVEN_15E0_XHCI 0x15e0
80 #define PCI_DEVICE_ID_AMD_RAVEN_15E1_XHCI 0x15e1
81 #define PCI_DEVICE_ID_AMD_RAVEN2_XHCI 0x15e5
82 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
83 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
84 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
85 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
86 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
87
88 #define PCI_DEVICE_ID_ATI_NAVI10_7316_XHCI 0x7316
89
90 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
91 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
92 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
93 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
94 #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042
95 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
96
97 static const char hcd_name[] = "xhci_hcd";
98
99 static struct hc_driver __read_mostly xhci_pci_hc_driver;
100
101 static int xhci_pci_setup(struct usb_hcd *hcd);
102 static int xhci_pci_run(struct usb_hcd *hcd);
103 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
104 struct usb_tt *tt, gfp_t mem_flags);
105
106 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
107 .reset = xhci_pci_setup,
108 .start = xhci_pci_run,
109 .update_hub_device = xhci_pci_update_hub_device,
110 };
111
112 /*
113 * Primary Legacy and MSI IRQ are synced in suspend_common().
114 * All MSI-X IRQs and secondary MSI IRQs should be synced here.
115 */
xhci_msix_sync_irqs(struct xhci_hcd * xhci)116 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
117 {
118 struct usb_hcd *hcd = xhci_to_hcd(xhci);
119
120 if (hcd->msix_enabled) {
121 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
122
123 /* for now, the driver only supports one primary interrupter */
124 synchronize_irq(pci_irq_vector(pdev, 0));
125 }
126 }
127
128 /* Legacy IRQ is freed by usb_remove_hcd() or usb_hcd_pci_shutdown() */
xhci_cleanup_msix(struct xhci_hcd * xhci)129 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
130 {
131 struct usb_hcd *hcd = xhci_to_hcd(xhci);
132 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
133
134 if (hcd->irq > 0)
135 return;
136
137 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
138 pci_free_irq_vectors(pdev);
139 hcd->msix_enabled = 0;
140 }
141
142 /* Try enabling MSI-X with MSI and legacy IRQ as fallback */
xhci_try_enable_msi(struct usb_hcd * hcd)143 static int xhci_try_enable_msi(struct usb_hcd *hcd)
144 {
145 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
146 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
147 int ret;
148
149 /*
150 * Some Fresco Logic host controllers advertise MSI, but fail to
151 * generate interrupts. Don't even try to enable MSI.
152 */
153 if (xhci->quirks & XHCI_BROKEN_MSI)
154 goto legacy_irq;
155
156 /* unregister the legacy interrupt */
157 if (hcd->irq)
158 free_irq(hcd->irq, hcd);
159 hcd->irq = 0;
160
161 /*
162 * Calculate number of MSI/MSI-X vectors supported.
163 * - max_interrupters: the max number of interrupts requested, capped to xhci HCSPARAMS1.
164 * - num_online_cpus: one vector per CPUs core, with at least one overall.
165 */
166 xhci->nvecs = min(num_online_cpus() + 1, xhci->max_interrupters);
167
168 /* TODO: Check with MSI Soc for sysdev */
169 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs,
170 PCI_IRQ_MSIX | PCI_IRQ_MSI);
171 if (xhci->nvecs < 0) {
172 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
173 "failed to allocate IRQ vectors");
174 goto legacy_irq;
175 }
176
177 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd",
178 xhci_to_hcd(xhci));
179 if (ret)
180 goto free_irq_vectors;
181
182 hcd->msi_enabled = 1;
183 hcd->msix_enabled = pdev->msix_enabled;
184 return 0;
185
186 free_irq_vectors:
187 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt",
188 pdev->msix_enabled ? "MSI-X" : "MSI");
189 pci_free_irq_vectors(pdev);
190
191 legacy_irq:
192 if (!pdev->irq) {
193 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
194 return -EINVAL;
195 }
196
197 if (!strlen(hcd->irq_descr))
198 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
199 hcd->driver->description, hcd->self.busnum);
200
201 /* fall back to legacy interrupt */
202 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd);
203 if (ret) {
204 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq);
205 return ret;
206 }
207 hcd->irq = pdev->irq;
208 return 0;
209 }
210
xhci_pci_run(struct usb_hcd * hcd)211 static int xhci_pci_run(struct usb_hcd *hcd)
212 {
213 int ret;
214
215 if (usb_hcd_is_primary_hcd(hcd)) {
216 ret = xhci_try_enable_msi(hcd);
217 if (ret)
218 return ret;
219 }
220
221 return xhci_run(hcd);
222 }
223
xhci_pci_stop(struct usb_hcd * hcd)224 static void xhci_pci_stop(struct usb_hcd *hcd)
225 {
226 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
227
228 xhci_stop(hcd);
229
230 if (usb_hcd_is_primary_hcd(hcd))
231 xhci_cleanup_msix(xhci);
232 }
233
234 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)235 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
236 {
237 /*
238 * TODO: Implement finding debug ports later.
239 * TODO: see if there are any quirks that need to be added to handle
240 * new extended capabilities.
241 */
242
243 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
244 if (!pci_set_mwi(pdev))
245 xhci_dbg(xhci, "MWI active\n");
246
247 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
248 return 0;
249 }
250
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)251 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
252 {
253 struct pci_dev *pdev = to_pci_dev(dev);
254
255 /* Look for vendor-specific quirks */
256 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
257 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
258 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
259 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
260 pdev->revision == 0x0) {
261 xhci->quirks |= XHCI_RESET_EP_QUIRK;
262 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
263 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
264 }
265 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
266 pdev->revision == 0x4) {
267 xhci->quirks |= XHCI_SLOW_SUSPEND;
268 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
269 "QUIRK: Fresco Logic xHC revision %u"
270 "must be suspended extra slowly",
271 pdev->revision);
272 }
273 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
274 xhci->quirks |= XHCI_BROKEN_STREAMS;
275 /* Fresco Logic confirms: all revisions of this chip do not
276 * support MSI, even though some of them claim to in their PCI
277 * capabilities.
278 */
279 xhci->quirks |= XHCI_BROKEN_MSI;
280 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
281 "QUIRK: Fresco Logic revision %u "
282 "has broken MSI implementation",
283 pdev->revision);
284 }
285
286 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
287 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
288 xhci->quirks |= XHCI_BROKEN_STREAMS;
289
290 if (pdev->vendor == PCI_VENDOR_ID_NEC)
291 xhci->quirks |= XHCI_NEC_HOST;
292
293 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
294 (pdev->device == PCI_DEVICE_ID_AMD_ARIEL_TYPEC_XHCI ||
295 pdev->device == PCI_DEVICE_ID_AMD_ARIEL_TYPEA_XHCI ||
296 pdev->device == PCI_DEVICE_ID_AMD_STARSHIP_XHCI ||
297 pdev->device == PCI_DEVICE_ID_AMD_FIREFLIGHT_15D4_XHCI ||
298 pdev->device == PCI_DEVICE_ID_AMD_FIREFLIGHT_15D5_XHCI ||
299 pdev->device == PCI_DEVICE_ID_AMD_RAVEN_15E0_XHCI ||
300 pdev->device == PCI_DEVICE_ID_AMD_RAVEN_15E1_XHCI ||
301 pdev->device == PCI_DEVICE_ID_AMD_RAVEN2_XHCI))
302 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_9;
303
304 if (pdev->vendor == PCI_VENDOR_ID_ATI &&
305 pdev->device == PCI_DEVICE_ID_ATI_NAVI10_7316_XHCI)
306 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_9;
307
308 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
309 xhci->quirks |= XHCI_AMD_0x96_HOST;
310
311 /* AMD PLL quirk */
312 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
313 xhci->quirks |= XHCI_AMD_PLL_FIX;
314
315 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
316 (pdev->device == 0x145c ||
317 pdev->device == 0x15e0 ||
318 pdev->device == 0x15e1 ||
319 pdev->device == 0x43bb))
320 xhci->quirks |= XHCI_SUSPEND_DELAY;
321
322 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
323 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
324 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
325
326 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
327 xhci->quirks |= XHCI_DISABLE_SPARSE;
328 xhci->quirks |= XHCI_RESET_ON_RESUME;
329 }
330
331 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7)
332 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
333
334 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
335 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
336 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
337 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
338 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
339 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
340
341 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
342 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
343 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
344
345 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
346 xhci->quirks |= XHCI_LPM_SUPPORT;
347 xhci->quirks |= XHCI_INTEL_HOST;
348 xhci->quirks |= XHCI_AVOID_BEI;
349 }
350 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
351 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
352 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
353 xhci->limit_active_eps = 64;
354 xhci->quirks |= XHCI_SW_BW_CHECKING;
355 /*
356 * PPT desktop boards DH77EB and DH77DF will power back on after
357 * a few seconds of being shutdown. The fix for this is to
358 * switch the ports from xHCI to EHCI on shutdown. We can't use
359 * DMI information to find those particular boards (since each
360 * vendor will change the board name), so we have to key off all
361 * PPT chipsets.
362 */
363 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
364 }
365 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
366 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
367 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
368 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
369 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
370 }
371 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
372 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
373 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
374 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
375 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
376 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
377 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI ||
378 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI ||
379 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) {
380 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
381 }
382 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
383 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
384 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
385 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
386 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
387 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
388 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI))
389 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
390 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
391 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
392 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
393 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
394 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI ||
395 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI))
396 xhci->quirks |= XHCI_MISSING_CAS;
397
398 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
399 (pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI ||
400 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
401 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
402 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
403
404 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
405 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
406 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
407 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
408 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
409 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
410 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
411 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
412 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
413 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
414 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
415 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
416 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
417
418 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
419 (pdev->device == PCI_DEVICE_ID_ETRON_EJ168 ||
420 pdev->device == PCI_DEVICE_ID_ETRON_EJ188)) {
421 xhci->quirks |= XHCI_ETRON_HOST;
422 xhci->quirks |= XHCI_RESET_ON_RESUME;
423 xhci->quirks |= XHCI_BROKEN_STREAMS;
424 xhci->quirks |= XHCI_NO_SOFT_RETRY;
425 }
426
427 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
428 pdev->device == 0x0014) {
429 xhci->quirks |= XHCI_ZERO_64B_REGS;
430 }
431 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
432 pdev->device == 0x0015) {
433 xhci->quirks |= XHCI_RESET_ON_RESUME;
434 xhci->quirks |= XHCI_ZERO_64B_REGS;
435 }
436 if (pdev->vendor == PCI_VENDOR_ID_VIA)
437 xhci->quirks |= XHCI_RESET_ON_RESUME;
438
439 if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM &&
440 pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI)
441 xhci->quirks |= XHCI_RESET_ON_RESUME;
442
443 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
444 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
445 pdev->device == 0x3432)
446 xhci->quirks |= XHCI_BROKEN_STREAMS;
447
448 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == PCI_DEVICE_ID_VIA_VL805) {
449 xhci->quirks |= XHCI_LPM_SUPPORT;
450 xhci->quirks |= XHCI_TRB_OVERFETCH;
451 }
452
453 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
454 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
455 /*
456 * try to tame the ASMedia 1042 controller which reports 0.96
457 * but appears to behave more like 1.0
458 */
459 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
460 xhci->quirks |= XHCI_BROKEN_STREAMS;
461 }
462 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
463 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
464 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
465 }
466 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
467 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
468 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
469 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
470 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
471
472 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
473 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
474 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
475
476 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
477 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI)
478 xhci->quirks |= XHCI_RESET_ON_RESUME;
479
480 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
481 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
482
483 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
484 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
485 pdev->device == 0x9026)
486 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
487
488 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
489 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
490 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
491 xhci->quirks |= XHCI_NO_SOFT_RETRY;
492
493 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
494 xhci->quirks |= XHCI_ZHAOXIN_HOST;
495 xhci->quirks |= XHCI_LPM_SUPPORT;
496
497 if (pdev->device == 0x9202) {
498 xhci->quirks |= XHCI_RESET_ON_RESUME;
499 xhci->quirks |= XHCI_TRB_OVERFETCH;
500 }
501
502 if (pdev->device == 0x9203)
503 xhci->quirks |= XHCI_TRB_OVERFETCH;
504 }
505
506 if (pdev->vendor == PCI_VENDOR_ID_CDNS &&
507 pdev->device == PCI_DEVICE_ID_CDNS_USBSSP)
508 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK;
509
510 /* xHC spec requires PCI devices to support D3hot and D3cold */
511 if (xhci->hci_version >= 0x120)
512 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
513
514 if (xhci->quirks & XHCI_RESET_ON_RESUME)
515 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
516 "QUIRK: Resetting on resume");
517 }
518
519 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)520 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
521 {
522 static const guid_t intel_dsm_guid =
523 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
524 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
525 union acpi_object *obj;
526
527 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
528 NULL);
529 ACPI_FREE(obj);
530 }
531
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)532 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
533 {
534 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
535 struct xhci_hub *rhub = &xhci->usb3_rhub;
536 int ret;
537 int i;
538
539 /* This is not the usb3 roothub we are looking for */
540 if (hcd != rhub->hcd)
541 return;
542
543 if (hdev->maxchild > rhub->num_ports) {
544 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
545 return;
546 }
547
548 for (i = 0; i < hdev->maxchild; i++) {
549 ret = usb_acpi_port_lpm_incapable(hdev, i);
550
551 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
552
553 if (ret >= 0) {
554 rhub->ports[i]->lpm_incapable = ret;
555 continue;
556 }
557 }
558 }
559
560 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)561 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)562 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
563 #endif /* CONFIG_ACPI */
564
565 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)566 static int xhci_pci_setup(struct usb_hcd *hcd)
567 {
568 struct xhci_hcd *xhci;
569 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
570 int retval;
571 u8 sbrn;
572
573 xhci = hcd_to_xhci(hcd);
574
575 /* imod_interval is the interrupt moderation value in nanoseconds. */
576 xhci->imod_interval = 40000;
577
578 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
579 if (retval)
580 return retval;
581
582 if (!usb_hcd_is_primary_hcd(hcd))
583 return 0;
584
585 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
586 xhci_pme_acpi_rtd3_enable(pdev);
587
588 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &sbrn);
589 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int)sbrn);
590
591 /* Find any debug ports */
592 return xhci_pci_reinit(xhci, pdev);
593 }
594
xhci_pci_update_hub_device(struct usb_hcd * hcd,struct usb_device * hdev,struct usb_tt * tt,gfp_t mem_flags)595 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
596 struct usb_tt *tt, gfp_t mem_flags)
597 {
598 /* Check if acpi claims some USB3 roothub ports are lpm incapable */
599 if (!hdev->parent)
600 xhci_find_lpm_incapable_ports(hcd, hdev);
601
602 return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
603 }
604
605 /*
606 * We need to register our own PCI probe function (instead of the USB core's
607 * function) in order to create a second roothub under xHCI.
608 */
xhci_pci_common_probe(struct pci_dev * dev,const struct pci_device_id * id)609 int xhci_pci_common_probe(struct pci_dev *dev, const struct pci_device_id *id)
610 {
611 int retval;
612 struct xhci_hcd *xhci;
613 struct usb_hcd *hcd;
614 struct reset_control *reset;
615
616 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
617 if (IS_ERR(reset))
618 return PTR_ERR(reset);
619 reset_control_reset(reset);
620
621 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
622 pm_runtime_get_noresume(&dev->dev);
623
624 /* Register the USB 2.0 roothub.
625 * FIXME: USB core must know to register the USB 2.0 roothub first.
626 * This is sort of silly, because we could just set the HCD driver flags
627 * to say USB 2.0, but I'm not sure what the implications would be in
628 * the other parts of the HCD code.
629 */
630 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
631
632 if (retval)
633 goto put_runtime_pm;
634
635 /* USB 2.0 roothub is stored in the PCI device now. */
636 hcd = dev_get_drvdata(&dev->dev);
637 xhci = hcd_to_xhci(hcd);
638 xhci->reset = reset;
639 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
640 pci_name(dev), hcd);
641 if (!xhci->shared_hcd) {
642 retval = -ENOMEM;
643 goto dealloc_usb2_hcd;
644 }
645
646 retval = xhci_ext_cap_init(xhci);
647 if (retval)
648 goto put_usb3_hcd;
649
650 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
651 IRQF_SHARED);
652 if (retval)
653 goto put_usb3_hcd;
654 /* Roothub already marked as USB 3.0 speed */
655
656 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
657 HCC_MAX_PSA(xhci->hcc_params) >= 4)
658 xhci->shared_hcd->can_do_streams = 1;
659
660 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
661 pm_runtime_put_noidle(&dev->dev);
662
663 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
664 pm_runtime_get(&dev->dev);
665 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
666 pm_runtime_allow(&dev->dev);
667
668 dma_set_max_seg_size(&dev->dev, UINT_MAX);
669
670 if (device_property_read_bool(&dev->dev, "ti,pwron-active-high"))
671 pci_clear_and_set_config_dword(dev, 0xE0, 0, 1 << 22);
672
673 return 0;
674
675 put_usb3_hcd:
676 usb_put_hcd(xhci->shared_hcd);
677 dealloc_usb2_hcd:
678 usb_hcd_pci_remove(dev);
679 put_runtime_pm:
680 pm_runtime_put_noidle(&dev->dev);
681 return retval;
682 }
683 EXPORT_SYMBOL_NS_GPL(xhci_pci_common_probe, "xhci");
684
685 /* handled by xhci-pci-renesas if enabled */
686 static const struct pci_device_id pci_ids_renesas[] = {
687 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014) },
688 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015) },
689 { /* end: all zeroes */ }
690 };
691
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)692 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
693 {
694 if (IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) &&
695 pci_match_id(pci_ids_renesas, dev))
696 return -ENODEV;
697
698 return xhci_pci_common_probe(dev, id);
699 }
700
xhci_pci_remove(struct pci_dev * dev)701 void xhci_pci_remove(struct pci_dev *dev)
702 {
703 struct xhci_hcd *xhci;
704 bool set_power_d3;
705
706 xhci = hcd_to_xhci(pci_get_drvdata(dev));
707 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP;
708
709 xhci->xhc_state |= XHCI_STATE_REMOVING;
710
711 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
712 pm_runtime_put(&dev->dev);
713 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
714 pm_runtime_forbid(&dev->dev);
715
716 if (xhci->shared_hcd) {
717 usb_remove_hcd(xhci->shared_hcd);
718 usb_put_hcd(xhci->shared_hcd);
719 xhci->shared_hcd = NULL;
720 }
721
722 usb_hcd_pci_remove(dev);
723
724 /* Workaround for spurious wakeups at shutdown with HSW */
725 if (set_power_d3)
726 pci_set_power_state(dev, PCI_D3hot);
727 }
728 EXPORT_SYMBOL_NS_GPL(xhci_pci_remove, "xhci");
729
730 /*
731 * In some Intel xHCI controllers, in order to get D3 working,
732 * through a vendor specific SSIC CONFIG register at offset 0x883c,
733 * SSIC PORT need to be marked as "unused" before putting xHCI
734 * into D3. After D3 exit, the SSIC port need to be marked as "used".
735 * Without this change, xHCI might not enter D3 state.
736 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)737 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
738 {
739 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
740 u32 val;
741 void __iomem *reg;
742 int i;
743
744 for (i = 0; i < SSIC_PORT_NUM; i++) {
745 reg = (void __iomem *) xhci->cap_regs +
746 SSIC_PORT_CFG2 +
747 i * SSIC_PORT_CFG2_OFFSET;
748
749 /* Notify SSIC that SSIC profile programming is not done. */
750 val = readl(reg) & ~PROG_DONE;
751 writel(val, reg);
752
753 /* Mark SSIC port as unused(suspend) or used(resume) */
754 val = readl(reg);
755 if (suspend)
756 val |= SSIC_PORT_UNUSED;
757 else
758 val &= ~SSIC_PORT_UNUSED;
759 writel(val, reg);
760
761 /* Notify SSIC that SSIC profile programming is done */
762 val = readl(reg) | PROG_DONE;
763 writel(val, reg);
764 readl(reg);
765 }
766 }
767
768 /*
769 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
770 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
771 */
xhci_pme_quirk(struct usb_hcd * hcd)772 static void xhci_pme_quirk(struct usb_hcd *hcd)
773 {
774 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
775 void __iomem *reg;
776 u32 val;
777
778 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
779 val = readl(reg);
780 writel(val | BIT(28), reg);
781 readl(reg);
782 }
783
xhci_sparse_control_quirk(struct usb_hcd * hcd)784 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
785 {
786 u32 reg;
787
788 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
789 reg &= ~BIT(SPARSE_DISABLE_BIT);
790 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
791 }
792
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)793 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
794 {
795 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
796 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
797 int ret;
798
799 /*
800 * Systems with the TI redriver that loses port status change events
801 * need to have the registers polled during D3, so avoid D3cold.
802 */
803 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
804 pci_d3cold_disable(pdev);
805
806 #ifdef CONFIG_SUSPEND
807 /* d3cold is broken, but only when s2idle is used */
808 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
809 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
810 pci_d3cold_disable(pdev);
811 #endif
812
813 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
814 xhci_pme_quirk(hcd);
815
816 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
817 xhci_ssic_port_unused_quirk(hcd, true);
818
819 if (xhci->quirks & XHCI_DISABLE_SPARSE)
820 xhci_sparse_control_quirk(hcd);
821
822 ret = xhci_suspend(xhci, do_wakeup);
823
824 /* synchronize irq when using MSI-X */
825 xhci_msix_sync_irqs(xhci);
826
827 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
828 xhci_ssic_port_unused_quirk(hcd, false);
829
830 return ret;
831 }
832
xhci_pci_resume(struct usb_hcd * hcd,pm_message_t msg)833 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
834 {
835 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
836 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
837 bool power_lost = msg.event == PM_EVENT_RESTORE;
838 bool is_auto_resume = msg.event == PM_EVENT_AUTO_RESUME;
839
840 reset_control_reset(xhci->reset);
841
842 /* The BIOS on systems with the Intel Panther Point chipset may or may
843 * not support xHCI natively. That means that during system resume, it
844 * may switch the ports back to EHCI so that users can use their
845 * keyboard to select a kernel from GRUB after resume from hibernate.
846 *
847 * The BIOS is supposed to remember whether the OS had xHCI ports
848 * enabled before resume, and switch the ports back to xHCI when the
849 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
850 * writers.
851 *
852 * Unconditionally switch the ports back to xHCI after a system resume.
853 * It should not matter whether the EHCI or xHCI controller is
854 * resumed first. It's enough to do the switchover in xHCI because
855 * USB core won't notice anything as the hub driver doesn't start
856 * running again until after all the devices (including both EHCI and
857 * xHCI host controllers) have been resumed.
858 */
859
860 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
861 usb_enable_intel_xhci_ports(pdev);
862
863 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
864 xhci_ssic_port_unused_quirk(hcd, false);
865
866 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
867 xhci_pme_quirk(hcd);
868
869 return xhci_resume(xhci, power_lost, is_auto_resume);
870 }
871
xhci_pci_poweroff_late(struct usb_hcd * hcd,bool do_wakeup)872 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
873 {
874 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
875 struct xhci_port *port;
876 struct usb_device *udev;
877 u32 portsc;
878 int i;
879
880 /*
881 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
882 * cause significant boot delay if usb ports are in suspended U3 state
883 * during boot. Some USB devices survive in U3 state over S4 hibernate
884 *
885 * Disable ports that are in U3 if remote wake is not enabled for either
886 * host controller or connected device
887 */
888
889 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
890 return 0;
891
892 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
893 port = &xhci->hw_ports[i];
894 portsc = readl(port->addr);
895
896 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
897 continue;
898
899 if (!port->slot_id || !xhci->devs[port->slot_id]) {
900 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
901 port->slot_id, port->rhub->hcd->self.busnum,
902 port->hcd_portnum + 1);
903 continue;
904 }
905
906 udev = xhci->devs[port->slot_id]->udev;
907
908 /* if wakeup is enabled then don't disable the port */
909 if (udev->do_remote_wakeup && do_wakeup)
910 continue;
911
912 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
913 port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
914 portsc = xhci_port_state_to_neutral(portsc);
915 writel(portsc | PORT_PE, port->addr);
916 }
917
918 return 0;
919 }
920
xhci_pci_shutdown(struct usb_hcd * hcd)921 static void xhci_pci_shutdown(struct usb_hcd *hcd)
922 {
923 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
924 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
925
926 xhci_shutdown(hcd);
927 xhci_cleanup_msix(xhci);
928
929 /* Yet another workaround for spurious wakeups at shutdown with HSW */
930 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
931 pci_set_power_state(pdev, PCI_D3hot);
932 }
933
934 /*-------------------------------------------------------------------------*/
935
936 /* PCI driver selection metadata; PCI hotplugging uses this */
937 static const struct pci_device_id pci_ids[] = {
938 /* handle any USB 3.0 xHCI controller */
939 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
940 },
941 { /* end: all zeroes */ }
942 };
943 MODULE_DEVICE_TABLE(pci, pci_ids);
944
945 /* pci driver glue; this is a "new style" PCI driver module */
946 static struct pci_driver xhci_pci_driver = {
947 .name = hcd_name,
948 .id_table = pci_ids,
949
950 .probe = xhci_pci_probe,
951 .remove = xhci_pci_remove,
952 /* suspend and resume implemented later */
953
954 .shutdown = usb_hcd_pci_shutdown,
955 .driver = {
956 .pm = pm_ptr(&usb_hcd_pci_pm_ops),
957 },
958 };
959
xhci_pci_init(void)960 static int __init xhci_pci_init(void)
961 {
962 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
963 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend);
964 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume);
965 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late);
966 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown);
967 xhci_pci_hc_driver.stop = xhci_pci_stop;
968 return pci_register_driver(&xhci_pci_driver);
969 }
970 module_init(xhci_pci_init);
971
xhci_pci_exit(void)972 static void __exit xhci_pci_exit(void)
973 {
974 pci_unregister_driver(&xhci_pci_driver);
975 }
976 module_exit(xhci_pci_exit);
977
978 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
979 MODULE_LICENSE("GPL");
980