1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 3 #ifndef _UAPI_ASM_X86_AMD_HSMP_H_ 4 #define _UAPI_ASM_X86_AMD_HSMP_H_ 5 6 #include <linux/types.h> 7 8 #pragma pack(4) 9 10 #define HSMP_MAX_MSG_LEN 8 11 12 /* 13 * HSMP client platforms (Ryzen Master SMC) accept at most four input 14 * argument words and four output/response words per message. 15 */ 16 #define HSMP_CLIENT_MAX_MSG_LEN 4 17 18 /* 19 * HSMP Messages supported 20 */ 21 enum hsmp_message_ids { 22 HSMP_TEST = 1, /* 01h Increments input value by 1 */ 23 HSMP_GET_SMU_VER, /* 02h SMU FW version */ 24 HSMP_GET_PROTO_VER, /* 03h HSMP interface version */ 25 HSMP_GET_SOCKET_POWER, /* 04h average package power consumption */ 26 HSMP_SET_SOCKET_POWER_LIMIT, /* 05h Set the socket power limit */ 27 HSMP_GET_SOCKET_POWER_LIMIT, /* 06h Get current socket power limit */ 28 HSMP_GET_SOCKET_POWER_LIMIT_MAX,/* 07h Get maximum socket power value */ 29 HSMP_SET_BOOST_LIMIT, /* 08h Set a core maximum frequency limit */ 30 HSMP_SET_BOOST_LIMIT_SOCKET, /* 09h Set socket maximum frequency level */ 31 HSMP_GET_BOOST_LIMIT, /* 0Ah Get current frequency limit */ 32 HSMP_GET_PROC_HOT, /* 0Bh Get PROCHOT status */ 33 HSMP_SET_XGMI_LINK_WIDTH, /* 0Ch Set max and min width of xGMI Link */ 34 HSMP_SET_DF_PSTATE, /* 0Dh Alter APEnable/Disable messages behavior */ 35 HSMP_SET_AUTO_DF_PSTATE, /* 0Eh Enable DF P-State Performance Boost algorithm */ 36 HSMP_GET_FCLK_MCLK, /* 0Fh Get FCLK and MEMCLK for current socket */ 37 HSMP_GET_CCLK_THROTTLE_LIMIT, /* 10h Get CCLK frequency limit in socket */ 38 HSMP_GET_C0_PERCENT, /* 11h Get average C0 residency in socket */ 39 HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */ 40 HSMP_GET_NBIO_DPM_LEVEL, /* 13h Get LCLK DPM level min and max for a given NBIO */ 41 HSMP_GET_DDR_BANDWIDTH, /* 14h Get theoretical maximum and current DDR Bandwidth */ 42 HSMP_GET_TEMP_MONITOR, /* 15h Get socket temperature */ 43 HSMP_GET_DIMM_TEMP_RANGE, /* 16h Get per-DIMM temperature range and refresh rate */ 44 HSMP_GET_DIMM_POWER, /* 17h Get per-DIMM power consumption */ 45 HSMP_GET_DIMM_THERMAL, /* 18h Get per-DIMM thermal sensors */ 46 HSMP_GET_SOCKET_FREQ_LIMIT, /* 19h Get current active frequency per socket */ 47 HSMP_GET_CCLK_CORE_LIMIT, /* 1Ah Get CCLK frequency limit per core */ 48 HSMP_GET_RAILS_SVI, /* 1Bh Get SVI-based Telemetry for all rails */ 49 HSMP_GET_SOCKET_FMAX_FMIN, /* 1Ch Get Fmax and Fmin per socket */ 50 HSMP_GET_IOLINK_BANDWITH, /* 1Dh Get current bandwidth on IO Link */ 51 HSMP_GET_XGMI_BANDWITH, /* 1Eh Get current bandwidth on xGMI Link */ 52 HSMP_SET_GMI3_WIDTH, /* 1Fh Set max and min GMI3 Link width */ 53 HSMP_SET_PCI_RATE, /* 20h Control link rate on PCIe devices */ 54 HSMP_SET_POWER_MODE, /* 21h Select power efficiency profile policy */ 55 HSMP_SET_PSTATE_MAX_MIN, /* 22h Set the max and min DF P-State */ 56 HSMP_GET_METRIC_TABLE_VER, /* 23h Get metrics table version */ 57 HSMP_GET_METRIC_TABLE, /* 24h Get metrics table */ 58 HSMP_GET_METRIC_TABLE_DRAM_ADDR,/* 25h Get metrics table dram address */ 59 HSMP_SET_XGMI_PSTATE_RANGE, /* 26h Set xGMI P-state range */ 60 HSMP_CPU_RAIL_ISO_FREQ_POLICY, /* 27h Get/Set Cpu Iso frequency policy */ 61 HSMP_DFC_ENABLE_CTRL, /* 28h Enable/Disable DF C-state */ 62 HSMP_PC6_ENABLE, /* 29h Get/Set PC6 enable/disable status */ 63 HSMP_CC6_ENABLE, /* 2Ah Get/Set CC6 enable/disable status */ 64 HSMP_GET_RAPL_UNITS = 0x30, /* 30h Get scaling factor for energy */ 65 HSMP_GET_RAPL_CORE_COUNTER, /* 31h Get core energy counter value */ 66 HSMP_GET_RAPL_PACKAGE_COUNTER, /* 32h Get package energy counter value */ 67 HSMP_DIMM_SB_RD, /* 33h Get DIMM sideband data */ 68 HSMP_READ_CCD_POWER, /* 34h Get average CCD power */ 69 HSMP_READ_TDELTA, /* 35h Get thermal behaviour */ 70 HSMP_GET_SVI3_VR_CTRL_TEMP, /* 36h Get SVI3 VR controller rail temp */ 71 HSMP_GET_ENABLED_HSMP_CMDS, /* 37h Get supported HSMP commands */ 72 HSMP_SET_GET_FLOOR_LIMIT, /* 38h Get/Set core floor frequency limit */ 73 HSMP_DIMM_SB_WR, /* 39h Set DIMM sideband data */ 74 HSMP_SDPS_LIMIT, /* 3Ah Get/Set SDPS limit */ 75 HSMP_PQOS_TRAFFIC_PRIORITY, /* 3Bh Get/Set traffic priority */ 76 HSMP_PQOS_FLOATING_BW, /* 3Ch Get/Set max floating bandwidth */ 77 HSMP_MSG_ID_MAX, 78 }; 79 80 /* 81 * The driver validates num_args and response_sz before sending a message. 82 * HSMP client platforms are bound to HSMP_CLIENT_MAX_MSG_LEN in each 83 * direction; server platforms are bound per-message by hsmp_msg_desc_table[]. 84 */ 85 struct hsmp_message { 86 __u32 msg_id; /* Message ID */ 87 __u16 num_args; /* Number of input argument words in message */ 88 __u16 response_sz; /* Number of expected output/response words */ 89 __u32 args[HSMP_MAX_MSG_LEN]; /* argument/response buffer */ 90 __u16 sock_ind; /* socket number */ 91 }; 92 93 enum hsmp_msg_type { 94 HSMP_RSVD = -1, 95 HSMP_SET = 0, 96 HSMP_GET = 1, 97 HSMP_SET_GET = 2, 98 }; 99 100 enum hsmp_proto_versions { 101 HSMP_PROTO_VER2 = 2, 102 HSMP_PROTO_VER3, 103 HSMP_PROTO_VER4, 104 HSMP_PROTO_VER5, 105 HSMP_PROTO_VER6, 106 HSMP_PROTO_VER7 107 }; 108 109 /* 110 * Ryzen Master SMC interface version, reported by 111 * HSMP_CLIENT_GET_INTERFACE_VER. Separate numbering space from enum 112 * hsmp_proto_versions, which applies to the server set only. 113 */ 114 enum ryzen_master_proto_versions { 115 RYZEN_MASTER_PROTO_VER1 = 1, 116 }; 117 118 struct hsmp_msg_desc { 119 int num_args; 120 int response_sz; 121 enum hsmp_msg_type type; 122 }; 123 124 /* 125 * User may use these comments as reference, please find the 126 * supported list of messages and message definition in the 127 * HSMP chapter of respective family/model PPR. 128 * 129 * Not supported messages would return -ENOMSG. 130 */ 131 static const struct hsmp_msg_desc hsmp_msg_desc_table[] 132 __attribute__((unused)) = { 133 /* RESERVED */ 134 {0, 0, HSMP_RSVD}, 135 136 /* 137 * HSMP_TEST, num_args = 1, response_sz = 1 138 * input: args[0] = xx 139 * output: args[0] = xx + 1 140 */ 141 {1, 1, HSMP_GET}, 142 143 /* 144 * HSMP_GET_SMU_VER, num_args = 0, response_sz = 1 145 * output: args[0] = smu fw ver 146 */ 147 {0, 1, HSMP_GET}, 148 149 /* 150 * HSMP_GET_PROTO_VER, num_args = 0, response_sz = 1 151 * output: args[0] = proto version 152 */ 153 {0, 1, HSMP_GET}, 154 155 /* 156 * HSMP_GET_SOCKET_POWER, num_args = 0, response_sz = 1 157 * output: args[0] = socket power in mWatts 158 */ 159 {0, 1, HSMP_GET}, 160 161 /* 162 * HSMP_SET_SOCKET_POWER_LIMIT, num_args = 1, response_sz = 0 163 * input: args[0] = power limit value in mWatts 164 */ 165 {1, 0, HSMP_SET}, 166 167 /* 168 * HSMP_GET_SOCKET_POWER_LIMIT, num_args = 0, response_sz = 1 169 * output: args[0] = socket power limit value in mWatts 170 */ 171 {0, 1, HSMP_GET}, 172 173 /* 174 * HSMP_GET_SOCKET_POWER_LIMIT_MAX, num_args = 0, response_sz = 1 175 * output: args[0] = maximuam socket power limit in mWatts 176 */ 177 {0, 1, HSMP_GET}, 178 179 /* 180 * HSMP_SET_BOOST_LIMIT, num_args = 1, response_sz = 0 181 * input: args[0] = apic id[31:16] + boost limit value in MHz[15:0] 182 */ 183 {1, 0, HSMP_SET}, 184 185 /* 186 * HSMP_SET_BOOST_LIMIT_SOCKET, num_args = 1, response_sz = 0 187 * input: args[0] = boost limit value in MHz 188 */ 189 {1, 0, HSMP_SET}, 190 191 /* 192 * HSMP_GET_BOOST_LIMIT, num_args = 1, response_sz = 1 193 * input: args[0] = apic id 194 * output: args[0] = boost limit value in MHz 195 */ 196 {1, 1, HSMP_GET}, 197 198 /* 199 * HSMP_GET_PROC_HOT, num_args = 0, response_sz = 1 200 * output: args[0] = proc hot status 201 */ 202 {0, 1, HSMP_GET}, 203 204 /* 205 * HSMP_SET_XGMI_LINK_WIDTH, num_args = 1, response_sz = 0/1 206 * input: args[0] = set/get XGMI Link width[31] (0 = set, 1 = get) + 207 * min link width[15:8] + max link width[7:0] 208 * Link width encoding: 0 = x4, 1 = x8, 2 = x16. 209 * On SET, max must be >= min. On GET, [15:0] are reserved. 210 * output: args[0] = reserved[31:16] + min link width[15:8] + 211 * max link width[7:0] 212 */ 213 {1, 1, HSMP_SET_GET}, 214 215 /* 216 * HSMP_SET_DF_PSTATE (APBDisable), num_args = 1, response_sz = 0/1 217 * input: args[0] = set APB_DISABLE / get APB state[31] 218 * (0 = set & lock DF P-state, 1 = get) + 219 * reserved[30:8] + 220 * DF P-state[7:0] (0..2; reserved on GET) 221 * output: args[0] = reserved[31:9] + 222 * APB state[8] (1 = disabled, 0 = enabled) + 223 * locked DF P-state[7:0] if [8] = 1, else reserved 224 */ 225 {1, 1, HSMP_SET_GET}, 226 227 /* HSMP_SET_AUTO_DF_PSTATE, num_args = 0, response_sz = 0 */ 228 {0, 0, HSMP_SET}, 229 230 /* 231 * HSMP_GET_FCLK_MCLK, num_args = 0, response_sz = 2 232 * output: args[0] = fclk in MHz, args[1] = mclk in MHz 233 */ 234 {0, 2, HSMP_GET}, 235 236 /* 237 * HSMP_GET_CCLK_THROTTLE_LIMIT, num_args = 0, response_sz = 1 238 * output: args[0] = core clock in MHz 239 */ 240 {0, 1, HSMP_GET}, 241 242 /* 243 * HSMP_GET_C0_PERCENT, num_args = 0, response_sz = 1 244 * output: args[0] = average c0 residency 245 */ 246 {0, 1, HSMP_GET}, 247 248 /* 249 * HSMP_SET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 0 250 * input: args[0] = nbioid[23:16] + max dpm level[15:8] + min dpm level[7:0] 251 */ 252 {1, 0, HSMP_SET}, 253 254 /* 255 * HSMP_GET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 1 256 * input: args[0] = nbioid[23:16] 257 * output: args[0] = max dpm level[15:8] + min dpm level[7:0] 258 */ 259 {1, 1, HSMP_GET}, 260 261 /* 262 * HSMP_GET_DDR_BANDWIDTH, num_args = 0, response_sz = 1 263 * output: args[0] = max bw in Gbps[31:20] + utilised bw in Gbps[19:8] + 264 * bw in percentage[7:0] 265 */ 266 {0, 1, HSMP_GET}, 267 268 /* 269 * HSMP_GET_TEMP_MONITOR, num_args = 0, response_sz = 1 270 * output: args[0] = temperature in degree celsius. [15:8] integer part + 271 * [7:5] fractional part 272 */ 273 {0, 1, HSMP_GET}, 274 275 /* 276 * HSMP_GET_DIMM_TEMP_RANGE, num_args = 1, response_sz = 1 277 * input: args[0] = DIMM address[7:0] 278 * output: args[0] = refresh rate[3] + temperature range[2:0] 279 */ 280 {1, 1, HSMP_GET}, 281 282 /* 283 * HSMP_GET_DIMM_POWER, num_args = 1, response_sz = 1 284 * input: args[0] = DIMM address[7:0] 285 * output: args[0] = DIMM power in mW[31:17] + update rate in ms[16:8] + 286 * DIMM address[7:0] 287 */ 288 {1, 1, HSMP_GET}, 289 290 /* 291 * HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1 292 * input: args[0] = DIMM address[7:0] 293 * output: args[0] = temperature in degree celsius[31:21] + update rate in ms[16:8] + 294 * DIMM address[7:0] 295 */ 296 {1, 1, HSMP_GET}, 297 298 /* 299 * HSMP_GET_SOCKET_FREQ_LIMIT, num_args = 0, response_sz = 1 300 * output: args[0] = frequency in MHz[31:16] + frequency source[15:0] 301 */ 302 {0, 1, HSMP_GET}, 303 304 /* 305 * HSMP_GET_CCLK_CORE_LIMIT, num_args = 1, response_sz = 1 306 * input: args[0] = apic id [31:0] 307 * output: args[0] = frequency in MHz[31:0] 308 */ 309 {1, 1, HSMP_GET}, 310 311 /* 312 * HSMP_GET_RAILS_SVI, num_args = 0, response_sz = 1 313 * output: args[0] = power in mW[31:0] 314 */ 315 {0, 1, HSMP_GET}, 316 317 /* 318 * HSMP_GET_SOCKET_FMAX_FMIN, num_args = 0, response_sz = 1 319 * output: args[0] = fmax in MHz[31:16] + fmin in MHz[15:0] 320 */ 321 {0, 1, HSMP_GET}, 322 323 /* 324 * HSMP_GET_IOLINK_BANDWITH, num_args = 1, response_sz = 1 325 * input: args[0] = link id[15:8] + bw type[2:0] 326 * output: args[0] = io bandwidth in Mbps[31:0] 327 */ 328 {1, 1, HSMP_GET}, 329 330 /* 331 * HSMP_GET_XGMI_BANDWITH, num_args = 1, response_sz = 1 332 * input: args[0] = link id[15:8] + bw type[2:0] 333 * output: args[0] = xgmi bandwidth in Mbps[31:0] 334 */ 335 {1, 1, HSMP_GET}, 336 337 /* 338 * HSMP_SET_GMI3_WIDTH, num_args = 1, response_sz = 0 339 * input: args[0] = min link width[15:8] + max link width[7:0] 340 */ 341 {1, 0, HSMP_SET}, 342 343 /* 344 * HSMP_SET_PCI_RATE, num_args = 1, response_sz = 1 345 * input: args[0] = link rate control value 346 * output: args[0] = previous link rate control value 347 */ 348 {1, 1, HSMP_SET}, 349 350 /* 351 * HSMP_SET_POWER_MODE (PwrEfficiencyModeSelection), 352 * num_args = 1, response_sz = 1 353 * input: args[0] = set/get policy[31] (0 = set, 1 = get) + 354 * high util point[30:24] + 355 * low util point[23:17] + 356 * PPT limit[16:5] + 357 * reserved[4:3] + mode selection[2:0] 358 * [30:5] are valid only when [2:0] is a balanced core mode 359 * (4 or 5). [2:0] is reserved when getting (bit[31] = 1). 360 * output: args[0] same layout, [31] reserved, [2:0] = arbitrated 361 * current efficiency mode. 362 */ 363 {1, 1, HSMP_SET_GET}, 364 365 /* 366 * HSMP_SET_PSTATE_MAX_MIN (DfPstateRange), num_args = 1, response_sz = 0/1 367 * input: args[0] = set/get DF P-state range[31] (0 = set, 1 = get) + 368 * reserved[30:16] + 369 * min DF P-state[15:8] + max DF P-state[7:0] 370 * DF P-state encoding: 0 = DFP0 (high performance), 371 * 1 = DFP1, 2 = DFP2 (low performance). 372 * [15:0] are reserved when getting (args[0] bit[31] = 1). 373 * output: args[0] = reserved[31:16] + min DF P-state[15:8] + 374 * max DF P-state[7:0] 375 */ 376 {1, 1, HSMP_SET_GET}, 377 378 /* 379 * HSMP_GET_METRIC_TABLE_VER, num_args = 0, response_sz = 1 380 * output: args[0] = metrics table version 381 */ 382 {0, 1, HSMP_GET}, 383 384 /* 385 * HSMP_GET_METRIC_TABLE, num_args = 0, response_sz = 0 386 */ 387 {0, 0, HSMP_GET}, 388 389 /* 390 * HSMP_GET_METRIC_TABLE_DRAM_ADDR, num_args = 0, response_sz = 3 391 * output: args[0] = lower 32 bits of the address 392 * output: args[1] = upper 32 bits of the address 393 * output: args[2] = DRAM region size in bytes 394 */ 395 {0, 3, HSMP_GET}, 396 397 /* 398 * HSMP_SET_XGMI_PSTATE_RANGE, num_args = 1, response_sz = 0 399 * input: args[0] = min xGMI p-state[15:8] + max xGMI p-state[7:0] 400 */ 401 {1, 0, HSMP_SET}, 402 403 /* 404 * HSMP_CPU_RAIL_ISO_FREQ_POLICY, num_args = 1, response_sz = 1 405 * input: args[0] = set/get policy[31] + 406 * disable/enable independent control[0] 407 * output: args[0] = current policy[0] 408 */ 409 {1, 1, HSMP_SET_GET}, 410 411 /* 412 * HSMP_DFC_ENABLE_CTRL, num_args = 1, response_sz = 1 413 * input: args[0] = set/get policy[31] + enable/disable DFC[0] 414 * output: args[0] = current policy[0] 415 */ 416 {1, 1, HSMP_SET_GET}, 417 418 /* 419 * HSMP_PC6_ENABLE (Pc6Enable), num_args = 1, response_sz = 0/1 420 * input: args[0] = set/get PC6 control[31] (0 = set, 1 = get) + 421 * reserved[30:1] + 422 * enable PC6[0] (0 = disable, 1 = enable; 423 * reserved on GET) 424 * output: args[0] = reserved[31:1] + current PC6 control[0] 425 * (last value configured via HSMP or APML) 426 */ 427 {1, 1, HSMP_SET_GET}, 428 429 /* 430 * HSMP_CC6_ENABLE (CC6Enable), num_args = 1, response_sz = 0/1 431 * Configures CC6 enable for all cores; changing the setting does 432 * not by itself transition cores in or out of CC6. 433 * input: args[0] = set/get CC6 control[31] (0 = set, 1 = get) + 434 * reserved[30:1] + 435 * enable CC6[0] (0 = disable, 1 = enable; 436 * reserved on GET) 437 * output: args[0] = reserved[31:1] + current CC6 control[0] 438 * (last value configured via HSMP or APML) 439 */ 440 {1, 1, HSMP_SET_GET}, 441 442 /* RESERVED(0x2B-0x2F) */ 443 {0, 0, HSMP_RSVD}, 444 {0, 0, HSMP_RSVD}, 445 {0, 0, HSMP_RSVD}, 446 {0, 0, HSMP_RSVD}, 447 {0, 0, HSMP_RSVD}, 448 449 /* 450 * HSMP_GET_RAPL_UNITS, response_sz = 1 451 * output: args[0] = tu value[19:16] + esu value[12:8] 452 */ 453 {0, 1, HSMP_GET}, 454 455 /* 456 * HSMP_GET_RAPL_CORE_COUNTER, num_args = 1, response_sz = 1 457 * input: args[0] = apic id[15:0] 458 * output: args[0] = lower 32 bits of energy 459 * output: args[1] = upper 32 bits of energy 460 */ 461 {1, 2, HSMP_GET}, 462 463 /* 464 * HSMP_GET_RAPL_PACKAGE_COUNTER, num_args = 0, response_sz = 1 465 * output: args[0] = lower 32 bits of energy 466 * output: args[1] = upper 32 bits of energy 467 */ 468 {0, 2, HSMP_GET}, 469 470 /* 471 * HSMP_DIMM_SB_RD, num_args = 1, response_sz = 1 472 * input: args[0] = reg space[23] + reg offset[22:12] + 473 * device LID[11:8] + DIMM address[7:0] 474 * output: args[0] = read data byte[3:0] 475 */ 476 {1, 1, HSMP_GET}, 477 478 /* 479 * HSMP_READ_CCD_POWER, num_args = 1, response_sz = 1 480 * input: args[0] = apic id of core[15:0] 481 * output: args[0] = CCD power(mWatts)[31:0] 482 */ 483 {1, 1, HSMP_GET}, 484 485 /* 486 * HSMP_READ_TDELTA, num_args = 0, response_sz = 1 487 * output: args[0] = thermal behaviour[31:0] 488 */ 489 {0, 1, HSMP_GET}, 490 491 /* 492 * HSMP_GET_SVI3_VR_CTRL_TEMP, num_args = 1, response_sz = 1 493 * input: args[0] = SVI3 rail index[3:1] + read temperature[0] 494 * output: args[0] = SVI3 rail index[30:28] + 495 * rail temperature in degree C[27:0] 496 */ 497 {1, 1, HSMP_GET}, 498 499 /* 500 * HSMP_GET_ENABLED_HSMP_CMDS, num_args = 1, response_sz = 3 501 * input: args[0] = HSMP command mask[0] 502 * output: status of HSMP command = args[0], args[1], args[2] 503 */ 504 {1, 3, HSMP_GET}, 505 506 /* 507 * HSMP_SET_GET_FLOOR_LIMIT, num_args = 1, response_sz = 1 508 * input: args[0] = op[31:30] + reserved[29:28] + 509 * apic id[27:16] + floor frequency MHz[15:0] 510 * op encoding: 00 = set per-core floor, 511 * 01 = set all-cores floor (apic id reserved), 512 * 10 = get per-core floor, 513 * 11 = get per-core effective floor. 514 * Floor frequency field is reserved on GET (bit[31] = 1). 515 * output: args[0] = floor frequency MHz[15:0] 516 * (effective for op 11, configured for op 10; 517 * reserved on SET) 518 */ 519 {1, 1, HSMP_SET_GET}, 520 521 /* 522 * HSMP_DIMM_SB_WR, num_args = 1, response_sz = 0 523 * input: args[0] = write data[31:24] + reg space[23] + 524 * reg offset[22:12] + device LID[11:8] + 525 * DIMM address[7:0] 526 */ 527 {1, 0, HSMP_SET}, 528 529 /* 530 * HSMP_SDPS_LIMIT, num_args = 1, response_sz = 1 531 * input: args[0] = set/get SDPS limit[31] (0 = set, 1 = get) + 532 * SDPS limit[30:0] 533 * output: args[0] = SDPS limit[30:0] 534 */ 535 {1, 1, HSMP_SET_GET}, 536 537 /* 538 * HSMP_PQOS_TRAFFIC_PRIORITY, num_args = 1, response_sz = 1 539 * input: args[0] = op[31:30] + priority sel[27:26] + 540 * priority val[21:20] + input[19:0] 541 * output: args[0] = supported priorities or priority val[1:0] 542 */ 543 {1, 1, HSMP_SET_GET}, 544 545 /* 546 * HSMP_PQOS_FLOATING_BW, num_args = 1, response_sz = 2 547 * input: args[0] = op[31] + sub-op[30:29] + params[28:0] 548 * output: args[0] = discovery bits or floating/global memory BW (Gbps) 549 * output: args[1] = reserved or config (drop adj, sampling delay, 550 * hysteresis) 551 */ 552 {1, 2, HSMP_SET_GET}, 553 }; 554 555 /* Metrics table (supported only with proto version 6) */ 556 struct hsmp_metric_table { 557 __u32 accumulation_counter; 558 559 /* TEMPERATURE */ 560 __u32 max_socket_temperature; 561 __u32 max_vr_temperature; 562 __u32 max_hbm_temperature; 563 __u64 max_socket_temperature_acc; 564 __u64 max_vr_temperature_acc; 565 __u64 max_hbm_temperature_acc; 566 567 /* POWER */ 568 __u32 socket_power_limit; 569 __u32 max_socket_power_limit; 570 __u32 socket_power; 571 572 /* ENERGY */ 573 __u64 timestamp; 574 __u64 socket_energy_acc; 575 __u64 ccd_energy_acc; 576 __u64 xcd_energy_acc; 577 __u64 aid_energy_acc; 578 __u64 hbm_energy_acc; 579 580 /* FREQUENCY */ 581 __u32 cclk_frequency_limit; 582 __u32 gfxclk_frequency_limit; 583 __u32 fclk_frequency; 584 __u32 uclk_frequency; 585 __u32 socclk_frequency[4]; 586 __u32 vclk_frequency[4]; 587 __u32 dclk_frequency[4]; 588 __u32 lclk_frequency[4]; 589 __u64 gfxclk_frequency_acc[8]; 590 __u64 cclk_frequency_acc[96]; 591 592 /* FREQUENCY RANGE */ 593 __u32 max_cclk_frequency; 594 __u32 min_cclk_frequency; 595 __u32 max_gfxclk_frequency; 596 __u32 min_gfxclk_frequency; 597 __u32 fclk_frequency_table[4]; 598 __u32 uclk_frequency_table[4]; 599 __u32 socclk_frequency_table[4]; 600 __u32 vclk_frequency_table[4]; 601 __u32 dclk_frequency_table[4]; 602 __u32 lclk_frequency_table[4]; 603 __u32 max_lclk_dpm_range; 604 __u32 min_lclk_dpm_range; 605 606 /* XGMI */ 607 __u32 xgmi_width; 608 __u32 xgmi_bitrate; 609 __u64 xgmi_read_bandwidth_acc[8]; 610 __u64 xgmi_write_bandwidth_acc[8]; 611 612 /* ACTIVITY */ 613 __u32 socket_c0_residency; 614 __u32 socket_gfx_busy; 615 __u32 dram_bandwidth_utilization; 616 __u64 socket_c0_residency_acc; 617 __u64 socket_gfx_busy_acc; 618 __u64 dram_bandwidth_acc; 619 __u32 max_dram_bandwidth; 620 __u64 dram_bandwidth_utilization_acc; 621 __u64 pcie_bandwidth_acc[4]; 622 623 /* THROTTLERS */ 624 __u32 prochot_residency_acc; 625 __u32 ppt_residency_acc; 626 __u32 socket_thm_residency_acc; 627 __u32 vr_thm_residency_acc; 628 __u32 hbm_thm_residency_acc; 629 __u32 spare; 630 631 /* New items at the end to maintain driver compatibility */ 632 __u32 gfxclk_frequency[8]; 633 }; 634 635 /** 636 * struct hsmp_telemetry_data - Request descriptor for HSMP telemetry IOCTL 637 * @buf: Input. Userspace pointer (encoded as __u64 to keep the layout 638 * stable between 32-bit and 64-bit callers) to the destination 639 * buffer that receives the metric table. 640 * @size: Input. Size in bytes of the buffer pointed to by @buf, and the 641 * number of bytes copied out on success. Must be non-zero and no 642 * larger than the metric table size firmware reports for this 643 * socket; a larger value is rejected with -EINVAL rather than 644 * short-written. A smaller value returns the leading @size bytes 645 * of the snapshot. The kernel does not write this field back. 646 * @sock_ind: Input. Socket index from which the metric table is read. 647 * @reserved: Reserved for future use. Callers should set this to zero; 648 * future kernels may begin interpreting the field, so passing 649 * a non-zero value today is not forwards compatible. 650 * 651 * Placing @buf first lets all fields fall on their natural alignment under 652 * the surrounding #pragma pack(4), so the struct is a tight 16 bytes with 653 * the same wire layout on 32-bit and 64-bit userspace. 654 * 655 * The metric table layout depends on the HSMP protocol version reported by 656 * firmware, which userspace can read from the protocol_version sysfs 657 * attribute. Protocol version 6 uses struct hsmp_metric_table, so callers on 658 * that version pass sizeof(struct hsmp_metric_table). Later version metrics 659 * table layout is documented in the Public PPR. 660 */ 661 struct hsmp_telemetry_data { 662 __u64 buf; 663 __u32 size; 664 __u16 sock_ind; 665 __u16 reserved; 666 }; 667 668 /* Reset to default packing */ 669 #pragma pack() 670 671 /* Define unique ioctl command for hsmp msgs using generic _IOWR */ 672 #define HSMP_BASE_IOCTL_NR 0xF8 673 #define HSMP_IOCTL_CMD _IOWR(HSMP_BASE_IOCTL_NR, 0, struct hsmp_message) 674 675 /* 676 * Fetch the firmware metric (telemetry) table for a given socket via the 677 * HSMP character device. This avoids the PAGE_SIZE limitation of the 678 * sysfs binary attribute path for tables larger than one page (such as the 679 * ~13 KB table used by HSMP protocol version 7). 680 * 681 * The direction is _IOW because the kernel only reads the request struct; 682 * the table itself is written to the buffer that @buf points at. 683 */ 684 #define HSMP_IOCTL_GET_TELEMETRY_DATA \ 685 _IOW(HSMP_BASE_IOCTL_NR, 1, struct hsmp_telemetry_data) 686 687 /** 688 * enum hsmp_client_message_ids - Ryzen Master SMC (RMSMC) message IDs 689 * @HSMP_CLIENT_TEST: 01h. Test message. input: args[0] = xx. output: 690 * args[0] = xx + 1. 691 * @HSMP_CLIENT_GET_SMU_VER: 02h. Get MP1 firmware version. output: 692 * args[0] = MP1 firmware version. 693 * @HSMP_CLIENT_GET_INTERFACE_VER: 03h. Get interface version. output: 694 * args[0] = interface version. 695 * @HSMP_CLIENT_GET_METRICS_TABLE_VER: 04h. Get metrics table version. 696 * output: args[0] = metrics table version. 697 * @HSMP_CLIENT_GET_METRICS_TABLE: 05h. Get metrics table. No arguments. 698 * Success means firmware has written the metrics table to the DRAM 699 * address reported by @HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR. 700 * @HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR: 06h. Get metrics table DRAM 701 * address. output: args[0] = address[31:0], args[1] = address[63:32], 702 * args[2] = table size in bytes. 703 * @HSMP_CLIENT_SET_CORE_PSM_MARGIN: 07h. Set core voltage margin. input: 704 * args[0] = ccx number[31:28] + core number[27:20] + reserved[19:16] + 705 * margin in mV[15:0]. 706 * @HSMP_CLIENT_SET_ALL_CORE_PSM_MARGIN: 08h. Set voltage margin for all 707 * cores. input: args[0] = margin in mV[15:0]. 708 * @HSMP_CLIENT_SET_FAST_PPT_LIMIT: 09h. Set APU fast PPT limit. input: 709 * args[0] = limit in mW. 710 * @HSMP_CLIENT_SET_VRM_VDD_CURRENT_LIMIT: 0Ah. Set VDDCR_VDD TDC. input: 711 * args[0] = limit in mA. 712 * @HSMP_CLIENT_SET_VRM_VDD_MAX_CURRENT_LIMIT: 0Bh. Set VDDCR_VDD EDC. 713 * input: args[0] = limit in mA. 714 * @HSMP_CLIENT_SET_TJ_MAX: 0Ch. Set maximum junction temperature. input: 715 * args[0] = temperature in degrees C. 716 * @HSMP_CLIENT_SET_FIT_LIMIT_SCALAR: 0Dh. Set failures-in-time limit 717 * scalar. input: args[0] = scalar (0 to 100). 718 * @HSMP_CLIENT_ENABLE_OVERCLOCKING: 0Eh. Enable overclocking. No 719 * arguments. 720 * @HSMP_CLIENT_DISABLE_OVERCLOCKING: 0Fh. Disable overclocking. No 721 * arguments. 722 * @HSMP_CLIENT_SET_OVERCLOCK_FREQ_ALL_CORES: 10h. Set all-core overclock 723 * frequency. input: args[0] = frequency in MHz[15:0]. 724 * @HSMP_CLIENT_SET_OVERCLOCK_FREQ_PER_CORE: 11h. Set per-core overclock 725 * frequency. input: args[0] = ccd number[31:28] + ccx number[27:24] + 726 * core number[23:20] + frequency in MHz[19:0]. 727 * @HSMP_CLIENT_SET_OVERCLOCK_VID: 12h. Set overclock VID. input: 728 * args[0] = reserved[31:17] + vid[16:8] + pstate[7:0]. 729 * @HSMP_CLIENT_SPARE_0X13: 13h. Reserved. 730 * @HSMP_CLIENT_GET_CORE_PERF_ORDER: 14h. Get core performance order. 731 * input: args[0] = core performance rank index[31:0] (0 to Enabled 732 * cores-1). output: args[0] = voltage in mV[31:21] + frequency in 733 * MHz[20:9] + fll[8:6] + core number[5:2] + ccx number[1:0]. 734 * @HSMP_CLIENT_SET_SUSTAINED_POWER_LIMIT: 15h. Set SOC sustained power 735 * limit. input: args[0] = limit in mW. 736 * @HSMP_CLIENT_SET_SLOW_PPT_LIMIT: 16h. Set APU slow PPT limit. input: 737 * args[0] = limit in mW. 738 * @HSMP_CLIENT_SET_VRM_GFX_MAX_CURRENT_LIMIT: 17h. Set VDDCR_GFX EDC. 739 * input: args[0] = limit in mA. 740 * @HSMP_CLIENT_SET_VRM_SOC_CURRENT_LIMIT: 18h. Set VDDCR_SOC TDC. input: 741 * args[0] = limit in mA. 742 * @HSMP_CLIENT_SET_FAST_SPM_LIMIT: 19h. Set fast SPM limit. input: 743 * args[0] = limit in mW. 744 * @HSMP_CLIENT_SET_SLOW_SPM_LIMIT: 1Ah. Set slow SPM limit. input: 745 * args[0] = limit in mW. 746 * @HSMP_CLIENT_GET_CORE_PSM_MARGIN: 1Bh. Get core voltage margin. input: 747 * args[0] = ccx number[31:28] + core number[27:20] + reserved[19:0]. 748 * output: args[0] = ccx number[31:28] + core number[27:20] + 749 * reserved[19:16] + margin in mV[15:0]. 750 * @HSMP_CLIENT_GET_GFX_PSM_MARGIN: 1Ch. Get graphics voltage margin. 751 * output: args[0] = margin in mV[15:0]. 752 * @HSMP_CLIENT_SPARE_0X1D: 1Dh. Reserved. 753 * @HSMP_CLIENT_SPARE_0X1E: 1Eh. Reserved. 754 * @HSMP_CLIENT_SPARE_0X1F: 1Fh. Reserved. 755 * @HSMP_CLIENT_SPARE_0X20: 20h. Reserved. 756 * @HSMP_CLIENT_SET_GFXCLK_OVERDRIVE_BY_FREQ_VID: 21h. Set GfxClk 757 * overdrive by frequency/VID. input: args[0] = reserved[31:25] + 758 * vid[24:16] + frequency in MHz[15:0]. 759 * @HSMP_CLIENT_DISABLE_GFXCLK_OVERDRIVE: 22h. Disable GfxClk overdrive. 760 * No arguments. 761 * @HSMP_CLIENT_SET_GFX_PSM_MARGIN: 23h. Set graphics voltage margin. 762 * input: args[0] = margin in mV[15:0]. 763 * @HSMP_CLIENT_SET_CCLK_FMAX_OFFSET: 24h. Set CCLK Fmax offset. input: 764 * args[0] = maximum frequency in MHz[15:0]. 765 * @HSMP_CLIENT_SET_CORE_POWER_LIMIT_OFFSET: 25h. Set core power limit 766 * offset. input: args[0] = limit in mW. 767 * @HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND: 26h. Add extra core PSM 768 * guardband. input: args[0] = PsmGuardband[2][31:24] + 769 * PsmGuardband[1][23:16] + PsmGuardband[0][15:8] + TriggerUpdate[7] + 770 * AvfsType[6:4] + frequency index[3:0]. 771 * @HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND_GFX: 27h. Add extra graphics PSM 772 * guardband. input: args[0] = PsmGuardband[2][31:24] + 773 * PsmGuardband[1][23:16] + PsmGuardband[0][15:8] + TriggerUpdate[7] + 774 * frequency index[6:0]. 775 * @HSMP_CLIENT_SET_GFXCLK_FMAX: 28h. Set GfxClk Fmax. input: args[0] = 776 * maximum frequency in MHz[15:0]. 777 * @HSMP_CLIENT_MSG_ID_MAX: Number of message IDs, not a valid ID itself. 778 * 779 * Message IDs accepted on the Family 1Ah client platforms, Models 80h-8Fh 780 * and E0h-E3h. These parts drive one mailbox and speak the Ryzen Master 781 * SMC message set instead of the server HSMP message set enumerated in 782 * &enum hsmp_message_ids. Not all platforms support all messages; consult 783 * the supported list of messages in the HSMP chapter of the respective 784 * family/model PPR. Unsupported messages return -ENOMSG. 785 */ 786 enum hsmp_client_message_ids { 787 HSMP_CLIENT_TEST = 1, 788 HSMP_CLIENT_GET_SMU_VER, 789 HSMP_CLIENT_GET_INTERFACE_VER, 790 HSMP_CLIENT_GET_METRICS_TABLE_VER, 791 HSMP_CLIENT_GET_METRICS_TABLE, 792 HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR, 793 HSMP_CLIENT_SET_CORE_PSM_MARGIN, 794 HSMP_CLIENT_SET_ALL_CORE_PSM_MARGIN, 795 HSMP_CLIENT_SET_FAST_PPT_LIMIT, 796 HSMP_CLIENT_SET_VRM_VDD_CURRENT_LIMIT, 797 HSMP_CLIENT_SET_VRM_VDD_MAX_CURRENT_LIMIT, 798 HSMP_CLIENT_SET_TJ_MAX, 799 HSMP_CLIENT_SET_FIT_LIMIT_SCALAR, 800 HSMP_CLIENT_ENABLE_OVERCLOCKING, 801 HSMP_CLIENT_DISABLE_OVERCLOCKING, 802 HSMP_CLIENT_SET_OVERCLOCK_FREQ_ALL_CORES, 803 HSMP_CLIENT_SET_OVERCLOCK_FREQ_PER_CORE, 804 HSMP_CLIENT_SET_OVERCLOCK_VID, 805 HSMP_CLIENT_SPARE_0X13, 806 HSMP_CLIENT_GET_CORE_PERF_ORDER, 807 HSMP_CLIENT_SET_SUSTAINED_POWER_LIMIT, 808 HSMP_CLIENT_SET_SLOW_PPT_LIMIT, 809 HSMP_CLIENT_SET_VRM_GFX_MAX_CURRENT_LIMIT, 810 HSMP_CLIENT_SET_VRM_SOC_CURRENT_LIMIT, 811 HSMP_CLIENT_SET_FAST_SPM_LIMIT, 812 HSMP_CLIENT_SET_SLOW_SPM_LIMIT, 813 HSMP_CLIENT_GET_CORE_PSM_MARGIN, 814 HSMP_CLIENT_GET_GFX_PSM_MARGIN, 815 HSMP_CLIENT_SPARE_0X1D, 816 HSMP_CLIENT_SPARE_0X1E, 817 HSMP_CLIENT_SPARE_0X1F, 818 HSMP_CLIENT_SPARE_0X20, 819 HSMP_CLIENT_SET_GFXCLK_OVERDRIVE_BY_FREQ_VID, 820 HSMP_CLIENT_DISABLE_GFXCLK_OVERDRIVE, 821 HSMP_CLIENT_SET_GFX_PSM_MARGIN, 822 HSMP_CLIENT_SET_CCLK_FMAX_OFFSET, 823 HSMP_CLIENT_SET_CORE_POWER_LIMIT_OFFSET, 824 HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND, 825 HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND_GFX, 826 HSMP_CLIENT_SET_GFXCLK_FMAX, 827 HSMP_CLIENT_MSG_ID_MAX, 828 }; 829 830 #define HSMP_TELEMETRY_RM_MAX_CCX 4 831 #define HSMP_TELEMETRY_RM_CORES_PER_CCX 12 832 #define HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE 8 833 #define HSMP_TELEMETRY_RM_NPU_BUSY_DOMAINS 3 834 #define HSMP_TELEMETRY_RM_OC_DOMAINS 5 835 #define HSMP_TELEMETRY_RM_OC_SUBDOMAINS 5 836 #define HSMP_TELEMETRY_RM_OC_GUARDBANDS 3 837 838 /* Firmware packs this table to a 4-byte boundary */ 839 #pragma pack(push, 4) 840 841 /* 842 * struct hsmp_telemetry_table_rm_iod - I/O die counters for RM telemetry. 843 * 844 * Accumulator (*_acc) fields are monotonic counters; consumers derive 845 * deltas across two snapshots and normalise by accumulation_counter. 846 */ 847 struct hsmp_telemetry_table_rm_iod { 848 __u32 accumulation_counter; 849 850 /* SET VOLTAGES */ 851 __u64 vddcr_set_voltage; 852 __u64 vddcr_soc_set_voltage; 853 __u64 vddcr_npu_set_voltage; 854 __u64 vddcr_lp_set_voltage; 855 __u64 vddcr_gfx_set_voltage; 856 __u64 vdd_misc_set_voltage; 857 858 /* TELEMETRY VOLTAGES */ 859 __u64 vddcr_telemetry_voltage; 860 __u64 vddcr_soc_telemetry_voltage; 861 __u64 vddcr_npu_telemetry_voltage; 862 __u64 vddcr_lp_telemetry_voltage; 863 __u64 vddcr_gfx_telemetry_voltage; 864 __u64 vdd_misc_telemetry_voltage; 865 866 /* TELEMETRY POWERS */ 867 __u64 vddcr_telemetry_power; 868 __u64 vddcr_soc_telemetry_power; 869 __u64 vddcr_npu_telemetry_power; 870 __u64 vddcr_lp_telemetry_power; 871 __u64 vddcr_gfx_telemetry_power; 872 __u64 vdd_misc_telemetry_power; 873 874 /* THROTTLERS - FAST PPT */ 875 __u32 fppt_fused_limit; 876 __u32 fppt_max_irm_limit; 877 __u32 fppt_max_pbo_limit; 878 __u32 fppt_limit; 879 __u64 fppt_value_acc; 880 __u32 fppt_residency_acc; 881 882 /* THROTTLERS - SLOW PPT */ 883 __u32 sppt_fused_limit; 884 __u32 sppt_max_irm_limit; 885 __u32 sppt_max_pbo_limit; 886 __u32 sppt_limit; 887 __u64 sppt_value_acc; 888 __u32 sppt_residency_acc; 889 890 /* THROTTLERS - SPL */ 891 __u32 spl_fused_limit; 892 __u32 spl_max_irm_limit; 893 __u32 spl_max_pbo_limit; 894 __u32 spl_limit; 895 __u64 spl_value_acc; 896 __u32 spl_residency_acc; 897 898 /* THROTTLERS - TDC VDDCR */ 899 __u32 tdc_vddcr_fused_limit; 900 __u32 tdc_vddcr_max_irm_limit; 901 __u32 tdc_vddcr_max_pbo_limit; 902 __u32 tdc_vddcr_limit; 903 __u64 tdc_vddcr_value_acc; 904 __u32 tdc_vddcr_residency_acc; 905 906 /* THROTTLERS - TDC VDDCR SOC */ 907 __u32 tdc_vddcr_soc_fused_limit; 908 __u32 tdc_vddcr_soc_max_irm_limit; 909 __u32 tdc_vddcr_soc_max_pbo_limit; 910 __u32 tdc_vddcr_soc_limit; 911 __u64 tdc_vddcr_soc_value_acc; 912 __u32 tdc_vddcr_soc_residency_acc; 913 914 /* THROTTLERS - TDC VDDCR NPU */ 915 __u32 tdc_vddcr_npu_fused_limit; 916 __u32 tdc_vddcr_npu_max_irm_limit; 917 __u32 tdc_vddcr_npu_max_pbo_limit; 918 __u32 tdc_vddcr_npu_limit; 919 __u64 tdc_vddcr_npu_value_acc; 920 __u32 tdc_vddcr_npu_residency_acc; 921 922 /* THROTTLERS - TDC VDDCR LP */ 923 __u32 tdc_vddcr_lp_fused_limit; 924 __u32 tdc_vddcr_lp_max_irm_limit; 925 __u32 tdc_vddcr_lp_max_pbo_limit; 926 __u32 tdc_vddcr_lp_limit; 927 __u64 tdc_vddcr_lp_value_acc; 928 __u32 tdc_vddcr_lp_residency_acc; 929 930 /* THROTTLERS - TDC VDDCR GFX */ 931 __u32 tdc_vddcr_gfx_fused_limit; 932 __u32 tdc_vddcr_gfx_max_irm_limit; 933 __u32 tdc_vddcr_gfx_max_pbo_limit; 934 __u32 tdc_vddcr_gfx_limit; 935 __u64 tdc_vddcr_gfx_value_acc; 936 __u32 tdc_vddcr_gfx_residency_acc; 937 938 /* THROTTLERS - EDC VDDCR */ 939 __u32 edc_vddcr_fused_limit; 940 __u32 edc_vddcr_max_irm_limit; 941 __u32 edc_vddcr_max_pbo_limit; 942 __u32 edc_vddcr_limit; 943 944 /* THROTTLERS - THERMAL */ 945 __u32 thm_fused_limit; 946 __u32 thm_limit; 947 __u64 thm_value_acc; 948 __u32 thm_residency_acc; 949 __u32 prochot_residency_acc; 950 __u64 gfx_temp_acc; 951 __u64 soc_temp_acc; 952 __u32 p3t_fused_limit; 953 __u64 p3t_value_acc; 954 955 /* POWER */ 956 __u64 system_power_acc; 957 __u64 apu_power_acc; 958 __u64 dgpu_power_acc; 959 __u64 npu_power_acc; 960 961 /* FREQUENCIES */ 962 __u64 fclk_freq_eff_acc; 963 __u64 memclk_freq_eff_acc; 964 __u64 lclk_freq_eff_acc; 965 __u64 gfxclk_freq_eff_acc; 966 __u64 socclk_freq_eff_acc; 967 __u64 vclk_freq_eff_acc; 968 __u64 vpeclk_freq_eff_acc; 969 __u64 aieclk_freq_eff_acc; 970 __u64 npuhclk_freq_eff_acc; 971 972 /* BANDWIDTH */ 973 __u64 dram_read_bandwidth; 974 __u64 dram_write_bandwidth; 975 976 /* ACTIVITY MONITORS */ 977 __u64 gfx_busy_acc; 978 __u64 vcn_busy_acc; 979 __u64 npu_busy_acc[HSMP_TELEMETRY_RM_NPU_BUSY_DOMAINS]; 980 981 /* STT (Skin Temperature Tracking) */ 982 __u32 stt_min_limit; 983 __u64 stt_apu_hot_spot_temp_acc; 984 __u64 stt_hs2_hot_spot_temp_acc; 985 __u32 stt_apu_temp_limit; 986 __u64 stt_apu_skin_temp_acc; 987 988 /* RESIDENCIES - per-CCX CPU off */ 989 __u64 cpu_off_residency[HSMP_TELEMETRY_RM_MAX_CCX]; 990 991 /* DF P-STATES */ 992 __u32 fclk_freq_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; 993 __u32 uclk_freq_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; 994 __u32 ddr_rate_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; 995 __u8 df_pstate_source[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; 996 997 /* SYSTEM */ 998 __u8 gfx_disabled; 999 __u8 spare2[3]; 1000 __u32 gfxclk_fmax; 1001 __u8 cclk_core_fuse_enable[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1002 __u8 cclk_core_enabled[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1003 __u32 cclk_fmax[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1004 1005 /* OVERCLOCK CAPABLE */ 1006 __u8 cpu_precise_and_direct_oc_capable; 1007 __u8 gfx_precise_and_direct_oc_capable; 1008 __u8 pbo_basic_oc_capable; 1009 __u8 pbo_advanced_oc_capable; 1010 __u8 pbo_nitro_oc_capable; 1011 __u8 memory_and_fabric_oc_capable; 1012 __u8 misc_oc_capable; 1013 __u8 extreme_cold_oc_capable; 1014 __u8 down_config_control_capable; 1015 __u8 spare0[3]; 1016 1017 /* OVERCLOCK STATUS */ 1018 __u32 fit_limit_scalar; 1019 __u8 ln2_enabled; 1020 __u8 cpu_precise_and_direct_oc_enabled; 1021 __u8 gfx_precise_and_direct_oc_enabled; 1022 __u8 spare1[2]; 1023 __s8 psm_guardband[HSMP_TELEMETRY_RM_OC_DOMAINS] 1024 [HSMP_TELEMETRY_RM_OC_SUBDOMAINS] 1025 [HSMP_TELEMETRY_RM_OC_GUARDBANDS]; 1026 __s32 core_power_limit_offset; 1027 __u32 max_freq_offset[HSMP_TELEMETRY_RM_OC_DOMAINS]; 1028 1029 __u64 npu_temp_acc; 1030 __u64 df_pstate_residency_acc[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; 1031 __u32 cclk_fboost; 1032 1033 /* PMF */ 1034 __u32 pmf_fast_apu_ppt_limit; 1035 __u64 pmf_fast_apu_ppt_value_acc; 1036 __u32 pmf_fast_apu_ppt_residency_acc; 1037 1038 __u32 pmf_slow_apu_ppt_limit; 1039 __u64 pmf_slow_apu_ppt_value_acc; 1040 __u32 pmf_slow_apu_ppt_residency_acc; 1041 1042 __u32 pmf_fast_spm_limit; 1043 __u64 pmf_fast_spm_value_acc; 1044 __u32 pmf_fast_spm_residency_acc; 1045 1046 __u32 pmf_slow_spm_limit; 1047 __u64 pmf_slow_spm_value_acc; 1048 __u32 pmf_slow_spm_residency_acc; 1049 1050 __u32 spare3[5]; 1051 }; 1052 1053 /* 1054 * struct hsmp_telemetry_table_rm_ccx - Per-CCX core counters for RM telemetry. 1055 * 1056 * Arrays are sized for the maximum cores per CCX; use the 1057 * cclk_core_enabled[] mask in struct hsmp_telemetry_table_rm_iod to tell 1058 * which entries are valid. 1059 */ 1060 struct hsmp_telemetry_table_rm_ccx { 1061 __u64 core_c0[HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1062 __u64 core_cc6[HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1063 __u64 core_freq[HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1064 __u64 core_freq_eff[HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1065 __u64 core_temp[HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1066 __u64 core_power[HSMP_TELEMETRY_RM_CORES_PER_CCX]; 1067 }; 1068 1069 /** 1070 * struct hsmp_telemetry_table_rm - Top-level RM telemetry table. 1071 * @iod: I/O die counters and per-rail/per-throttler/SYSTEM telemetry. 1072 * @ccx: Per-CCX core counters, one entry per CCX. 1073 * 1074 * Layout of the table returned by HSMP_CLIENT_GET_METRICS_TABLE on the 1075 * Family 1Ah client (Models 80h-8Fh and E0h-E3h), reported as table 1076 * version 5 by HSMP_CLIENT_GET_METRICS_TABLE_VER. Units are 1077 * firmware-defined; see the AMD HSMP/Ryzen Master SMC spec. Spare 1078 * fields are firmware padding and must be preserved. 1079 */ 1080 struct hsmp_telemetry_table_rm { 1081 struct hsmp_telemetry_table_rm_iod iod; 1082 struct hsmp_telemetry_table_rm_ccx ccx[HSMP_TELEMETRY_RM_MAX_CCX]; 1083 }; 1084 1085 #pragma pack(pop) 1086 1087 #endif /*_ASM_X86_AMD_HSMP_H_*/ 1088