1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/kmod.h>
11 #include <linux/mdio.h>
12 #include <linux/phy.h>
13 #include <linux/of.h>
14 #include <linux/bitops.h>
15 #include <linux/jiffies.h>
16
17 #include "xgbe.h"
18 #include "xgbe-common.h"
19
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata,struct ethtool_eeprom * eeprom,u8 * data)20 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
21 struct ethtool_eeprom *eeprom, u8 *data)
22 {
23 if (!pdata->phy_if.phy_impl.module_eeprom)
24 return -ENXIO;
25
26 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
27 }
28
xgbe_phy_module_info(struct xgbe_prv_data * pdata,struct ethtool_modinfo * modinfo)29 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
30 struct ethtool_modinfo *modinfo)
31 {
32 if (!pdata->phy_if.phy_impl.module_info)
33 return -ENXIO;
34
35 return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
36 }
37
xgbe_an37_clear_interrupts(struct xgbe_prv_data * pdata)38 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
39 {
40 int reg;
41
42 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
43 reg &= ~XGBE_AN_CL37_INT_MASK;
44 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
45 }
46
xgbe_an37_disable_interrupts(struct xgbe_prv_data * pdata)47 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
48 {
49 int reg;
50
51 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
52 reg &= ~XGBE_AN_CL37_INT_MASK;
53 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
54
55 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
56 reg &= ~XGBE_PCS_CL37_BP;
57 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
58 }
59
xgbe_an37_enable_interrupts(struct xgbe_prv_data * pdata)60 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
61 {
62 int reg;
63
64 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
65 reg |= XGBE_PCS_CL37_BP;
66 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
67
68 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
69 reg |= XGBE_AN_CL37_INT_MASK;
70 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
71 }
72
xgbe_an73_clear_interrupts(struct xgbe_prv_data * pdata)73 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
74 {
75 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
76 }
77
xgbe_an73_disable_interrupts(struct xgbe_prv_data * pdata)78 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
79 {
80 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
81 }
82
xgbe_an73_enable_interrupts(struct xgbe_prv_data * pdata)83 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
84 {
85 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
86 }
87
xgbe_an_enable_interrupts(struct xgbe_prv_data * pdata)88 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
89 {
90 switch (pdata->an_mode) {
91 case XGBE_AN_MODE_CL73:
92 case XGBE_AN_MODE_CL73_REDRV:
93 xgbe_an73_enable_interrupts(pdata);
94 break;
95 case XGBE_AN_MODE_CL37:
96 case XGBE_AN_MODE_CL37_SGMII:
97 xgbe_an37_enable_interrupts(pdata);
98 break;
99 default:
100 break;
101 }
102 }
103
xgbe_an_clear_interrupts_all(struct xgbe_prv_data * pdata)104 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
105 {
106 xgbe_an73_clear_interrupts(pdata);
107 xgbe_an37_clear_interrupts(pdata);
108 }
109
xgbe_kr_mode(struct xgbe_prv_data * pdata)110 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
111 {
112 /* Set MAC to 10G speed */
113 pdata->hw_if.set_speed(pdata, SPEED_10000);
114
115 /* Call PHY implementation support to complete rate change */
116 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
117 }
118
xgbe_kx_2500_mode(struct xgbe_prv_data * pdata)119 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
120 {
121 /* Set MAC to 2.5G speed */
122 pdata->hw_if.set_speed(pdata, SPEED_2500);
123
124 /* Call PHY implementation support to complete rate change */
125 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
126 }
127
xgbe_kx_1000_mode(struct xgbe_prv_data * pdata)128 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
129 {
130 /* Set MAC to 1G speed */
131 pdata->hw_if.set_speed(pdata, SPEED_1000);
132
133 /* Call PHY implementation support to complete rate change */
134 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
135 }
136
xgbe_sfi_mode(struct xgbe_prv_data * pdata)137 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
138 {
139 /* If a KR re-driver is present, change to KR mode instead */
140 if (pdata->kr_redrv)
141 return xgbe_kr_mode(pdata);
142
143 /* Set MAC to 10G speed */
144 pdata->hw_if.set_speed(pdata, SPEED_10000);
145
146 /* Call PHY implementation support to complete rate change */
147 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
148 }
149
xgbe_x_mode(struct xgbe_prv_data * pdata)150 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
151 {
152 /* Set MAC to 1G speed */
153 pdata->hw_if.set_speed(pdata, SPEED_1000);
154
155 /* Call PHY implementation support to complete rate change */
156 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
157 }
158
xgbe_sgmii_1000_mode(struct xgbe_prv_data * pdata)159 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
160 {
161 /* Set MAC to 1G speed */
162 pdata->hw_if.set_speed(pdata, SPEED_1000);
163
164 /* Call PHY implementation support to complete rate change */
165 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
166 }
167
xgbe_sgmii_10_mode(struct xgbe_prv_data * pdata)168 static void xgbe_sgmii_10_mode(struct xgbe_prv_data *pdata)
169 {
170 /* Set MAC to 10M speed */
171 pdata->hw_if.set_speed(pdata, SPEED_10);
172
173 /* Call PHY implementation support to complete rate change */
174 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_10);
175 }
176
xgbe_sgmii_100_mode(struct xgbe_prv_data * pdata)177 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
178 {
179 /* Set MAC to 1G speed */
180 pdata->hw_if.set_speed(pdata, SPEED_1000);
181
182 /* Call PHY implementation support to complete rate change */
183 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
184 }
185
xgbe_cur_mode(struct xgbe_prv_data * pdata)186 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
187 {
188 return pdata->phy_if.phy_impl.cur_mode(pdata);
189 }
190
xgbe_in_kr_mode(struct xgbe_prv_data * pdata)191 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
192 {
193 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
194 }
195
xgbe_change_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)196 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
197 enum xgbe_mode mode)
198 {
199 switch (mode) {
200 case XGBE_MODE_KX_1000:
201 xgbe_kx_1000_mode(pdata);
202 break;
203 case XGBE_MODE_KX_2500:
204 xgbe_kx_2500_mode(pdata);
205 break;
206 case XGBE_MODE_KR:
207 xgbe_kr_mode(pdata);
208 break;
209 case XGBE_MODE_SGMII_10:
210 xgbe_sgmii_10_mode(pdata);
211 break;
212 case XGBE_MODE_SGMII_100:
213 xgbe_sgmii_100_mode(pdata);
214 break;
215 case XGBE_MODE_SGMII_1000:
216 xgbe_sgmii_1000_mode(pdata);
217 break;
218 case XGBE_MODE_X:
219 xgbe_x_mode(pdata);
220 break;
221 case XGBE_MODE_SFI:
222 xgbe_sfi_mode(pdata);
223 break;
224 case XGBE_MODE_UNKNOWN:
225 break;
226 default:
227 netif_dbg(pdata, link, pdata->netdev,
228 "invalid operation mode requested (%u)\n", mode);
229 }
230 }
231
xgbe_switch_mode(struct xgbe_prv_data * pdata)232 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
233 {
234 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
235 }
236
xgbe_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)237 static bool xgbe_set_mode(struct xgbe_prv_data *pdata,
238 enum xgbe_mode mode)
239 {
240 if (mode == xgbe_cur_mode(pdata))
241 return false;
242
243 xgbe_change_mode(pdata, mode);
244
245 return true;
246 }
247
xgbe_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)248 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
249 enum xgbe_mode mode)
250 {
251 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
252 }
253
xgbe_an37_set(struct xgbe_prv_data * pdata,bool enable,bool restart)254 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
255 bool restart)
256 {
257 unsigned int reg;
258
259 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
260 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
261
262 if (enable)
263 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
264
265 if (restart)
266 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
267
268 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
269
270 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL);
271 reg |= XGBE_VEND2_MAC_AUTO_SW;
272 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL, reg);
273 }
274
xgbe_an37_restart(struct xgbe_prv_data * pdata)275 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
276 {
277 xgbe_an37_enable_interrupts(pdata);
278 xgbe_an37_set(pdata, true, true);
279
280 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
281 }
282
xgbe_an37_disable(struct xgbe_prv_data * pdata)283 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
284 {
285 xgbe_an37_set(pdata, false, false);
286 xgbe_an37_disable_interrupts(pdata);
287
288 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
289 }
290
xgbe_an73_set(struct xgbe_prv_data * pdata,bool enable,bool restart)291 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
292 bool restart)
293 {
294 unsigned int reg;
295
296 /* Disable KR training for now */
297 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
298 reg &= ~XGBE_KR_TRAINING_ENABLE;
299 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
300
301 /* Update AN settings */
302 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
303 reg &= ~MDIO_AN_CTRL1_ENABLE;
304
305 if (enable)
306 reg |= MDIO_AN_CTRL1_ENABLE;
307
308 if (restart)
309 reg |= MDIO_AN_CTRL1_RESTART;
310
311 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
312 }
313
xgbe_an73_restart(struct xgbe_prv_data * pdata)314 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
315 {
316 xgbe_an73_enable_interrupts(pdata);
317 xgbe_an73_set(pdata, true, true);
318
319 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
320 }
321
xgbe_an73_disable(struct xgbe_prv_data * pdata)322 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
323 {
324 xgbe_an73_set(pdata, false, false);
325 xgbe_an73_disable_interrupts(pdata);
326
327 pdata->an_start = 0;
328
329 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
330 }
331
xgbe_an_restart(struct xgbe_prv_data * pdata)332 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
333 {
334 if (pdata->phy_if.phy_impl.an_pre)
335 pdata->phy_if.phy_impl.an_pre(pdata);
336
337 switch (pdata->an_mode) {
338 case XGBE_AN_MODE_CL73:
339 case XGBE_AN_MODE_CL73_REDRV:
340 xgbe_an73_restart(pdata);
341 break;
342 case XGBE_AN_MODE_CL37:
343 case XGBE_AN_MODE_CL37_SGMII:
344 xgbe_an37_restart(pdata);
345 break;
346 default:
347 break;
348 }
349 }
350
xgbe_an_disable(struct xgbe_prv_data * pdata)351 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
352 {
353 if (pdata->phy_if.phy_impl.an_post)
354 pdata->phy_if.phy_impl.an_post(pdata);
355
356 switch (pdata->an_mode) {
357 case XGBE_AN_MODE_CL73:
358 case XGBE_AN_MODE_CL73_REDRV:
359 xgbe_an73_disable(pdata);
360 break;
361 case XGBE_AN_MODE_CL37:
362 case XGBE_AN_MODE_CL37_SGMII:
363 xgbe_an37_disable(pdata);
364 break;
365 default:
366 break;
367 }
368 }
369
xgbe_an_disable_all(struct xgbe_prv_data * pdata)370 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
371 {
372 xgbe_an73_disable(pdata);
373 xgbe_an37_disable(pdata);
374 }
375
xgbe_an73_tx_training(struct xgbe_prv_data * pdata,enum xgbe_rx * state)376 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
377 enum xgbe_rx *state)
378 {
379 unsigned int ad_reg, lp_reg, reg;
380
381 *state = XGBE_RX_COMPLETE;
382
383 /* If we're not in KR mode then we're done */
384 if (!xgbe_in_kr_mode(pdata))
385 return XGBE_AN_PAGE_RECEIVED;
386
387 /* Enable/Disable FEC */
388 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
389 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
390
391 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
392 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
393 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
394 reg |= pdata->fec_ability;
395
396 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
397
398 /* Start KR training */
399 if (pdata->phy_if.phy_impl.kr_training_pre)
400 pdata->phy_if.phy_impl.kr_training_pre(pdata);
401
402 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
403 reg |= XGBE_KR_TRAINING_ENABLE;
404 reg |= XGBE_KR_TRAINING_START;
405 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
406 pdata->kr_start_time = jiffies;
407
408 netif_dbg(pdata, link, pdata->netdev,
409 "KR training initiated\n");
410
411 if (pdata->phy_if.phy_impl.kr_training_post)
412 pdata->phy_if.phy_impl.kr_training_post(pdata);
413
414 return XGBE_AN_PAGE_RECEIVED;
415 }
416
xgbe_an73_tx_xnp(struct xgbe_prv_data * pdata,enum xgbe_rx * state)417 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
418 enum xgbe_rx *state)
419 {
420 u16 msg;
421
422 *state = XGBE_RX_XNP;
423
424 msg = XGBE_XNP_MCF_NULL_MESSAGE;
425 msg |= XGBE_XNP_MP_FORMATTED;
426
427 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
428 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
429 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
430
431 return XGBE_AN_PAGE_RECEIVED;
432 }
433
xgbe_an73_rx_bpa(struct xgbe_prv_data * pdata,enum xgbe_rx * state)434 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
435 enum xgbe_rx *state)
436 {
437 unsigned int link_support;
438 unsigned int reg, ad_reg, lp_reg;
439
440 /* Read Base Ability register 2 first */
441 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
442
443 /* Check for a supported mode, otherwise restart in a different one */
444 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
445 if (!(reg & link_support))
446 return XGBE_AN_INCOMPAT_LINK;
447
448 /* Check Extended Next Page support */
449 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
450 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
451
452 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
453 (lp_reg & XGBE_XNP_NP_EXCHANGE))
454 ? xgbe_an73_tx_xnp(pdata, state)
455 : xgbe_an73_tx_training(pdata, state);
456 }
457
xgbe_an73_rx_xnp(struct xgbe_prv_data * pdata,enum xgbe_rx * state)458 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
459 enum xgbe_rx *state)
460 {
461 unsigned int ad_reg, lp_reg;
462
463 /* Check Extended Next Page support */
464 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
465 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
466
467 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
468 (lp_reg & XGBE_XNP_NP_EXCHANGE))
469 ? xgbe_an73_tx_xnp(pdata, state)
470 : xgbe_an73_tx_training(pdata, state);
471 }
472
xgbe_an73_page_received(struct xgbe_prv_data * pdata)473 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
474 {
475 enum xgbe_rx *state;
476 unsigned long an_timeout;
477 enum xgbe_an ret;
478
479 if (!pdata->an_start) {
480 pdata->an_start = jiffies;
481 } else {
482 an_timeout = pdata->an_start +
483 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
484 if (time_after(jiffies, an_timeout)) {
485 /* Auto-negotiation timed out, reset state */
486 pdata->kr_state = XGBE_RX_BPA;
487 pdata->kx_state = XGBE_RX_BPA;
488
489 pdata->an_start = jiffies;
490
491 netif_dbg(pdata, link, pdata->netdev,
492 "CL73 AN timed out, resetting state\n");
493 }
494 }
495
496 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
497 : &pdata->kx_state;
498
499 switch (*state) {
500 case XGBE_RX_BPA:
501 ret = xgbe_an73_rx_bpa(pdata, state);
502 break;
503
504 case XGBE_RX_XNP:
505 ret = xgbe_an73_rx_xnp(pdata, state);
506 break;
507
508 default:
509 ret = XGBE_AN_ERROR;
510 }
511
512 return ret;
513 }
514
xgbe_an73_incompat_link(struct xgbe_prv_data * pdata)515 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
516 {
517 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
518
519 /* Be sure we aren't looping trying to negotiate */
520 if (xgbe_in_kr_mode(pdata)) {
521 pdata->kr_state = XGBE_RX_ERROR;
522
523 if (!XGBE_ADV(lks, 1000baseKX_Full) &&
524 !XGBE_ADV(lks, 2500baseX_Full))
525 return XGBE_AN_NO_LINK;
526
527 if (pdata->kx_state != XGBE_RX_BPA)
528 return XGBE_AN_NO_LINK;
529 } else {
530 pdata->kx_state = XGBE_RX_ERROR;
531
532 if (!XGBE_ADV(lks, 10000baseKR_Full))
533 return XGBE_AN_NO_LINK;
534
535 if (pdata->kr_state != XGBE_RX_BPA)
536 return XGBE_AN_NO_LINK;
537 }
538
539 xgbe_an_disable(pdata);
540
541 xgbe_switch_mode(pdata);
542
543 pdata->an_result = XGBE_AN_READY;
544
545 xgbe_an_restart(pdata);
546
547 return XGBE_AN_INCOMPAT_LINK;
548 }
549
xgbe_an37_isr(struct xgbe_prv_data * pdata)550 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
551 {
552 unsigned int reg;
553
554 /* Disable AN interrupts */
555 xgbe_an37_disable_interrupts(pdata);
556
557 /* Save the interrupt(s) that fired */
558 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
559 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
560 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
561
562 if (pdata->an_int) {
563 /* Clear the interrupt(s) that fired and process them */
564 reg &= ~XGBE_AN_CL37_INT_MASK;
565 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
566
567 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
568 } else {
569 /* Enable AN interrupts */
570 xgbe_an37_enable_interrupts(pdata);
571
572 /* Reissue interrupt if status is not clear */
573 if (pdata->vdata->irq_reissue_support)
574 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
575 }
576 }
577
xgbe_an73_isr(struct xgbe_prv_data * pdata)578 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
579 {
580 /* Disable AN interrupts */
581 xgbe_an73_disable_interrupts(pdata);
582
583 /* Save the interrupt(s) that fired */
584 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
585
586 if (pdata->an_int) {
587 /* Clear the interrupt(s) that fired and process them */
588 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
589
590 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
591 } else {
592 /* Enable AN interrupts */
593 xgbe_an73_enable_interrupts(pdata);
594
595 /* Reissue interrupt if status is not clear */
596 if (pdata->vdata->irq_reissue_support)
597 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
598 }
599 }
600
xgbe_an_isr_bh_work(struct work_struct * work)601 static void xgbe_an_isr_bh_work(struct work_struct *work)
602 {
603 struct xgbe_prv_data *pdata = from_work(pdata, work, an_bh_work);
604
605 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
606
607 switch (pdata->an_mode) {
608 case XGBE_AN_MODE_CL73:
609 case XGBE_AN_MODE_CL73_REDRV:
610 xgbe_an73_isr(pdata);
611 break;
612 case XGBE_AN_MODE_CL37:
613 case XGBE_AN_MODE_CL37_SGMII:
614 xgbe_an37_isr(pdata);
615 break;
616 default:
617 break;
618 }
619 }
620
xgbe_an_isr(int irq,void * data)621 static irqreturn_t xgbe_an_isr(int irq, void *data)
622 {
623 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
624
625 if (pdata->isr_as_bh_work)
626 queue_work(system_bh_wq, &pdata->an_bh_work);
627 else
628 xgbe_an_isr_bh_work(&pdata->an_bh_work);
629
630 return IRQ_HANDLED;
631 }
632
xgbe_an_combined_isr(struct xgbe_prv_data * pdata)633 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
634 {
635 xgbe_an_isr_bh_work(&pdata->an_bh_work);
636
637 return IRQ_HANDLED;
638 }
639
xgbe_an_irq_work(struct work_struct * work)640 static void xgbe_an_irq_work(struct work_struct *work)
641 {
642 struct xgbe_prv_data *pdata = container_of(work,
643 struct xgbe_prv_data,
644 an_irq_work);
645
646 /* Avoid a race between enabling the IRQ and exiting the work by
647 * waiting for the work to finish and then queueing it
648 */
649 flush_work(&pdata->an_work);
650 queue_work(pdata->an_workqueue, &pdata->an_work);
651 }
652
xgbe_state_as_string(enum xgbe_an state)653 static const char *xgbe_state_as_string(enum xgbe_an state)
654 {
655 switch (state) {
656 case XGBE_AN_READY:
657 return "Ready";
658 case XGBE_AN_PAGE_RECEIVED:
659 return "Page-Received";
660 case XGBE_AN_INCOMPAT_LINK:
661 return "Incompatible-Link";
662 case XGBE_AN_COMPLETE:
663 return "Complete";
664 case XGBE_AN_NO_LINK:
665 return "No-Link";
666 case XGBE_AN_ERROR:
667 return "Error";
668 default:
669 return "Undefined";
670 }
671 }
672
xgbe_an37_state_machine(struct xgbe_prv_data * pdata)673 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
674 {
675 enum xgbe_an cur_state = pdata->an_state;
676
677 if (!pdata->an_int)
678 return;
679
680 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
681 pdata->an_state = XGBE_AN_COMPLETE;
682 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
683
684 /* If SGMII is enabled, check the link status */
685 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
686 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
687 pdata->an_state = XGBE_AN_NO_LINK;
688 }
689
690 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
691 xgbe_state_as_string(pdata->an_state));
692
693 cur_state = pdata->an_state;
694
695 switch (pdata->an_state) {
696 case XGBE_AN_READY:
697 break;
698
699 case XGBE_AN_COMPLETE:
700 netif_dbg(pdata, link, pdata->netdev,
701 "Auto negotiation successful\n");
702 break;
703
704 case XGBE_AN_NO_LINK:
705 break;
706
707 default:
708 pdata->an_state = XGBE_AN_ERROR;
709 }
710
711 if (pdata->an_state == XGBE_AN_ERROR) {
712 netdev_err(pdata->netdev,
713 "error during auto-negotiation, state=%u\n",
714 cur_state);
715
716 pdata->an_int = 0;
717 xgbe_an37_clear_interrupts(pdata);
718 }
719
720 if (pdata->an_state >= XGBE_AN_COMPLETE) {
721 pdata->an_result = pdata->an_state;
722 pdata->an_state = XGBE_AN_READY;
723
724 if (pdata->phy_if.phy_impl.an_post)
725 pdata->phy_if.phy_impl.an_post(pdata);
726
727 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
728 xgbe_state_as_string(pdata->an_result));
729 }
730
731 xgbe_an37_enable_interrupts(pdata);
732 }
733
xgbe_an73_state_machine(struct xgbe_prv_data * pdata)734 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
735 {
736 enum xgbe_an cur_state = pdata->an_state;
737
738 if (!pdata->an_int)
739 return;
740
741 next_int:
742 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
743 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
744 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
745 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
746 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
747 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
748 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
749 pdata->an_state = XGBE_AN_COMPLETE;
750 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
751 } else {
752 pdata->an_state = XGBE_AN_ERROR;
753 }
754
755 again:
756 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
757 xgbe_state_as_string(pdata->an_state));
758
759 cur_state = pdata->an_state;
760
761 switch (pdata->an_state) {
762 case XGBE_AN_READY:
763 pdata->an_supported = 0;
764 break;
765
766 case XGBE_AN_PAGE_RECEIVED:
767 pdata->an_state = xgbe_an73_page_received(pdata);
768 pdata->an_supported++;
769 break;
770
771 case XGBE_AN_INCOMPAT_LINK:
772 pdata->an_supported = 0;
773 pdata->parallel_detect = 0;
774 pdata->an_state = xgbe_an73_incompat_link(pdata);
775 break;
776
777 case XGBE_AN_COMPLETE:
778 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
779 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
780 pdata->an_supported ? "Auto negotiation"
781 : "Parallel detection");
782 break;
783
784 case XGBE_AN_NO_LINK:
785 break;
786
787 default:
788 pdata->an_state = XGBE_AN_ERROR;
789 }
790
791 if (pdata->an_state == XGBE_AN_NO_LINK) {
792 pdata->an_int = 0;
793 xgbe_an73_clear_interrupts(pdata);
794 } else if (pdata->an_state == XGBE_AN_ERROR) {
795 netdev_err(pdata->netdev,
796 "error during auto-negotiation, state=%u\n",
797 cur_state);
798
799 pdata->an_int = 0;
800 xgbe_an73_clear_interrupts(pdata);
801 }
802
803 if (pdata->an_state >= XGBE_AN_COMPLETE) {
804 pdata->an_result = pdata->an_state;
805 pdata->an_state = XGBE_AN_READY;
806 pdata->kr_state = XGBE_RX_BPA;
807 pdata->kx_state = XGBE_RX_BPA;
808 pdata->an_start = 0;
809
810 if (pdata->phy_if.phy_impl.an_post)
811 pdata->phy_if.phy_impl.an_post(pdata);
812
813 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
814 xgbe_state_as_string(pdata->an_result));
815 }
816
817 if (cur_state != pdata->an_state)
818 goto again;
819
820 if (pdata->an_int)
821 goto next_int;
822
823 xgbe_an73_enable_interrupts(pdata);
824 }
825
xgbe_an_state_machine(struct work_struct * work)826 static void xgbe_an_state_machine(struct work_struct *work)
827 {
828 struct xgbe_prv_data *pdata = container_of(work,
829 struct xgbe_prv_data,
830 an_work);
831
832 mutex_lock(&pdata->an_mutex);
833
834 switch (pdata->an_mode) {
835 case XGBE_AN_MODE_CL73:
836 case XGBE_AN_MODE_CL73_REDRV:
837 xgbe_an73_state_machine(pdata);
838 break;
839 case XGBE_AN_MODE_CL37:
840 case XGBE_AN_MODE_CL37_SGMII:
841 xgbe_an37_state_machine(pdata);
842 break;
843 default:
844 break;
845 }
846
847 /* Reissue interrupt if status is not clear */
848 if (pdata->vdata->irq_reissue_support)
849 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
850
851 mutex_unlock(&pdata->an_mutex);
852 }
853
xgbe_an37_init(struct xgbe_prv_data * pdata)854 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
855 {
856 struct ethtool_link_ksettings lks;
857 unsigned int reg;
858
859 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
860
861 /* Set up Advertisement register */
862 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
863 if (XGBE_ADV(&lks, Pause))
864 reg |= 0x100;
865 else
866 reg &= ~0x100;
867
868 if (XGBE_ADV(&lks, Asym_Pause))
869 reg |= 0x80;
870 else
871 reg &= ~0x80;
872
873 /* Full duplex, but not half */
874 reg |= XGBE_AN_CL37_FD_MASK;
875 reg &= ~XGBE_AN_CL37_HD_MASK;
876
877 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
878
879 /* Set up the Control register */
880 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
881 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
882 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
883
884 switch (pdata->an_mode) {
885 case XGBE_AN_MODE_CL37:
886 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
887 break;
888 case XGBE_AN_MODE_CL37_SGMII:
889 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
890 break;
891 default:
892 break;
893 }
894
895 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
896
897 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
898
899 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
900 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
901
902 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
903 reg &= ~MDIO_AN_CTRL1_ENABLE;
904 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
905
906 }
907
xgbe_an73_init(struct xgbe_prv_data * pdata)908 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
909 {
910 struct ethtool_link_ksettings lks;
911 unsigned int reg;
912
913 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
914
915 /* Set up Advertisement register 3 first */
916 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
917 if (XGBE_ADV(&lks, 10000baseR_FEC))
918 reg |= 0xc000;
919 else
920 reg &= ~0xc000;
921
922 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
923
924 /* Set up Advertisement register 2 next */
925 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
926 if (XGBE_ADV(&lks, 10000baseKR_Full))
927 reg |= 0x80;
928 else
929 reg &= ~0x80;
930
931 if (XGBE_ADV(&lks, 1000baseKX_Full) ||
932 XGBE_ADV(&lks, 2500baseX_Full))
933 reg |= 0x20;
934 else
935 reg &= ~0x20;
936
937 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
938
939 /* Set up Advertisement register 1 last */
940 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
941 if (XGBE_ADV(&lks, Pause))
942 reg |= 0x400;
943 else
944 reg &= ~0x400;
945
946 if (XGBE_ADV(&lks, Asym_Pause))
947 reg |= 0x800;
948 else
949 reg &= ~0x800;
950
951 /* We don't intend to perform XNP */
952 reg &= ~XGBE_XNP_NP_EXCHANGE;
953
954 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
955
956 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
957 }
958
xgbe_an_init(struct xgbe_prv_data * pdata)959 static void xgbe_an_init(struct xgbe_prv_data *pdata)
960 {
961 /* Set up advertisement registers based on current settings */
962 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
963 switch (pdata->an_mode) {
964 case XGBE_AN_MODE_CL73:
965 case XGBE_AN_MODE_CL73_REDRV:
966 xgbe_an73_init(pdata);
967 break;
968 case XGBE_AN_MODE_CL37:
969 case XGBE_AN_MODE_CL37_SGMII:
970 xgbe_an37_init(pdata);
971 break;
972 default:
973 break;
974 }
975 }
976
xgbe_phy_fc_string(struct xgbe_prv_data * pdata)977 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
978 {
979 if (pdata->tx_pause && pdata->rx_pause)
980 return "rx/tx";
981 else if (pdata->rx_pause)
982 return "rx";
983 else if (pdata->tx_pause)
984 return "tx";
985 else
986 return "off";
987 }
988
xgbe_phy_speed_string(int speed)989 static const char *xgbe_phy_speed_string(int speed)
990 {
991 switch (speed) {
992 case SPEED_10:
993 return "10Mbps";
994 case SPEED_100:
995 return "100Mbps";
996 case SPEED_1000:
997 return "1Gbps";
998 case SPEED_2500:
999 return "2.5Gbps";
1000 case SPEED_10000:
1001 return "10Gbps";
1002 case SPEED_UNKNOWN:
1003 return "Unknown";
1004 default:
1005 return "Unsupported";
1006 }
1007 }
1008
xgbe_phy_print_status(struct xgbe_prv_data * pdata)1009 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1010 {
1011 if (pdata->phy.link)
1012 netdev_info(pdata->netdev,
1013 "Link is Up - %s/%s - flow control %s\n",
1014 xgbe_phy_speed_string(pdata->phy.speed),
1015 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1016 xgbe_phy_fc_string(pdata));
1017 else
1018 netdev_info(pdata->netdev, "Link is Down\n");
1019 }
1020
xgbe_phy_adjust_link(struct xgbe_prv_data * pdata)1021 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1022 {
1023 int new_state = 0;
1024
1025 if (pdata->phy.link) {
1026 /* Flow control support */
1027 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1028
1029 if (pdata->tx_pause != pdata->phy.tx_pause) {
1030 new_state = 1;
1031 pdata->tx_pause = pdata->phy.tx_pause;
1032 pdata->hw_if.config_tx_flow_control(pdata);
1033 }
1034
1035 if (pdata->rx_pause != pdata->phy.rx_pause) {
1036 new_state = 1;
1037 pdata->rx_pause = pdata->phy.rx_pause;
1038 pdata->hw_if.config_rx_flow_control(pdata);
1039 }
1040
1041 /* Speed support */
1042 if (pdata->phy_speed != pdata->phy.speed) {
1043 new_state = 1;
1044 pdata->phy_speed = pdata->phy.speed;
1045 }
1046
1047 if (pdata->phy_link != pdata->phy.link) {
1048 new_state = 1;
1049 pdata->phy_link = pdata->phy.link;
1050 }
1051 } else if (pdata->phy_link) {
1052 new_state = 1;
1053 pdata->phy_link = 0;
1054 pdata->phy_speed = SPEED_UNKNOWN;
1055 }
1056
1057 if (new_state && netif_msg_link(pdata))
1058 xgbe_phy_print_status(pdata);
1059 }
1060
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)1061 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1062 {
1063 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1064 }
1065
xgbe_phy_config_fixed(struct xgbe_prv_data * pdata)1066 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1067 {
1068 enum xgbe_mode mode;
1069
1070 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1071
1072 /* Disable auto-negotiation */
1073 xgbe_an_disable(pdata);
1074
1075 /* Set specified mode for specified speed */
1076 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1077 switch (mode) {
1078 case XGBE_MODE_KX_1000:
1079 case XGBE_MODE_KX_2500:
1080 case XGBE_MODE_KR:
1081 case XGBE_MODE_SGMII_10:
1082 case XGBE_MODE_SGMII_100:
1083 case XGBE_MODE_SGMII_1000:
1084 case XGBE_MODE_X:
1085 case XGBE_MODE_SFI:
1086 break;
1087 case XGBE_MODE_UNKNOWN:
1088 default:
1089 return -EINVAL;
1090 }
1091
1092 /* Validate duplex mode */
1093 if (pdata->phy.duplex != DUPLEX_FULL)
1094 return -EINVAL;
1095
1096 /* Force the mode change for SFI in Fixed PHY config.
1097 * Fixed PHY configs needs PLL to be enabled while doing mode set.
1098 * When the SFP module isn't connected during boot, driver assumes
1099 * AN is ON and attempts autonegotiation. However, if the connected
1100 * SFP comes up in Fixed PHY config, the link will not come up as
1101 * PLL isn't enabled while the initial mode set command is issued.
1102 * So, force the mode change for SFI in Fixed PHY configuration to
1103 * fix link issues.
1104 */
1105 if (mode == XGBE_MODE_SFI)
1106 xgbe_change_mode(pdata, mode);
1107 else
1108 xgbe_set_mode(pdata, mode);
1109
1110 return 0;
1111 }
1112
__xgbe_phy_config_aneg(struct xgbe_prv_data * pdata,bool set_mode)1113 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode)
1114 {
1115 int ret;
1116
1117 mutex_lock(&pdata->an_mutex);
1118
1119 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1120 pdata->link_check = jiffies;
1121
1122 ret = pdata->phy_if.phy_impl.an_config(pdata);
1123 if (ret)
1124 goto out;
1125
1126 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1127 ret = xgbe_phy_config_fixed(pdata);
1128 if (ret || !pdata->kr_redrv)
1129 goto out;
1130
1131 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1132 } else {
1133 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1134 }
1135
1136 /* Disable auto-negotiation interrupt */
1137 disable_irq(pdata->an_irq);
1138
1139 if (set_mode) {
1140 /* Start auto-negotiation in a supported mode */
1141 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1142 xgbe_set_mode(pdata, XGBE_MODE_KR);
1143 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1144 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1145 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1146 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1147 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1148 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1149 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1150 xgbe_set_mode(pdata, XGBE_MODE_X);
1151 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1152 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1153 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1154 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1155 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1156 xgbe_set_mode(pdata, XGBE_MODE_SGMII_10);
1157 } else {
1158 enable_irq(pdata->an_irq);
1159 ret = -EINVAL;
1160 goto out;
1161 }
1162 }
1163
1164 /* Disable and stop any in progress auto-negotiation */
1165 xgbe_an_disable_all(pdata);
1166
1167 /* Clear any auto-negotitation interrupts */
1168 xgbe_an_clear_interrupts_all(pdata);
1169
1170 pdata->an_result = XGBE_AN_READY;
1171 pdata->an_state = XGBE_AN_READY;
1172 pdata->kr_state = XGBE_RX_BPA;
1173 pdata->kx_state = XGBE_RX_BPA;
1174
1175 /* Re-enable auto-negotiation interrupt */
1176 enable_irq(pdata->an_irq);
1177
1178 xgbe_an_init(pdata);
1179 xgbe_an_restart(pdata);
1180
1181 out:
1182 if (ret)
1183 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1184 else
1185 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1186
1187 mutex_unlock(&pdata->an_mutex);
1188
1189 return ret;
1190 }
1191
xgbe_phy_config_aneg(struct xgbe_prv_data * pdata)1192 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1193 {
1194 return __xgbe_phy_config_aneg(pdata, true);
1195 }
1196
xgbe_phy_reconfig_aneg(struct xgbe_prv_data * pdata)1197 static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata)
1198 {
1199 return __xgbe_phy_config_aneg(pdata, false);
1200 }
1201
xgbe_phy_aneg_done(struct xgbe_prv_data * pdata)1202 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1203 {
1204 return (pdata->an_result == XGBE_AN_COMPLETE);
1205 }
1206
xgbe_check_link_timeout(struct xgbe_prv_data * pdata)1207 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1208 {
1209 unsigned long link_timeout;
1210 unsigned long kr_time;
1211 int wait;
1212
1213 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1214 if (time_after(jiffies, link_timeout)) {
1215 if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) &&
1216 pdata->phy.autoneg == AUTONEG_ENABLE) {
1217 /* AN restart should not happen while KR training is in progress.
1218 * The while loop ensures no AN restart during KR training,
1219 * waits up to 500ms and AN restart is triggered only if KR
1220 * training is failed.
1221 */
1222 wait = XGBE_KR_TRAINING_WAIT_ITER;
1223 while (wait--) {
1224 kr_time = pdata->kr_start_time +
1225 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
1226 if (time_after(jiffies, kr_time))
1227 break;
1228 /* AN restart is not required, if AN result is COMPLETE */
1229 if (pdata->an_result == XGBE_AN_COMPLETE)
1230 return;
1231 usleep_range(10000, 11000);
1232 }
1233 }
1234 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1235 xgbe_phy_config_aneg(pdata);
1236 }
1237 }
1238
xgbe_phy_status_aneg(struct xgbe_prv_data * pdata)1239 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1240 {
1241 return pdata->phy_if.phy_impl.an_outcome(pdata);
1242 }
1243
xgbe_phy_status_result(struct xgbe_prv_data * pdata)1244 static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1245 {
1246 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1247 enum xgbe_mode mode;
1248
1249 XGBE_ZERO_LP_ADV(lks);
1250
1251 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1252 mode = xgbe_cur_mode(pdata);
1253 else
1254 mode = xgbe_phy_status_aneg(pdata);
1255
1256 switch (mode) {
1257 case XGBE_MODE_SGMII_10:
1258 pdata->phy.speed = SPEED_10;
1259 break;
1260 case XGBE_MODE_SGMII_100:
1261 pdata->phy.speed = SPEED_100;
1262 break;
1263 case XGBE_MODE_X:
1264 case XGBE_MODE_KX_1000:
1265 case XGBE_MODE_SGMII_1000:
1266 pdata->phy.speed = SPEED_1000;
1267 break;
1268 case XGBE_MODE_KX_2500:
1269 pdata->phy.speed = SPEED_2500;
1270 break;
1271 case XGBE_MODE_KR:
1272 case XGBE_MODE_SFI:
1273 pdata->phy.speed = SPEED_10000;
1274 break;
1275 case XGBE_MODE_UNKNOWN:
1276 default:
1277 pdata->phy.speed = SPEED_UNKNOWN;
1278 }
1279
1280 pdata->phy.duplex = DUPLEX_FULL;
1281
1282 if (!xgbe_set_mode(pdata, mode))
1283 return false;
1284
1285 if (pdata->an_again)
1286 xgbe_phy_reconfig_aneg(pdata);
1287
1288 return true;
1289 }
1290
xgbe_phy_status(struct xgbe_prv_data * pdata)1291 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1292 {
1293 unsigned int link_aneg;
1294 int an_restart;
1295
1296 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1297 netif_carrier_off(pdata->netdev);
1298
1299 pdata->phy.link = 0;
1300 goto adjust_link;
1301 }
1302
1303 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1304
1305 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1306 &an_restart);
1307 /* bail out if the link status register read fails */
1308 if (pdata->phy.link < 0)
1309 return;
1310
1311 if (an_restart) {
1312 xgbe_phy_config_aneg(pdata);
1313 goto adjust_link;
1314 }
1315
1316 if (pdata->phy.link) {
1317 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1318 xgbe_check_link_timeout(pdata);
1319 return;
1320 }
1321
1322 if (xgbe_phy_status_result(pdata))
1323 return;
1324
1325 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1326 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1327
1328 netif_carrier_on(pdata->netdev);
1329 } else {
1330 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1331 xgbe_check_link_timeout(pdata);
1332
1333 if (link_aneg)
1334 return;
1335 }
1336
1337 xgbe_phy_status_result(pdata);
1338
1339 netif_carrier_off(pdata->netdev);
1340 }
1341
1342 adjust_link:
1343 xgbe_phy_adjust_link(pdata);
1344 }
1345
xgbe_phy_stop(struct xgbe_prv_data * pdata)1346 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1347 {
1348 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1349
1350 if (!pdata->phy_started)
1351 return;
1352
1353 /* Indicate the PHY is down */
1354 pdata->phy_started = 0;
1355
1356 /* Disable auto-negotiation */
1357 xgbe_an_disable_all(pdata);
1358
1359 if (pdata->dev_irq != pdata->an_irq) {
1360 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1361 cancel_work_sync(&pdata->an_bh_work);
1362 }
1363
1364 pdata->phy_if.phy_impl.stop(pdata);
1365
1366 pdata->phy.link = 0;
1367
1368 xgbe_phy_adjust_link(pdata);
1369 }
1370
xgbe_phy_start(struct xgbe_prv_data * pdata)1371 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1372 {
1373 struct net_device *netdev = pdata->netdev;
1374 int ret;
1375
1376 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1377
1378 ret = pdata->phy_if.phy_impl.start(pdata);
1379 if (ret)
1380 return ret;
1381
1382 /* If we have a separate AN irq, enable it */
1383 if (pdata->dev_irq != pdata->an_irq) {
1384 INIT_WORK(&pdata->an_bh_work, xgbe_an_isr_bh_work);
1385
1386 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1387 xgbe_an_isr, 0, pdata->an_name,
1388 pdata);
1389 if (ret) {
1390 netdev_err(netdev, "phy irq request failed\n");
1391 goto err_stop;
1392 }
1393 }
1394
1395 /* Set initial mode - call the mode setting routines
1396 * directly to insure we are properly configured
1397 */
1398 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1399 xgbe_kr_mode(pdata);
1400 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1401 xgbe_kx_2500_mode(pdata);
1402 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1403 xgbe_kx_1000_mode(pdata);
1404 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1405 xgbe_sfi_mode(pdata);
1406 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1407 xgbe_x_mode(pdata);
1408 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1409 xgbe_sgmii_1000_mode(pdata);
1410 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1411 xgbe_sgmii_100_mode(pdata);
1412 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1413 xgbe_sgmii_10_mode(pdata);
1414 } else {
1415 ret = -EINVAL;
1416 goto err_irq;
1417 }
1418
1419 /* Indicate the PHY is up and running */
1420 pdata->phy_started = 1;
1421
1422 xgbe_an_init(pdata);
1423 xgbe_an_enable_interrupts(pdata);
1424
1425 return xgbe_phy_config_aneg(pdata);
1426
1427 err_irq:
1428 if (pdata->dev_irq != pdata->an_irq)
1429 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1430
1431 err_stop:
1432 pdata->phy_if.phy_impl.stop(pdata);
1433
1434 return ret;
1435 }
1436
xgbe_phy_reset(struct xgbe_prv_data * pdata)1437 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1438 {
1439 int ret;
1440
1441 ret = pdata->phy_if.phy_impl.reset(pdata);
1442 if (ret)
1443 return ret;
1444
1445 /* Disable auto-negotiation for now */
1446 xgbe_an_disable_all(pdata);
1447
1448 /* Clear auto-negotiation interrupts */
1449 xgbe_an_clear_interrupts_all(pdata);
1450
1451 return 0;
1452 }
1453
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)1454 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1455 {
1456 struct device *dev = pdata->dev;
1457
1458 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1459
1460 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1461 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1462 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1463 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1464 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1465 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1466 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1467 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1468 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1469 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1470 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1471 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1472
1473 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1474 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1475 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1476 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1477 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1478 MDIO_AN_ADVERTISE,
1479 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1480 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1481 MDIO_AN_ADVERTISE + 1,
1482 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1483 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1484 MDIO_AN_ADVERTISE + 2,
1485 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1486 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1487 MDIO_AN_COMP_STAT,
1488 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1489
1490 dev_dbg(dev, "\n*************************************************\n");
1491 }
1492
xgbe_phy_best_advertised_speed(struct xgbe_prv_data * pdata)1493 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1494 {
1495 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1496
1497 if (XGBE_ADV(lks, 10000baseKR_Full))
1498 return SPEED_10000;
1499 else if (XGBE_ADV(lks, 10000baseT_Full))
1500 return SPEED_10000;
1501 else if (XGBE_ADV(lks, 2500baseX_Full))
1502 return SPEED_2500;
1503 else if (XGBE_ADV(lks, 2500baseT_Full))
1504 return SPEED_2500;
1505 else if (XGBE_ADV(lks, 1000baseKX_Full))
1506 return SPEED_1000;
1507 else if (XGBE_ADV(lks, 1000baseT_Full))
1508 return SPEED_1000;
1509 else if (XGBE_ADV(lks, 100baseT_Full))
1510 return SPEED_100;
1511 else if (XGBE_ADV(lks, 10baseT_Full))
1512 return SPEED_10;
1513
1514 return SPEED_UNKNOWN;
1515 }
1516
xgbe_phy_exit(struct xgbe_prv_data * pdata)1517 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1518 {
1519 pdata->phy_if.phy_impl.exit(pdata);
1520 }
1521
xgbe_phy_init(struct xgbe_prv_data * pdata)1522 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1523 {
1524 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1525 int ret;
1526
1527 mutex_init(&pdata->an_mutex);
1528 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1529 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1530 pdata->mdio_mmd = MDIO_MMD_PCS;
1531
1532 /* Check for FEC support */
1533 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1534 MDIO_PMA_10GBR_FECABLE);
1535 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1536 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1537
1538 /* Setup the phy (including supported features) */
1539 ret = pdata->phy_if.phy_impl.init(pdata);
1540 if (ret)
1541 return ret;
1542
1543 /* Copy supported link modes to advertising link modes */
1544 XGBE_LM_COPY(lks, advertising, lks, supported);
1545
1546 pdata->phy.address = 0;
1547
1548 if (XGBE_ADV(lks, Autoneg)) {
1549 pdata->phy.autoneg = AUTONEG_ENABLE;
1550 pdata->phy.speed = SPEED_UNKNOWN;
1551 pdata->phy.duplex = DUPLEX_UNKNOWN;
1552 } else {
1553 pdata->phy.autoneg = AUTONEG_DISABLE;
1554 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1555 pdata->phy.duplex = DUPLEX_FULL;
1556 }
1557
1558 pdata->phy.link = 0;
1559
1560 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1561 pdata->phy.tx_pause = pdata->tx_pause;
1562 pdata->phy.rx_pause = pdata->rx_pause;
1563
1564 /* Fix up Flow Control advertising */
1565 XGBE_CLR_ADV(lks, Pause);
1566 XGBE_CLR_ADV(lks, Asym_Pause);
1567
1568 if (pdata->rx_pause) {
1569 XGBE_SET_ADV(lks, Pause);
1570 XGBE_SET_ADV(lks, Asym_Pause);
1571 }
1572
1573 if (pdata->tx_pause) {
1574 /* Equivalent to XOR of Asym_Pause */
1575 if (XGBE_ADV(lks, Asym_Pause))
1576 XGBE_CLR_ADV(lks, Asym_Pause);
1577 else
1578 XGBE_SET_ADV(lks, Asym_Pause);
1579 }
1580
1581 if (netif_msg_drv(pdata))
1582 xgbe_dump_phy_registers(pdata);
1583
1584 return 0;
1585 }
1586
xgbe_init_function_ptrs_phy(struct xgbe_phy_if * phy_if)1587 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1588 {
1589 phy_if->phy_init = xgbe_phy_init;
1590 phy_if->phy_exit = xgbe_phy_exit;
1591
1592 phy_if->phy_reset = xgbe_phy_reset;
1593 phy_if->phy_start = xgbe_phy_start;
1594 phy_if->phy_stop = xgbe_phy_stop;
1595
1596 phy_if->phy_status = xgbe_phy_status;
1597 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1598
1599 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1600
1601 phy_if->an_isr = xgbe_an_combined_isr;
1602
1603 phy_if->module_info = xgbe_phy_module_info;
1604 phy_if->module_eeprom = xgbe_phy_module_eeprom;
1605 }
1606