1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #include <linux/module.h>
9 #include <linux/device.h>
10 #include <linux/kmod.h>
11 #include <linux/mdio.h>
12 #include <linux/phy.h>
13 #include <linux/ethtool.h>
14
15 #include "xgbe.h"
16 #include "xgbe-common.h"
17
18 #define XGBE_PHY_PORT_SPEED_10 BIT(0)
19 #define XGBE_PHY_PORT_SPEED_100 BIT(1)
20 #define XGBE_PHY_PORT_SPEED_1000 BIT(2)
21 #define XGBE_PHY_PORT_SPEED_2500 BIT(3)
22 #define XGBE_PHY_PORT_SPEED_10000 BIT(4)
23
24 #define XGBE_MUTEX_RELEASE 0x80000000
25
26 #define XGBE_SFP_DIRECT 7
27
28 /* I2C target addresses */
29 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
30 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
31 #define XGBE_SFP_PHY_ADDRESS 0x56
32 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
33
34 /* SFP sideband signal indicators */
35 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
36 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
37 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
38 #define XGBE_GPIO_NO_RX_LOS BIT(3)
39
40 /* Rate-change complete wait/retry count */
41 #define XGBE_RATECHANGE_COUNT 500
42
43 /* CDR delay values for KR support (in usec) */
44 #define XGBE_CDR_DELAY_INIT 10000
45 #define XGBE_CDR_DELAY_INC 10000
46 #define XGBE_CDR_DELAY_MAX 100000
47
48 /* RRC frequency during link status check */
49 #define XGBE_RRC_FREQUENCY 10
50
51 enum xgbe_port_mode {
52 XGBE_PORT_MODE_RSVD = 0,
53 XGBE_PORT_MODE_BACKPLANE,
54 XGBE_PORT_MODE_BACKPLANE_2500,
55 XGBE_PORT_MODE_1000BASE_T,
56 XGBE_PORT_MODE_1000BASE_X,
57 XGBE_PORT_MODE_NBASE_T,
58 XGBE_PORT_MODE_10GBASE_T,
59 XGBE_PORT_MODE_10GBASE_R,
60 XGBE_PORT_MODE_SFP,
61 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
62 XGBE_PORT_MODE_MAX,
63 };
64
65 enum xgbe_conn_type {
66 XGBE_CONN_TYPE_NONE = 0,
67 XGBE_CONN_TYPE_SFP,
68 XGBE_CONN_TYPE_MDIO,
69 XGBE_CONN_TYPE_RSVD1,
70 XGBE_CONN_TYPE_BACKPLANE,
71 XGBE_CONN_TYPE_MAX,
72 };
73
74 /* SFP/SFP+ related definitions */
75 enum xgbe_sfp_comm {
76 XGBE_SFP_COMM_DIRECT = 0,
77 XGBE_SFP_COMM_PCA9545,
78 };
79
80 enum xgbe_sfp_cable {
81 XGBE_SFP_CABLE_UNKNOWN = 0,
82 XGBE_SFP_CABLE_ACTIVE,
83 XGBE_SFP_CABLE_PASSIVE,
84 XGBE_SFP_CABLE_FIBER,
85 };
86
87 enum xgbe_sfp_base {
88 XGBE_SFP_BASE_UNKNOWN = 0,
89 XGBE_SFP_BASE_1000_T,
90 XGBE_SFP_BASE_1000_SX,
91 XGBE_SFP_BASE_1000_LX,
92 XGBE_SFP_BASE_1000_CX,
93 XGBE_SFP_BASE_10000_SR,
94 XGBE_SFP_BASE_10000_LR,
95 XGBE_SFP_BASE_10000_LRM,
96 XGBE_SFP_BASE_10000_ER,
97 XGBE_SFP_BASE_10000_CR,
98 };
99
100 enum xgbe_sfp_speed {
101 XGBE_SFP_SPEED_UNKNOWN = 0,
102 XGBE_SFP_SPEED_100_1000,
103 XGBE_SFP_SPEED_1000,
104 XGBE_SFP_SPEED_10000,
105 };
106
107 /* SFP Serial ID Base ID values relative to an offset of 0 */
108 #define XGBE_SFP_BASE_ID 0
109 #define XGBE_SFP_ID_SFP 0x03
110
111 #define XGBE_SFP_BASE_EXT_ID 1
112 #define XGBE_SFP_EXT_ID_SFP 0x04
113
114 #define XGBE_SFP_BASE_10GBE_CC 3
115 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
116 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
117 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
118 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
119
120 #define XGBE_SFP_BASE_1GBE_CC 6
121 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
122 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
123 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
124 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
125
126 #define XGBE_SFP_BASE_CABLE 8
127 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
128 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
129
130 #define XGBE_SFP_BASE_BR 12
131 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
132 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
133
134 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
135
136 #define XGBE_SFP_BASE_VENDOR_NAME 20
137 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
138 #define XGBE_SFP_BASE_VENDOR_PN 40
139 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
140 #define XGBE_SFP_BASE_VENDOR_REV 56
141 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
142
143 #define XGBE_SFP_BASE_CC 63
144
145 /* SFP Serial ID Extended ID values relative to an offset of 64 */
146 #define XGBE_SFP_BASE_VENDOR_SN 4
147 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
148
149 #define XGBE_SFP_EXTD_OPT1 1
150 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
151 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
152
153 #define XGBE_SFP_EXTD_DIAG 28
154 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
155
156 #define XGBE_SFP_EXTD_SFF_8472 30
157
158 #define XGBE_SFP_EXTD_CC 31
159
160 struct xgbe_sfp_eeprom {
161 u8 base[64];
162 u8 extd[32];
163 u8 vendor[32];
164 };
165
166 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
167 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
168 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
169
170 #define XGBE_SFP_EEPROM_BASE_LEN 256
171 #define XGBE_SFP_EEPROM_DIAG_LEN 256
172 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
173 XGBE_SFP_EEPROM_DIAG_LEN)
174
175 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
176 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
177
178 #define XGBE_MOLEX_VENDOR "Molex Inc. "
179
180 struct xgbe_sfp_ascii {
181 union {
182 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
183 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
184 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
185 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
186 } u;
187 };
188
189 /* MDIO PHY reset types */
190 enum xgbe_mdio_reset {
191 XGBE_MDIO_RESET_NONE = 0,
192 XGBE_MDIO_RESET_I2C_GPIO,
193 XGBE_MDIO_RESET_INT_GPIO,
194 XGBE_MDIO_RESET_MAX,
195 };
196
197 /* Re-driver related definitions */
198 enum xgbe_phy_redrv_if {
199 XGBE_PHY_REDRV_IF_MDIO = 0,
200 XGBE_PHY_REDRV_IF_I2C,
201 XGBE_PHY_REDRV_IF_MAX,
202 };
203
204 enum xgbe_phy_redrv_model {
205 XGBE_PHY_REDRV_MODEL_4223 = 0,
206 XGBE_PHY_REDRV_MODEL_4227,
207 XGBE_PHY_REDRV_MODEL_MAX,
208 };
209
210 enum xgbe_phy_redrv_mode {
211 XGBE_PHY_REDRV_MODE_CX = 5,
212 XGBE_PHY_REDRV_MODE_SR = 9,
213 };
214
215 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
216
217 /* PHY related configuration information */
218 struct xgbe_phy_data {
219 enum xgbe_port_mode port_mode;
220
221 unsigned int port_id;
222
223 unsigned int port_speeds;
224
225 enum xgbe_conn_type conn_type;
226
227 enum xgbe_mode cur_mode;
228 enum xgbe_mode start_mode;
229
230 unsigned int rrc_count;
231
232 unsigned int mdio_addr;
233
234 /* SFP Support */
235 enum xgbe_sfp_comm sfp_comm;
236 unsigned int sfp_mux_address;
237 unsigned int sfp_mux_channel;
238
239 unsigned int sfp_gpio_address;
240 unsigned int sfp_gpio_mask;
241 unsigned int sfp_gpio_inputs;
242 unsigned int sfp_gpio_rx_los;
243 unsigned int sfp_gpio_tx_fault;
244 unsigned int sfp_gpio_mod_absent;
245 unsigned int sfp_gpio_rate_select;
246
247 unsigned int sfp_rx_los;
248 unsigned int sfp_tx_fault;
249 unsigned int sfp_mod_absent;
250 unsigned int sfp_changed;
251 unsigned int sfp_phy_avail;
252 unsigned int sfp_cable_len;
253 enum xgbe_sfp_base sfp_base;
254 enum xgbe_sfp_cable sfp_cable;
255 enum xgbe_sfp_speed sfp_speed;
256 struct xgbe_sfp_eeprom sfp_eeprom;
257
258 /* External PHY support */
259 enum xgbe_mdio_mode phydev_mode;
260 struct mii_bus *mii;
261 struct phy_device *phydev;
262 enum xgbe_mdio_reset mdio_reset;
263 unsigned int mdio_reset_addr;
264 unsigned int mdio_reset_gpio;
265
266 /* Re-driver support */
267 unsigned int redrv;
268 unsigned int redrv_if;
269 unsigned int redrv_addr;
270 unsigned int redrv_lane;
271 unsigned int redrv_model;
272
273 /* KR AN support */
274 unsigned int phy_cdr_notrack;
275 unsigned int phy_cdr_delay;
276 };
277
278 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
279 static DEFINE_MUTEX(xgbe_phy_comm_lock);
280
281 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
282 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata);
283 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
284 enum xgbe_mb_cmd cmd,
285 enum xgbe_mb_subcmd sub_cmd);
286
xgbe_phy_i2c_xfer(struct xgbe_prv_data * pdata,struct xgbe_i2c_op * i2c_op)287 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
288 struct xgbe_i2c_op *i2c_op)
289 {
290 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
291 }
292
xgbe_phy_redrv_write(struct xgbe_prv_data * pdata,unsigned int reg,unsigned int val)293 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
294 unsigned int val)
295 {
296 struct xgbe_phy_data *phy_data = pdata->phy_data;
297 struct xgbe_i2c_op i2c_op;
298 __be16 *redrv_val;
299 u8 redrv_data[5], csum;
300 unsigned int i, retry;
301 int ret;
302
303 /* High byte of register contains read/write indicator */
304 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
305 redrv_data[1] = reg & 0xff;
306 redrv_val = (__be16 *)&redrv_data[2];
307 *redrv_val = cpu_to_be16(val);
308
309 /* Calculate 1 byte checksum */
310 csum = 0;
311 for (i = 0; i < 4; i++) {
312 csum += redrv_data[i];
313 if (redrv_data[i] > csum)
314 csum++;
315 }
316 redrv_data[4] = ~csum;
317
318 retry = 1;
319 again1:
320 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
321 i2c_op.target = phy_data->redrv_addr;
322 i2c_op.len = sizeof(redrv_data);
323 i2c_op.buf = redrv_data;
324 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
325 if (ret) {
326 if ((ret == -EAGAIN) && retry--)
327 goto again1;
328
329 return ret;
330 }
331
332 retry = 1;
333 again2:
334 i2c_op.cmd = XGBE_I2C_CMD_READ;
335 i2c_op.target = phy_data->redrv_addr;
336 i2c_op.len = 1;
337 i2c_op.buf = redrv_data;
338 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
339 if (ret) {
340 if ((ret == -EAGAIN) && retry--)
341 goto again2;
342
343 return ret;
344 }
345
346 if (redrv_data[0] != 0xff) {
347 netif_dbg(pdata, drv, pdata->netdev,
348 "Redriver write checksum error\n");
349 ret = -EIO;
350 }
351
352 return ret;
353 }
354
xgbe_phy_i2c_write(struct xgbe_prv_data * pdata,unsigned int target,void * val,unsigned int val_len)355 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
356 void *val, unsigned int val_len)
357 {
358 struct xgbe_i2c_op i2c_op;
359 int retry, ret;
360
361 retry = 1;
362 again:
363 /* Write the specfied register */
364 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
365 i2c_op.target = target;
366 i2c_op.len = val_len;
367 i2c_op.buf = val;
368 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
369 if ((ret == -EAGAIN) && retry--)
370 goto again;
371
372 return ret;
373 }
374
xgbe_phy_i2c_read(struct xgbe_prv_data * pdata,unsigned int target,void * reg,unsigned int reg_len,void * val,unsigned int val_len)375 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
376 void *reg, unsigned int reg_len,
377 void *val, unsigned int val_len)
378 {
379 struct xgbe_i2c_op i2c_op;
380 int retry, ret;
381
382 retry = 1;
383 again1:
384 /* Set the specified register to read */
385 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
386 i2c_op.target = target;
387 i2c_op.len = reg_len;
388 i2c_op.buf = reg;
389 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
390 if (ret) {
391 if ((ret == -EAGAIN) && retry--)
392 goto again1;
393
394 return ret;
395 }
396
397 retry = 1;
398 again2:
399 /* Read the specfied register */
400 i2c_op.cmd = XGBE_I2C_CMD_READ;
401 i2c_op.target = target;
402 i2c_op.len = val_len;
403 i2c_op.buf = val;
404 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
405 if ((ret == -EAGAIN) && retry--)
406 goto again2;
407
408 return ret;
409 }
410
xgbe_phy_sfp_put_mux(struct xgbe_prv_data * pdata)411 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
412 {
413 struct xgbe_phy_data *phy_data = pdata->phy_data;
414 struct xgbe_i2c_op i2c_op;
415 u8 mux_channel;
416
417 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
418 return 0;
419
420 /* Select no mux channels */
421 mux_channel = 0;
422 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
423 i2c_op.target = phy_data->sfp_mux_address;
424 i2c_op.len = sizeof(mux_channel);
425 i2c_op.buf = &mux_channel;
426
427 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
428 }
429
xgbe_phy_sfp_get_mux(struct xgbe_prv_data * pdata)430 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
431 {
432 struct xgbe_phy_data *phy_data = pdata->phy_data;
433 struct xgbe_i2c_op i2c_op;
434 u8 mux_channel;
435
436 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
437 return 0;
438
439 /* Select desired mux channel */
440 mux_channel = 1 << phy_data->sfp_mux_channel;
441 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
442 i2c_op.target = phy_data->sfp_mux_address;
443 i2c_op.len = sizeof(mux_channel);
444 i2c_op.buf = &mux_channel;
445
446 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
447 }
448
xgbe_phy_put_comm_ownership(struct xgbe_prv_data * pdata)449 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
450 {
451 mutex_unlock(&xgbe_phy_comm_lock);
452 }
453
xgbe_phy_get_comm_ownership(struct xgbe_prv_data * pdata)454 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
455 {
456 struct xgbe_phy_data *phy_data = pdata->phy_data;
457 unsigned long timeout;
458 unsigned int mutex_id;
459
460 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
461 * the driver needs to take the software mutex and then the hardware
462 * mutexes before being able to use the busses.
463 */
464 mutex_lock(&xgbe_phy_comm_lock);
465
466 /* Clear the mutexes */
467 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
468 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
469
470 /* Mutex formats are the same for I2C and MDIO/GPIO */
471 mutex_id = 0;
472 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
473 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
474
475 timeout = jiffies + (5 * HZ);
476 while (time_before(jiffies, timeout)) {
477 /* Must be all zeroes in order to obtain the mutex */
478 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
479 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
480 usleep_range(100, 200);
481 continue;
482 }
483
484 /* Obtain the mutex */
485 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
486 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
487
488 return 0;
489 }
490
491 mutex_unlock(&xgbe_phy_comm_lock);
492
493 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
494
495 return -ETIMEDOUT;
496 }
497
xgbe_phy_mdio_mii_write_c22(struct xgbe_prv_data * pdata,int addr,int reg,u16 val)498 static int xgbe_phy_mdio_mii_write_c22(struct xgbe_prv_data *pdata, int addr,
499 int reg, u16 val)
500 {
501 struct xgbe_phy_data *phy_data = pdata->phy_data;
502
503 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
504 return -EOPNOTSUPP;
505
506 return pdata->hw_if.write_ext_mii_regs_c22(pdata, addr, reg, val);
507 }
508
xgbe_phy_mdio_mii_write_c45(struct xgbe_prv_data * pdata,int addr,int devad,int reg,u16 val)509 static int xgbe_phy_mdio_mii_write_c45(struct xgbe_prv_data *pdata, int addr,
510 int devad, int reg, u16 val)
511 {
512 struct xgbe_phy_data *phy_data = pdata->phy_data;
513
514 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
515 return -EOPNOTSUPP;
516
517 return pdata->hw_if.write_ext_mii_regs_c45(pdata, addr, devad,
518 reg, val);
519 }
520
xgbe_phy_i2c_mii_write(struct xgbe_prv_data * pdata,int reg,u16 val)521 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
522 {
523 __be16 *mii_val;
524 u8 mii_data[3];
525 int ret;
526
527 ret = xgbe_phy_sfp_get_mux(pdata);
528 if (ret)
529 return ret;
530
531 mii_data[0] = reg & 0xff;
532 mii_val = (__be16 *)&mii_data[1];
533 *mii_val = cpu_to_be16(val);
534
535 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
536 mii_data, sizeof(mii_data));
537
538 xgbe_phy_sfp_put_mux(pdata);
539
540 return ret;
541 }
542
xgbe_phy_mii_write_c22(struct mii_bus * mii,int addr,int reg,u16 val)543 static int xgbe_phy_mii_write_c22(struct mii_bus *mii, int addr, int reg,
544 u16 val)
545 {
546 struct xgbe_prv_data *pdata = mii->priv;
547 struct xgbe_phy_data *phy_data = pdata->phy_data;
548 int ret;
549
550 ret = xgbe_phy_get_comm_ownership(pdata);
551 if (ret)
552 return ret;
553
554 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
555 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
556 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
557 ret = xgbe_phy_mdio_mii_write_c22(pdata, addr, reg, val);
558 else
559 ret = -EOPNOTSUPP;
560
561 xgbe_phy_put_comm_ownership(pdata);
562
563 return ret;
564 }
565
xgbe_phy_mii_write_c45(struct mii_bus * mii,int addr,int devad,int reg,u16 val)566 static int xgbe_phy_mii_write_c45(struct mii_bus *mii, int addr, int devad,
567 int reg, u16 val)
568 {
569 struct xgbe_prv_data *pdata = mii->priv;
570 struct xgbe_phy_data *phy_data = pdata->phy_data;
571 int ret;
572
573 ret = xgbe_phy_get_comm_ownership(pdata);
574 if (ret)
575 return ret;
576
577 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
578 ret = -EOPNOTSUPP;
579 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
580 ret = xgbe_phy_mdio_mii_write_c45(pdata, addr, devad, reg, val);
581 else
582 ret = -EOPNOTSUPP;
583
584 xgbe_phy_put_comm_ownership(pdata);
585
586 return ret;
587 }
588
xgbe_phy_mdio_mii_read_c22(struct xgbe_prv_data * pdata,int addr,int reg)589 static int xgbe_phy_mdio_mii_read_c22(struct xgbe_prv_data *pdata, int addr,
590 int reg)
591 {
592 struct xgbe_phy_data *phy_data = pdata->phy_data;
593
594 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
595 return -EOPNOTSUPP;
596
597 return pdata->hw_if.read_ext_mii_regs_c22(pdata, addr, reg);
598 }
599
xgbe_phy_mdio_mii_read_c45(struct xgbe_prv_data * pdata,int addr,int devad,int reg)600 static int xgbe_phy_mdio_mii_read_c45(struct xgbe_prv_data *pdata, int addr,
601 int devad, int reg)
602 {
603 struct xgbe_phy_data *phy_data = pdata->phy_data;
604
605 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
606 return -EOPNOTSUPP;
607
608 return pdata->hw_if.read_ext_mii_regs_c45(pdata, addr, devad, reg);
609 }
610
xgbe_phy_i2c_mii_read(struct xgbe_prv_data * pdata,int reg)611 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
612 {
613 __be16 mii_val;
614 u8 mii_reg;
615 int ret;
616
617 ret = xgbe_phy_sfp_get_mux(pdata);
618 if (ret)
619 return ret;
620
621 mii_reg = reg;
622 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
623 &mii_reg, sizeof(mii_reg),
624 &mii_val, sizeof(mii_val));
625 if (!ret)
626 ret = be16_to_cpu(mii_val);
627
628 xgbe_phy_sfp_put_mux(pdata);
629
630 return ret;
631 }
632
xgbe_phy_mii_read_c22(struct mii_bus * mii,int addr,int reg)633 static int xgbe_phy_mii_read_c22(struct mii_bus *mii, int addr, int reg)
634 {
635 struct xgbe_prv_data *pdata = mii->priv;
636 struct xgbe_phy_data *phy_data = pdata->phy_data;
637 int ret;
638
639 ret = xgbe_phy_get_comm_ownership(pdata);
640 if (ret)
641 return ret;
642
643 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
644 ret = xgbe_phy_i2c_mii_read(pdata, reg);
645 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
646 ret = xgbe_phy_mdio_mii_read_c22(pdata, addr, reg);
647 else
648 ret = -EOPNOTSUPP;
649
650 xgbe_phy_put_comm_ownership(pdata);
651
652 return ret;
653 }
654
xgbe_phy_mii_read_c45(struct mii_bus * mii,int addr,int devad,int reg)655 static int xgbe_phy_mii_read_c45(struct mii_bus *mii, int addr, int devad,
656 int reg)
657 {
658 struct xgbe_prv_data *pdata = mii->priv;
659 struct xgbe_phy_data *phy_data = pdata->phy_data;
660 int ret;
661
662 ret = xgbe_phy_get_comm_ownership(pdata);
663 if (ret)
664 return ret;
665
666 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
667 ret = -EOPNOTSUPP;
668 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
669 ret = xgbe_phy_mdio_mii_read_c45(pdata, addr, devad, reg);
670 else
671 ret = -EOPNOTSUPP;
672
673 xgbe_phy_put_comm_ownership(pdata);
674
675 return ret;
676 }
677
xgbe_phy_sfp_phy_settings(struct xgbe_prv_data * pdata)678 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
679 {
680 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
681 struct xgbe_phy_data *phy_data = pdata->phy_data;
682
683 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
684 return;
685
686 XGBE_ZERO_SUP(lks);
687
688 if (phy_data->sfp_mod_absent) {
689 pdata->phy.speed = SPEED_UNKNOWN;
690 pdata->phy.duplex = DUPLEX_UNKNOWN;
691 pdata->phy.autoneg = AUTONEG_ENABLE;
692 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
693
694 XGBE_SET_SUP(lks, Autoneg);
695 XGBE_SET_SUP(lks, Pause);
696 XGBE_SET_SUP(lks, Asym_Pause);
697 XGBE_SET_SUP(lks, TP);
698 XGBE_SET_SUP(lks, FIBRE);
699
700 XGBE_LM_COPY(lks, advertising, lks, supported);
701
702 return;
703 }
704
705 switch (phy_data->sfp_base) {
706 case XGBE_SFP_BASE_1000_T:
707 case XGBE_SFP_BASE_1000_SX:
708 case XGBE_SFP_BASE_1000_LX:
709 case XGBE_SFP_BASE_1000_CX:
710 pdata->phy.speed = SPEED_UNKNOWN;
711 pdata->phy.duplex = DUPLEX_UNKNOWN;
712 pdata->phy.autoneg = AUTONEG_ENABLE;
713 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
714 XGBE_SET_SUP(lks, Autoneg);
715 XGBE_SET_SUP(lks, Pause);
716 XGBE_SET_SUP(lks, Asym_Pause);
717 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
718 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)
719 XGBE_SET_SUP(lks, 10baseT_Full);
720 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
721 XGBE_SET_SUP(lks, 100baseT_Full);
722 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
723 XGBE_SET_SUP(lks, 1000baseT_Full);
724 } else {
725 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
726 XGBE_SET_SUP(lks, 1000baseX_Full);
727 }
728 break;
729 case XGBE_SFP_BASE_10000_SR:
730 case XGBE_SFP_BASE_10000_LR:
731 case XGBE_SFP_BASE_10000_LRM:
732 case XGBE_SFP_BASE_10000_ER:
733 case XGBE_SFP_BASE_10000_CR:
734 pdata->phy.speed = SPEED_10000;
735 pdata->phy.duplex = DUPLEX_FULL;
736 pdata->phy.autoneg = AUTONEG_DISABLE;
737 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
738 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
739 switch (phy_data->sfp_base) {
740 case XGBE_SFP_BASE_10000_SR:
741 XGBE_SET_SUP(lks, 10000baseSR_Full);
742 break;
743 case XGBE_SFP_BASE_10000_LR:
744 XGBE_SET_SUP(lks, 10000baseLR_Full);
745 break;
746 case XGBE_SFP_BASE_10000_LRM:
747 XGBE_SET_SUP(lks, 10000baseLRM_Full);
748 break;
749 case XGBE_SFP_BASE_10000_ER:
750 XGBE_SET_SUP(lks, 10000baseER_Full);
751 break;
752 case XGBE_SFP_BASE_10000_CR:
753 XGBE_SET_SUP(lks, 10000baseCR_Full);
754 break;
755 default:
756 break;
757 }
758 }
759 break;
760 default:
761 pdata->phy.speed = SPEED_UNKNOWN;
762 pdata->phy.duplex = DUPLEX_UNKNOWN;
763 pdata->phy.autoneg = AUTONEG_DISABLE;
764 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
765 break;
766 }
767
768 switch (phy_data->sfp_base) {
769 case XGBE_SFP_BASE_1000_T:
770 case XGBE_SFP_BASE_1000_CX:
771 case XGBE_SFP_BASE_10000_CR:
772 XGBE_SET_SUP(lks, TP);
773 break;
774 default:
775 XGBE_SET_SUP(lks, FIBRE);
776 break;
777 }
778
779 XGBE_LM_COPY(lks, advertising, lks, supported);
780 }
781
xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom * sfp_eeprom,enum xgbe_sfp_speed sfp_speed)782 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
783 enum xgbe_sfp_speed sfp_speed)
784 {
785 u8 *sfp_base, min;
786
787 sfp_base = sfp_eeprom->base;
788
789 switch (sfp_speed) {
790 case XGBE_SFP_SPEED_1000:
791 min = XGBE_SFP_BASE_BR_1GBE_MIN;
792 break;
793 case XGBE_SFP_SPEED_10000:
794 min = XGBE_SFP_BASE_BR_10GBE_MIN;
795 break;
796 default:
797 return false;
798 }
799
800 return sfp_base[XGBE_SFP_BASE_BR] >= min;
801 }
802
xgbe_phy_free_phy_device(struct xgbe_prv_data * pdata)803 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
804 {
805 struct xgbe_phy_data *phy_data = pdata->phy_data;
806
807 if (phy_data->phydev) {
808 phy_detach(phy_data->phydev);
809 phy_device_remove(phy_data->phydev);
810 phy_device_free(phy_data->phydev);
811 phy_data->phydev = NULL;
812 }
813 }
814
xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data * pdata)815 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
816 {
817 struct xgbe_phy_data *phy_data = pdata->phy_data;
818 unsigned int phy_id = phy_data->phydev->phy_id;
819
820 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
821 return false;
822
823 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
824 return false;
825
826 /* Enable Base-T AN */
827 phy_write(phy_data->phydev, 0x16, 0x0001);
828 phy_write(phy_data->phydev, 0x00, 0x9140);
829 phy_write(phy_data->phydev, 0x16, 0x0000);
830
831 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
832 phy_write(phy_data->phydev, 0x1b, 0x9084);
833 phy_write(phy_data->phydev, 0x09, 0x0e00);
834 phy_write(phy_data->phydev, 0x00, 0x8140);
835 phy_write(phy_data->phydev, 0x04, 0x0d01);
836 phy_write(phy_data->phydev, 0x00, 0x9140);
837
838 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES);
839
840 phy_support_asym_pause(phy_data->phydev);
841
842 netif_dbg(pdata, drv, pdata->netdev,
843 "Finisar PHY quirk in place\n");
844
845 return true;
846 }
847
xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data * pdata)848 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
849 {
850 struct xgbe_phy_data *phy_data = pdata->phy_data;
851 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
852 unsigned int phy_id = phy_data->phydev->phy_id;
853 int reg;
854
855 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
856 return false;
857
858 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
859 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
860 return false;
861
862 /* For Bel-Fuse, use the extra AN flag */
863 pdata->an_again = 1;
864
865 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
866 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
867 return false;
868
869 if ((phy_id & 0xfffffff0) != 0x03625d10)
870 return false;
871
872 /* Reset PHY - wait for self-clearing reset bit to clear */
873 genphy_soft_reset(phy_data->phydev);
874
875 /* Disable RGMII mode */
876 phy_write(phy_data->phydev, 0x18, 0x7007);
877 reg = phy_read(phy_data->phydev, 0x18);
878 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
879
880 /* Enable fiber register bank */
881 phy_write(phy_data->phydev, 0x1c, 0x7c00);
882 reg = phy_read(phy_data->phydev, 0x1c);
883 reg &= 0x03ff;
884 reg &= ~0x0001;
885 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
886
887 /* Power down SerDes */
888 reg = phy_read(phy_data->phydev, 0x00);
889 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
890
891 /* Configure SGMII-to-Copper mode */
892 phy_write(phy_data->phydev, 0x1c, 0x7c00);
893 reg = phy_read(phy_data->phydev, 0x1c);
894 reg &= 0x03ff;
895 reg &= ~0x0006;
896 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
897
898 /* Power up SerDes */
899 reg = phy_read(phy_data->phydev, 0x00);
900 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
901
902 /* Enable copper register bank */
903 phy_write(phy_data->phydev, 0x1c, 0x7c00);
904 reg = phy_read(phy_data->phydev, 0x1c);
905 reg &= 0x03ff;
906 reg &= ~0x0001;
907 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
908
909 /* Power up SerDes */
910 reg = phy_read(phy_data->phydev, 0x00);
911 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
912
913 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES);
914 phy_support_asym_pause(phy_data->phydev);
915
916 netif_dbg(pdata, drv, pdata->netdev,
917 "BelFuse PHY quirk in place\n");
918
919 return true;
920 }
921
xgbe_phy_external_phy_quirks(struct xgbe_prv_data * pdata)922 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
923 {
924 if (xgbe_phy_belfuse_phy_quirks(pdata))
925 return;
926
927 if (xgbe_phy_finisar_phy_quirks(pdata))
928 return;
929 }
930
xgbe_phy_find_phy_device(struct xgbe_prv_data * pdata)931 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
932 {
933 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
934 struct xgbe_phy_data *phy_data = pdata->phy_data;
935 struct phy_device *phydev;
936 int ret;
937
938 /* If we already have a PHY, just return */
939 if (phy_data->phydev)
940 return 0;
941
942 /* Clear the extra AN flag */
943 pdata->an_again = 0;
944
945 /* Check for the use of an external PHY */
946 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
947 return 0;
948
949 /* For SFP, only use an external PHY if available */
950 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
951 !phy_data->sfp_phy_avail)
952 return 0;
953
954 /* Set the proper MDIO mode for the PHY */
955 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
956 phy_data->phydev_mode);
957 if (ret) {
958 netdev_err(pdata->netdev,
959 "mdio port/clause not compatible (%u/%u)\n",
960 phy_data->mdio_addr, phy_data->phydev_mode);
961 return ret;
962 }
963
964 /* Create and connect to the PHY device */
965 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
966 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
967 if (IS_ERR(phydev)) {
968 netdev_err(pdata->netdev, "get_phy_device failed\n");
969 return -ENODEV;
970 }
971 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
972 phydev->phy_id);
973
974 /*TODO: If c45, add request_module based on one of the MMD ids? */
975
976 ret = phy_device_register(phydev);
977 if (ret) {
978 netdev_err(pdata->netdev, "phy_device_register failed\n");
979 phy_device_free(phydev);
980 return ret;
981 }
982
983 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
984 PHY_INTERFACE_MODE_SGMII);
985 if (ret) {
986 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
987 phy_device_remove(phydev);
988 phy_device_free(phydev);
989 return ret;
990 }
991 phy_data->phydev = phydev;
992 phy_data->phydev->mac_managed_pm = true;
993
994 xgbe_phy_external_phy_quirks(pdata);
995
996 linkmode_and(phydev->advertising, phydev->advertising,
997 lks->link_modes.advertising);
998
999 phy_start_aneg(phy_data->phydev);
1000
1001 return 0;
1002 }
1003
xgbe_phy_sfp_external_phy(struct xgbe_prv_data * pdata)1004 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1005 {
1006 struct xgbe_phy_data *phy_data = pdata->phy_data;
1007 int ret;
1008
1009 if (!phy_data->sfp_changed)
1010 return;
1011
1012 phy_data->sfp_phy_avail = 0;
1013
1014 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1015 return;
1016
1017 /* Check access to the PHY by reading CTRL1 */
1018 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1019 if (ret < 0)
1020 return;
1021
1022 /* Successfully accessed the PHY */
1023 phy_data->sfp_phy_avail = 1;
1024 }
1025
xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data * phy_data)1026 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1027 {
1028 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1029
1030 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1031 return false;
1032
1033 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1034 return false;
1035
1036 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1037 return true;
1038
1039 return false;
1040 }
1041
xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data * phy_data)1042 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1043 {
1044 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1045
1046 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1047 return false;
1048
1049 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1050 return false;
1051
1052 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1053 return true;
1054
1055 return false;
1056 }
1057
xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data * phy_data)1058 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1059 {
1060 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1061 return false;
1062
1063 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1064 return true;
1065
1066 return false;
1067 }
1068
xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data * pdata)1069 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1070 {
1071 struct xgbe_phy_data *phy_data = pdata->phy_data;
1072 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1073 u8 *sfp_base;
1074
1075 sfp_base = sfp_eeprom->base;
1076
1077 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1078 return;
1079
1080 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1081 return;
1082
1083 /* Update transceiver signals (eeprom extd/options) */
1084 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1085 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1086
1087 /* Assume FIBER cable unless told otherwise */
1088 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1089 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1090 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1091 } else if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_ACTIVE) {
1092 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1093 } else {
1094 phy_data->sfp_cable = XGBE_SFP_CABLE_FIBER;
1095 }
1096
1097 /* Determine the type of SFP */
1098 if (phy_data->sfp_cable != XGBE_SFP_CABLE_FIBER &&
1099 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1100 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1101 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1102 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1103 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1104 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1105 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1106 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1107 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1108 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1109 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1110 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1111 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1112 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1113 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1114 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1115 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1116 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1117
1118 switch (phy_data->sfp_base) {
1119 case XGBE_SFP_BASE_1000_T:
1120 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1121 break;
1122 case XGBE_SFP_BASE_1000_SX:
1123 case XGBE_SFP_BASE_1000_LX:
1124 case XGBE_SFP_BASE_1000_CX:
1125 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1126 break;
1127 case XGBE_SFP_BASE_10000_SR:
1128 case XGBE_SFP_BASE_10000_LR:
1129 case XGBE_SFP_BASE_10000_LRM:
1130 case XGBE_SFP_BASE_10000_ER:
1131 case XGBE_SFP_BASE_10000_CR:
1132 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1133 break;
1134 default:
1135 break;
1136 }
1137 }
1138
xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data * pdata,struct xgbe_sfp_eeprom * sfp_eeprom)1139 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1140 struct xgbe_sfp_eeprom *sfp_eeprom)
1141 {
1142 struct xgbe_sfp_ascii sfp_ascii;
1143 char *sfp_data = (char *)&sfp_ascii;
1144
1145 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1146 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1147 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1148 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1149 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1150 sfp_data);
1151
1152 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1153 XGBE_SFP_BASE_VENDOR_PN_LEN);
1154 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1155 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1156 sfp_data);
1157
1158 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1159 XGBE_SFP_BASE_VENDOR_REV_LEN);
1160 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1161 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1162 sfp_data);
1163
1164 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1165 XGBE_SFP_BASE_VENDOR_SN_LEN);
1166 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1167 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1168 sfp_data);
1169 }
1170
xgbe_phy_sfp_verify_eeprom(u8 cc_in,u8 * buf,unsigned int len)1171 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1172 {
1173 u8 cc;
1174
1175 for (cc = 0; len; buf++, len--)
1176 cc += *buf;
1177
1178 return cc == cc_in;
1179 }
1180
xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data * pdata)1181 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1182 {
1183 struct xgbe_phy_data *phy_data = pdata->phy_data;
1184 struct xgbe_sfp_eeprom sfp_eeprom;
1185 u8 eeprom_addr;
1186 int ret;
1187
1188 ret = xgbe_phy_sfp_get_mux(pdata);
1189 if (ret) {
1190 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1191 netdev_name(pdata->netdev));
1192 return ret;
1193 }
1194
1195 /* Read the SFP serial ID eeprom */
1196 eeprom_addr = 0;
1197 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1198 &eeprom_addr, sizeof(eeprom_addr),
1199 &sfp_eeprom, sizeof(sfp_eeprom));
1200 if (ret) {
1201 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1202 netdev_name(pdata->netdev));
1203 goto put;
1204 }
1205
1206 /* Validate the contents read */
1207 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1208 sfp_eeprom.base,
1209 sizeof(sfp_eeprom.base) - 1)) {
1210 ret = -EINVAL;
1211 goto put;
1212 }
1213
1214 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1215 sfp_eeprom.extd,
1216 sizeof(sfp_eeprom.extd) - 1)) {
1217 ret = -EINVAL;
1218 goto put;
1219 }
1220
1221 /* Check for an added or changed SFP */
1222 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1223 phy_data->sfp_changed = 1;
1224
1225 if (netif_msg_drv(pdata))
1226 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1227
1228 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1229
1230 xgbe_phy_free_phy_device(pdata);
1231 } else {
1232 phy_data->sfp_changed = 0;
1233 }
1234
1235 put:
1236 xgbe_phy_sfp_put_mux(pdata);
1237
1238 return ret;
1239 }
1240
xgbe_phy_sfp_signals(struct xgbe_prv_data * pdata)1241 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1242 {
1243 struct xgbe_phy_data *phy_data = pdata->phy_data;
1244 u8 gpio_reg, gpio_ports[2];
1245 int ret;
1246
1247 /* Read the input port registers */
1248 gpio_reg = 0;
1249 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1250 &gpio_reg, sizeof(gpio_reg),
1251 gpio_ports, sizeof(gpio_ports));
1252 if (ret) {
1253 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1254 netdev_name(pdata->netdev));
1255 return;
1256 }
1257
1258 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1259
1260 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1261 }
1262
xgbe_phy_sfp_mod_absent(struct xgbe_prv_data * pdata)1263 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1264 {
1265 struct xgbe_phy_data *phy_data = pdata->phy_data;
1266
1267 xgbe_phy_free_phy_device(pdata);
1268
1269 phy_data->sfp_mod_absent = 1;
1270 phy_data->sfp_phy_avail = 0;
1271 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1272 }
1273
xgbe_phy_sfp_reset(struct xgbe_phy_data * phy_data)1274 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1275 {
1276 phy_data->sfp_rx_los = 0;
1277 phy_data->sfp_tx_fault = 0;
1278 phy_data->sfp_mod_absent = 1;
1279 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1280 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1281 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1282 }
1283
xgbe_phy_sfp_detect(struct xgbe_prv_data * pdata)1284 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1285 {
1286 struct xgbe_phy_data *phy_data = pdata->phy_data;
1287 int ret;
1288
1289 /* Reset the SFP signals and info */
1290 xgbe_phy_sfp_reset(phy_data);
1291
1292 ret = xgbe_phy_get_comm_ownership(pdata);
1293 if (ret)
1294 return;
1295
1296 /* Read the SFP signals and check for module presence */
1297 xgbe_phy_sfp_signals(pdata);
1298 if (phy_data->sfp_mod_absent) {
1299 xgbe_phy_sfp_mod_absent(pdata);
1300 goto put;
1301 }
1302
1303 ret = xgbe_phy_sfp_read_eeprom(pdata);
1304 if (ret) {
1305 /* Treat any error as if there isn't an SFP plugged in */
1306 xgbe_phy_sfp_reset(phy_data);
1307 xgbe_phy_sfp_mod_absent(pdata);
1308 goto put;
1309 }
1310
1311 xgbe_phy_sfp_parse_eeprom(pdata);
1312
1313 xgbe_phy_sfp_external_phy(pdata);
1314
1315 put:
1316 xgbe_phy_sfp_phy_settings(pdata);
1317
1318 xgbe_phy_put_comm_ownership(pdata);
1319 }
1320
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata,struct ethtool_eeprom * eeprom,u8 * data)1321 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1322 struct ethtool_eeprom *eeprom, u8 *data)
1323 {
1324 struct xgbe_phy_data *phy_data = pdata->phy_data;
1325 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1326 struct xgbe_sfp_eeprom *sfp_eeprom;
1327 unsigned int i, j, rem;
1328 int ret;
1329
1330 rem = eeprom->len;
1331
1332 if (!eeprom->len) {
1333 ret = -EINVAL;
1334 goto done;
1335 }
1336
1337 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1338 ret = -EINVAL;
1339 goto done;
1340 }
1341
1342 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1343 ret = -ENXIO;
1344 goto done;
1345 }
1346
1347 if (!netif_running(pdata->netdev)) {
1348 ret = -EIO;
1349 goto done;
1350 }
1351
1352 if (phy_data->sfp_mod_absent) {
1353 ret = -EIO;
1354 goto done;
1355 }
1356
1357 ret = xgbe_phy_get_comm_ownership(pdata);
1358 if (ret) {
1359 ret = -EIO;
1360 goto done;
1361 }
1362
1363 ret = xgbe_phy_sfp_get_mux(pdata);
1364 if (ret) {
1365 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1366 ret = -EIO;
1367 goto put_own;
1368 }
1369
1370 /* Read the SFP serial ID eeprom */
1371 eeprom_addr = 0;
1372 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1373 &eeprom_addr, sizeof(eeprom_addr),
1374 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1375 if (ret) {
1376 netdev_err(pdata->netdev,
1377 "I2C error reading SFP EEPROM\n");
1378 ret = -EIO;
1379 goto put_mux;
1380 }
1381
1382 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1383
1384 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1385 /* Read the SFP diagnostic eeprom */
1386 eeprom_addr = 0;
1387 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1388 &eeprom_addr, sizeof(eeprom_addr),
1389 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1390 XGBE_SFP_EEPROM_DIAG_LEN);
1391 if (ret) {
1392 netdev_err(pdata->netdev,
1393 "I2C error reading SFP DIAGS\n");
1394 ret = -EIO;
1395 goto put_mux;
1396 }
1397 }
1398
1399 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1400 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1401 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1402 break;
1403
1404 data[i] = eeprom_data[j];
1405 rem--;
1406 }
1407
1408 put_mux:
1409 xgbe_phy_sfp_put_mux(pdata);
1410
1411 put_own:
1412 xgbe_phy_put_comm_ownership(pdata);
1413
1414 done:
1415 eeprom->len -= rem;
1416
1417 return ret;
1418 }
1419
xgbe_phy_module_info(struct xgbe_prv_data * pdata,struct ethtool_modinfo * modinfo)1420 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1421 struct ethtool_modinfo *modinfo)
1422 {
1423 struct xgbe_phy_data *phy_data = pdata->phy_data;
1424
1425 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1426 return -ENXIO;
1427
1428 if (!netif_running(pdata->netdev))
1429 return -EIO;
1430
1431 if (phy_data->sfp_mod_absent)
1432 return -EIO;
1433
1434 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1435 modinfo->type = ETH_MODULE_SFF_8472;
1436 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1437 } else {
1438 modinfo->type = ETH_MODULE_SFF_8079;
1439 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1440 }
1441
1442 return 0;
1443 }
1444
xgbe_phy_phydev_flowctrl(struct xgbe_prv_data * pdata)1445 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1446 {
1447 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1448 struct xgbe_phy_data *phy_data = pdata->phy_data;
1449 u16 lcl_adv = 0, rmt_adv = 0;
1450 u8 fc;
1451
1452 pdata->phy.tx_pause = 0;
1453 pdata->phy.rx_pause = 0;
1454
1455 if (!phy_data->phydev)
1456 return;
1457
1458 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
1459
1460 if (phy_data->phydev->pause) {
1461 XGBE_SET_LP_ADV(lks, Pause);
1462 rmt_adv |= LPA_PAUSE_CAP;
1463 }
1464 if (phy_data->phydev->asym_pause) {
1465 XGBE_SET_LP_ADV(lks, Asym_Pause);
1466 rmt_adv |= LPA_PAUSE_ASYM;
1467 }
1468
1469 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1470 if (fc & FLOW_CTRL_TX)
1471 pdata->phy.tx_pause = 1;
1472 if (fc & FLOW_CTRL_RX)
1473 pdata->phy.rx_pause = 1;
1474 }
1475
xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data * pdata)1476 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1477 {
1478 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1479 enum xgbe_mode mode;
1480
1481 XGBE_SET_LP_ADV(lks, Autoneg);
1482 XGBE_SET_LP_ADV(lks, TP);
1483
1484 /* Use external PHY to determine flow control */
1485 if (pdata->phy.pause_autoneg)
1486 xgbe_phy_phydev_flowctrl(pdata);
1487
1488 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1489 case XGBE_SGMII_AN_LINK_SPEED_10:
1490 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1491 XGBE_SET_LP_ADV(lks, 10baseT_Full);
1492 mode = XGBE_MODE_SGMII_10;
1493 } else {
1494 /* Half-duplex not supported */
1495 XGBE_SET_LP_ADV(lks, 10baseT_Half);
1496 mode = XGBE_MODE_UNKNOWN;
1497 }
1498 break;
1499 case XGBE_SGMII_AN_LINK_SPEED_100:
1500 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1501 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1502 mode = XGBE_MODE_SGMII_100;
1503 } else {
1504 /* Half-duplex not supported */
1505 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1506 mode = XGBE_MODE_UNKNOWN;
1507 }
1508 break;
1509 case XGBE_SGMII_AN_LINK_SPEED_1000:
1510 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1511 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1512 mode = XGBE_MODE_SGMII_1000;
1513 } else {
1514 /* Half-duplex not supported */
1515 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1516 mode = XGBE_MODE_UNKNOWN;
1517 }
1518 break;
1519 default:
1520 mode = XGBE_MODE_UNKNOWN;
1521 }
1522
1523 return mode;
1524 }
1525
xgbe_phy_an37_outcome(struct xgbe_prv_data * pdata)1526 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1527 {
1528 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1529 enum xgbe_mode mode;
1530 unsigned int ad_reg, lp_reg;
1531
1532 XGBE_SET_LP_ADV(lks, Autoneg);
1533 XGBE_SET_LP_ADV(lks, FIBRE);
1534
1535 /* Compare Advertisement and Link Partner register */
1536 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1537 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1538 if (lp_reg & 0x100)
1539 XGBE_SET_LP_ADV(lks, Pause);
1540 if (lp_reg & 0x80)
1541 XGBE_SET_LP_ADV(lks, Asym_Pause);
1542
1543 if (pdata->phy.pause_autoneg) {
1544 /* Set flow control based on auto-negotiation result */
1545 pdata->phy.tx_pause = 0;
1546 pdata->phy.rx_pause = 0;
1547
1548 if (ad_reg & lp_reg & 0x100) {
1549 pdata->phy.tx_pause = 1;
1550 pdata->phy.rx_pause = 1;
1551 } else if (ad_reg & lp_reg & 0x80) {
1552 if (ad_reg & 0x100)
1553 pdata->phy.rx_pause = 1;
1554 else if (lp_reg & 0x100)
1555 pdata->phy.tx_pause = 1;
1556 }
1557 }
1558
1559 if (lp_reg & 0x20)
1560 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1561
1562 /* Half duplex is not supported */
1563 ad_reg &= lp_reg;
1564 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1565
1566 return mode;
1567 }
1568
xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data * pdata)1569 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1570 {
1571 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1572 struct xgbe_phy_data *phy_data = pdata->phy_data;
1573 enum xgbe_mode mode;
1574 unsigned int ad_reg, lp_reg;
1575
1576 XGBE_SET_LP_ADV(lks, Autoneg);
1577 XGBE_SET_LP_ADV(lks, Backplane);
1578
1579 /* Use external PHY to determine flow control */
1580 if (pdata->phy.pause_autoneg)
1581 xgbe_phy_phydev_flowctrl(pdata);
1582
1583 /* Compare Advertisement and Link Partner register 2 */
1584 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1585 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1586 if (lp_reg & 0x80)
1587 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1588 if (lp_reg & 0x20)
1589 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1590
1591 ad_reg &= lp_reg;
1592 if (ad_reg & 0x80) {
1593 switch (phy_data->port_mode) {
1594 case XGBE_PORT_MODE_BACKPLANE:
1595 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1596 mode = XGBE_MODE_KR;
1597 break;
1598 default:
1599 mode = XGBE_MODE_SFI;
1600 break;
1601 }
1602 } else if (ad_reg & 0x20) {
1603 switch (phy_data->port_mode) {
1604 case XGBE_PORT_MODE_BACKPLANE:
1605 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1606 mode = XGBE_MODE_KX_1000;
1607 break;
1608 case XGBE_PORT_MODE_1000BASE_X:
1609 mode = XGBE_MODE_X;
1610 break;
1611 case XGBE_PORT_MODE_SFP:
1612 switch (phy_data->sfp_base) {
1613 case XGBE_SFP_BASE_1000_T:
1614 if (phy_data->phydev &&
1615 (phy_data->phydev->speed == SPEED_10))
1616 mode = XGBE_MODE_SGMII_10;
1617 else if (phy_data->phydev &&
1618 (phy_data->phydev->speed == SPEED_100))
1619 mode = XGBE_MODE_SGMII_100;
1620 else
1621 mode = XGBE_MODE_SGMII_1000;
1622 break;
1623 case XGBE_SFP_BASE_1000_SX:
1624 case XGBE_SFP_BASE_1000_LX:
1625 case XGBE_SFP_BASE_1000_CX:
1626 default:
1627 mode = XGBE_MODE_X;
1628 break;
1629 }
1630 break;
1631 default:
1632 if (phy_data->phydev &&
1633 (phy_data->phydev->speed == SPEED_10))
1634 mode = XGBE_MODE_SGMII_10;
1635 else if (phy_data->phydev &&
1636 (phy_data->phydev->speed == SPEED_100))
1637 mode = XGBE_MODE_SGMII_100;
1638 else
1639 mode = XGBE_MODE_SGMII_1000;
1640 break;
1641 }
1642 } else {
1643 mode = XGBE_MODE_UNKNOWN;
1644 }
1645
1646 /* Compare Advertisement and Link Partner register 3 */
1647 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1648 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1649 if (lp_reg & 0xc000)
1650 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1651
1652 return mode;
1653 }
1654
xgbe_phy_an73_outcome(struct xgbe_prv_data * pdata)1655 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1656 {
1657 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1658 enum xgbe_mode mode;
1659 unsigned int ad_reg, lp_reg;
1660
1661 XGBE_SET_LP_ADV(lks, Autoneg);
1662 XGBE_SET_LP_ADV(lks, Backplane);
1663
1664 /* Compare Advertisement and Link Partner register 1 */
1665 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1666 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1667 if (lp_reg & 0x400)
1668 XGBE_SET_LP_ADV(lks, Pause);
1669 if (lp_reg & 0x800)
1670 XGBE_SET_LP_ADV(lks, Asym_Pause);
1671
1672 if (pdata->phy.pause_autoneg) {
1673 /* Set flow control based on auto-negotiation result */
1674 pdata->phy.tx_pause = 0;
1675 pdata->phy.rx_pause = 0;
1676
1677 if (ad_reg & lp_reg & 0x400) {
1678 pdata->phy.tx_pause = 1;
1679 pdata->phy.rx_pause = 1;
1680 } else if (ad_reg & lp_reg & 0x800) {
1681 if (ad_reg & 0x400)
1682 pdata->phy.rx_pause = 1;
1683 else if (lp_reg & 0x400)
1684 pdata->phy.tx_pause = 1;
1685 }
1686 }
1687
1688 /* Compare Advertisement and Link Partner register 2 */
1689 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1690 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1691 if (lp_reg & 0x80)
1692 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1693 if (lp_reg & 0x20)
1694 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1695
1696 ad_reg &= lp_reg;
1697 if (ad_reg & 0x80)
1698 mode = XGBE_MODE_KR;
1699 else if (ad_reg & 0x20)
1700 mode = XGBE_MODE_KX_1000;
1701 else
1702 mode = XGBE_MODE_UNKNOWN;
1703
1704 /* Compare Advertisement and Link Partner register 3 */
1705 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1706 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1707 if (lp_reg & 0xc000)
1708 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1709
1710 return mode;
1711 }
1712
xgbe_phy_an_outcome(struct xgbe_prv_data * pdata)1713 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1714 {
1715 switch (pdata->an_mode) {
1716 case XGBE_AN_MODE_CL73:
1717 return xgbe_phy_an73_outcome(pdata);
1718 case XGBE_AN_MODE_CL73_REDRV:
1719 return xgbe_phy_an73_redrv_outcome(pdata);
1720 case XGBE_AN_MODE_CL37:
1721 return xgbe_phy_an37_outcome(pdata);
1722 case XGBE_AN_MODE_CL37_SGMII:
1723 return xgbe_phy_an37_sgmii_outcome(pdata);
1724 default:
1725 return XGBE_MODE_UNKNOWN;
1726 }
1727 }
1728
xgbe_phy_an_advertising(struct xgbe_prv_data * pdata,struct ethtool_link_ksettings * dlks)1729 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1730 struct ethtool_link_ksettings *dlks)
1731 {
1732 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1733 struct xgbe_phy_data *phy_data = pdata->phy_data;
1734
1735 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1736
1737 /* Without a re-driver, just return current advertising */
1738 if (!phy_data->redrv)
1739 return;
1740
1741 /* With the KR re-driver we need to advertise a single speed */
1742 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1743 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1744
1745 /* Advertise FEC support is present */
1746 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1747 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1748
1749 switch (phy_data->port_mode) {
1750 case XGBE_PORT_MODE_BACKPLANE:
1751 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1752 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1753 break;
1754 case XGBE_PORT_MODE_BACKPLANE_2500:
1755 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1756 break;
1757 case XGBE_PORT_MODE_1000BASE_T:
1758 case XGBE_PORT_MODE_1000BASE_X:
1759 case XGBE_PORT_MODE_NBASE_T:
1760 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1761 break;
1762 case XGBE_PORT_MODE_10GBASE_T:
1763 if (phy_data->phydev &&
1764 (phy_data->phydev->speed == SPEED_10000))
1765 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1766 else if (phy_data->phydev &&
1767 (phy_data->phydev->speed == SPEED_2500))
1768 XGBE_SET_ADV(dlks, 2500baseX_Full);
1769 else
1770 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1771 break;
1772 case XGBE_PORT_MODE_10GBASE_R:
1773 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1774 break;
1775 case XGBE_PORT_MODE_SFP:
1776 switch (phy_data->sfp_base) {
1777 case XGBE_SFP_BASE_1000_T:
1778 case XGBE_SFP_BASE_1000_SX:
1779 case XGBE_SFP_BASE_1000_LX:
1780 case XGBE_SFP_BASE_1000_CX:
1781 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1782 break;
1783 default:
1784 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1785 break;
1786 }
1787 break;
1788 default:
1789 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1790 break;
1791 }
1792 }
1793
xgbe_phy_an_config(struct xgbe_prv_data * pdata)1794 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1795 {
1796 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1797 struct xgbe_phy_data *phy_data = pdata->phy_data;
1798 int ret;
1799
1800 ret = xgbe_phy_find_phy_device(pdata);
1801 if (ret)
1802 return ret;
1803
1804 if (!phy_data->phydev)
1805 return 0;
1806
1807 phy_data->phydev->autoneg = pdata->phy.autoneg;
1808 linkmode_and(phy_data->phydev->advertising,
1809 phy_data->phydev->supported,
1810 lks->link_modes.advertising);
1811
1812 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1813 phy_data->phydev->speed = pdata->phy.speed;
1814 phy_data->phydev->duplex = pdata->phy.duplex;
1815 }
1816
1817 ret = phy_start_aneg(phy_data->phydev);
1818
1819 return ret;
1820 }
1821
xgbe_phy_an_sfp_mode(struct xgbe_phy_data * phy_data)1822 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1823 {
1824 switch (phy_data->sfp_base) {
1825 case XGBE_SFP_BASE_1000_T:
1826 return XGBE_AN_MODE_CL37_SGMII;
1827 case XGBE_SFP_BASE_1000_SX:
1828 case XGBE_SFP_BASE_1000_LX:
1829 case XGBE_SFP_BASE_1000_CX:
1830 return XGBE_AN_MODE_CL37;
1831 default:
1832 return XGBE_AN_MODE_NONE;
1833 }
1834 }
1835
xgbe_phy_an_mode(struct xgbe_prv_data * pdata)1836 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1837 {
1838 struct xgbe_phy_data *phy_data = pdata->phy_data;
1839
1840 /* A KR re-driver will always require CL73 AN */
1841 if (phy_data->redrv)
1842 return XGBE_AN_MODE_CL73_REDRV;
1843
1844 switch (phy_data->port_mode) {
1845 case XGBE_PORT_MODE_BACKPLANE:
1846 return XGBE_AN_MODE_CL73;
1847 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1848 case XGBE_PORT_MODE_BACKPLANE_2500:
1849 return XGBE_AN_MODE_NONE;
1850 case XGBE_PORT_MODE_1000BASE_T:
1851 return XGBE_AN_MODE_CL37_SGMII;
1852 case XGBE_PORT_MODE_1000BASE_X:
1853 return XGBE_AN_MODE_CL37;
1854 case XGBE_PORT_MODE_NBASE_T:
1855 return XGBE_AN_MODE_CL37_SGMII;
1856 case XGBE_PORT_MODE_10GBASE_T:
1857 return XGBE_AN_MODE_CL73;
1858 case XGBE_PORT_MODE_10GBASE_R:
1859 return XGBE_AN_MODE_NONE;
1860 case XGBE_PORT_MODE_SFP:
1861 return xgbe_phy_an_sfp_mode(phy_data);
1862 default:
1863 return XGBE_AN_MODE_NONE;
1864 }
1865 }
1866
xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1867 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1868 enum xgbe_phy_redrv_mode mode)
1869 {
1870 struct xgbe_phy_data *phy_data = pdata->phy_data;
1871 u16 redrv_reg, redrv_val;
1872
1873 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1874 redrv_val = (u16)mode;
1875
1876 return pdata->hw_if.write_ext_mii_regs_c22(pdata, phy_data->redrv_addr,
1877 redrv_reg, redrv_val);
1878 }
1879
xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1880 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1881 enum xgbe_phy_redrv_mode mode)
1882 {
1883 struct xgbe_phy_data *phy_data = pdata->phy_data;
1884 unsigned int redrv_reg;
1885 int ret;
1886
1887 /* Calculate the register to write */
1888 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1889
1890 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1891
1892 return ret;
1893 }
1894
xgbe_phy_set_redrv_mode(struct xgbe_prv_data * pdata)1895 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1896 {
1897 struct xgbe_phy_data *phy_data = pdata->phy_data;
1898 enum xgbe_phy_redrv_mode mode;
1899 int ret;
1900
1901 if (!phy_data->redrv)
1902 return;
1903
1904 mode = XGBE_PHY_REDRV_MODE_CX;
1905 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1906 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1907 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1908 mode = XGBE_PHY_REDRV_MODE_SR;
1909
1910 ret = xgbe_phy_get_comm_ownership(pdata);
1911 if (ret)
1912 return;
1913
1914 if (phy_data->redrv_if)
1915 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1916 else
1917 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1918
1919 xgbe_phy_put_comm_ownership(pdata);
1920 }
1921
1922 #define MAX_RX_ADAPT_RETRIES 1
1923 #define XGBE_PMA_RX_VAL_SIG_MASK (XGBE_PMA_RX_SIG_DET_0_MASK | \
1924 XGBE_PMA_RX_VALID_0_MASK)
1925
xgbe_set_rx_adap_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)1926 static void xgbe_set_rx_adap_mode(struct xgbe_prv_data *pdata,
1927 enum xgbe_mode mode)
1928 {
1929 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {
1930 pdata->rx_adapt_retries = 0;
1931 pdata->mode_set = false;
1932 return;
1933 }
1934
1935 xgbe_phy_perform_ratechange(pdata,
1936 mode == XGBE_MODE_KR ?
1937 XGBE_MB_CMD_SET_10G_KR :
1938 XGBE_MB_CMD_SET_10G_SFI,
1939 XGBE_MB_SUBCMD_RX_ADAP);
1940 }
1941
xgbe_rx_adaptation(struct xgbe_prv_data * pdata)1942 static void xgbe_rx_adaptation(struct xgbe_prv_data *pdata)
1943 {
1944 struct xgbe_phy_data *phy_data = pdata->phy_data;
1945 int reg;
1946
1947 /* step 2: force PCS to send RX_ADAPT Req to PHY */
1948 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,
1949 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_ENABLE);
1950
1951 /* Step 3: Wait for RX_ADAPT ACK from the PHY */
1952 msleep(200);
1953
1954 /* Software polls for coefficient update command (given by local PHY) */
1955 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_PHY_RX_EQ_CEU);
1956
1957 /* Clear the RX_AD_REQ bit */
1958 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,
1959 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_DISABLE);
1960
1961 /* Check if coefficient update command is set */
1962 if ((reg & XGBE_PMA_CFF_UPDT_MASK) != XGBE_PMA_CFF_UPDT_MASK)
1963 goto set_mode;
1964
1965 /* Step 4: Check for Block lock */
1966
1967 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1968 if (reg < 0)
1969 goto set_mode;
1970
1971 /* Link status is latched low so that momentary link drops
1972 * can be detected. If link was already down read again
1973 * to get the latest state.
1974 */
1975 if (!pdata->phy.link && !(reg & MDIO_STAT1_LSTATUS)) {
1976 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1977 if (reg < 0)
1978 goto set_mode;
1979 }
1980
1981 if (reg & MDIO_STAT1_LSTATUS) {
1982 /* If the block lock is found, update the helpers
1983 * and declare the link up
1984 */
1985 netif_dbg(pdata, link, pdata->netdev, "Block_lock done");
1986 pdata->rx_adapt_done = true;
1987 pdata->rx_adapt_retries = 0;
1988 pdata->mode_set = false;
1989 return;
1990 }
1991
1992 set_mode:
1993 xgbe_set_rx_adap_mode(pdata, phy_data->cur_mode);
1994 }
1995
xgbe_phy_rx_adaptation(struct xgbe_prv_data * pdata)1996 static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata)
1997 {
1998 unsigned int reg;
1999
2000 rx_adapt_reinit:
2001 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_LSTS,
2002 XGBE_PMA_RX_VAL_SIG_MASK);
2003
2004 /* step 1: Check for RX_VALID && LF_SIGDET */
2005 if ((reg & XGBE_PMA_RX_VAL_SIG_MASK) != XGBE_PMA_RX_VAL_SIG_MASK) {
2006 netif_dbg(pdata, link, pdata->netdev,
2007 "RX_VALID or LF_SIGDET is unset, issue rrc");
2008 xgbe_phy_rrc(pdata);
2009 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {
2010 pdata->rx_adapt_retries = 0;
2011 return;
2012 }
2013 goto rx_adapt_reinit;
2014 }
2015
2016 /* perform rx adaptation */
2017 xgbe_rx_adaptation(pdata);
2018 }
2019
2020 /*
2021 * xgbe_phy_stop_data_path - Stop TX/RX to prevent packet corruption
2022 * @pdata: driver private data
2023 *
2024 * This function stops the data path (TX and RX) to prevent packet
2025 * corruption during critical PHY operations like RX adaptation.
2026 * Must be called before initiating RX adaptation when link goes down.
2027 */
xgbe_phy_stop_data_path(struct xgbe_prv_data * pdata)2028 static void xgbe_phy_stop_data_path(struct xgbe_prv_data *pdata)
2029 {
2030 if (pdata->data_path_stopped)
2031 return;
2032
2033 /* Stop TX/RX to prevent packet corruption during RX adaptation */
2034 pdata->hw_if.disable_tx(pdata);
2035 pdata->hw_if.disable_rx(pdata);
2036 pdata->data_path_stopped = true;
2037
2038 netif_dbg(pdata, link, pdata->netdev,
2039 "stopping data path for RX adaptation\n");
2040 }
2041
2042 /*
2043 * xgbe_phy_start_data_path - Re-enable TX/RX after RX adaptation
2044 * @pdata: driver private data
2045 *
2046 * This function re-enables the data path (TX and RX) after RX adaptation
2047 * has completed successfully. Only called when link is confirmed up.
2048 */
xgbe_phy_start_data_path(struct xgbe_prv_data * pdata)2049 static void xgbe_phy_start_data_path(struct xgbe_prv_data *pdata)
2050 {
2051 if (!pdata->data_path_stopped)
2052 return;
2053
2054 pdata->hw_if.enable_rx(pdata);
2055 pdata->hw_if.enable_tx(pdata);
2056 pdata->data_path_stopped = false;
2057
2058 netif_dbg(pdata, link, pdata->netdev,
2059 "restarting data path after RX adaptation\n");
2060 }
2061
xgbe_phy_rx_reset(struct xgbe_prv_data * pdata)2062 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
2063 {
2064 int reg;
2065
2066 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
2067 XGBE_PCS_PSEQ_STATE_MASK);
2068 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
2069 /* Mailbox command timed out, reset of RX block is required.
2070 * This can be done by asseting the reset bit and wait for
2071 * its compeletion.
2072 */
2073 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2074 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
2075 ndelay(20);
2076 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2077 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
2078 usleep_range(40, 50);
2079 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
2080 }
2081 }
2082
xgbe_phy_pll_ctrl(struct xgbe_prv_data * pdata,bool enable)2083 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
2084 {
2085 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
2086 if (pdata->phy.autoneg != AUTONEG_DISABLE)
2087 return;
2088
2089 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
2090 XGBE_PMA_PLL_CTRL_MASK,
2091 enable ? XGBE_PMA_PLL_CTRL_ENABLE
2092 : XGBE_PMA_PLL_CTRL_DISABLE);
2093
2094 /* Wait for command to complete */
2095 usleep_range(100, 200);
2096 }
2097
xgbe_phy_perform_ratechange(struct xgbe_prv_data * pdata,enum xgbe_mb_cmd cmd,enum xgbe_mb_subcmd sub_cmd)2098 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
2099 enum xgbe_mb_cmd cmd, enum xgbe_mb_subcmd sub_cmd)
2100 {
2101 unsigned int s0 = 0;
2102 unsigned int wait;
2103
2104 /* Disable PLL re-initialization during FW command processing */
2105 xgbe_phy_pll_ctrl(pdata, false);
2106
2107 /* Log if a previous command did not complete */
2108 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2109 netif_dbg(pdata, link, pdata->netdev,
2110 "firmware mailbox not ready for command\n");
2111 xgbe_phy_rx_reset(pdata);
2112 }
2113
2114 /* Construct the command */
2115 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2116 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2117
2118 /* Issue the command */
2119 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2120 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2121 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2122
2123 /* Wait for command to complete */
2124 wait = XGBE_RATECHANGE_COUNT;
2125 while (wait--) {
2126 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2127 goto do_rx_adaptation;
2128
2129 usleep_range(1000, 2000);
2130 }
2131
2132 netif_dbg(pdata, link, pdata->netdev,
2133 "firmware mailbox command did not complete\n");
2134
2135 /* Reset on error */
2136 xgbe_phy_rx_reset(pdata);
2137 goto reenable_pll;
2138
2139 do_rx_adaptation:
2140 if (pdata->en_rx_adap && sub_cmd == XGBE_MB_SUBCMD_RX_ADAP &&
2141 (cmd == XGBE_MB_CMD_SET_10G_KR || cmd == XGBE_MB_CMD_SET_10G_SFI)) {
2142 netif_dbg(pdata, link, pdata->netdev,
2143 "Enabling RX adaptation\n");
2144 pdata->mode_set = true;
2145 xgbe_phy_rx_adaptation(pdata);
2146 /* return from here to avoid enabling PLL ctrl
2147 * during adaptation phase
2148 */
2149 return;
2150 }
2151
2152 reenable_pll:
2153 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
2154 if (cmd != XGBE_MB_CMD_POWER_OFF &&
2155 cmd != XGBE_MB_CMD_RRC)
2156 xgbe_phy_pll_ctrl(pdata, true);
2157 }
2158
xgbe_phy_rrc(struct xgbe_prv_data * pdata)2159 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2160 {
2161 /* Receiver Reset Cycle */
2162 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_RRC, XGBE_MB_SUBCMD_NONE);
2163
2164 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2165 }
2166
xgbe_phy_power_off(struct xgbe_prv_data * pdata)2167 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2168 {
2169 struct xgbe_phy_data *phy_data = pdata->phy_data;
2170
2171 /* Power off */
2172 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_POWER_OFF, XGBE_MB_SUBCMD_NONE);
2173
2174 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2175
2176 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2177 }
2178
enable_rx_adap(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2179 static bool enable_rx_adap(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2180 {
2181 struct xgbe_phy_data *phy_data = pdata->phy_data;
2182 unsigned int ver;
2183
2184 /* Rx-Adaptation is not supported on older platforms(< 0x30H) */
2185 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2186 if (ver < XGBE_MAC_VER_30)
2187 return false;
2188
2189 /* Rx adaptation not yet supported on P100a */
2190 if (ver == XGBE_MAC_VER_33)
2191 return false;
2192
2193 /* Re-driver models 4223 && 4227 do not support Rx-Adaptation */
2194 if (phy_data->redrv &&
2195 (phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4223 ||
2196 phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4227))
2197 return false;
2198
2199 /* 10G KR mode with AN does not support Rx-Adaptation */
2200 if (mode == XGBE_MODE_KR &&
2201 phy_data->port_mode != XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG)
2202 return false;
2203
2204 pdata->en_rx_adap = 1;
2205 return true;
2206 }
2207
xgbe_phy_sfi_mode(struct xgbe_prv_data * pdata)2208 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2209 {
2210 struct xgbe_phy_data *phy_data = pdata->phy_data;
2211
2212 xgbe_phy_set_redrv_mode(pdata);
2213
2214 /* 10G/SFI */
2215 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2216 pdata->en_rx_adap = 0;
2217 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, XGBE_MB_SUBCMD_ACTIVE);
2218 } else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
2219 (enable_rx_adap(pdata, XGBE_MODE_SFI))) {
2220 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2221 XGBE_MB_SUBCMD_RX_ADAP);
2222 } else {
2223 if (phy_data->sfp_cable_len <= 1)
2224 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2225 XGBE_MB_SUBCMD_PASSIVE_1M);
2226 else if (phy_data->sfp_cable_len <= 3)
2227 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2228 XGBE_MB_SUBCMD_PASSIVE_3M);
2229 else
2230 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2231 XGBE_MB_SUBCMD_PASSIVE_OTHER);
2232 }
2233
2234 phy_data->cur_mode = XGBE_MODE_SFI;
2235
2236 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2237 }
2238
xgbe_phy_x_mode(struct xgbe_prv_data * pdata)2239 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2240 {
2241 struct xgbe_phy_data *phy_data = pdata->phy_data;
2242
2243 xgbe_phy_set_redrv_mode(pdata);
2244
2245 /* 1G/X */
2246 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2247
2248 phy_data->cur_mode = XGBE_MODE_X;
2249
2250 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2251 }
2252
xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data * pdata)2253 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2254 {
2255 struct xgbe_phy_data *phy_data = pdata->phy_data;
2256
2257 xgbe_phy_set_redrv_mode(pdata);
2258
2259 /* 1G/SGMII */
2260 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_SGMII);
2261
2262 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2263
2264 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2265 }
2266
xgbe_phy_sgmii_100_mode(struct xgbe_prv_data * pdata)2267 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2268 {
2269 struct xgbe_phy_data *phy_data = pdata->phy_data;
2270
2271 xgbe_phy_set_redrv_mode(pdata);
2272
2273 /* 100M/SGMII */
2274 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_100MBITS);
2275
2276 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2277
2278 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2279 }
2280
xgbe_phy_sgmii_10_mode(struct xgbe_prv_data * pdata)2281 static void xgbe_phy_sgmii_10_mode(struct xgbe_prv_data *pdata)
2282 {
2283 struct xgbe_phy_data *phy_data = pdata->phy_data;
2284
2285 xgbe_phy_set_redrv_mode(pdata);
2286
2287 /* 10M/SGMII */
2288 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_10MBITS);
2289
2290 phy_data->cur_mode = XGBE_MODE_SGMII_10;
2291
2292 netif_dbg(pdata, link, pdata->netdev, "10MbE SGMII mode set\n");
2293 }
2294
xgbe_phy_kr_mode(struct xgbe_prv_data * pdata)2295 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2296 {
2297 struct xgbe_phy_data *phy_data = pdata->phy_data;
2298
2299 xgbe_phy_set_redrv_mode(pdata);
2300
2301 /* 10G/KR */
2302 if (enable_rx_adap(pdata, XGBE_MODE_KR))
2303 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR,
2304 XGBE_MB_SUBCMD_RX_ADAP);
2305 else
2306 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR,
2307 XGBE_MB_SUBCMD_NONE);
2308
2309 phy_data->cur_mode = XGBE_MODE_KR;
2310
2311 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2312 }
2313
xgbe_phy_kx_2500_mode(struct xgbe_prv_data * pdata)2314 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2315 {
2316 unsigned int ver;
2317
2318 struct xgbe_phy_data *phy_data = pdata->phy_data;
2319
2320 xgbe_phy_set_redrv_mode(pdata);
2321
2322 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2323
2324 /*
2325 * P100a uses XGMII mode for 2.5G which requires the 2.5G_KX subcommand.
2326 * Older platforms use GMII mode.
2327 */
2328 if (ver == XGBE_MAC_VER_33)
2329 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G,
2330 XGBE_MB_SUBCMD_2_5G_KX);
2331 else
2332 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G,
2333 XGBE_MB_SUBCMD_NONE);
2334
2335 phy_data->cur_mode = XGBE_MODE_KX_2500;
2336
2337 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2338 }
2339
xgbe_phy_kx_1000_mode(struct xgbe_prv_data * pdata)2340 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2341 {
2342 struct xgbe_phy_data *phy_data = pdata->phy_data;
2343
2344 xgbe_phy_set_redrv_mode(pdata);
2345
2346 /* 1G/KX */
2347 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2348
2349 phy_data->cur_mode = XGBE_MODE_KX_1000;
2350
2351 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2352 }
2353
xgbe_phy_cur_mode(struct xgbe_prv_data * pdata)2354 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2355 {
2356 struct xgbe_phy_data *phy_data = pdata->phy_data;
2357
2358 return phy_data->cur_mode;
2359 }
2360
xgbe_phy_switch_baset_mode(struct xgbe_prv_data * pdata)2361 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2362 {
2363 struct xgbe_phy_data *phy_data = pdata->phy_data;
2364
2365 /* No switching if not 10GBase-T */
2366 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2367 return xgbe_phy_cur_mode(pdata);
2368
2369 switch (xgbe_phy_cur_mode(pdata)) {
2370 case XGBE_MODE_SGMII_10:
2371 case XGBE_MODE_SGMII_100:
2372 case XGBE_MODE_SGMII_1000:
2373 return XGBE_MODE_KR;
2374 case XGBE_MODE_KX_2500:
2375 return XGBE_MODE_SGMII_1000;
2376 case XGBE_MODE_KR:
2377 default:
2378 return XGBE_MODE_KX_2500;
2379 }
2380 }
2381
xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data * pdata)2382 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2383 {
2384 return XGBE_MODE_KX_2500;
2385 }
2386
xgbe_phy_switch_bp_mode(struct xgbe_prv_data * pdata)2387 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2388 {
2389 /* If we are in KR switch to KX, and vice-versa */
2390 switch (xgbe_phy_cur_mode(pdata)) {
2391 case XGBE_MODE_KX_1000:
2392 return XGBE_MODE_KR;
2393 case XGBE_MODE_KR:
2394 default:
2395 return XGBE_MODE_KX_1000;
2396 }
2397 }
2398
xgbe_phy_switch_mode(struct xgbe_prv_data * pdata)2399 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2400 {
2401 struct xgbe_phy_data *phy_data = pdata->phy_data;
2402
2403 switch (phy_data->port_mode) {
2404 case XGBE_PORT_MODE_BACKPLANE:
2405 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2406 return xgbe_phy_switch_bp_mode(pdata);
2407 case XGBE_PORT_MODE_BACKPLANE_2500:
2408 return xgbe_phy_switch_bp_2500_mode(pdata);
2409 case XGBE_PORT_MODE_1000BASE_T:
2410 case XGBE_PORT_MODE_NBASE_T:
2411 case XGBE_PORT_MODE_10GBASE_T:
2412 return xgbe_phy_switch_baset_mode(pdata);
2413 case XGBE_PORT_MODE_1000BASE_X:
2414 case XGBE_PORT_MODE_10GBASE_R:
2415 case XGBE_PORT_MODE_SFP:
2416 /* No switching, so just return current mode */
2417 return xgbe_phy_cur_mode(pdata);
2418 default:
2419 return XGBE_MODE_UNKNOWN;
2420 }
2421 }
2422
xgbe_phy_get_basex_mode(struct xgbe_phy_data * phy_data,int speed)2423 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2424 int speed)
2425 {
2426 switch (speed) {
2427 case SPEED_1000:
2428 return XGBE_MODE_X;
2429 case SPEED_10000:
2430 return XGBE_MODE_KR;
2431 default:
2432 return XGBE_MODE_UNKNOWN;
2433 }
2434 }
2435
xgbe_phy_get_baset_mode(struct xgbe_phy_data * phy_data,int speed)2436 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2437 int speed)
2438 {
2439 switch (speed) {
2440 case SPEED_10:
2441 return XGBE_MODE_SGMII_10;
2442 case SPEED_100:
2443 return XGBE_MODE_SGMII_100;
2444 case SPEED_1000:
2445 return XGBE_MODE_SGMII_1000;
2446 case SPEED_2500:
2447 return XGBE_MODE_KX_2500;
2448 case SPEED_10000:
2449 return XGBE_MODE_KR;
2450 default:
2451 return XGBE_MODE_UNKNOWN;
2452 }
2453 }
2454
xgbe_phy_get_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2455 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2456 int speed)
2457 {
2458 switch (speed) {
2459 case SPEED_10:
2460 return XGBE_MODE_SGMII_10;
2461 case SPEED_100:
2462 return XGBE_MODE_SGMII_100;
2463 case SPEED_1000:
2464 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2465 return XGBE_MODE_SGMII_1000;
2466 else
2467 return XGBE_MODE_X;
2468 case SPEED_10000:
2469 case SPEED_UNKNOWN:
2470 return XGBE_MODE_SFI;
2471 default:
2472 return XGBE_MODE_UNKNOWN;
2473 }
2474 }
2475
xgbe_phy_get_bp_2500_mode(int speed)2476 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2477 {
2478 switch (speed) {
2479 case SPEED_2500:
2480 return XGBE_MODE_KX_2500;
2481 default:
2482 return XGBE_MODE_UNKNOWN;
2483 }
2484 }
2485
xgbe_phy_get_bp_mode(int speed)2486 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2487 {
2488 switch (speed) {
2489 case SPEED_1000:
2490 return XGBE_MODE_KX_1000;
2491 case SPEED_10000:
2492 return XGBE_MODE_KR;
2493 default:
2494 return XGBE_MODE_UNKNOWN;
2495 }
2496 }
2497
xgbe_phy_get_mode(struct xgbe_prv_data * pdata,int speed)2498 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2499 int speed)
2500 {
2501 struct xgbe_phy_data *phy_data = pdata->phy_data;
2502
2503 switch (phy_data->port_mode) {
2504 case XGBE_PORT_MODE_BACKPLANE:
2505 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2506 return xgbe_phy_get_bp_mode(speed);
2507 case XGBE_PORT_MODE_BACKPLANE_2500:
2508 return xgbe_phy_get_bp_2500_mode(speed);
2509 case XGBE_PORT_MODE_1000BASE_T:
2510 case XGBE_PORT_MODE_NBASE_T:
2511 case XGBE_PORT_MODE_10GBASE_T:
2512 return xgbe_phy_get_baset_mode(phy_data, speed);
2513 case XGBE_PORT_MODE_1000BASE_X:
2514 case XGBE_PORT_MODE_10GBASE_R:
2515 return xgbe_phy_get_basex_mode(phy_data, speed);
2516 case XGBE_PORT_MODE_SFP:
2517 return xgbe_phy_get_sfp_mode(phy_data, speed);
2518 default:
2519 return XGBE_MODE_UNKNOWN;
2520 }
2521 }
2522
xgbe_phy_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2523 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2524 {
2525 switch (mode) {
2526 case XGBE_MODE_KX_1000:
2527 xgbe_phy_kx_1000_mode(pdata);
2528 break;
2529 case XGBE_MODE_KX_2500:
2530 xgbe_phy_kx_2500_mode(pdata);
2531 break;
2532 case XGBE_MODE_KR:
2533 xgbe_phy_kr_mode(pdata);
2534 break;
2535 case XGBE_MODE_SGMII_10:
2536 xgbe_phy_sgmii_10_mode(pdata);
2537 break;
2538 case XGBE_MODE_SGMII_100:
2539 xgbe_phy_sgmii_100_mode(pdata);
2540 break;
2541 case XGBE_MODE_SGMII_1000:
2542 xgbe_phy_sgmii_1000_mode(pdata);
2543 break;
2544 case XGBE_MODE_X:
2545 xgbe_phy_x_mode(pdata);
2546 break;
2547 case XGBE_MODE_SFI:
2548 xgbe_phy_sfi_mode(pdata);
2549 break;
2550 default:
2551 break;
2552 }
2553 }
2554
xgbe_phy_check_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode,bool advert)2555 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2556 enum xgbe_mode mode, bool advert)
2557 {
2558 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2559 return advert;
2560 } else {
2561 enum xgbe_mode cur_mode;
2562
2563 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2564 if (cur_mode == mode)
2565 return true;
2566 }
2567
2568 return false;
2569 }
2570
xgbe_phy_use_basex_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2571 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2572 enum xgbe_mode mode)
2573 {
2574 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2575
2576 switch (mode) {
2577 case XGBE_MODE_X:
2578 return xgbe_phy_check_mode(pdata, mode,
2579 XGBE_ADV(lks, 1000baseX_Full));
2580 case XGBE_MODE_KR:
2581 return xgbe_phy_check_mode(pdata, mode,
2582 XGBE_ADV(lks, 10000baseKR_Full));
2583 default:
2584 return false;
2585 }
2586 }
2587
xgbe_phy_use_baset_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2588 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2589 enum xgbe_mode mode)
2590 {
2591 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2592
2593 switch (mode) {
2594 case XGBE_MODE_SGMII_10:
2595 return xgbe_phy_check_mode(pdata, mode,
2596 XGBE_ADV(lks, 10baseT_Full));
2597 case XGBE_MODE_SGMII_100:
2598 return xgbe_phy_check_mode(pdata, mode,
2599 XGBE_ADV(lks, 100baseT_Full));
2600 case XGBE_MODE_SGMII_1000:
2601 return xgbe_phy_check_mode(pdata, mode,
2602 XGBE_ADV(lks, 1000baseT_Full));
2603 case XGBE_MODE_KX_2500:
2604 return xgbe_phy_check_mode(pdata, mode,
2605 XGBE_ADV(lks, 2500baseT_Full));
2606 case XGBE_MODE_KR:
2607 return xgbe_phy_check_mode(pdata, mode,
2608 XGBE_ADV(lks, 10000baseT_Full));
2609 default:
2610 return false;
2611 }
2612 }
2613
xgbe_phy_use_sfp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2614 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2615 enum xgbe_mode mode)
2616 {
2617 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2618 struct xgbe_phy_data *phy_data = pdata->phy_data;
2619
2620 switch (mode) {
2621 case XGBE_MODE_X:
2622 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2623 return false;
2624 return xgbe_phy_check_mode(pdata, mode,
2625 XGBE_ADV(lks, 1000baseX_Full));
2626 case XGBE_MODE_SGMII_10:
2627 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2628 return false;
2629 return xgbe_phy_check_mode(pdata, mode,
2630 XGBE_ADV(lks, 10baseT_Full));
2631 case XGBE_MODE_SGMII_100:
2632 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2633 return false;
2634 return xgbe_phy_check_mode(pdata, mode,
2635 XGBE_ADV(lks, 100baseT_Full));
2636 case XGBE_MODE_SGMII_1000:
2637 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2638 return false;
2639 return xgbe_phy_check_mode(pdata, mode,
2640 XGBE_ADV(lks, 1000baseT_Full));
2641 case XGBE_MODE_SFI:
2642 if (phy_data->sfp_mod_absent)
2643 return true;
2644 return xgbe_phy_check_mode(pdata, mode,
2645 XGBE_ADV(lks, 10000baseSR_Full) ||
2646 XGBE_ADV(lks, 10000baseLR_Full) ||
2647 XGBE_ADV(lks, 10000baseLRM_Full) ||
2648 XGBE_ADV(lks, 10000baseER_Full) ||
2649 XGBE_ADV(lks, 10000baseCR_Full));
2650 default:
2651 return false;
2652 }
2653 }
2654
xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2655 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2656 enum xgbe_mode mode)
2657 {
2658 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2659
2660 switch (mode) {
2661 case XGBE_MODE_KX_2500:
2662 return xgbe_phy_check_mode(pdata, mode,
2663 XGBE_ADV(lks, 2500baseX_Full));
2664 default:
2665 return false;
2666 }
2667 }
2668
xgbe_phy_use_bp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2669 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2670 enum xgbe_mode mode)
2671 {
2672 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2673
2674 switch (mode) {
2675 case XGBE_MODE_KX_1000:
2676 return xgbe_phy_check_mode(pdata, mode,
2677 XGBE_ADV(lks, 1000baseKX_Full));
2678 case XGBE_MODE_KR:
2679 return xgbe_phy_check_mode(pdata, mode,
2680 XGBE_ADV(lks, 10000baseKR_Full));
2681 default:
2682 return false;
2683 }
2684 }
2685
xgbe_phy_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2686 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2687 {
2688 struct xgbe_phy_data *phy_data = pdata->phy_data;
2689
2690 switch (phy_data->port_mode) {
2691 case XGBE_PORT_MODE_BACKPLANE:
2692 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2693 return xgbe_phy_use_bp_mode(pdata, mode);
2694 case XGBE_PORT_MODE_BACKPLANE_2500:
2695 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2696 case XGBE_PORT_MODE_1000BASE_T:
2697 case XGBE_PORT_MODE_NBASE_T:
2698 case XGBE_PORT_MODE_10GBASE_T:
2699 return xgbe_phy_use_baset_mode(pdata, mode);
2700 case XGBE_PORT_MODE_1000BASE_X:
2701 case XGBE_PORT_MODE_10GBASE_R:
2702 return xgbe_phy_use_basex_mode(pdata, mode);
2703 case XGBE_PORT_MODE_SFP:
2704 return xgbe_phy_use_sfp_mode(pdata, mode);
2705 default:
2706 return false;
2707 }
2708 }
2709
xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data * phy_data,int speed)2710 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2711 int speed)
2712 {
2713 switch (speed) {
2714 case SPEED_1000:
2715 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2716 case SPEED_10000:
2717 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2718 default:
2719 return false;
2720 }
2721 }
2722
xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data * pdata,int speed)2723 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data *pdata,
2724 int speed)
2725 {
2726 struct xgbe_phy_data *phy_data = pdata->phy_data;
2727 unsigned int ver;
2728
2729 switch (speed) {
2730 case SPEED_10:
2731 /* Supported in ver 21H and ver >= 30H */
2732 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2733 return (ver == 0x21 || ver >= 0x30);
2734 case SPEED_100:
2735 case SPEED_1000:
2736 return true;
2737 case SPEED_2500:
2738 return ((phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T) ||
2739 (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T));
2740 case SPEED_10000:
2741 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2742 default:
2743 return false;
2744 }
2745 }
2746
xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data * pdata,int speed)2747 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data *pdata,
2748 int speed)
2749 {
2750 struct xgbe_phy_data *phy_data = pdata->phy_data;
2751 unsigned int ver;
2752
2753 switch (speed) {
2754 case SPEED_10:
2755 /* Supported in ver 21H and ver >= 30H */
2756 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2757 return ((ver == 0x21 || ver >= 0x30) &&
2758 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000));
2759 case SPEED_100:
2760 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2761 case SPEED_1000:
2762 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2763 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2764 case SPEED_10000:
2765 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2766 default:
2767 return false;
2768 }
2769 }
2770
xgbe_phy_valid_speed_bp_2500_mode(int speed)2771 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2772 {
2773 switch (speed) {
2774 case SPEED_2500:
2775 return true;
2776 default:
2777 return false;
2778 }
2779 }
2780
xgbe_phy_valid_speed_bp_mode(int speed)2781 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2782 {
2783 switch (speed) {
2784 case SPEED_1000:
2785 case SPEED_10000:
2786 return true;
2787 default:
2788 return false;
2789 }
2790 }
2791
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)2792 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2793 {
2794 struct xgbe_phy_data *phy_data = pdata->phy_data;
2795
2796 switch (phy_data->port_mode) {
2797 case XGBE_PORT_MODE_BACKPLANE:
2798 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2799 return xgbe_phy_valid_speed_bp_mode(speed);
2800 case XGBE_PORT_MODE_BACKPLANE_2500:
2801 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2802 case XGBE_PORT_MODE_1000BASE_T:
2803 case XGBE_PORT_MODE_NBASE_T:
2804 case XGBE_PORT_MODE_10GBASE_T:
2805 return xgbe_phy_valid_speed_baset_mode(pdata, speed);
2806 case XGBE_PORT_MODE_1000BASE_X:
2807 case XGBE_PORT_MODE_10GBASE_R:
2808 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2809 case XGBE_PORT_MODE_SFP:
2810 return xgbe_phy_valid_speed_sfp_mode(pdata, speed);
2811 default:
2812 return false;
2813 }
2814 }
2815
xgbe_phy_link_status(struct xgbe_prv_data * pdata,int * an_restart)2816 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2817 {
2818 struct xgbe_phy_data *phy_data = pdata->phy_data;
2819 int reg, ret;
2820
2821 *an_restart = 0;
2822
2823 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2824 /* Check SFP signals */
2825 xgbe_phy_sfp_detect(pdata);
2826
2827 if (phy_data->sfp_changed) {
2828 *an_restart = 1;
2829 return 0;
2830 }
2831
2832 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
2833 if (pdata->en_rx_adap)
2834 pdata->rx_adapt_done = false;
2835 return 0;
2836 }
2837 }
2838
2839 if (phy_data->phydev) {
2840 /* Check external PHY */
2841 ret = phy_read_status(phy_data->phydev);
2842 if (ret < 0)
2843 return 0;
2844
2845 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2846 !phy_aneg_done(phy_data->phydev))
2847 return 0;
2848
2849 if (!phy_data->phydev->link)
2850 return 0;
2851 }
2852
2853 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2854 if (reg < 0)
2855 return reg;
2856
2857 /* Link status is latched low so that momentary link drops
2858 * can be detected. If link was already down read again
2859 * to get the latest state.
2860 */
2861
2862 if (!pdata->phy.link && !(reg & MDIO_STAT1_LSTATUS)) {
2863 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2864 if (reg < 0)
2865 return reg;
2866 }
2867
2868 if (pdata->en_rx_adap) {
2869 /* if the link is available and adaptation is done,
2870 * declare link up
2871 *
2872 * Note: When link is up and adaptation is done, we can
2873 * safely re-enable the data path if it was stopped
2874 * for adaptation.
2875 */
2876 if ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done) {
2877 xgbe_phy_start_data_path(pdata);
2878 return 1;
2879 }
2880 /* If either link is not available or adaptation is not done,
2881 * retrigger the adaptation logic. (if the mode is not set,
2882 * then issue mailbox command first)
2883 */
2884
2885 /* CRITICAL: Stop data path BEFORE triggering RX adaptation
2886 * to prevent CRC errors from packets corrupted during
2887 * the adaptation process. This is especially important
2888 * when AN is OFF in 10G KR mode.
2889 */
2890 xgbe_phy_stop_data_path(pdata);
2891
2892 if (pdata->mode_set) {
2893 xgbe_phy_rx_adaptation(pdata);
2894 } else {
2895 pdata->rx_adapt_done = false;
2896 xgbe_phy_set_mode(pdata, phy_data->cur_mode);
2897 }
2898
2899 if (pdata->rx_adapt_done) {
2900 /* Adaptation complete, safe to re-enable data path */
2901 xgbe_phy_start_data_path(pdata);
2902 return 1;
2903 }
2904 } else if (reg & MDIO_STAT1_LSTATUS)
2905 return 1;
2906
2907 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2908 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2909 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2910 netif_carrier_off(pdata->netdev);
2911 *an_restart = 1;
2912 }
2913 }
2914
2915 /* No link, attempt a receiver reset cycle */
2916 if (pdata->vdata->enable_rrc && phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2917 phy_data->rrc_count = 0;
2918 xgbe_phy_rrc(pdata);
2919 }
2920
2921 return 0;
2922 }
2923
xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data * pdata)2924 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2925 {
2926 struct xgbe_phy_data *phy_data = pdata->phy_data;
2927
2928 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2929 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2930 GPIO_ADDR);
2931
2932 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2933 GPIO_MASK);
2934
2935 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2936 GPIO_RX_LOS);
2937 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2938 GPIO_TX_FAULT);
2939 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2940 GPIO_MOD_ABS);
2941 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2942 GPIO_RATE_SELECT);
2943
2944 if (netif_msg_probe(pdata)) {
2945 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2946 phy_data->sfp_gpio_address);
2947 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2948 phy_data->sfp_gpio_mask);
2949 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2950 phy_data->sfp_gpio_rx_los);
2951 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2952 phy_data->sfp_gpio_tx_fault);
2953 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2954 phy_data->sfp_gpio_mod_absent);
2955 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2956 phy_data->sfp_gpio_rate_select);
2957 }
2958 }
2959
xgbe_phy_sfp_comm_setup(struct xgbe_prv_data * pdata)2960 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2961 {
2962 struct xgbe_phy_data *phy_data = pdata->phy_data;
2963 unsigned int mux_addr_hi, mux_addr_lo;
2964
2965 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2966 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2967 if (mux_addr_lo == XGBE_SFP_DIRECT)
2968 return;
2969
2970 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2971 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2972 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2973 MUX_CHAN);
2974
2975 if (netif_msg_probe(pdata)) {
2976 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2977 phy_data->sfp_mux_address);
2978 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2979 phy_data->sfp_mux_channel);
2980 }
2981 }
2982
xgbe_phy_sfp_setup(struct xgbe_prv_data * pdata)2983 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2984 {
2985 xgbe_phy_sfp_comm_setup(pdata);
2986 xgbe_phy_sfp_gpio_setup(pdata);
2987 }
2988
xgbe_phy_int_mdio_reset(struct xgbe_prv_data * pdata)2989 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2990 {
2991 struct xgbe_phy_data *phy_data = pdata->phy_data;
2992 int ret;
2993
2994 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2995 if (ret)
2996 return ret;
2997
2998 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2999
3000 return ret;
3001 }
3002
xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data * pdata)3003 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
3004 {
3005 struct xgbe_phy_data *phy_data = pdata->phy_data;
3006 u8 gpio_reg, gpio_ports[2], gpio_data[3];
3007 int ret;
3008
3009 /* Read the output port registers */
3010 gpio_reg = 2;
3011 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
3012 &gpio_reg, sizeof(gpio_reg),
3013 gpio_ports, sizeof(gpio_ports));
3014 if (ret)
3015 return ret;
3016
3017 /* Prepare to write the GPIO data */
3018 gpio_data[0] = 2;
3019 gpio_data[1] = gpio_ports[0];
3020 gpio_data[2] = gpio_ports[1];
3021
3022 /* Set the GPIO pin */
3023 if (phy_data->mdio_reset_gpio < 8)
3024 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
3025 else
3026 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
3027
3028 /* Write the output port registers */
3029 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3030 gpio_data, sizeof(gpio_data));
3031 if (ret)
3032 return ret;
3033
3034 /* Clear the GPIO pin */
3035 if (phy_data->mdio_reset_gpio < 8)
3036 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3037 else
3038 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3039
3040 /* Write the output port registers */
3041 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3042 gpio_data, sizeof(gpio_data));
3043
3044 return ret;
3045 }
3046
xgbe_phy_mdio_reset(struct xgbe_prv_data * pdata)3047 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
3048 {
3049 struct xgbe_phy_data *phy_data = pdata->phy_data;
3050 int ret;
3051
3052 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3053 return 0;
3054
3055 ret = xgbe_phy_get_comm_ownership(pdata);
3056 if (ret)
3057 return ret;
3058
3059 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
3060 ret = xgbe_phy_i2c_mdio_reset(pdata);
3061 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3062 ret = xgbe_phy_int_mdio_reset(pdata);
3063
3064 xgbe_phy_put_comm_ownership(pdata);
3065
3066 return ret;
3067 }
3068
xgbe_phy_redrv_error(struct xgbe_phy_data * phy_data)3069 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
3070 {
3071 if (!phy_data->redrv)
3072 return false;
3073
3074 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
3075 return true;
3076
3077 switch (phy_data->redrv_model) {
3078 case XGBE_PHY_REDRV_MODEL_4223:
3079 if (phy_data->redrv_lane > 3)
3080 return true;
3081 break;
3082 case XGBE_PHY_REDRV_MODEL_4227:
3083 if (phy_data->redrv_lane > 1)
3084 return true;
3085 break;
3086 default:
3087 return true;
3088 }
3089
3090 return false;
3091 }
3092
xgbe_phy_mdio_reset_setup(struct xgbe_prv_data * pdata)3093 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
3094 {
3095 struct xgbe_phy_data *phy_data = pdata->phy_data;
3096
3097 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3098 return 0;
3099
3100 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3101 switch (phy_data->mdio_reset) {
3102 case XGBE_MDIO_RESET_NONE:
3103 case XGBE_MDIO_RESET_I2C_GPIO:
3104 case XGBE_MDIO_RESET_INT_GPIO:
3105 break;
3106 default:
3107 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
3108 phy_data->mdio_reset);
3109 return -EINVAL;
3110 }
3111
3112 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3113 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3114 XP_GET_BITS(pdata->pp3, XP_PROP_3,
3115 MDIO_RESET_I2C_ADDR);
3116 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3117 MDIO_RESET_I2C_GPIO);
3118 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
3119 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3120 MDIO_RESET_INT_GPIO);
3121 }
3122
3123 return 0;
3124 }
3125
xgbe_phy_port_mode_mismatch(struct xgbe_prv_data * pdata)3126 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
3127 {
3128 struct xgbe_phy_data *phy_data = pdata->phy_data;
3129 unsigned int ver;
3130
3131 /* 10 Mbps speed is supported in ver 21H and ver >= 30H */
3132 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
3133 if ((ver < 0x30 && ver != 0x21) && (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10))
3134 return true;
3135
3136 switch (phy_data->port_mode) {
3137 case XGBE_PORT_MODE_BACKPLANE:
3138 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3139 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3140 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3141 return false;
3142 break;
3143 case XGBE_PORT_MODE_BACKPLANE_2500:
3144 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3145 return false;
3146 break;
3147 case XGBE_PORT_MODE_1000BASE_T:
3148 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3149 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3150 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3151 return false;
3152 break;
3153 case XGBE_PORT_MODE_1000BASE_X:
3154 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3155 return false;
3156 break;
3157 case XGBE_PORT_MODE_NBASE_T:
3158 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3159 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3160 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3161 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3162 return false;
3163 break;
3164 case XGBE_PORT_MODE_10GBASE_T:
3165 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3166 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3167 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3168 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) ||
3169 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3170 return false;
3171 break;
3172 case XGBE_PORT_MODE_10GBASE_R:
3173 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3174 return false;
3175 break;
3176 case XGBE_PORT_MODE_SFP:
3177 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3178 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3179 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3180 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3181 return false;
3182 break;
3183 default:
3184 break;
3185 }
3186
3187 return true;
3188 }
3189
xgbe_phy_conn_type_mismatch(struct xgbe_prv_data * pdata)3190 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
3191 {
3192 struct xgbe_phy_data *phy_data = pdata->phy_data;
3193
3194 switch (phy_data->port_mode) {
3195 case XGBE_PORT_MODE_BACKPLANE:
3196 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3197 case XGBE_PORT_MODE_BACKPLANE_2500:
3198 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3199 return false;
3200 break;
3201 case XGBE_PORT_MODE_1000BASE_T:
3202 case XGBE_PORT_MODE_1000BASE_X:
3203 case XGBE_PORT_MODE_NBASE_T:
3204 case XGBE_PORT_MODE_10GBASE_T:
3205 case XGBE_PORT_MODE_10GBASE_R:
3206 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3207 return false;
3208 break;
3209 case XGBE_PORT_MODE_SFP:
3210 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3211 return false;
3212 break;
3213 default:
3214 break;
3215 }
3216
3217 return true;
3218 }
3219
xgbe_phy_port_enabled(struct xgbe_prv_data * pdata)3220 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
3221 {
3222 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3223 return false;
3224 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3225 return false;
3226
3227 return true;
3228 }
3229
xgbe_phy_cdr_track(struct xgbe_prv_data * pdata)3230 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
3231 {
3232 struct xgbe_phy_data *phy_data = pdata->phy_data;
3233
3234 if (!pdata->debugfs_an_cdr_workaround)
3235 return;
3236
3237 if (!phy_data->phy_cdr_notrack)
3238 return;
3239
3240 usleep_range(phy_data->phy_cdr_delay,
3241 phy_data->phy_cdr_delay + 500);
3242
3243 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3244 XGBE_PMA_CDR_TRACK_EN_MASK,
3245 XGBE_PMA_CDR_TRACK_EN_ON);
3246
3247 phy_data->phy_cdr_notrack = 0;
3248 }
3249
xgbe_phy_cdr_notrack(struct xgbe_prv_data * pdata)3250 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
3251 {
3252 struct xgbe_phy_data *phy_data = pdata->phy_data;
3253
3254 if (!pdata->debugfs_an_cdr_workaround)
3255 return;
3256
3257 if (phy_data->phy_cdr_notrack)
3258 return;
3259
3260 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3261 XGBE_PMA_CDR_TRACK_EN_MASK,
3262 XGBE_PMA_CDR_TRACK_EN_OFF);
3263
3264 xgbe_phy_rrc(pdata);
3265
3266 phy_data->phy_cdr_notrack = 1;
3267 }
3268
xgbe_phy_kr_training_post(struct xgbe_prv_data * pdata)3269 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3270 {
3271 if (!pdata->debugfs_an_cdr_track_early)
3272 xgbe_phy_cdr_track(pdata);
3273 }
3274
xgbe_phy_kr_training_pre(struct xgbe_prv_data * pdata)3275 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3276 {
3277 if (pdata->debugfs_an_cdr_track_early)
3278 xgbe_phy_cdr_track(pdata);
3279 }
3280
xgbe_phy_an_post(struct xgbe_prv_data * pdata)3281 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3282 {
3283 struct xgbe_phy_data *phy_data = pdata->phy_data;
3284
3285 switch (pdata->an_mode) {
3286 case XGBE_AN_MODE_CL73:
3287 case XGBE_AN_MODE_CL73_REDRV:
3288 if (phy_data->cur_mode != XGBE_MODE_KR)
3289 break;
3290
3291 xgbe_phy_cdr_track(pdata);
3292
3293 switch (pdata->an_result) {
3294 case XGBE_AN_READY:
3295 case XGBE_AN_COMPLETE:
3296 break;
3297 default:
3298 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3299 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3300 else
3301 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3302 break;
3303 }
3304 break;
3305 default:
3306 break;
3307 }
3308 }
3309
xgbe_phy_an_pre(struct xgbe_prv_data * pdata)3310 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3311 {
3312 struct xgbe_phy_data *phy_data = pdata->phy_data;
3313
3314 switch (pdata->an_mode) {
3315 case XGBE_AN_MODE_CL73:
3316 case XGBE_AN_MODE_CL73_REDRV:
3317 if (phy_data->cur_mode != XGBE_MODE_KR)
3318 break;
3319
3320 xgbe_phy_cdr_notrack(pdata);
3321 break;
3322 default:
3323 break;
3324 }
3325 }
3326
xgbe_phy_stop(struct xgbe_prv_data * pdata)3327 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3328 {
3329 struct xgbe_phy_data *phy_data = pdata->phy_data;
3330
3331 /* If we have an external PHY, free it */
3332 xgbe_phy_free_phy_device(pdata);
3333
3334 /* Reset SFP data */
3335 xgbe_phy_sfp_reset(phy_data);
3336 xgbe_phy_sfp_mod_absent(pdata);
3337
3338 /* Reset CDR support */
3339 xgbe_phy_cdr_track(pdata);
3340
3341 /* Power off the PHY */
3342 xgbe_phy_power_off(pdata);
3343
3344 /* Stop the I2C controller */
3345 pdata->i2c_if.i2c_stop(pdata);
3346 }
3347
xgbe_phy_start(struct xgbe_prv_data * pdata)3348 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3349 {
3350 struct xgbe_phy_data *phy_data = pdata->phy_data;
3351 int ret;
3352
3353 /* Start the I2C controller */
3354 ret = pdata->i2c_if.i2c_start(pdata);
3355 if (ret)
3356 return ret;
3357
3358 /* Set the proper MDIO mode for the re-driver */
3359 if (phy_data->redrv && !phy_data->redrv_if) {
3360 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3361 XGBE_MDIO_MODE_CL22);
3362 if (ret) {
3363 netdev_err(pdata->netdev,
3364 "redriver mdio port not compatible (%u)\n",
3365 phy_data->redrv_addr);
3366 return ret;
3367 }
3368 }
3369
3370 /* Start in highest supported mode */
3371 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3372
3373 /* Reset CDR support */
3374 xgbe_phy_cdr_track(pdata);
3375
3376 /* After starting the I2C controller, we can check for an SFP */
3377 switch (phy_data->port_mode) {
3378 case XGBE_PORT_MODE_SFP:
3379 xgbe_phy_sfp_detect(pdata);
3380 break;
3381 default:
3382 break;
3383 }
3384
3385 /* If we have an external PHY, start it */
3386 ret = xgbe_phy_find_phy_device(pdata);
3387 if (ret)
3388 goto err_i2c;
3389
3390 return 0;
3391
3392 err_i2c:
3393 pdata->i2c_if.i2c_stop(pdata);
3394
3395 return ret;
3396 }
3397
xgbe_phy_reset(struct xgbe_prv_data * pdata)3398 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3399 {
3400 struct xgbe_phy_data *phy_data = pdata->phy_data;
3401 enum xgbe_mode cur_mode;
3402 int ret;
3403
3404 /* Reset by power cycling the PHY */
3405 cur_mode = phy_data->cur_mode;
3406 xgbe_phy_power_off(pdata);
3407 xgbe_phy_set_mode(pdata, cur_mode);
3408
3409 if (!phy_data->phydev)
3410 return 0;
3411
3412 /* Reset the external PHY */
3413 ret = xgbe_phy_mdio_reset(pdata);
3414 if (ret)
3415 return ret;
3416
3417 return phy_init_hw(phy_data->phydev);
3418 }
3419
xgbe_phy_exit(struct xgbe_prv_data * pdata)3420 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3421 {
3422 struct xgbe_phy_data *phy_data = pdata->phy_data;
3423
3424 /* Unregister for driving external PHYs */
3425 mdiobus_unregister(phy_data->mii);
3426 }
3427
xgbe_phy_init(struct xgbe_prv_data * pdata)3428 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3429 {
3430 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3431 struct xgbe_phy_data *phy_data;
3432 struct mii_bus *mii;
3433 int ret;
3434
3435 /* Check if enabled */
3436 if (!xgbe_phy_port_enabled(pdata)) {
3437 dev_info(pdata->dev, "device is not enabled\n");
3438 return -ENODEV;
3439 }
3440
3441 /* Initialize the I2C controller */
3442 ret = pdata->i2c_if.i2c_init(pdata);
3443 if (ret)
3444 return ret;
3445
3446 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3447 if (!phy_data)
3448 return -ENOMEM;
3449 pdata->phy_data = phy_data;
3450
3451 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3452 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3453 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3454 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3455 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3456 if (netif_msg_probe(pdata)) {
3457 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3458 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3459 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3460 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3461 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3462 }
3463
3464 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3465 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3466 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3467 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3468 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3469 if (phy_data->redrv && netif_msg_probe(pdata)) {
3470 dev_dbg(pdata->dev, "redrv present\n");
3471 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3472 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3473 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3474 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3475 }
3476
3477 /* Validate the connection requested */
3478 if (xgbe_phy_conn_type_mismatch(pdata)) {
3479 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3480 phy_data->port_mode, phy_data->conn_type);
3481 return -EINVAL;
3482 }
3483
3484 /* Validate the mode requested */
3485 if (xgbe_phy_port_mode_mismatch(pdata)) {
3486 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3487 phy_data->port_mode, phy_data->port_speeds);
3488 return -EINVAL;
3489 }
3490
3491 /* Check for and validate MDIO reset support */
3492 ret = xgbe_phy_mdio_reset_setup(pdata);
3493 if (ret)
3494 return ret;
3495
3496 /* Validate the re-driver information */
3497 if (xgbe_phy_redrv_error(phy_data)) {
3498 dev_err(pdata->dev, "phy re-driver settings error\n");
3499 return -EINVAL;
3500 }
3501 pdata->kr_redrv = phy_data->redrv;
3502
3503 /* Indicate current mode is unknown */
3504 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3505
3506 /* Initialize supported features */
3507 XGBE_ZERO_SUP(lks);
3508
3509 switch (phy_data->port_mode) {
3510 /* Backplane support */
3511 case XGBE_PORT_MODE_BACKPLANE:
3512 XGBE_SET_SUP(lks, Autoneg);
3513 fallthrough;
3514 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3515 XGBE_SET_SUP(lks, Pause);
3516 XGBE_SET_SUP(lks, Asym_Pause);
3517 XGBE_SET_SUP(lks, Backplane);
3518 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3519 XGBE_SET_SUP(lks, 1000baseKX_Full);
3520 phy_data->start_mode = XGBE_MODE_KX_1000;
3521 }
3522 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3523 XGBE_SET_SUP(lks, 10000baseKR_Full);
3524 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3525 XGBE_SET_SUP(lks, 10000baseR_FEC);
3526 phy_data->start_mode = XGBE_MODE_KR;
3527 }
3528
3529 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3530 break;
3531 case XGBE_PORT_MODE_BACKPLANE_2500:
3532 XGBE_SET_SUP(lks, Pause);
3533 XGBE_SET_SUP(lks, Asym_Pause);
3534 XGBE_SET_SUP(lks, Backplane);
3535 XGBE_SET_SUP(lks, 2500baseX_Full);
3536 phy_data->start_mode = XGBE_MODE_KX_2500;
3537
3538 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3539 break;
3540
3541 /* MDIO 1GBase-T support */
3542 case XGBE_PORT_MODE_1000BASE_T:
3543 XGBE_SET_SUP(lks, Autoneg);
3544 XGBE_SET_SUP(lks, Pause);
3545 XGBE_SET_SUP(lks, Asym_Pause);
3546 XGBE_SET_SUP(lks, TP);
3547 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3548 XGBE_SET_SUP(lks, 10baseT_Full);
3549 phy_data->start_mode = XGBE_MODE_SGMII_10;
3550 }
3551 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3552 XGBE_SET_SUP(lks, 100baseT_Full);
3553 phy_data->start_mode = XGBE_MODE_SGMII_100;
3554 }
3555 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3556 XGBE_SET_SUP(lks, 1000baseT_Full);
3557 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3558 }
3559
3560 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3561 break;
3562
3563 /* MDIO Base-X support */
3564 case XGBE_PORT_MODE_1000BASE_X:
3565 XGBE_SET_SUP(lks, Autoneg);
3566 XGBE_SET_SUP(lks, Pause);
3567 XGBE_SET_SUP(lks, Asym_Pause);
3568 XGBE_SET_SUP(lks, FIBRE);
3569 XGBE_SET_SUP(lks, 1000baseX_Full);
3570 phy_data->start_mode = XGBE_MODE_X;
3571
3572 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3573 break;
3574
3575 /* MDIO NBase-T support */
3576 case XGBE_PORT_MODE_NBASE_T:
3577 XGBE_SET_SUP(lks, Autoneg);
3578 XGBE_SET_SUP(lks, Pause);
3579 XGBE_SET_SUP(lks, Asym_Pause);
3580 XGBE_SET_SUP(lks, TP);
3581 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3582 XGBE_SET_SUP(lks, 10baseT_Full);
3583 phy_data->start_mode = XGBE_MODE_SGMII_10;
3584 }
3585 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3586 XGBE_SET_SUP(lks, 100baseT_Full);
3587 phy_data->start_mode = XGBE_MODE_SGMII_100;
3588 }
3589 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3590 XGBE_SET_SUP(lks, 1000baseT_Full);
3591 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3592 }
3593 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3594 XGBE_SET_SUP(lks, 2500baseT_Full);
3595 phy_data->start_mode = XGBE_MODE_KX_2500;
3596 }
3597
3598 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3599 break;
3600
3601 /* 10GBase-T support */
3602 case XGBE_PORT_MODE_10GBASE_T:
3603 XGBE_SET_SUP(lks, Autoneg);
3604 XGBE_SET_SUP(lks, Pause);
3605 XGBE_SET_SUP(lks, Asym_Pause);
3606 XGBE_SET_SUP(lks, TP);
3607 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3608 XGBE_SET_SUP(lks, 10baseT_Full);
3609 phy_data->start_mode = XGBE_MODE_SGMII_10;
3610 }
3611 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3612 XGBE_SET_SUP(lks, 100baseT_Full);
3613 phy_data->start_mode = XGBE_MODE_SGMII_100;
3614 }
3615 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3616 XGBE_SET_SUP(lks, 1000baseT_Full);
3617 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3618 }
3619 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3620 XGBE_SET_SUP(lks, 2500baseT_Full);
3621 phy_data->start_mode = XGBE_MODE_KX_2500;
3622 }
3623 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3624 XGBE_SET_SUP(lks, 10000baseT_Full);
3625 phy_data->start_mode = XGBE_MODE_KR;
3626 }
3627
3628 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3629 break;
3630
3631 /* 10GBase-R support */
3632 case XGBE_PORT_MODE_10GBASE_R:
3633 XGBE_SET_SUP(lks, Autoneg);
3634 XGBE_SET_SUP(lks, Pause);
3635 XGBE_SET_SUP(lks, Asym_Pause);
3636 XGBE_SET_SUP(lks, FIBRE);
3637 XGBE_SET_SUP(lks, 10000baseSR_Full);
3638 XGBE_SET_SUP(lks, 10000baseLR_Full);
3639 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3640 XGBE_SET_SUP(lks, 10000baseER_Full);
3641 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3642 XGBE_SET_SUP(lks, 10000baseR_FEC);
3643 phy_data->start_mode = XGBE_MODE_SFI;
3644
3645 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3646 break;
3647
3648 /* SFP support */
3649 case XGBE_PORT_MODE_SFP:
3650 XGBE_SET_SUP(lks, Autoneg);
3651 XGBE_SET_SUP(lks, Pause);
3652 XGBE_SET_SUP(lks, Asym_Pause);
3653 XGBE_SET_SUP(lks, TP);
3654 XGBE_SET_SUP(lks, FIBRE);
3655 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)
3656 phy_data->start_mode = XGBE_MODE_SGMII_10;
3657 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3658 phy_data->start_mode = XGBE_MODE_SGMII_100;
3659 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3660 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3661 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3662 phy_data->start_mode = XGBE_MODE_SFI;
3663
3664 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3665
3666 xgbe_phy_sfp_setup(pdata);
3667 break;
3668 default:
3669 return -EINVAL;
3670 }
3671
3672 if (netif_msg_probe(pdata))
3673 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3674 __ETHTOOL_LINK_MODE_MASK_NBITS,
3675 lks->link_modes.supported);
3676
3677 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3678 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3679 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3680 phy_data->phydev_mode);
3681 if (ret) {
3682 dev_err(pdata->dev,
3683 "mdio port/clause not compatible (%d/%u)\n",
3684 phy_data->mdio_addr, phy_data->phydev_mode);
3685 return -EINVAL;
3686 }
3687 }
3688
3689 if (phy_data->redrv && !phy_data->redrv_if) {
3690 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3691 XGBE_MDIO_MODE_CL22);
3692 if (ret) {
3693 dev_err(pdata->dev,
3694 "redriver mdio port not compatible (%u)\n",
3695 phy_data->redrv_addr);
3696 return -EINVAL;
3697 }
3698 }
3699
3700 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3701
3702 /* Register for driving external PHYs */
3703 mii = devm_mdiobus_alloc(pdata->dev);
3704 if (!mii) {
3705 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3706 return -ENOMEM;
3707 }
3708
3709 mii->priv = pdata;
3710 mii->name = "amd-xgbe-mii";
3711 mii->read = xgbe_phy_mii_read_c22;
3712 mii->write = xgbe_phy_mii_write_c22;
3713 mii->read_c45 = xgbe_phy_mii_read_c45;
3714 mii->write_c45 = xgbe_phy_mii_write_c45;
3715 mii->parent = pdata->dev;
3716 mii->phy_mask = ~0;
3717 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3718 ret = mdiobus_register(mii);
3719 if (ret) {
3720 dev_err(pdata->dev, "mdiobus_register failed\n");
3721 return ret;
3722 }
3723 phy_data->mii = mii;
3724
3725 return 0;
3726 }
3727
xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if * phy_if)3728 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3729 {
3730 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3731
3732 phy_impl->init = xgbe_phy_init;
3733 phy_impl->exit = xgbe_phy_exit;
3734
3735 phy_impl->reset = xgbe_phy_reset;
3736 phy_impl->start = xgbe_phy_start;
3737 phy_impl->stop = xgbe_phy_stop;
3738
3739 phy_impl->link_status = xgbe_phy_link_status;
3740
3741 phy_impl->valid_speed = xgbe_phy_valid_speed;
3742
3743 phy_impl->use_mode = xgbe_phy_use_mode;
3744 phy_impl->set_mode = xgbe_phy_set_mode;
3745 phy_impl->get_mode = xgbe_phy_get_mode;
3746 phy_impl->switch_mode = xgbe_phy_switch_mode;
3747 phy_impl->cur_mode = xgbe_phy_cur_mode;
3748
3749 phy_impl->an_mode = xgbe_phy_an_mode;
3750
3751 phy_impl->an_config = xgbe_phy_an_config;
3752
3753 phy_impl->an_advertising = xgbe_phy_an_advertising;
3754
3755 phy_impl->an_outcome = xgbe_phy_an_outcome;
3756
3757 phy_impl->an_pre = xgbe_phy_an_pre;
3758 phy_impl->an_post = xgbe_phy_an_post;
3759
3760 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3761 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3762
3763 phy_impl->module_info = xgbe_phy_module_info;
3764 phy_impl->module_eeprom = xgbe_phy_module_eeprom;
3765 }
3766