1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/kmod.h>
11 #include <linux/mdio.h>
12 #include <linux/phy.h>
13 #include <linux/of.h>
14 #include <linux/bitops.h>
15 #include <linux/jiffies.h>
16
17 #include "xgbe.h"
18 #include "xgbe-common.h"
19
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata,struct ethtool_eeprom * eeprom,u8 * data)20 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
21 struct ethtool_eeprom *eeprom, u8 *data)
22 {
23 if (!pdata->phy_if.phy_impl.module_eeprom)
24 return -ENXIO;
25
26 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
27 }
28
xgbe_phy_module_info(struct xgbe_prv_data * pdata,struct ethtool_modinfo * modinfo)29 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
30 struct ethtool_modinfo *modinfo)
31 {
32 if (!pdata->phy_if.phy_impl.module_info)
33 return -ENXIO;
34
35 return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
36 }
37
xgbe_an37_clear_interrupts(struct xgbe_prv_data * pdata)38 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
39 {
40 int reg;
41
42 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
43 reg &= ~XGBE_AN_CL37_INT_MASK;
44 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
45 }
46
xgbe_an37_disable_interrupts(struct xgbe_prv_data * pdata)47 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
48 {
49 int reg;
50
51 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
52 reg &= ~XGBE_AN_CL37_INT_MASK;
53 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
54
55 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
56 reg &= ~XGBE_PCS_CL37_BP;
57 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
58 }
59
xgbe_an37_enable_interrupts(struct xgbe_prv_data * pdata)60 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
61 {
62 int reg;
63
64 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
65 reg |= XGBE_PCS_CL37_BP;
66 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
67
68 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
69 reg |= XGBE_AN_CL37_INT_MASK;
70 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
71 }
72
xgbe_an73_clear_interrupts(struct xgbe_prv_data * pdata)73 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
74 {
75 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
76 }
77
xgbe_an73_disable_interrupts(struct xgbe_prv_data * pdata)78 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
79 {
80 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
81 }
82
xgbe_an73_enable_interrupts(struct xgbe_prv_data * pdata)83 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
84 {
85 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
86 }
87
xgbe_an_enable_interrupts(struct xgbe_prv_data * pdata)88 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
89 {
90 switch (pdata->an_mode) {
91 case XGBE_AN_MODE_CL73:
92 case XGBE_AN_MODE_CL73_REDRV:
93 xgbe_an73_enable_interrupts(pdata);
94 break;
95 case XGBE_AN_MODE_CL37:
96 case XGBE_AN_MODE_CL37_SGMII:
97 xgbe_an37_enable_interrupts(pdata);
98 break;
99 default:
100 break;
101 }
102 }
103
xgbe_an_clear_interrupts_all(struct xgbe_prv_data * pdata)104 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
105 {
106 xgbe_an73_clear_interrupts(pdata);
107 xgbe_an37_clear_interrupts(pdata);
108 }
109
xgbe_kr_mode(struct xgbe_prv_data * pdata)110 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
111 {
112 /* Set MAC to 10G speed */
113 pdata->hw_if.set_speed(pdata, SPEED_10000);
114
115 /* Call PHY implementation support to complete rate change */
116 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
117 }
118
xgbe_kx_2500_mode(struct xgbe_prv_data * pdata)119 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
120 {
121 /* Set MAC to 2.5G speed */
122 pdata->hw_if.set_speed(pdata, SPEED_2500);
123
124 /* Call PHY implementation support to complete rate change */
125 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
126 }
127
xgbe_kx_1000_mode(struct xgbe_prv_data * pdata)128 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
129 {
130 /* Set MAC to 1G speed */
131 pdata->hw_if.set_speed(pdata, SPEED_1000);
132
133 /* Call PHY implementation support to complete rate change */
134 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
135 }
136
xgbe_sfi_mode(struct xgbe_prv_data * pdata)137 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
138 {
139 /* If a KR re-driver is present, change to KR mode instead */
140 if (pdata->kr_redrv)
141 return xgbe_kr_mode(pdata);
142
143 /* Set MAC to 10G speed */
144 pdata->hw_if.set_speed(pdata, SPEED_10000);
145
146 /* Call PHY implementation support to complete rate change */
147 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
148 }
149
xgbe_x_mode(struct xgbe_prv_data * pdata)150 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
151 {
152 /* Set MAC to 1G speed */
153 pdata->hw_if.set_speed(pdata, SPEED_1000);
154
155 /* Call PHY implementation support to complete rate change */
156 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
157 }
158
xgbe_sgmii_1000_mode(struct xgbe_prv_data * pdata)159 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
160 {
161 /* Set MAC to 1G speed */
162 pdata->hw_if.set_speed(pdata, SPEED_1000);
163
164 /* Call PHY implementation support to complete rate change */
165 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
166 }
167
xgbe_sgmii_10_mode(struct xgbe_prv_data * pdata)168 static void xgbe_sgmii_10_mode(struct xgbe_prv_data *pdata)
169 {
170 /* Set MAC to 10M speed */
171 pdata->hw_if.set_speed(pdata, SPEED_10);
172
173 /* Call PHY implementation support to complete rate change */
174 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_10);
175 }
176
xgbe_sgmii_100_mode(struct xgbe_prv_data * pdata)177 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
178 {
179 /* Set MAC to 1G speed */
180 pdata->hw_if.set_speed(pdata, SPEED_1000);
181
182 /* Call PHY implementation support to complete rate change */
183 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
184 }
185
xgbe_cur_mode(struct xgbe_prv_data * pdata)186 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
187 {
188 return pdata->phy_if.phy_impl.cur_mode(pdata);
189 }
190
xgbe_in_kr_mode(struct xgbe_prv_data * pdata)191 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
192 {
193 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
194 }
195
xgbe_change_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)196 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
197 enum xgbe_mode mode)
198 {
199 switch (mode) {
200 case XGBE_MODE_KX_1000:
201 xgbe_kx_1000_mode(pdata);
202 break;
203 case XGBE_MODE_KX_2500:
204 xgbe_kx_2500_mode(pdata);
205 break;
206 case XGBE_MODE_KR:
207 xgbe_kr_mode(pdata);
208 break;
209 case XGBE_MODE_SGMII_10:
210 xgbe_sgmii_10_mode(pdata);
211 break;
212 case XGBE_MODE_SGMII_100:
213 xgbe_sgmii_100_mode(pdata);
214 break;
215 case XGBE_MODE_SGMII_1000:
216 xgbe_sgmii_1000_mode(pdata);
217 break;
218 case XGBE_MODE_X:
219 xgbe_x_mode(pdata);
220 break;
221 case XGBE_MODE_SFI:
222 xgbe_sfi_mode(pdata);
223 break;
224 case XGBE_MODE_UNKNOWN:
225 break;
226 default:
227 netif_dbg(pdata, link, pdata->netdev,
228 "invalid operation mode requested (%u)\n", mode);
229 }
230 }
231
xgbe_switch_mode(struct xgbe_prv_data * pdata)232 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
233 {
234 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
235 }
236
xgbe_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)237 static bool xgbe_set_mode(struct xgbe_prv_data *pdata,
238 enum xgbe_mode mode)
239 {
240 if (mode == xgbe_cur_mode(pdata))
241 return false;
242
243 xgbe_change_mode(pdata, mode);
244
245 return true;
246 }
247
xgbe_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)248 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
249 enum xgbe_mode mode)
250 {
251 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
252 }
253
xgbe_an37_set(struct xgbe_prv_data * pdata,bool enable,bool restart)254 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
255 bool restart)
256 {
257 unsigned int reg;
258
259 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
260 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
261
262 if (enable)
263 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
264
265 if (restart)
266 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
267
268 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
269
270 if (pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) {
271 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL);
272 if (enable)
273 reg |= XGBE_VEND2_MAC_AUTO_SW;
274 else
275 reg &= ~XGBE_VEND2_MAC_AUTO_SW;
276 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL, reg);
277 }
278 }
279
xgbe_an37_restart(struct xgbe_prv_data * pdata)280 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
281 {
282 xgbe_an37_enable_interrupts(pdata);
283 xgbe_an37_set(pdata, true, true);
284
285 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
286 }
287
xgbe_an37_disable(struct xgbe_prv_data * pdata)288 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
289 {
290 xgbe_an37_set(pdata, false, false);
291 xgbe_an37_disable_interrupts(pdata);
292
293 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
294 }
295
xgbe_an73_set(struct xgbe_prv_data * pdata,bool enable,bool restart)296 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
297 bool restart)
298 {
299 unsigned int reg;
300
301 /* Disable KR training for now */
302 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
303 reg &= ~XGBE_KR_TRAINING_ENABLE;
304 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
305
306 /* Update AN settings */
307 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
308 reg &= ~MDIO_AN_CTRL1_ENABLE;
309
310 if (enable)
311 reg |= MDIO_AN_CTRL1_ENABLE;
312
313 if (restart)
314 reg |= MDIO_AN_CTRL1_RESTART;
315
316 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
317 }
318
xgbe_an73_restart(struct xgbe_prv_data * pdata)319 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
320 {
321 xgbe_an73_enable_interrupts(pdata);
322 xgbe_an73_set(pdata, true, true);
323
324 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
325 }
326
xgbe_an73_disable(struct xgbe_prv_data * pdata)327 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
328 {
329 xgbe_an73_set(pdata, false, false);
330 xgbe_an73_disable_interrupts(pdata);
331
332 pdata->an_start = 0;
333
334 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
335 }
336
xgbe_an_restart(struct xgbe_prv_data * pdata)337 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
338 {
339 if (pdata->phy_if.phy_impl.an_pre)
340 pdata->phy_if.phy_impl.an_pre(pdata);
341
342 switch (pdata->an_mode) {
343 case XGBE_AN_MODE_CL73:
344 case XGBE_AN_MODE_CL73_REDRV:
345 xgbe_an73_restart(pdata);
346 break;
347 case XGBE_AN_MODE_CL37:
348 case XGBE_AN_MODE_CL37_SGMII:
349 xgbe_an37_restart(pdata);
350 break;
351 default:
352 break;
353 }
354 }
355
xgbe_an_disable(struct xgbe_prv_data * pdata)356 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
357 {
358 if (pdata->phy_if.phy_impl.an_post)
359 pdata->phy_if.phy_impl.an_post(pdata);
360
361 switch (pdata->an_mode) {
362 case XGBE_AN_MODE_CL73:
363 case XGBE_AN_MODE_CL73_REDRV:
364 xgbe_an73_disable(pdata);
365 break;
366 case XGBE_AN_MODE_CL37:
367 case XGBE_AN_MODE_CL37_SGMII:
368 xgbe_an37_disable(pdata);
369 break;
370 default:
371 break;
372 }
373 }
374
xgbe_an_disable_all(struct xgbe_prv_data * pdata)375 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
376 {
377 xgbe_an73_disable(pdata);
378 xgbe_an37_disable(pdata);
379 }
380
xgbe_an73_tx_training(struct xgbe_prv_data * pdata,enum xgbe_rx * state)381 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
382 enum xgbe_rx *state)
383 {
384 unsigned int ad_reg, lp_reg, reg;
385
386 *state = XGBE_RX_COMPLETE;
387
388 /* If we're not in KR mode then we're done */
389 if (!xgbe_in_kr_mode(pdata))
390 return XGBE_AN_PAGE_RECEIVED;
391
392 /* Enable/Disable FEC */
393 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
394 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
395
396 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
397 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
398 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
399 reg |= pdata->fec_ability;
400
401 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
402
403 /* Start KR training */
404 if (pdata->phy_if.phy_impl.kr_training_pre)
405 pdata->phy_if.phy_impl.kr_training_pre(pdata);
406
407 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
408 reg |= XGBE_KR_TRAINING_ENABLE;
409 reg |= XGBE_KR_TRAINING_START;
410 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
411 pdata->kr_start_time = jiffies;
412
413 netif_dbg(pdata, link, pdata->netdev,
414 "KR training initiated\n");
415
416 if (pdata->phy_if.phy_impl.kr_training_post)
417 pdata->phy_if.phy_impl.kr_training_post(pdata);
418
419 return XGBE_AN_PAGE_RECEIVED;
420 }
421
xgbe_an73_tx_xnp(struct xgbe_prv_data * pdata,enum xgbe_rx * state)422 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
423 enum xgbe_rx *state)
424 {
425 u16 msg;
426
427 *state = XGBE_RX_XNP;
428
429 msg = XGBE_XNP_MCF_NULL_MESSAGE;
430 msg |= XGBE_XNP_MP_FORMATTED;
431
432 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
433 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
434 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
435
436 return XGBE_AN_PAGE_RECEIVED;
437 }
438
xgbe_an73_rx_bpa(struct xgbe_prv_data * pdata,enum xgbe_rx * state)439 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
440 enum xgbe_rx *state)
441 {
442 unsigned int link_support;
443 unsigned int reg, ad_reg, lp_reg;
444
445 /* Read Base Ability register 2 first */
446 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
447
448 /* Check for a supported mode, otherwise restart in a different one */
449 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
450 if (!(reg & link_support))
451 return XGBE_AN_INCOMPAT_LINK;
452
453 /* Check Extended Next Page support */
454 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
455 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
456
457 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
458 (lp_reg & XGBE_XNP_NP_EXCHANGE))
459 ? xgbe_an73_tx_xnp(pdata, state)
460 : xgbe_an73_tx_training(pdata, state);
461 }
462
xgbe_an73_rx_xnp(struct xgbe_prv_data * pdata,enum xgbe_rx * state)463 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
464 enum xgbe_rx *state)
465 {
466 unsigned int ad_reg, lp_reg;
467
468 /* Check Extended Next Page support */
469 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
470 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
471
472 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
473 (lp_reg & XGBE_XNP_NP_EXCHANGE))
474 ? xgbe_an73_tx_xnp(pdata, state)
475 : xgbe_an73_tx_training(pdata, state);
476 }
477
xgbe_an73_page_received(struct xgbe_prv_data * pdata)478 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
479 {
480 enum xgbe_rx *state;
481 unsigned long an_timeout;
482 enum xgbe_an ret;
483
484 if (!pdata->an_start) {
485 pdata->an_start = jiffies;
486 } else {
487 an_timeout = pdata->an_start +
488 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
489 if (time_after(jiffies, an_timeout)) {
490 /* Auto-negotiation timed out, reset state */
491 pdata->kr_state = XGBE_RX_BPA;
492 pdata->kx_state = XGBE_RX_BPA;
493
494 pdata->an_start = jiffies;
495
496 netif_dbg(pdata, link, pdata->netdev,
497 "CL73 AN timed out, resetting state\n");
498 }
499 }
500
501 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
502 : &pdata->kx_state;
503
504 switch (*state) {
505 case XGBE_RX_BPA:
506 ret = xgbe_an73_rx_bpa(pdata, state);
507 break;
508
509 case XGBE_RX_XNP:
510 ret = xgbe_an73_rx_xnp(pdata, state);
511 break;
512
513 default:
514 ret = XGBE_AN_ERROR;
515 }
516
517 return ret;
518 }
519
xgbe_an73_incompat_link(struct xgbe_prv_data * pdata)520 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
521 {
522 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
523
524 /* Be sure we aren't looping trying to negotiate */
525 if (xgbe_in_kr_mode(pdata)) {
526 pdata->kr_state = XGBE_RX_ERROR;
527
528 if (!XGBE_ADV(lks, 1000baseKX_Full) &&
529 !XGBE_ADV(lks, 2500baseX_Full))
530 return XGBE_AN_NO_LINK;
531
532 if (pdata->kx_state != XGBE_RX_BPA)
533 return XGBE_AN_NO_LINK;
534 } else {
535 pdata->kx_state = XGBE_RX_ERROR;
536
537 if (!XGBE_ADV(lks, 10000baseKR_Full))
538 return XGBE_AN_NO_LINK;
539
540 if (pdata->kr_state != XGBE_RX_BPA)
541 return XGBE_AN_NO_LINK;
542 }
543
544 xgbe_an_disable(pdata);
545
546 xgbe_switch_mode(pdata);
547
548 pdata->an_result = XGBE_AN_READY;
549
550 xgbe_an_restart(pdata);
551
552 return XGBE_AN_INCOMPAT_LINK;
553 }
554
xgbe_an37_isr(struct xgbe_prv_data * pdata)555 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
556 {
557 unsigned int reg;
558
559 /* Disable AN interrupts */
560 xgbe_an37_disable_interrupts(pdata);
561
562 /* Save the interrupt(s) that fired */
563 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
564 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
565 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
566
567 if (pdata->an_int) {
568 /* Clear the interrupt(s) that fired and process them */
569 reg &= ~XGBE_AN_CL37_INT_MASK;
570 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
571
572 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
573 } else {
574 /* Enable AN interrupts */
575 xgbe_an37_enable_interrupts(pdata);
576
577 /* Reissue interrupt if status is not clear */
578 if (pdata->vdata->irq_reissue_support)
579 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
580 }
581 }
582
xgbe_an73_isr(struct xgbe_prv_data * pdata)583 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
584 {
585 /* Disable AN interrupts */
586 xgbe_an73_disable_interrupts(pdata);
587
588 /* Save the interrupt(s) that fired */
589 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
590
591 if (pdata->an_int) {
592 /* Clear the interrupt(s) that fired and process them */
593 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
594
595 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
596 } else {
597 /* Enable AN interrupts */
598 xgbe_an73_enable_interrupts(pdata);
599
600 /* Reissue interrupt if status is not clear */
601 if (pdata->vdata->irq_reissue_support)
602 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
603 }
604 }
605
xgbe_an_isr_bh_work(struct work_struct * work)606 static void xgbe_an_isr_bh_work(struct work_struct *work)
607 {
608 struct xgbe_prv_data *pdata = from_work(pdata, work, an_bh_work);
609
610 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
611
612 switch (pdata->an_mode) {
613 case XGBE_AN_MODE_CL73:
614 case XGBE_AN_MODE_CL73_REDRV:
615 xgbe_an73_isr(pdata);
616 break;
617 case XGBE_AN_MODE_CL37:
618 case XGBE_AN_MODE_CL37_SGMII:
619 xgbe_an37_isr(pdata);
620 break;
621 default:
622 break;
623 }
624 }
625
xgbe_an_isr(int irq,void * data)626 static irqreturn_t xgbe_an_isr(int irq, void *data)
627 {
628 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
629
630 if (pdata->isr_as_bh_work)
631 queue_work(system_bh_wq, &pdata->an_bh_work);
632 else
633 xgbe_an_isr_bh_work(&pdata->an_bh_work);
634
635 return IRQ_HANDLED;
636 }
637
xgbe_an_combined_isr(struct xgbe_prv_data * pdata)638 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
639 {
640 xgbe_an_isr_bh_work(&pdata->an_bh_work);
641
642 return IRQ_HANDLED;
643 }
644
xgbe_an_irq_work(struct work_struct * work)645 static void xgbe_an_irq_work(struct work_struct *work)
646 {
647 struct xgbe_prv_data *pdata = container_of(work,
648 struct xgbe_prv_data,
649 an_irq_work);
650
651 /* Avoid a race between enabling the IRQ and exiting the work by
652 * waiting for the work to finish and then queueing it
653 */
654 flush_work(&pdata->an_work);
655 queue_work(pdata->an_workqueue, &pdata->an_work);
656 }
657
xgbe_state_as_string(enum xgbe_an state)658 static const char *xgbe_state_as_string(enum xgbe_an state)
659 {
660 switch (state) {
661 case XGBE_AN_READY:
662 return "Ready";
663 case XGBE_AN_PAGE_RECEIVED:
664 return "Page-Received";
665 case XGBE_AN_INCOMPAT_LINK:
666 return "Incompatible-Link";
667 case XGBE_AN_COMPLETE:
668 return "Complete";
669 case XGBE_AN_NO_LINK:
670 return "No-Link";
671 case XGBE_AN_ERROR:
672 return "Error";
673 default:
674 return "Undefined";
675 }
676 }
677
xgbe_an37_state_machine(struct xgbe_prv_data * pdata)678 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
679 {
680 enum xgbe_an cur_state = pdata->an_state;
681
682 if (!pdata->an_int)
683 return;
684
685 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
686 pdata->an_state = XGBE_AN_COMPLETE;
687 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
688
689 /* If SGMII is enabled, check the link status */
690 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
691 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
692 pdata->an_state = XGBE_AN_NO_LINK;
693 }
694
695 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
696 xgbe_state_as_string(pdata->an_state));
697
698 cur_state = pdata->an_state;
699
700 switch (pdata->an_state) {
701 case XGBE_AN_READY:
702 break;
703
704 case XGBE_AN_COMPLETE:
705 netif_dbg(pdata, link, pdata->netdev,
706 "Auto negotiation successful\n");
707 break;
708
709 case XGBE_AN_NO_LINK:
710 break;
711
712 default:
713 pdata->an_state = XGBE_AN_ERROR;
714 }
715
716 if (pdata->an_state == XGBE_AN_ERROR) {
717 netdev_err(pdata->netdev,
718 "error during auto-negotiation, state=%u\n",
719 cur_state);
720
721 pdata->an_int = 0;
722 xgbe_an37_clear_interrupts(pdata);
723 }
724
725 if (pdata->an_state >= XGBE_AN_COMPLETE) {
726 pdata->an_result = pdata->an_state;
727 pdata->an_state = XGBE_AN_READY;
728
729 if (pdata->phy_if.phy_impl.an_post)
730 pdata->phy_if.phy_impl.an_post(pdata);
731
732 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
733 xgbe_state_as_string(pdata->an_result));
734 }
735
736 xgbe_an37_enable_interrupts(pdata);
737 }
738
xgbe_an73_state_machine(struct xgbe_prv_data * pdata)739 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
740 {
741 enum xgbe_an cur_state = pdata->an_state;
742
743 if (!pdata->an_int)
744 return;
745
746 next_int:
747 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
748 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
749 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
750 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
751 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
752 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
753 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
754 pdata->an_state = XGBE_AN_COMPLETE;
755 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
756 } else {
757 pdata->an_state = XGBE_AN_ERROR;
758 }
759
760 again:
761 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
762 xgbe_state_as_string(pdata->an_state));
763
764 cur_state = pdata->an_state;
765
766 switch (pdata->an_state) {
767 case XGBE_AN_READY:
768 pdata->an_supported = 0;
769 break;
770
771 case XGBE_AN_PAGE_RECEIVED:
772 pdata->an_state = xgbe_an73_page_received(pdata);
773 pdata->an_supported++;
774 break;
775
776 case XGBE_AN_INCOMPAT_LINK:
777 pdata->an_supported = 0;
778 pdata->parallel_detect = 0;
779 pdata->an_state = xgbe_an73_incompat_link(pdata);
780 break;
781
782 case XGBE_AN_COMPLETE:
783 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
784 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
785 pdata->an_supported ? "Auto negotiation"
786 : "Parallel detection");
787 break;
788
789 case XGBE_AN_NO_LINK:
790 break;
791
792 default:
793 pdata->an_state = XGBE_AN_ERROR;
794 }
795
796 if (pdata->an_state == XGBE_AN_NO_LINK) {
797 pdata->an_int = 0;
798 xgbe_an73_clear_interrupts(pdata);
799 } else if (pdata->an_state == XGBE_AN_ERROR) {
800 netdev_err(pdata->netdev,
801 "error during auto-negotiation, state=%u\n",
802 cur_state);
803
804 pdata->an_int = 0;
805 xgbe_an73_clear_interrupts(pdata);
806 }
807
808 if (pdata->an_state >= XGBE_AN_COMPLETE) {
809 pdata->an_result = pdata->an_state;
810 pdata->an_state = XGBE_AN_READY;
811 pdata->kr_state = XGBE_RX_BPA;
812 pdata->kx_state = XGBE_RX_BPA;
813 pdata->an_start = 0;
814
815 if (pdata->phy_if.phy_impl.an_post)
816 pdata->phy_if.phy_impl.an_post(pdata);
817
818 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
819 xgbe_state_as_string(pdata->an_result));
820 }
821
822 if (cur_state != pdata->an_state)
823 goto again;
824
825 if (pdata->an_int)
826 goto next_int;
827
828 xgbe_an73_enable_interrupts(pdata);
829 }
830
xgbe_an_state_machine(struct work_struct * work)831 static void xgbe_an_state_machine(struct work_struct *work)
832 {
833 struct xgbe_prv_data *pdata = container_of(work,
834 struct xgbe_prv_data,
835 an_work);
836
837 mutex_lock(&pdata->an_mutex);
838
839 switch (pdata->an_mode) {
840 case XGBE_AN_MODE_CL73:
841 case XGBE_AN_MODE_CL73_REDRV:
842 xgbe_an73_state_machine(pdata);
843 break;
844 case XGBE_AN_MODE_CL37:
845 case XGBE_AN_MODE_CL37_SGMII:
846 xgbe_an37_state_machine(pdata);
847 break;
848 default:
849 break;
850 }
851
852 /* Reissue interrupt if status is not clear */
853 if (pdata->vdata->irq_reissue_support)
854 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
855
856 mutex_unlock(&pdata->an_mutex);
857 }
858
xgbe_an37_init(struct xgbe_prv_data * pdata)859 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
860 {
861 struct ethtool_link_ksettings lks;
862 unsigned int reg;
863
864 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
865
866 /* Set up Advertisement register */
867 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
868 if (XGBE_ADV(&lks, Pause))
869 reg |= 0x100;
870 else
871 reg &= ~0x100;
872
873 if (XGBE_ADV(&lks, Asym_Pause))
874 reg |= 0x80;
875 else
876 reg &= ~0x80;
877
878 /* Full duplex, but not half */
879 reg |= XGBE_AN_CL37_FD_MASK;
880 reg &= ~XGBE_AN_CL37_HD_MASK;
881
882 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
883
884 /* Set up the Control register */
885 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
886 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
887 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
888
889 switch (pdata->an_mode) {
890 case XGBE_AN_MODE_CL37:
891 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
892 break;
893 case XGBE_AN_MODE_CL37_SGMII:
894 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
895 break;
896 default:
897 break;
898 }
899
900 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
901
902 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
903
904 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
905 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
906
907 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
908 reg &= ~MDIO_AN_CTRL1_ENABLE;
909 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
910
911 }
912
xgbe_an73_init(struct xgbe_prv_data * pdata)913 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
914 {
915 struct ethtool_link_ksettings lks;
916 unsigned int reg;
917
918 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
919
920 /* Set up Advertisement register 3 first */
921 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
922 if (XGBE_ADV(&lks, 10000baseR_FEC))
923 reg |= 0xc000;
924 else
925 reg &= ~0xc000;
926
927 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
928
929 /* Set up Advertisement register 2 next */
930 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
931 if (XGBE_ADV(&lks, 10000baseKR_Full))
932 reg |= 0x80;
933 else
934 reg &= ~0x80;
935
936 if (XGBE_ADV(&lks, 1000baseKX_Full) ||
937 XGBE_ADV(&lks, 2500baseX_Full))
938 reg |= 0x20;
939 else
940 reg &= ~0x20;
941
942 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
943
944 /* Set up Advertisement register 1 last */
945 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
946 if (XGBE_ADV(&lks, Pause))
947 reg |= 0x400;
948 else
949 reg &= ~0x400;
950
951 if (XGBE_ADV(&lks, Asym_Pause))
952 reg |= 0x800;
953 else
954 reg &= ~0x800;
955
956 /* We don't intend to perform XNP */
957 reg &= ~XGBE_XNP_NP_EXCHANGE;
958
959 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
960
961 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
962 }
963
xgbe_an_init(struct xgbe_prv_data * pdata)964 static void xgbe_an_init(struct xgbe_prv_data *pdata)
965 {
966 /* Set up advertisement registers based on current settings */
967 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
968 switch (pdata->an_mode) {
969 case XGBE_AN_MODE_CL73:
970 case XGBE_AN_MODE_CL73_REDRV:
971 xgbe_an73_init(pdata);
972 break;
973 case XGBE_AN_MODE_CL37:
974 case XGBE_AN_MODE_CL37_SGMII:
975 xgbe_an37_init(pdata);
976 break;
977 default:
978 break;
979 }
980 }
981
xgbe_phy_fc_string(struct xgbe_prv_data * pdata)982 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
983 {
984 if (pdata->tx_pause && pdata->rx_pause)
985 return "rx/tx";
986 else if (pdata->rx_pause)
987 return "rx";
988 else if (pdata->tx_pause)
989 return "tx";
990 else
991 return "off";
992 }
993
xgbe_phy_speed_string(int speed)994 static const char *xgbe_phy_speed_string(int speed)
995 {
996 switch (speed) {
997 case SPEED_10:
998 return "10Mbps";
999 case SPEED_100:
1000 return "100Mbps";
1001 case SPEED_1000:
1002 return "1Gbps";
1003 case SPEED_2500:
1004 return "2.5Gbps";
1005 case SPEED_10000:
1006 return "10Gbps";
1007 case SPEED_UNKNOWN:
1008 return "Unknown";
1009 default:
1010 return "Unsupported";
1011 }
1012 }
1013
xgbe_phy_print_status(struct xgbe_prv_data * pdata)1014 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1015 {
1016 if (pdata->phy.link)
1017 netdev_info(pdata->netdev,
1018 "Link is Up - %s/%s - flow control %s\n",
1019 xgbe_phy_speed_string(pdata->phy.speed),
1020 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1021 xgbe_phy_fc_string(pdata));
1022 else
1023 netdev_info(pdata->netdev, "Link is Down\n");
1024 }
1025
xgbe_phy_adjust_link(struct xgbe_prv_data * pdata)1026 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1027 {
1028 int new_state = 0;
1029
1030 if (pdata->phy.link) {
1031 /* Flow control support */
1032 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1033
1034 if (pdata->tx_pause != pdata->phy.tx_pause) {
1035 new_state = 1;
1036 pdata->tx_pause = pdata->phy.tx_pause;
1037 pdata->hw_if.config_tx_flow_control(pdata);
1038 }
1039
1040 if (pdata->rx_pause != pdata->phy.rx_pause) {
1041 new_state = 1;
1042 pdata->rx_pause = pdata->phy.rx_pause;
1043 pdata->hw_if.config_rx_flow_control(pdata);
1044 }
1045
1046 /* Speed support */
1047 if (pdata->phy_speed != pdata->phy.speed) {
1048 new_state = 1;
1049 pdata->phy_speed = pdata->phy.speed;
1050 }
1051
1052 if (pdata->phy_link != pdata->phy.link) {
1053 new_state = 1;
1054 pdata->phy_link = pdata->phy.link;
1055
1056 /* Link is coming up - wake TX queues */
1057 netif_tx_wake_all_queues(pdata->netdev);
1058 }
1059 } else if (pdata->phy_link) {
1060 new_state = 1;
1061 pdata->phy_link = 0;
1062 pdata->phy_speed = SPEED_UNKNOWN;
1063
1064 /* Proactive TX queue management on link-down.
1065 *
1066 * Immediately stop TX queues to enable clean link-down
1067 * handling:
1068 * - Prevents queueing packets that can't be transmitted
1069 * - Allows orderly descriptor cleanup by NAPI poll
1070 * - Enables rapid failover in link aggregation configurations
1071 *
1072 * Note: We do NOT call netdev_tx_reset_queue() here because
1073 * NAPI poll may still be running and would trigger BQL
1074 * assertion. BQL state is cleaned up naturally during
1075 * descriptor reclamation.
1076 */
1077 netif_tx_stop_all_queues(pdata->netdev);
1078 }
1079
1080 if (new_state && netif_msg_link(pdata))
1081 xgbe_phy_print_status(pdata);
1082 }
1083
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)1084 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1085 {
1086 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1087 }
1088
xgbe_phy_config_fixed(struct xgbe_prv_data * pdata)1089 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1090 {
1091 enum xgbe_mode mode;
1092
1093 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1094
1095 /* Disable auto-negotiation */
1096 xgbe_an_disable(pdata);
1097
1098 /* Set specified mode for specified speed */
1099 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1100 switch (mode) {
1101 case XGBE_MODE_KX_1000:
1102 case XGBE_MODE_KX_2500:
1103 case XGBE_MODE_KR:
1104 case XGBE_MODE_SGMII_10:
1105 case XGBE_MODE_SGMII_100:
1106 case XGBE_MODE_SGMII_1000:
1107 case XGBE_MODE_X:
1108 case XGBE_MODE_SFI:
1109 break;
1110 case XGBE_MODE_UNKNOWN:
1111 default:
1112 return -EINVAL;
1113 }
1114
1115 /* Validate duplex mode */
1116 if (pdata->phy.duplex != DUPLEX_FULL)
1117 return -EINVAL;
1118
1119 /* Force the mode change for SFI in Fixed PHY config.
1120 * Fixed PHY configs needs PLL to be enabled while doing mode set.
1121 * When the SFP module isn't connected during boot, driver assumes
1122 * AN is ON and attempts autonegotiation. However, if the connected
1123 * SFP comes up in Fixed PHY config, the link will not come up as
1124 * PLL isn't enabled while the initial mode set command is issued.
1125 * So, force the mode change for SFI in Fixed PHY configuration to
1126 * fix link issues.
1127 */
1128 if (mode == XGBE_MODE_SFI)
1129 xgbe_change_mode(pdata, mode);
1130 else
1131 xgbe_set_mode(pdata, mode);
1132
1133 return 0;
1134 }
1135
__xgbe_phy_config_aneg(struct xgbe_prv_data * pdata,bool set_mode)1136 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode)
1137 {
1138 int ret;
1139
1140 mutex_lock(&pdata->an_mutex);
1141
1142 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1143 pdata->link_check = jiffies;
1144
1145 ret = pdata->phy_if.phy_impl.an_config(pdata);
1146 if (ret)
1147 goto out;
1148
1149 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1150 ret = xgbe_phy_config_fixed(pdata);
1151 if (ret || !pdata->kr_redrv)
1152 goto out;
1153
1154 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1155 } else {
1156 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1157 }
1158
1159 /* Disable auto-negotiation interrupt */
1160 disable_irq(pdata->an_irq);
1161
1162 if (set_mode) {
1163 /* Start auto-negotiation in a supported mode */
1164 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1165 xgbe_set_mode(pdata, XGBE_MODE_KR);
1166 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1167 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1168 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1169 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1170 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1171 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1172 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1173 xgbe_set_mode(pdata, XGBE_MODE_X);
1174 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1175 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1176 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1177 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1178 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1179 xgbe_set_mode(pdata, XGBE_MODE_SGMII_10);
1180 } else {
1181 enable_irq(pdata->an_irq);
1182 ret = -EINVAL;
1183 goto out;
1184 }
1185 }
1186
1187 /* Disable and stop any in progress auto-negotiation */
1188 xgbe_an_disable_all(pdata);
1189
1190 /* Clear any auto-negotitation interrupts */
1191 xgbe_an_clear_interrupts_all(pdata);
1192
1193 pdata->an_result = XGBE_AN_READY;
1194 pdata->an_state = XGBE_AN_READY;
1195 pdata->kr_state = XGBE_RX_BPA;
1196 pdata->kx_state = XGBE_RX_BPA;
1197
1198 /* Re-enable auto-negotiation interrupt */
1199 enable_irq(pdata->an_irq);
1200
1201 xgbe_an_init(pdata);
1202 xgbe_an_restart(pdata);
1203
1204 out:
1205 if (ret)
1206 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1207 else
1208 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1209
1210 mutex_unlock(&pdata->an_mutex);
1211
1212 return ret;
1213 }
1214
xgbe_phy_config_aneg(struct xgbe_prv_data * pdata)1215 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1216 {
1217 return __xgbe_phy_config_aneg(pdata, true);
1218 }
1219
xgbe_phy_reconfig_aneg(struct xgbe_prv_data * pdata)1220 static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata)
1221 {
1222 return __xgbe_phy_config_aneg(pdata, false);
1223 }
1224
xgbe_phy_aneg_done(struct xgbe_prv_data * pdata)1225 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1226 {
1227 return (pdata->an_result == XGBE_AN_COMPLETE);
1228 }
1229
xgbe_check_link_timeout(struct xgbe_prv_data * pdata)1230 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1231 {
1232 unsigned long link_timeout;
1233 unsigned long kr_time;
1234 int wait;
1235
1236 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1237 if (time_after(jiffies, link_timeout)) {
1238 if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) &&
1239 pdata->phy.autoneg == AUTONEG_ENABLE) {
1240 /* AN restart should not happen while KR training is in progress.
1241 * The while loop ensures no AN restart during KR training,
1242 * waits up to 500ms and AN restart is triggered only if KR
1243 * training is failed.
1244 */
1245 wait = XGBE_KR_TRAINING_WAIT_ITER;
1246 while (wait--) {
1247 kr_time = pdata->kr_start_time +
1248 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
1249 if (time_after(jiffies, kr_time))
1250 break;
1251 /* AN restart is not required, if AN result is COMPLETE */
1252 if (pdata->an_result == XGBE_AN_COMPLETE)
1253 return;
1254 usleep_range(10000, 11000);
1255 }
1256 }
1257 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1258 xgbe_phy_config_aneg(pdata);
1259 }
1260 }
1261
xgbe_phy_status_aneg(struct xgbe_prv_data * pdata)1262 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1263 {
1264 return pdata->phy_if.phy_impl.an_outcome(pdata);
1265 }
1266
xgbe_phy_status_result(struct xgbe_prv_data * pdata)1267 static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1268 {
1269 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1270 enum xgbe_mode mode;
1271
1272 XGBE_ZERO_LP_ADV(lks);
1273
1274 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1275 mode = xgbe_cur_mode(pdata);
1276 else
1277 mode = xgbe_phy_status_aneg(pdata);
1278
1279 switch (mode) {
1280 case XGBE_MODE_SGMII_10:
1281 pdata->phy.speed = SPEED_10;
1282 break;
1283 case XGBE_MODE_SGMII_100:
1284 pdata->phy.speed = SPEED_100;
1285 break;
1286 case XGBE_MODE_X:
1287 case XGBE_MODE_KX_1000:
1288 case XGBE_MODE_SGMII_1000:
1289 pdata->phy.speed = SPEED_1000;
1290 break;
1291 case XGBE_MODE_KX_2500:
1292 pdata->phy.speed = SPEED_2500;
1293 break;
1294 case XGBE_MODE_KR:
1295 case XGBE_MODE_SFI:
1296 pdata->phy.speed = SPEED_10000;
1297 break;
1298 case XGBE_MODE_UNKNOWN:
1299 default:
1300 pdata->phy.speed = SPEED_UNKNOWN;
1301 }
1302
1303 pdata->phy.duplex = DUPLEX_FULL;
1304
1305 if (!xgbe_set_mode(pdata, mode))
1306 return false;
1307
1308 if (pdata->an_again)
1309 xgbe_phy_reconfig_aneg(pdata);
1310
1311 return true;
1312 }
1313
xgbe_phy_status(struct xgbe_prv_data * pdata)1314 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1315 {
1316 unsigned int link_aneg;
1317 int an_restart;
1318
1319 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1320 netif_carrier_off(pdata->netdev);
1321
1322 pdata->phy.link = 0;
1323 goto adjust_link;
1324 }
1325
1326 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1327
1328 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1329 &an_restart);
1330 /* bail out if the link status register read fails */
1331 if (pdata->phy.link < 0)
1332 return;
1333
1334 if (an_restart) {
1335 xgbe_phy_config_aneg(pdata);
1336 goto adjust_link;
1337 }
1338
1339 if (pdata->phy.link) {
1340 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1341 xgbe_check_link_timeout(pdata);
1342 return;
1343 }
1344
1345 if (xgbe_phy_status_result(pdata))
1346 return;
1347
1348 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1349 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1350
1351 netif_carrier_on(pdata->netdev);
1352 } else {
1353 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1354 xgbe_check_link_timeout(pdata);
1355
1356 if (link_aneg)
1357 return;
1358 }
1359
1360 xgbe_phy_status_result(pdata);
1361
1362 netif_carrier_off(pdata->netdev);
1363 }
1364
1365 adjust_link:
1366 xgbe_phy_adjust_link(pdata);
1367 }
1368
xgbe_phy_stop(struct xgbe_prv_data * pdata)1369 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1370 {
1371 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1372
1373 if (!pdata->phy_started)
1374 return;
1375
1376 /* Indicate the PHY is down */
1377 pdata->phy_started = 0;
1378
1379 /* Disable auto-negotiation */
1380 xgbe_an_disable_all(pdata);
1381
1382 if (pdata->dev_irq != pdata->an_irq) {
1383 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1384 cancel_work_sync(&pdata->an_bh_work);
1385 }
1386
1387 pdata->phy_if.phy_impl.stop(pdata);
1388
1389 pdata->phy.link = 0;
1390
1391 xgbe_phy_adjust_link(pdata);
1392 }
1393
xgbe_phy_start(struct xgbe_prv_data * pdata)1394 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1395 {
1396 struct net_device *netdev = pdata->netdev;
1397 int ret;
1398
1399 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1400
1401 ret = pdata->phy_if.phy_impl.start(pdata);
1402 if (ret)
1403 return ret;
1404
1405 /* If we have a separate AN irq, enable it */
1406 if (pdata->dev_irq != pdata->an_irq) {
1407 INIT_WORK(&pdata->an_bh_work, xgbe_an_isr_bh_work);
1408
1409 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1410 xgbe_an_isr, 0, pdata->an_name,
1411 pdata);
1412 if (ret) {
1413 netdev_err(netdev, "phy irq request failed\n");
1414 goto err_stop;
1415 }
1416 }
1417
1418 /* Set initial mode - call the mode setting routines
1419 * directly to insure we are properly configured
1420 */
1421 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1422 xgbe_kr_mode(pdata);
1423 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1424 xgbe_kx_2500_mode(pdata);
1425 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1426 xgbe_kx_1000_mode(pdata);
1427 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1428 xgbe_sfi_mode(pdata);
1429 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1430 xgbe_x_mode(pdata);
1431 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1432 xgbe_sgmii_1000_mode(pdata);
1433 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1434 xgbe_sgmii_100_mode(pdata);
1435 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1436 xgbe_sgmii_10_mode(pdata);
1437 } else {
1438 ret = -EINVAL;
1439 goto err_irq;
1440 }
1441
1442 /* Indicate the PHY is up and running */
1443 pdata->phy_started = 1;
1444
1445 xgbe_an_init(pdata);
1446 xgbe_an_enable_interrupts(pdata);
1447
1448 return xgbe_phy_config_aneg(pdata);
1449
1450 err_irq:
1451 if (pdata->dev_irq != pdata->an_irq)
1452 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1453
1454 err_stop:
1455 pdata->phy_if.phy_impl.stop(pdata);
1456
1457 return ret;
1458 }
1459
xgbe_phy_reset(struct xgbe_prv_data * pdata)1460 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1461 {
1462 int ret;
1463
1464 ret = pdata->phy_if.phy_impl.reset(pdata);
1465 if (ret)
1466 return ret;
1467
1468 /* Disable auto-negotiation for now */
1469 xgbe_an_disable_all(pdata);
1470
1471 /* Clear auto-negotiation interrupts */
1472 xgbe_an_clear_interrupts_all(pdata);
1473
1474 return 0;
1475 }
1476
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)1477 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1478 {
1479 struct device *dev = pdata->dev;
1480
1481 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1482
1483 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1484 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1485 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1486 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1487 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1488 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1489 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1490 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1491 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1492 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1493 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1494 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1495
1496 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1497 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1498 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1499 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1500 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1501 MDIO_AN_ADVERTISE,
1502 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1503 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1504 MDIO_AN_ADVERTISE + 1,
1505 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1506 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1507 MDIO_AN_ADVERTISE + 2,
1508 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1509 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1510 MDIO_AN_COMP_STAT,
1511 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1512
1513 dev_dbg(dev, "\n*************************************************\n");
1514 }
1515
xgbe_phy_best_advertised_speed(struct xgbe_prv_data * pdata)1516 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1517 {
1518 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1519
1520 if (XGBE_ADV(lks, 10000baseKR_Full))
1521 return SPEED_10000;
1522 else if (XGBE_ADV(lks, 10000baseT_Full))
1523 return SPEED_10000;
1524 else if (XGBE_ADV(lks, 2500baseX_Full))
1525 return SPEED_2500;
1526 else if (XGBE_ADV(lks, 2500baseT_Full))
1527 return SPEED_2500;
1528 else if (XGBE_ADV(lks, 1000baseKX_Full))
1529 return SPEED_1000;
1530 else if (XGBE_ADV(lks, 1000baseT_Full))
1531 return SPEED_1000;
1532 else if (XGBE_ADV(lks, 100baseT_Full))
1533 return SPEED_100;
1534 else if (XGBE_ADV(lks, 10baseT_Full))
1535 return SPEED_10;
1536
1537 return SPEED_UNKNOWN;
1538 }
1539
xgbe_phy_exit(struct xgbe_prv_data * pdata)1540 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1541 {
1542 pdata->phy_if.phy_impl.exit(pdata);
1543 }
1544
xgbe_phy_init(struct xgbe_prv_data * pdata)1545 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1546 {
1547 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1548 int ret;
1549
1550 mutex_init(&pdata->an_mutex);
1551 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1552 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1553 pdata->mdio_mmd = MDIO_MMD_PCS;
1554
1555 /* Check for FEC support */
1556 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1557 MDIO_PMA_10GBR_FECABLE);
1558 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1559 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1560
1561 /* Setup the phy (including supported features) */
1562 ret = pdata->phy_if.phy_impl.init(pdata);
1563 if (ret)
1564 return ret;
1565
1566 /* Copy supported link modes to advertising link modes */
1567 XGBE_LM_COPY(lks, advertising, lks, supported);
1568
1569 pdata->phy.address = 0;
1570
1571 if (XGBE_ADV(lks, Autoneg)) {
1572 pdata->phy.autoneg = AUTONEG_ENABLE;
1573 pdata->phy.speed = SPEED_UNKNOWN;
1574 pdata->phy.duplex = DUPLEX_UNKNOWN;
1575 } else {
1576 pdata->phy.autoneg = AUTONEG_DISABLE;
1577 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1578 pdata->phy.duplex = DUPLEX_FULL;
1579 }
1580
1581 pdata->phy_link = 0;
1582 pdata->phy.link = 0;
1583
1584 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1585 pdata->phy.tx_pause = pdata->tx_pause;
1586 pdata->phy.rx_pause = pdata->rx_pause;
1587
1588 /* Fix up Flow Control advertising */
1589 XGBE_CLR_ADV(lks, Pause);
1590 XGBE_CLR_ADV(lks, Asym_Pause);
1591
1592 if (pdata->rx_pause) {
1593 XGBE_SET_ADV(lks, Pause);
1594 XGBE_SET_ADV(lks, Asym_Pause);
1595 }
1596
1597 if (pdata->tx_pause) {
1598 /* Equivalent to XOR of Asym_Pause */
1599 if (XGBE_ADV(lks, Asym_Pause))
1600 XGBE_CLR_ADV(lks, Asym_Pause);
1601 else
1602 XGBE_SET_ADV(lks, Asym_Pause);
1603 }
1604
1605 if (netif_msg_drv(pdata))
1606 xgbe_dump_phy_registers(pdata);
1607
1608 return 0;
1609 }
1610
xgbe_init_function_ptrs_phy(struct xgbe_phy_if * phy_if)1611 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1612 {
1613 phy_if->phy_init = xgbe_phy_init;
1614 phy_if->phy_exit = xgbe_phy_exit;
1615
1616 phy_if->phy_reset = xgbe_phy_reset;
1617 phy_if->phy_start = xgbe_phy_start;
1618 phy_if->phy_stop = xgbe_phy_stop;
1619
1620 phy_if->phy_status = xgbe_phy_status;
1621 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1622
1623 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1624
1625 phy_if->an_isr = xgbe_an_combined_isr;
1626
1627 phy_if->module_info = xgbe_phy_module_info;
1628 phy_if->module_eeprom = xgbe_phy_module_eeprom;
1629 }
1630