1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #ifndef __XGBE_H__
9 #define __XGBE_H__
10
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/workqueue.h>
14 #include <linux/phy.h>
15 #include <linux/if_vlan.h>
16 #include <linux/bitops.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
19 #include <linux/net_tstamp.h>
20 #include <net/dcbnl.h>
21 #include <linux/completion.h>
22 #include <linux/cpumask.h>
23 #include <linux/interrupt.h>
24 #include <linux/dcache.h>
25 #include <linux/ethtool.h>
26 #include <linux/list.h>
27
28 #define XGBE_DRV_NAME "amd-xgbe"
29 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
30
31 /* Descriptor related defines */
32 #define XGBE_TX_DESC_CNT 512
33 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
34 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
35 #define XGBE_RX_DESC_CNT 512
36
37 #define XGBE_TX_DESC_CNT_MIN 64
38 #define XGBE_TX_DESC_CNT_MAX 4096
39 #define XGBE_RX_DESC_CNT_MIN 64
40 #define XGBE_RX_DESC_CNT_MAX 4096
41
42 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
43
44 /* Descriptors required for maximum contiguous TSO/GSO packet */
45 #define XGBE_TX_MAX_SPLIT \
46 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
47
48 /* Maximum possible descriptors needed for an SKB:
49 * - Maximum number of SKB frags
50 * - Maximum descriptors for contiguous TSO/GSO packet
51 * - Possible context descriptor
52 * - Possible TSO header descriptor
53 */
54 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
55
56 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
57 #define XGBE_RX_BUF_ALIGN 64
58 #define XGBE_SKB_ALLOC_SIZE 256
59 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
60
61 #define XGBE_MAX_DMA_CHANNELS 16
62 #define XGBE_MAX_QUEUES 16
63 #define XGBE_PRIORITY_QUEUES 8
64 #define XGBE_DMA_STOP_TIMEOUT 1
65
66 /* DMA cache settings - Outer sharable, write-back, write-allocate */
67 #define XGBE_DMA_OS_ARCR 0x002b2b2b
68 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f
69
70 /* DMA cache settings - System, no caches used */
71 #define XGBE_DMA_SYS_ARCR 0x00303030
72 #define XGBE_DMA_SYS_AWCR 0x30303030
73
74 /* DMA cache settings - PCI device */
75 #define XGBE_DMA_PCI_ARCR 0x000f0f0f
76 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f
77 #define XGBE_DMA_PCI_AWARCR 0x00000f0f
78
79 /* DMA channel interrupt modes */
80 #define XGBE_IRQ_MODE_EDGE 0
81 #define XGBE_IRQ_MODE_LEVEL 1
82
83 #define XGMAC_MIN_PACKET 60
84 #define XGMAC_STD_PACKET_MTU 1500
85 #define XGMAC_MAX_STD_PACKET 1518
86 #define XGMAC_JUMBO_PACKET_MTU 9000
87 #define XGMAC_MAX_JUMBO_PACKET 9018
88 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
89
90 #define XGMAC_PFC_DATA_LEN 46
91 #define XGMAC_PFC_DELAYS 14000
92
93 #define XGMAC_PRIO_QUEUES(_cnt) \
94 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
95
96 /* Common property names */
97 #define XGBE_MAC_ADDR_PROPERTY "mac-address"
98 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
99 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
100 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
101
102 /* Device-tree clock names */
103 #define XGBE_DMA_CLOCK "dma_clk"
104 #define XGBE_PTP_CLOCK "ptp_clk"
105
106 /* ACPI property names */
107 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
108 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
109
110 /* PCI BAR mapping */
111 #define XGBE_XGMAC_BAR 0
112 #define XGBE_XPCS_BAR 1
113 #define XGBE_MAC_PROP_OFFSET 0x1d000
114 #define XGBE_I2C_CTRL_OFFSET 0x1e000
115
116 /* PCI MSI/MSIx support */
117 #define XGBE_MSI_BASE_COUNT 4
118 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1)
119
120 /* PCI clock frequencies */
121 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
122 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
123
124 /* Timestamp support - values based on 50MHz PTP clock
125 * 50MHz => 20 nsec
126 */
127 #define XGBE_TSTAMP_SSINC 20
128 #define XGBE_TSTAMP_SNSINC 0
129
130 /* Driver PMT macros */
131 #define XGMAC_DRIVER_CONTEXT 1
132 #define XGMAC_IOCTL_CONTEXT 2
133
134 #define XGMAC_FIFO_MIN_ALLOC 2048
135 #define XGMAC_FIFO_UNIT 256
136 #define XGMAC_FIFO_ALIGN(_x) \
137 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
138 #define XGMAC_FIFO_FC_OFF 2048
139 #define XGMAC_FIFO_FC_MIN 4096
140
141 #define XGBE_TC_MIN_QUANTUM 10
142
143 /* Helper macro for descriptor handling
144 * Always use XGBE_GET_DESC_DATA to access the descriptor data
145 * since the index is free-running and needs to be and-ed
146 * with the descriptor count value of the ring to index to
147 * the proper descriptor data.
148 */
149 #define XGBE_GET_DESC_DATA(_ring, _idx) \
150 ((_ring)->rdata + \
151 ((_idx) & ((_ring)->rdesc_count - 1)))
152
153 /* Default coalescing parameters */
154 #define XGMAC_INIT_DMA_TX_USECS 1000
155 #define XGMAC_INIT_DMA_TX_FRAMES 25
156
157 #define XGMAC_MAX_DMA_RIWT 0xff
158 #define XGMAC_INIT_DMA_RX_USECS 30
159 #define XGMAC_INIT_DMA_RX_FRAMES 25
160
161 /* Flow control queue count */
162 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
163
164 /* Flow control threshold units */
165 #define XGMAC_FLOW_CONTROL_UNIT 512
166 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \
167 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
168 #define XGMAC_FLOW_CONTROL_VALUE(_x) \
169 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
170 #define XGMAC_FLOW_CONTROL_MAX 33280
171
172 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
173 #define XGBE_MAC_HASH_TABLE_SIZE 8
174
175 /* Receive Side Scaling */
176 #define XGBE_RSS_HASH_KEY_SIZE 40
177 #define XGBE_RSS_MAX_TABLE_SIZE 256
178 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
179 #define XGBE_RSS_HASH_KEY_TYPE 1
180
181 /* Auto-negotiation */
182 #define XGBE_AN_MS_TIMEOUT 500
183 #define XGBE_LINK_TIMEOUT 5
184 #define XGBE_KR_TRAINING_WAIT_ITER 50
185
186 #define XGBE_SGMII_AN_LINK_STATUS BIT(1)
187 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
188 #define XGBE_SGMII_AN_LINK_SPEED_10 0x00
189 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04
190 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
191 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4)
192
193 /* ECC correctable error notification window (seconds) */
194 #define XGBE_ECC_LIMIT 60
195
196 /* MDIO port types */
197 #define XGMAC_MAX_C22_PORT 3
198
199 /* Link mode bit operations */
200 #define XGBE_ZERO_SUP(_ls) \
201 ethtool_link_ksettings_zero_link_mode((_ls), supported)
202
203 #define XGBE_SET_SUP(_ls, _mode) \
204 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode)
205
206 #define XGBE_CLR_SUP(_ls, _mode) \
207 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode)
208
209 #define XGBE_IS_SUP(_ls, _mode) \
210 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode)
211
212 #define XGBE_ZERO_ADV(_ls) \
213 ethtool_link_ksettings_zero_link_mode((_ls), advertising)
214
215 #define XGBE_SET_ADV(_ls, _mode) \
216 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode)
217
218 #define XGBE_CLR_ADV(_ls, _mode) \
219 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode)
220
221 #define XGBE_ADV(_ls, _mode) \
222 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode)
223
224 #define XGBE_ZERO_LP_ADV(_ls) \
225 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising)
226
227 #define XGBE_SET_LP_ADV(_ls, _mode) \
228 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode)
229
230 #define XGBE_CLR_LP_ADV(_ls, _mode) \
231 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode)
232
233 #define XGBE_LP_ADV(_ls, _mode) \
234 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode)
235
236 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \
237 bitmap_copy((_dst)->link_modes._dname, \
238 (_src)->link_modes._sname, \
239 __ETHTOOL_LINK_MODE_MASK_NBITS)
240
241 /* XGBE PCI device id */
242 #define XGBE_RV_PCI_DEVICE_ID 0x15d0
243 #define XGBE_YC_PCI_DEVICE_ID 0x14b5
244 #define XGBE_RN_PCI_DEVICE_ID 0x1630
245
246 /* Generic low and high masks */
247 #define XGBE_GEN_HI_MASK GENMASK(31, 16)
248 #define XGBE_GEN_LO_MASK GENMASK(15, 0)
249
250 struct xgbe_prv_data;
251
252 struct xgbe_packet_data {
253 struct sk_buff *skb;
254
255 unsigned int attributes;
256
257 unsigned int errors;
258
259 unsigned int rdesc_count;
260 unsigned int length;
261
262 unsigned int header_len;
263 unsigned int tcp_header_len;
264 unsigned int tcp_payload_len;
265 unsigned short mss;
266
267 unsigned short vlan_ctag;
268
269 u64 rx_tstamp;
270
271 u32 rss_hash;
272 enum pkt_hash_types rss_hash_type;
273
274 unsigned int tx_packets;
275 unsigned int tx_bytes;
276 };
277
278 /* Common Rx and Tx descriptor mapping */
279 struct xgbe_ring_desc {
280 __le32 desc0;
281 __le32 desc1;
282 __le32 desc2;
283 __le32 desc3;
284 };
285
286 /* Page allocation related values */
287 struct xgbe_page_alloc {
288 struct page *pages;
289 unsigned int pages_len;
290 unsigned int pages_offset;
291
292 dma_addr_t pages_dma;
293 };
294
295 /* Ring entry buffer data */
296 struct xgbe_buffer_data {
297 struct xgbe_page_alloc pa;
298 struct xgbe_page_alloc pa_unmap;
299
300 dma_addr_t dma_base;
301 unsigned long dma_off;
302 unsigned int dma_len;
303 };
304
305 /* Tx-related ring data */
306 struct xgbe_tx_ring_data {
307 unsigned int packets; /* BQL packet count */
308 unsigned int bytes; /* BQL byte count */
309 };
310
311 /* Rx-related ring data */
312 struct xgbe_rx_ring_data {
313 struct xgbe_buffer_data hdr; /* Header locations */
314 struct xgbe_buffer_data buf; /* Payload locations */
315
316 unsigned short hdr_len; /* Length of received header */
317 unsigned short len; /* Length of received packet */
318 };
319
320 /* Structure used to hold information related to the descriptor
321 * and the packet associated with the descriptor (always use
322 * the XGBE_GET_DESC_DATA macro to access this data from the ring)
323 */
324 struct xgbe_ring_data {
325 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
326 dma_addr_t rdesc_dma; /* DMA address of descriptor */
327
328 struct sk_buff *skb; /* Virtual address of SKB */
329 dma_addr_t skb_dma; /* DMA address of SKB data */
330 unsigned int skb_dma_len; /* Length of SKB DMA area */
331
332 struct xgbe_tx_ring_data tx; /* Tx-related data */
333 struct xgbe_rx_ring_data rx; /* Rx-related data */
334
335 unsigned int mapped_as_page;
336
337 /* Incomplete receive save location. If the budget is exhausted
338 * or the last descriptor (last normal descriptor or a following
339 * context descriptor) has not been DMA'd yet the current state
340 * of the receive processing needs to be saved.
341 */
342 unsigned int state_saved;
343 struct {
344 struct sk_buff *skb;
345 unsigned int len;
346 unsigned int error;
347 } state;
348 };
349
350 struct xgbe_ring {
351 /* Ring lock - used just for TX rings at the moment */
352 spinlock_t lock;
353
354 /* Per packet related information */
355 struct xgbe_packet_data packet_data;
356
357 /* Virtual/DMA addresses and count of allocated descriptor memory */
358 struct xgbe_ring_desc *rdesc;
359 dma_addr_t rdesc_dma;
360 unsigned int rdesc_count;
361
362 /* Array of descriptor data corresponding the descriptor memory
363 * (always use the XGBE_GET_DESC_DATA macro to access this data)
364 */
365 struct xgbe_ring_data *rdata;
366
367 /* Page allocation for RX buffers */
368 struct xgbe_page_alloc rx_hdr_pa;
369 struct xgbe_page_alloc rx_buf_pa;
370 int node;
371
372 /* Ring index values
373 * cur - Tx: index of descriptor to be used for current transfer
374 * Rx: index of descriptor to check for packet availability
375 * dirty - Tx: index of descriptor to check for transfer complete
376 * Rx: index of descriptor to check for buffer reallocation
377 */
378 unsigned int cur;
379 unsigned int dirty;
380
381 /* Coalesce frame count used for interrupt bit setting */
382 unsigned int coalesce_count;
383
384 union {
385 struct {
386 unsigned int queue_stopped;
387 unsigned int xmit_more;
388 unsigned short cur_mss;
389 unsigned short cur_vlan_ctag;
390 } tx;
391 };
392 } ____cacheline_aligned;
393
394 /* Structure used to describe the descriptor rings associated with
395 * a DMA channel.
396 */
397 struct xgbe_channel {
398 char name[20];
399
400 /* Address of private data area for device */
401 struct xgbe_prv_data *pdata;
402
403 /* Queue index and base address of queue's DMA registers */
404 unsigned int queue_index;
405 void __iomem *dma_regs;
406
407 /* Per channel interrupt irq number */
408 int dma_irq;
409 char dma_irq_name[IFNAMSIZ + 32];
410
411 /* Netdev related settings */
412 struct napi_struct napi;
413
414 /* Per channel interrupt enablement tracker */
415 unsigned int curr_ier;
416 unsigned int saved_ier;
417
418 unsigned int tx_timer_active;
419 struct timer_list tx_timer;
420
421 struct xgbe_ring *tx_ring;
422 struct xgbe_ring *rx_ring;
423
424 int node;
425 cpumask_t affinity_mask;
426 } ____cacheline_aligned;
427
428 enum xgbe_state {
429 XGBE_DOWN,
430 XGBE_LINK_INIT,
431 XGBE_LINK_ERR,
432 XGBE_STOPPED,
433 };
434
435 enum xgbe_int {
436 XGMAC_INT_DMA_CH_SR_TI,
437 XGMAC_INT_DMA_CH_SR_TPS,
438 XGMAC_INT_DMA_CH_SR_TBU,
439 XGMAC_INT_DMA_CH_SR_RI,
440 XGMAC_INT_DMA_CH_SR_RBU,
441 XGMAC_INT_DMA_CH_SR_RPS,
442 XGMAC_INT_DMA_CH_SR_TI_RI,
443 XGMAC_INT_DMA_CH_SR_FBE,
444 XGMAC_INT_DMA_ALL,
445 };
446
447 enum xgbe_int_state {
448 XGMAC_INT_STATE_SAVE,
449 XGMAC_INT_STATE_RESTORE,
450 };
451
452 enum xgbe_ecc_sec {
453 XGBE_ECC_SEC_TX,
454 XGBE_ECC_SEC_RX,
455 XGBE_ECC_SEC_DESC,
456 };
457
458 enum xgbe_speed {
459 XGBE_SPEED_1000 = 0,
460 XGBE_SPEED_2500,
461 XGBE_SPEED_10000,
462 XGBE_SPEEDS,
463 };
464
465 enum xgbe_xpcs_access {
466 XGBE_XPCS_ACCESS_V1 = 0,
467 XGBE_XPCS_ACCESS_V2,
468 XGBE_XPCS_ACCESS_V3,
469 };
470
471 enum xgbe_an_mode {
472 XGBE_AN_MODE_CL73 = 0,
473 XGBE_AN_MODE_CL73_REDRV,
474 XGBE_AN_MODE_CL37,
475 XGBE_AN_MODE_CL37_SGMII,
476 XGBE_AN_MODE_NONE,
477 };
478
479 enum xgbe_an {
480 XGBE_AN_READY = 0,
481 XGBE_AN_PAGE_RECEIVED,
482 XGBE_AN_INCOMPAT_LINK,
483 XGBE_AN_COMPLETE,
484 XGBE_AN_NO_LINK,
485 XGBE_AN_ERROR,
486 };
487
488 enum xgbe_rx {
489 XGBE_RX_BPA = 0,
490 XGBE_RX_XNP,
491 XGBE_RX_COMPLETE,
492 XGBE_RX_ERROR,
493 };
494
495 enum xgbe_mode {
496 XGBE_MODE_KX_1000 = 0,
497 XGBE_MODE_KX_2500,
498 XGBE_MODE_KR,
499 XGBE_MODE_X,
500 XGBE_MODE_SGMII_10,
501 XGBE_MODE_SGMII_100,
502 XGBE_MODE_SGMII_1000,
503 XGBE_MODE_SFI,
504 XGBE_MODE_UNKNOWN,
505 };
506
507 enum xgbe_speedset {
508 XGBE_SPEEDSET_1000_10000 = 0,
509 XGBE_SPEEDSET_2500_10000,
510 };
511
512 enum xgbe_mdio_mode {
513 XGBE_MDIO_MODE_NONE = 0,
514 XGBE_MDIO_MODE_CL22,
515 XGBE_MDIO_MODE_CL45,
516 };
517
518 enum xgbe_mb_cmd {
519 XGBE_MB_CMD_POWER_OFF = 0,
520 XGBE_MB_CMD_SET_1G,
521 XGBE_MB_CMD_SET_2_5G,
522 XGBE_MB_CMD_SET_10G_SFI,
523 XGBE_MB_CMD_SET_10G_KR,
524 XGBE_MB_CMD_RRC
525 };
526
527 enum xgbe_mb_subcmd {
528 XGBE_MB_SUBCMD_NONE = 0,
529 XGBE_MB_SUBCMD_RX_ADAP,
530
531 /* 10GbE SFP subcommands */
532 XGBE_MB_SUBCMD_ACTIVE = 0,
533 XGBE_MB_SUBCMD_PASSIVE_1M,
534 XGBE_MB_SUBCMD_PASSIVE_3M,
535 XGBE_MB_SUBCMD_PASSIVE_OTHER,
536
537 /* 1GbE Mode subcommands */
538 XGBE_MB_SUBCMD_10MBITS = 0,
539 XGBE_MB_SUBCMD_100MBITS,
540 XGBE_MB_SUBCMD_1G_SGMII,
541 XGBE_MB_SUBCMD_1G_KX
542 };
543
544 struct xgbe_phy {
545 struct ethtool_link_ksettings lks;
546
547 int address;
548
549 int autoneg;
550 int speed;
551 int duplex;
552
553 int link;
554
555 int pause_autoneg;
556 int tx_pause;
557 int rx_pause;
558 };
559
560 enum xgbe_i2c_cmd {
561 XGBE_I2C_CMD_READ = 0,
562 XGBE_I2C_CMD_WRITE,
563 };
564
565 struct xgbe_i2c_op {
566 enum xgbe_i2c_cmd cmd;
567
568 unsigned int target;
569
570 void *buf;
571 unsigned int len;
572 };
573
574 struct xgbe_i2c_op_state {
575 struct xgbe_i2c_op *op;
576
577 unsigned int tx_len;
578 unsigned char *tx_buf;
579
580 unsigned int rx_len;
581 unsigned char *rx_buf;
582
583 unsigned int tx_abort_source;
584
585 int ret;
586 };
587
588 struct xgbe_i2c {
589 unsigned int started;
590 unsigned int max_speed_mode;
591 unsigned int rx_fifo_size;
592 unsigned int tx_fifo_size;
593
594 struct xgbe_i2c_op_state op_state;
595 };
596
597 struct xgbe_mmc_stats {
598 /* Tx Stats */
599 u64 txoctetcount_gb;
600 u64 txframecount_gb;
601 u64 txbroadcastframes_g;
602 u64 txmulticastframes_g;
603 u64 tx64octets_gb;
604 u64 tx65to127octets_gb;
605 u64 tx128to255octets_gb;
606 u64 tx256to511octets_gb;
607 u64 tx512to1023octets_gb;
608 u64 tx1024tomaxoctets_gb;
609 u64 txunicastframes_gb;
610 u64 txmulticastframes_gb;
611 u64 txbroadcastframes_gb;
612 u64 txunderflowerror;
613 u64 txoctetcount_g;
614 u64 txframecount_g;
615 u64 txpauseframes;
616 u64 txvlanframes_g;
617
618 /* Rx Stats */
619 u64 rxframecount_gb;
620 u64 rxoctetcount_gb;
621 u64 rxoctetcount_g;
622 u64 rxbroadcastframes_g;
623 u64 rxmulticastframes_g;
624 u64 rxcrcerror;
625 u64 rxrunterror;
626 u64 rxjabbererror;
627 u64 rxundersize_g;
628 u64 rxoversize_g;
629 u64 rx64octets_gb;
630 u64 rx65to127octets_gb;
631 u64 rx128to255octets_gb;
632 u64 rx256to511octets_gb;
633 u64 rx512to1023octets_gb;
634 u64 rx1024tomaxoctets_gb;
635 u64 rxunicastframes_g;
636 u64 rxlengtherror;
637 u64 rxoutofrangetype;
638 u64 rxpauseframes;
639 u64 rxfifooverflow;
640 u64 rxvlanframes_gb;
641 u64 rxwatchdogerror;
642 };
643
644 struct xgbe_ext_stats {
645 u64 tx_tso_packets;
646 u64 rx_split_header_packets;
647 u64 rx_buffer_unavailable;
648
649 u64 txq_packets[XGBE_MAX_DMA_CHANNELS];
650 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS];
651 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS];
652 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS];
653
654 u64 tx_vxlan_packets;
655 u64 rx_vxlan_packets;
656 u64 rx_csum_errors;
657 u64 rx_vxlan_csum_errors;
658 };
659
660 struct xgbe_hw_if {
661 int (*tx_complete)(struct xgbe_ring_desc *);
662
663 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr);
664 int (*config_rx_mode)(struct xgbe_prv_data *);
665
666 int (*enable_rx_csum)(struct xgbe_prv_data *);
667 int (*disable_rx_csum)(struct xgbe_prv_data *);
668
669 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
670 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
671 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
672 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
673 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
674
675 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
676 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
677 int (*set_speed)(struct xgbe_prv_data *, int);
678
679 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
680 enum xgbe_mdio_mode);
681 int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int);
682 int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16);
683 int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int);
684 int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int,
685 u16);
686
687 int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
688 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
689
690 void (*enable_tx)(struct xgbe_prv_data *);
691 void (*disable_tx)(struct xgbe_prv_data *);
692 void (*enable_rx)(struct xgbe_prv_data *);
693 void (*disable_rx)(struct xgbe_prv_data *);
694
695 void (*powerup_tx)(struct xgbe_prv_data *);
696 void (*powerdown_tx)(struct xgbe_prv_data *);
697 void (*powerup_rx)(struct xgbe_prv_data *);
698 void (*powerdown_rx)(struct xgbe_prv_data *);
699
700 int (*init)(struct xgbe_prv_data *);
701 int (*exit)(struct xgbe_prv_data *);
702
703 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
704 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
705 void (*dev_xmit)(struct xgbe_channel *);
706 int (*dev_read)(struct xgbe_channel *);
707 void (*tx_desc_init)(struct xgbe_channel *);
708 void (*rx_desc_init)(struct xgbe_channel *);
709 void (*tx_desc_reset)(struct xgbe_ring_data *);
710 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
711 unsigned int);
712 int (*is_last_desc)(struct xgbe_ring_desc *);
713 int (*is_context_desc)(struct xgbe_ring_desc *);
714 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
715
716 /* For FLOW ctrl */
717 int (*config_tx_flow_control)(struct xgbe_prv_data *);
718 int (*config_rx_flow_control)(struct xgbe_prv_data *);
719
720 /* For RX coalescing */
721 int (*config_rx_coalesce)(struct xgbe_prv_data *);
722 int (*config_tx_coalesce)(struct xgbe_prv_data *);
723 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
724 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
725
726 /* For RX and TX threshold config */
727 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
728 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
729
730 /* For RX and TX Store and Forward Mode config */
731 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
732 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
733
734 /* For TX DMA Operate on Second Frame config */
735 int (*config_osp_mode)(struct xgbe_prv_data *);
736
737 /* For MMC statistics */
738 void (*rx_mmc_int)(struct xgbe_prv_data *);
739 void (*tx_mmc_int)(struct xgbe_prv_data *);
740 void (*read_mmc_stats)(struct xgbe_prv_data *);
741
742 /* For Timestamp config */
743 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
744 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
745 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
746 unsigned int nsec);
747 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
748 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
749
750 /* For Data Center Bridging config */
751 void (*config_tc)(struct xgbe_prv_data *);
752 void (*config_dcb_tc)(struct xgbe_prv_data *);
753 void (*config_dcb_pfc)(struct xgbe_prv_data *);
754
755 /* For Receive Side Scaling */
756 int (*enable_rss)(struct xgbe_prv_data *);
757 int (*disable_rss)(struct xgbe_prv_data *);
758 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
759 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
760
761 /* For ECC */
762 void (*disable_ecc_ded)(struct xgbe_prv_data *);
763 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
764
765 /* For VXLAN */
766 void (*enable_vxlan)(struct xgbe_prv_data *);
767 void (*disable_vxlan)(struct xgbe_prv_data *);
768 void (*set_vxlan_id)(struct xgbe_prv_data *);
769
770 /* For Split Header */
771 void (*enable_sph)(struct xgbe_prv_data *pdata);
772 void (*disable_sph)(struct xgbe_prv_data *pdata);
773 };
774
775 /* This structure represents implementation specific routines for an
776 * implementation of a PHY. All routines are required unless noted below.
777 * Optional routines:
778 * an_pre, an_post
779 * kr_training_pre, kr_training_post
780 * module_info, module_eeprom
781 */
782 struct xgbe_phy_impl_if {
783 /* Perform Setup/teardown actions */
784 int (*init)(struct xgbe_prv_data *);
785 void (*exit)(struct xgbe_prv_data *);
786
787 /* Perform start/stop specific actions */
788 int (*reset)(struct xgbe_prv_data *);
789 int (*start)(struct xgbe_prv_data *);
790 void (*stop)(struct xgbe_prv_data *);
791
792 /* Return the link status */
793 int (*link_status)(struct xgbe_prv_data *, int *);
794
795 /* Indicate if a particular speed is valid */
796 bool (*valid_speed)(struct xgbe_prv_data *, int);
797
798 /* Check if the specified mode can/should be used */
799 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
800 /* Switch the PHY into various modes */
801 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
802 /* Retrieve mode needed for a specific speed */
803 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
804 /* Retrieve new/next mode when trying to auto-negotiate */
805 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
806 /* Retrieve current mode */
807 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
808
809 /* Retrieve current auto-negotiation mode */
810 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
811
812 /* Configure auto-negotiation settings */
813 int (*an_config)(struct xgbe_prv_data *);
814
815 /* Set/override auto-negotiation advertisement settings */
816 void (*an_advertising)(struct xgbe_prv_data *,
817 struct ethtool_link_ksettings *);
818
819 /* Process results of auto-negotiation */
820 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
821
822 /* Pre/Post auto-negotiation support */
823 void (*an_pre)(struct xgbe_prv_data *);
824 void (*an_post)(struct xgbe_prv_data *);
825
826 /* Pre/Post KR training enablement support */
827 void (*kr_training_pre)(struct xgbe_prv_data *);
828 void (*kr_training_post)(struct xgbe_prv_data *);
829
830 /* SFP module related info */
831 int (*module_info)(struct xgbe_prv_data *pdata,
832 struct ethtool_modinfo *modinfo);
833 int (*module_eeprom)(struct xgbe_prv_data *pdata,
834 struct ethtool_eeprom *eeprom, u8 *data);
835 };
836
837 struct xgbe_phy_if {
838 /* For PHY setup/teardown */
839 int (*phy_init)(struct xgbe_prv_data *);
840 void (*phy_exit)(struct xgbe_prv_data *);
841
842 /* For PHY support when setting device up/down */
843 int (*phy_reset)(struct xgbe_prv_data *);
844 int (*phy_start)(struct xgbe_prv_data *);
845 void (*phy_stop)(struct xgbe_prv_data *);
846
847 /* For PHY support while device is up */
848 void (*phy_status)(struct xgbe_prv_data *);
849 int (*phy_config_aneg)(struct xgbe_prv_data *);
850
851 /* For PHY settings validation */
852 bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
853
854 /* For single interrupt support */
855 irqreturn_t (*an_isr)(struct xgbe_prv_data *);
856
857 /* For ethtool PHY support */
858 int (*module_info)(struct xgbe_prv_data *pdata,
859 struct ethtool_modinfo *modinfo);
860 int (*module_eeprom)(struct xgbe_prv_data *pdata,
861 struct ethtool_eeprom *eeprom, u8 *data);
862
863 /* PHY implementation specific services */
864 struct xgbe_phy_impl_if phy_impl;
865 };
866
867 struct xgbe_i2c_if {
868 /* For initial I2C setup */
869 int (*i2c_init)(struct xgbe_prv_data *);
870
871 /* For I2C support when setting device up/down */
872 int (*i2c_start)(struct xgbe_prv_data *);
873 void (*i2c_stop)(struct xgbe_prv_data *);
874
875 /* For performing I2C operations */
876 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
877
878 /* For single interrupt support */
879 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *);
880 };
881
882 struct xgbe_desc_if {
883 int (*alloc_ring_resources)(struct xgbe_prv_data *);
884 void (*free_ring_resources)(struct xgbe_prv_data *);
885 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
886 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
887 struct xgbe_ring_data *);
888 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
889 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
890 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
891 };
892
893 /* This structure contains flags that indicate what hardware features
894 * or configurations are present in the device.
895 */
896 struct xgbe_hw_features {
897 /* HW Version */
898 unsigned int version;
899
900 /* HW Feature Register0 */
901 unsigned int gmii; /* 1000 Mbps support */
902 unsigned int vlhash; /* VLAN Hash Filter */
903 unsigned int sma; /* SMA(MDIO) Interface */
904 unsigned int rwk; /* PMT remote wake-up packet */
905 unsigned int mgk; /* PMT magic packet */
906 unsigned int mmc; /* RMON module */
907 unsigned int aoe; /* ARP Offload */
908 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
909 unsigned int eee; /* Energy Efficient Ethernet */
910 unsigned int tx_coe; /* Tx Checksum Offload */
911 unsigned int rx_coe; /* Rx Checksum Offload */
912 unsigned int addn_mac; /* Additional MAC Addresses */
913 unsigned int ts_src; /* Timestamp Source */
914 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
915 unsigned int vxn; /* VXLAN/NVGRE */
916
917 /* HW Feature Register1 */
918 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
919 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
920 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
921 unsigned int dma_width; /* DMA width */
922 unsigned int dcb; /* DCB Feature */
923 unsigned int sph; /* Split Header Feature */
924 unsigned int tso; /* TCP Segmentation Offload */
925 unsigned int dma_debug; /* DMA Debug Registers */
926 unsigned int rss; /* Receive Side Scaling */
927 unsigned int tc_cnt; /* Number of Traffic Classes */
928 unsigned int hash_table_size; /* Hash Table Size */
929 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
930
931 /* HW Feature Register2 */
932 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
933 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
934 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
935 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
936 unsigned int pps_out_num; /* Number of PPS outputs */
937 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
938 };
939
940 struct xgbe_version_data {
941 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
942 enum xgbe_xpcs_access xpcs_access;
943 unsigned int mmc_64bit;
944 unsigned int tx_max_fifo_size;
945 unsigned int rx_max_fifo_size;
946 unsigned int tx_tstamp_workaround;
947 unsigned int ecc_support;
948 unsigned int i2c_support;
949 unsigned int irq_reissue_support;
950 unsigned int tx_desc_prefetch;
951 unsigned int rx_desc_prefetch;
952 unsigned int an_cdr_workaround;
953 unsigned int enable_rrc;
954 };
955
956 struct xgbe_prv_data {
957 struct net_device *netdev;
958 struct pci_dev *pcidev;
959 struct platform_device *platdev;
960 struct acpi_device *adev;
961 struct device *dev;
962 struct platform_device *phy_platdev;
963 struct device *phy_dev;
964 unsigned int smn_base;
965
966 /* Version related data */
967 struct xgbe_version_data *vdata;
968
969 /* ACPI or DT flag */
970 unsigned int use_acpi;
971
972 /* XGMAC/XPCS related mmio registers */
973 void __iomem *xgmac_regs; /* XGMAC CSRs */
974 void __iomem *xpcs_regs; /* XPCS MMD registers */
975 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
976 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
977 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
978 void __iomem *xprop_regs; /* XGBE property registers */
979 void __iomem *xi2c_regs; /* XGBE I2C CSRs */
980
981 /* Port property registers */
982 unsigned int pp0;
983 unsigned int pp1;
984 unsigned int pp2;
985 unsigned int pp3;
986 unsigned int pp4;
987
988 /* Overall device lock */
989 spinlock_t lock;
990
991 /* XPCS indirect addressing lock */
992 spinlock_t xpcs_lock;
993 unsigned int xpcs_window_def_reg;
994 unsigned int xpcs_window_sel_reg;
995 unsigned int xpcs_window;
996 unsigned int xpcs_window_size;
997 unsigned int xpcs_window_mask;
998
999 /* RSS addressing mutex */
1000 struct mutex rss_mutex;
1001
1002 /* Flags representing xgbe_state */
1003 unsigned long dev_state;
1004
1005 /* ECC support */
1006 unsigned long tx_sec_period;
1007 unsigned long tx_ded_period;
1008 unsigned long rx_sec_period;
1009 unsigned long rx_ded_period;
1010 unsigned long desc_sec_period;
1011 unsigned long desc_ded_period;
1012
1013 unsigned int tx_sec_count;
1014 unsigned int tx_ded_count;
1015 unsigned int rx_sec_count;
1016 unsigned int rx_ded_count;
1017 unsigned int desc_ded_count;
1018 unsigned int desc_sec_count;
1019
1020 int dev_irq;
1021 int ecc_irq;
1022 int i2c_irq;
1023 int channel_irq[XGBE_MAX_DMA_CHANNELS];
1024
1025 unsigned int per_channel_irq;
1026 unsigned int irq_count;
1027 unsigned int channel_irq_count;
1028 unsigned int channel_irq_mode;
1029
1030 char ecc_name[IFNAMSIZ + 32];
1031
1032 struct xgbe_hw_if hw_if;
1033 struct xgbe_phy_if phy_if;
1034 struct xgbe_desc_if desc_if;
1035 struct xgbe_i2c_if i2c_if;
1036
1037 /* AXI DMA settings */
1038 unsigned int coherent;
1039 unsigned int arcr;
1040 unsigned int awcr;
1041 unsigned int awarcr;
1042
1043 /* Service routine support */
1044 struct workqueue_struct *dev_workqueue;
1045 struct work_struct service_work;
1046 struct timer_list service_timer;
1047
1048 /* Rings for Tx/Rx on a DMA channel */
1049 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS];
1050 unsigned int tx_max_channel_count;
1051 unsigned int rx_max_channel_count;
1052 unsigned int channel_count;
1053 unsigned int tx_ring_count;
1054 unsigned int tx_desc_count;
1055 unsigned int rx_ring_count;
1056 unsigned int rx_desc_count;
1057
1058 unsigned int new_tx_ring_count;
1059 unsigned int new_rx_ring_count;
1060
1061 unsigned int tx_max_q_count;
1062 unsigned int rx_max_q_count;
1063 unsigned int tx_q_count;
1064 unsigned int rx_q_count;
1065
1066 /* Tx/Rx common settings */
1067 unsigned int blen;
1068 unsigned int pbl;
1069 unsigned int aal;
1070 unsigned int rd_osr_limit;
1071 unsigned int wr_osr_limit;
1072
1073 /* Tx settings */
1074 unsigned int tx_sf_mode;
1075 unsigned int tx_threshold;
1076 unsigned int tx_osp_mode;
1077 unsigned int tx_max_fifo_size;
1078
1079 /* Rx settings */
1080 unsigned int rx_sf_mode;
1081 unsigned int rx_threshold;
1082 unsigned int rx_max_fifo_size;
1083
1084 /* Tx coalescing settings */
1085 unsigned int tx_usecs;
1086 unsigned int tx_frames;
1087
1088 /* Rx coalescing settings */
1089 unsigned int rx_riwt;
1090 unsigned int rx_usecs;
1091 unsigned int rx_frames;
1092
1093 /* Current Rx buffer size */
1094 unsigned int rx_buf_size;
1095
1096 /* Flow control settings */
1097 unsigned int pause_autoneg;
1098 unsigned int tx_pause;
1099 unsigned int rx_pause;
1100 unsigned int rx_rfa[XGBE_MAX_QUEUES];
1101 unsigned int rx_rfd[XGBE_MAX_QUEUES];
1102
1103 /* Receive Side Scaling settings */
1104 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
1105 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
1106 u32 rss_options;
1107
1108 /* VXLAN settings */
1109 u16 vxlan_port;
1110
1111 /* Netdev related settings */
1112 unsigned char mac_addr[ETH_ALEN];
1113 netdev_features_t netdev_features;
1114 struct napi_struct napi;
1115 struct xgbe_mmc_stats mmc_stats;
1116 struct xgbe_ext_stats ext_stats;
1117
1118 /* Filtering support */
1119 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1120
1121 /* Device clocks */
1122 struct clk *sysclk;
1123 unsigned long sysclk_rate;
1124 struct clk *ptpclk;
1125 unsigned long ptpclk_rate;
1126
1127 /* Timestamp support */
1128 spinlock_t tstamp_lock;
1129 struct ptp_clock_info ptp_clock_info;
1130 struct ptp_clock *ptp_clock;
1131 struct hwtstamp_config tstamp_config;
1132 struct cyclecounter tstamp_cc;
1133 struct timecounter tstamp_tc;
1134 unsigned int tstamp_addend;
1135 struct work_struct tx_tstamp_work;
1136 struct sk_buff *tx_tstamp_skb;
1137 u64 tx_tstamp;
1138
1139 /* DCB support */
1140 struct ieee_ets *ets;
1141 struct ieee_pfc *pfc;
1142 unsigned int q2tc_map[XGBE_MAX_QUEUES];
1143 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
1144 unsigned int pfcq[XGBE_MAX_QUEUES];
1145 unsigned int pfc_rfa;
1146 u8 num_tcs;
1147
1148 /* Hardware features of the device */
1149 struct xgbe_hw_features hw_feat;
1150
1151 /* Device work structures */
1152 struct work_struct restart_work;
1153 struct work_struct stopdev_work;
1154
1155 /* Keeps track of power mode */
1156 unsigned int power_down;
1157
1158 /* Network interface message level setting */
1159 u32 msg_enable;
1160
1161 /* Current PHY settings */
1162 phy_interface_t phy_mode;
1163 int phy_link;
1164 int phy_speed;
1165
1166 /* MDIO/PHY related settings */
1167 unsigned int phy_started;
1168 void *phy_data;
1169 struct xgbe_phy phy;
1170 int mdio_mmd;
1171 unsigned long link_check;
1172 struct completion mdio_complete;
1173
1174 unsigned int kr_redrv;
1175
1176 char an_name[IFNAMSIZ + 32];
1177 struct workqueue_struct *an_workqueue;
1178
1179 int an_irq;
1180 struct work_struct an_irq_work;
1181
1182 /* Auto-negotiation state machine support */
1183 unsigned int an_int;
1184 unsigned int an_status;
1185 struct mutex an_mutex;
1186 enum xgbe_an an_result;
1187 enum xgbe_an an_state;
1188 enum xgbe_rx kr_state;
1189 enum xgbe_rx kx_state;
1190 struct work_struct an_work;
1191 unsigned int an_again;
1192 unsigned int an_supported;
1193 unsigned int parallel_detect;
1194 unsigned int fec_ability;
1195 unsigned long an_start;
1196 unsigned long kr_start_time;
1197 enum xgbe_an_mode an_mode;
1198
1199 /* I2C support */
1200 struct xgbe_i2c i2c;
1201 struct mutex i2c_mutex;
1202 struct completion i2c_complete;
1203 char i2c_name[IFNAMSIZ + 32];
1204
1205 unsigned int lpm_ctrl; /* CTRL1 for resume */
1206
1207 unsigned int isr_as_bh_work;
1208 struct work_struct dev_bh_work;
1209 struct work_struct ecc_bh_work;
1210 struct work_struct i2c_bh_work;
1211 struct work_struct an_bh_work;
1212
1213 struct dentry *xgbe_debugfs;
1214
1215 unsigned int debugfs_xgmac_reg;
1216
1217 unsigned int debugfs_xpcs_mmd;
1218 unsigned int debugfs_xpcs_reg;
1219
1220 unsigned int debugfs_xprop_reg;
1221
1222 unsigned int debugfs_xi2c_reg;
1223
1224 bool debugfs_an_cdr_workaround;
1225 bool debugfs_an_cdr_track_early;
1226 bool en_rx_adap;
1227 int rx_adapt_retries;
1228 bool rx_adapt_done;
1229 bool mode_set;
1230 };
1231
1232 /* Function prototypes*/
1233 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *);
1234 void xgbe_free_pdata(struct xgbe_prv_data *);
1235 void xgbe_set_counts(struct xgbe_prv_data *);
1236 int xgbe_config_netdev(struct xgbe_prv_data *);
1237 void xgbe_deconfig_netdev(struct xgbe_prv_data *);
1238
1239 int xgbe_platform_init(void);
1240 void xgbe_platform_exit(void);
1241 #ifdef CONFIG_PCI
1242 int xgbe_pci_init(void);
1243 void xgbe_pci_exit(void);
1244 #else
xgbe_pci_init(void)1245 static inline int xgbe_pci_init(void) { return 0; }
xgbe_pci_exit(void)1246 static inline void xgbe_pci_exit(void) { }
1247 #endif
1248
1249 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
1250 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
1251 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
1252 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
1253 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
1254 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
1255 const struct net_device_ops *xgbe_get_netdev_ops(void);
1256 const struct ethtool_ops *xgbe_get_ethtool_ops(void);
1257 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void);
1258
1259 #ifdef CONFIG_AMD_XGBE_DCB
1260 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
1261 #endif
1262
1263 void xgbe_ptp_register(struct xgbe_prv_data *);
1264 void xgbe_ptp_unregister(struct xgbe_prv_data *);
1265 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1266 unsigned int, unsigned int, unsigned int);
1267 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1268 unsigned int);
1269 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
1270 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
1271 int xgbe_powerup(struct net_device *, unsigned int);
1272 int xgbe_powerdown(struct net_device *, unsigned int);
1273 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
1274 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
1275 void xgbe_restart_dev(struct xgbe_prv_data *pdata);
1276 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata);
1277
1278 #ifdef CONFIG_DEBUG_FS
1279 void xgbe_debugfs_init(struct xgbe_prv_data *);
1280 void xgbe_debugfs_exit(struct xgbe_prv_data *);
1281 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata);
1282 #else
xgbe_debugfs_init(struct xgbe_prv_data * pdata)1283 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_exit(struct xgbe_prv_data * pdata)1284 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_rename(struct xgbe_prv_data * pdata)1285 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {}
1286 #endif /* CONFIG_DEBUG_FS */
1287
1288 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
1289 #if 0
1290 #define YDEBUG
1291 #define YDEBUG_MDIO
1292 #endif
1293
1294 /* For debug prints */
1295 #ifdef YDEBUG
1296 #define DBGPR(x...) pr_alert(x)
1297 #else
1298 #define DBGPR(x...) do { } while (0)
1299 #endif
1300
1301 #ifdef YDEBUG_MDIO
1302 #define DBGPR_MDIO(x...) pr_alert(x)
1303 #else
1304 #define DBGPR_MDIO(x...) do { } while (0)
1305 #endif
1306
1307 #endif
1308