1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #ifndef __XGBE_H__
9 #define __XGBE_H__
10
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/workqueue.h>
14 #include <linux/phy.h>
15 #include <linux/if_vlan.h>
16 #include <linux/bitops.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
19 #include <linux/net_tstamp.h>
20 #include <net/dcbnl.h>
21 #include <linux/completion.h>
22 #include <linux/cpumask.h>
23 #include <linux/interrupt.h>
24 #include <linux/dcache.h>
25 #include <linux/ethtool.h>
26 #include <linux/list.h>
27
28 #define XGBE_DRV_NAME "amd-xgbe"
29 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
30
31 /* Descriptor related defines */
32 #define XGBE_TX_DESC_CNT 512
33 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
34 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
35 #define XGBE_RX_DESC_CNT 512
36
37 #define XGBE_TX_DESC_CNT_MIN 64
38 #define XGBE_TX_DESC_CNT_MAX 4096
39 #define XGBE_RX_DESC_CNT_MIN 64
40 #define XGBE_RX_DESC_CNT_MAX 4096
41
42 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
43
44 /* Descriptors required for maximum contiguous TSO/GSO packet */
45 #define XGBE_TX_MAX_SPLIT \
46 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
47
48 /* Maximum possible descriptors needed for an SKB:
49 * - Maximum number of SKB frags
50 * - Maximum descriptors for contiguous TSO/GSO packet
51 * - Possible context descriptor
52 * - Possible TSO header descriptor
53 */
54 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
55
56 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
57 #define XGBE_RX_BUF_ALIGN 64
58 #define XGBE_SKB_ALLOC_SIZE 256
59 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
60
61 #define XGBE_MAX_DMA_CHANNELS 16
62 #define XGBE_MAX_QUEUES 16
63 #define XGBE_PRIORITY_QUEUES 8
64 #define XGBE_DMA_STOP_TIMEOUT 1
65
66 /* DMA cache settings - Outer sharable, write-back, write-allocate */
67 #define XGBE_DMA_OS_ARCR 0x002b2b2b
68 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f
69
70 /* DMA cache settings - System, no caches used */
71 #define XGBE_DMA_SYS_ARCR 0x00303030
72 #define XGBE_DMA_SYS_AWCR 0x30303030
73
74 /* DMA cache settings - PCI device */
75 #define XGBE_DMA_PCI_ARCR 0x000f0f0f
76 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f
77 #define XGBE_DMA_PCI_AWARCR 0x00000f0f
78
79 /* DMA channel interrupt modes */
80 #define XGBE_IRQ_MODE_EDGE 0
81 #define XGBE_IRQ_MODE_LEVEL 1
82
83 #define XGBE_ETH_FRAME_HDR (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
84 #define XGMAC_MIN_PACKET 60
85 #define XGMAC_STD_PACKET_MTU 1500
86 #define XGMAC_MAX_STD_PACKET 1518
87 #define XGMAC_JUMBO_PACKET_MTU 9000
88 #define XGMAC_MAX_JUMBO_PACKET 9018
89 #define XGMAC_GIANT_PACKET_MTU 16368
90 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
91
92 #define XGMAC_PFC_DATA_LEN 46
93 #define XGMAC_PFC_DELAYS 14000
94
95 #define XGMAC_PRIO_QUEUES(_cnt) \
96 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
97
98 /* Common property names */
99 #define XGBE_MAC_ADDR_PROPERTY "mac-address"
100 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
101 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
102 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
103
104 /* Device-tree clock names */
105 #define XGBE_DMA_CLOCK "dma_clk"
106 #define XGBE_PTP_CLOCK "ptp_clk"
107
108 /* ACPI property names */
109 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
110 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
111
112 /* PCI BAR mapping */
113 #define XGBE_XGMAC_BAR 0
114 #define XGBE_XPCS_BAR 1
115 #define XGBE_MAC_PROP_OFFSET 0x1d000
116 #define XGBE_I2C_CTRL_OFFSET 0x1e000
117
118 /* PCI MSI/MSIx support */
119 #define XGBE_MSI_BASE_COUNT 4
120 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1)
121
122 /* Initial PTP register values based on Link Speed. */
123 #define MAC_TICNR_1G_INITVAL 0x10
124 #define MAC_TECNR_1G_INITVAL 0x28
125
126 #define MAC_TICSNR_10G_INITVAL 0x33
127 #define MAC_TECNR_10G_INITVAL 0x14
128 #define MAC_TECSNR_10G_INITVAL 0xCC
129
130 /* PCI clock frequencies */
131 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
132 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
133
134 /* Timestamp support - values based on 50MHz PTP clock
135 * 50MHz => 20 nsec
136 */
137 #define XGBE_TSTAMP_SSINC 20
138 #define XGBE_TSTAMP_SNSINC 0
139 #define XGBE_PTP_ACT_CLK_FREQ 500000000
140
141 #define XGBE_V2_TSTAMP_SSINC 0xA
142 #define XGBE_V2_TSTAMP_SNSINC 0
143 #define XGBE_V2_PTP_ACT_CLK_FREQ 1000000000
144
145 /* Define maximum supported values */
146 #define XGBE_MAX_PPS_OUT 4
147 #define XGBE_MAX_AUX_SNAP 4
148
149 /* Driver PMT macros */
150 #define XGMAC_DRIVER_CONTEXT 1
151 #define XGMAC_IOCTL_CONTEXT 2
152
153 #define XGMAC_FIFO_MIN_ALLOC 2048
154 #define XGMAC_FIFO_UNIT 256
155 #define XGMAC_FIFO_ALIGN(_x) \
156 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
157 #define XGMAC_FIFO_FC_OFF 2048
158 #define XGMAC_FIFO_FC_MIN 4096
159
160 #define XGBE_TC_MIN_QUANTUM 10
161
162 /* Helper macro for descriptor handling
163 * Always use XGBE_GET_DESC_DATA to access the descriptor data
164 * since the index is free-running and needs to be and-ed
165 * with the descriptor count value of the ring to index to
166 * the proper descriptor data.
167 */
168 #define XGBE_GET_DESC_DATA(_ring, _idx) \
169 ((_ring)->rdata + \
170 ((_idx) & ((_ring)->rdesc_count - 1)))
171
172 /* Default coalescing parameters */
173 #define XGMAC_INIT_DMA_TX_USECS 1000
174 #define XGMAC_INIT_DMA_TX_FRAMES 25
175 #define XGMAC_MAX_COAL_TX_TICK 100000
176
177 #define XGMAC_MAX_DMA_RIWT 0xff
178 #define XGMAC_INIT_DMA_RX_USECS 30
179 #define XGMAC_INIT_DMA_RX_FRAMES 25
180
181 /* Flow control queue count */
182 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
183
184 /* Flow control threshold units */
185 #define XGMAC_FLOW_CONTROL_UNIT 512
186 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \
187 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
188 #define XGMAC_FLOW_CONTROL_VALUE(_x) \
189 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
190 #define XGMAC_FLOW_CONTROL_MAX 33280
191
192 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
193 #define XGBE_MAC_HASH_TABLE_SIZE 8
194
195 /* Receive Side Scaling */
196 #define XGBE_RSS_HASH_KEY_SIZE 40
197 #define XGBE_RSS_MAX_TABLE_SIZE 256
198 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
199 #define XGBE_RSS_HASH_KEY_TYPE 1
200
201 /* Auto-negotiation */
202 #define XGBE_AN_MS_TIMEOUT 500
203 #define XGBE_LINK_TIMEOUT 5
204 #define XGBE_KR_TRAINING_WAIT_ITER 50
205
206 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(1)
207 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
208 #define XGBE_SGMII_AN_LINK_SPEED_10 0x00
209 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04
210 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
211 #define XGBE_SGMII_AN_LINK_STATUS BIT(4)
212
213 /* ECC correctable error notification window (seconds) */
214 #define XGBE_ECC_LIMIT 60
215
216 /* MDIO port types */
217 #define XGMAC_MAX_C22_PORT 3
218
219 /* Link mode bit operations */
220 #define XGBE_ZERO_SUP(_ls) \
221 ethtool_link_ksettings_zero_link_mode((_ls), supported)
222
223 #define XGBE_SET_SUP(_ls, _mode) \
224 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode)
225
226 #define XGBE_CLR_SUP(_ls, _mode) \
227 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode)
228
229 #define XGBE_IS_SUP(_ls, _mode) \
230 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode)
231
232 #define XGBE_ZERO_ADV(_ls) \
233 ethtool_link_ksettings_zero_link_mode((_ls), advertising)
234
235 #define XGBE_SET_ADV(_ls, _mode) \
236 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode)
237
238 #define XGBE_CLR_ADV(_ls, _mode) \
239 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode)
240
241 #define XGBE_ADV(_ls, _mode) \
242 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode)
243
244 #define XGBE_ZERO_LP_ADV(_ls) \
245 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising)
246
247 #define XGBE_SET_LP_ADV(_ls, _mode) \
248 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode)
249
250 #define XGBE_CLR_LP_ADV(_ls, _mode) \
251 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode)
252
253 #define XGBE_LP_ADV(_ls, _mode) \
254 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode)
255
256 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \
257 bitmap_copy((_dst)->link_modes._dname, \
258 (_src)->link_modes._sname, \
259 __ETHTOOL_LINK_MODE_MASK_NBITS)
260
261 /* XGBE PCI device id */
262 #define XGBE_RV_PCI_DEVICE_ID 0x15d0
263 #define XGBE_YC_PCI_DEVICE_ID 0x14b5
264 #define XGBE_RN_PCI_DEVICE_ID 0x1630
265
266 /* Generic low and high masks */
267 #define XGBE_GEN_HI_MASK GENMASK(31, 16)
268 #define XGBE_GEN_LO_MASK GENMASK(15, 0)
269
270 struct xgbe_prv_data;
271
272 struct xgbe_packet_data {
273 struct sk_buff *skb;
274
275 unsigned int attributes;
276
277 unsigned int errors;
278
279 unsigned int rdesc_count;
280 unsigned int length;
281
282 unsigned int header_len;
283 unsigned int tcp_header_len;
284 unsigned int tcp_payload_len;
285 unsigned short mss;
286
287 unsigned short vlan_ctag;
288
289 u64 rx_tstamp;
290
291 u32 rss_hash;
292 enum pkt_hash_types rss_hash_type;
293
294 unsigned int tx_packets;
295 unsigned int tx_bytes;
296 };
297
298 /* Common Rx and Tx descriptor mapping */
299 struct xgbe_ring_desc {
300 __le32 desc0;
301 __le32 desc1;
302 __le32 desc2;
303 __le32 desc3;
304 };
305
306 /* Page allocation related values */
307 struct xgbe_page_alloc {
308 struct page *pages;
309 unsigned int pages_len;
310 unsigned int pages_offset;
311
312 dma_addr_t pages_dma;
313 };
314
315 /* Ring entry buffer data */
316 struct xgbe_buffer_data {
317 struct xgbe_page_alloc pa;
318 struct xgbe_page_alloc pa_unmap;
319
320 dma_addr_t dma_base;
321 unsigned long dma_off;
322 unsigned int dma_len;
323 };
324
325 /* Tx-related ring data */
326 struct xgbe_tx_ring_data {
327 unsigned int packets; /* BQL packet count */
328 unsigned int bytes; /* BQL byte count */
329 };
330
331 /* Rx-related ring data */
332 struct xgbe_rx_ring_data {
333 struct xgbe_buffer_data hdr; /* Header locations */
334 struct xgbe_buffer_data buf; /* Payload locations */
335
336 unsigned short hdr_len; /* Length of received header */
337 unsigned short len; /* Length of received packet */
338 };
339
340 /* Structure used to hold information related to the descriptor
341 * and the packet associated with the descriptor (always use
342 * the XGBE_GET_DESC_DATA macro to access this data from the ring)
343 */
344 struct xgbe_ring_data {
345 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
346 dma_addr_t rdesc_dma; /* DMA address of descriptor */
347
348 struct sk_buff *skb; /* Virtual address of SKB */
349 dma_addr_t skb_dma; /* DMA address of SKB data */
350 unsigned int skb_dma_len; /* Length of SKB DMA area */
351
352 struct xgbe_tx_ring_data tx; /* Tx-related data */
353 struct xgbe_rx_ring_data rx; /* Rx-related data */
354
355 unsigned int mapped_as_page;
356
357 /* Incomplete receive save location. If the budget is exhausted
358 * or the last descriptor (last normal descriptor or a following
359 * context descriptor) has not been DMA'd yet the current state
360 * of the receive processing needs to be saved.
361 */
362 unsigned int state_saved;
363 struct {
364 struct sk_buff *skb;
365 unsigned int len;
366 unsigned int error;
367 } state;
368 };
369
370 struct xgbe_ring {
371 /* Ring lock - used just for TX rings at the moment */
372 spinlock_t lock;
373
374 /* Per packet related information */
375 struct xgbe_packet_data packet_data;
376
377 /* Virtual/DMA addresses and count of allocated descriptor memory */
378 struct xgbe_ring_desc *rdesc;
379 dma_addr_t rdesc_dma;
380 unsigned int rdesc_count;
381
382 /* Array of descriptor data corresponding the descriptor memory
383 * (always use the XGBE_GET_DESC_DATA macro to access this data)
384 */
385 struct xgbe_ring_data *rdata;
386
387 /* Page allocation for RX buffers */
388 struct xgbe_page_alloc rx_hdr_pa;
389 struct xgbe_page_alloc rx_buf_pa;
390 int node;
391
392 /* Ring index values
393 * cur - Tx: index of descriptor to be used for current transfer
394 * Rx: index of descriptor to check for packet availability
395 * dirty - Tx: index of descriptor to check for transfer complete
396 * Rx: index of descriptor to check for buffer reallocation
397 */
398 unsigned int cur;
399 unsigned int dirty;
400
401 /* Coalesce frame count used for interrupt bit setting */
402 unsigned int coalesce_count;
403
404 union {
405 struct {
406 unsigned int queue_stopped;
407 unsigned int xmit_more;
408 unsigned short cur_mss;
409 unsigned short cur_vlan_ctag;
410 } tx;
411 };
412 } ____cacheline_aligned;
413
414 /* Structure used to describe the descriptor rings associated with
415 * a DMA channel.
416 */
417 struct xgbe_channel {
418 char name[20];
419
420 /* Address of private data area for device */
421 struct xgbe_prv_data *pdata;
422
423 /* Queue index and base address of queue's DMA registers */
424 unsigned int queue_index;
425 void __iomem *dma_regs;
426
427 /* Per channel interrupt irq number */
428 int dma_irq;
429 char dma_irq_name[IFNAMSIZ + 32];
430
431 /* Netdev related settings */
432 struct napi_struct napi;
433
434 /* Per channel interrupt enablement tracker */
435 unsigned int curr_ier;
436 unsigned int saved_ier;
437
438 unsigned int tx_timer_active;
439 struct timer_list tx_timer;
440
441 struct xgbe_ring *tx_ring;
442 struct xgbe_ring *rx_ring;
443
444 int node;
445 cpumask_t affinity_mask;
446 } ____cacheline_aligned;
447
448 enum xgbe_state {
449 XGBE_DOWN,
450 XGBE_LINK_INIT,
451 XGBE_LINK_ERR,
452 XGBE_STOPPED,
453 };
454
455 enum xgbe_int {
456 XGMAC_INT_DMA_CH_SR_TI,
457 XGMAC_INT_DMA_CH_SR_TPS,
458 XGMAC_INT_DMA_CH_SR_TBU,
459 XGMAC_INT_DMA_CH_SR_RI,
460 XGMAC_INT_DMA_CH_SR_RBU,
461 XGMAC_INT_DMA_CH_SR_RPS,
462 XGMAC_INT_DMA_CH_SR_TI_RI,
463 XGMAC_INT_DMA_CH_SR_FBE,
464 XGMAC_INT_DMA_ALL,
465 };
466
467 enum xgbe_int_state {
468 XGMAC_INT_STATE_SAVE,
469 XGMAC_INT_STATE_RESTORE,
470 };
471
472 enum xgbe_ecc_sec {
473 XGBE_ECC_SEC_TX,
474 XGBE_ECC_SEC_RX,
475 XGBE_ECC_SEC_DESC,
476 };
477
478 enum xgbe_speed {
479 XGBE_SPEED_1000 = 0,
480 XGBE_SPEED_2500,
481 XGBE_SPEED_10000,
482 XGBE_SPEEDS,
483 };
484
485 enum xgbe_xpcs_access {
486 XGBE_XPCS_ACCESS_V1 = 0,
487 XGBE_XPCS_ACCESS_V2,
488 XGBE_XPCS_ACCESS_V3,
489 };
490
491 enum xgbe_an_mode {
492 XGBE_AN_MODE_CL73 = 0,
493 XGBE_AN_MODE_CL73_REDRV,
494 XGBE_AN_MODE_CL37,
495 XGBE_AN_MODE_CL37_SGMII,
496 XGBE_AN_MODE_NONE,
497 };
498
499 enum xgbe_an {
500 XGBE_AN_READY = 0,
501 XGBE_AN_PAGE_RECEIVED,
502 XGBE_AN_INCOMPAT_LINK,
503 XGBE_AN_COMPLETE,
504 XGBE_AN_NO_LINK,
505 XGBE_AN_ERROR,
506 };
507
508 enum xgbe_rx {
509 XGBE_RX_BPA = 0,
510 XGBE_RX_XNP,
511 XGBE_RX_COMPLETE,
512 XGBE_RX_ERROR,
513 };
514
515 enum xgbe_mode {
516 XGBE_MODE_KX_1000 = 0,
517 XGBE_MODE_KX_2500,
518 XGBE_MODE_KR,
519 XGBE_MODE_X,
520 XGBE_MODE_SGMII_10,
521 XGBE_MODE_SGMII_100,
522 XGBE_MODE_SGMII_1000,
523 XGBE_MODE_SFI,
524 XGBE_MODE_UNKNOWN,
525 };
526
527 enum xgbe_speedset {
528 XGBE_SPEEDSET_1000_10000 = 0,
529 XGBE_SPEEDSET_2500_10000,
530 };
531
532 enum xgbe_mdio_mode {
533 XGBE_MDIO_MODE_NONE = 0,
534 XGBE_MDIO_MODE_CL22,
535 XGBE_MDIO_MODE_CL45,
536 };
537
538 enum xgbe_mb_cmd {
539 XGBE_MB_CMD_POWER_OFF = 0,
540 XGBE_MB_CMD_SET_1G,
541 XGBE_MB_CMD_SET_2_5G,
542 XGBE_MB_CMD_SET_10G_SFI,
543 XGBE_MB_CMD_SET_10G_KR,
544 XGBE_MB_CMD_RRC
545 };
546
547 enum xgbe_mb_subcmd {
548 XGBE_MB_SUBCMD_NONE = 0,
549 XGBE_MB_SUBCMD_RX_ADAP,
550
551 /* 10GbE SFP subcommands */
552 XGBE_MB_SUBCMD_ACTIVE = 0,
553 XGBE_MB_SUBCMD_PASSIVE_1M,
554 XGBE_MB_SUBCMD_PASSIVE_3M,
555 XGBE_MB_SUBCMD_PASSIVE_OTHER,
556
557 /* 1GbE Mode subcommands */
558 XGBE_MB_SUBCMD_10MBITS = 0,
559 XGBE_MB_SUBCMD_100MBITS,
560 XGBE_MB_SUBCMD_1G_SGMII,
561 XGBE_MB_SUBCMD_1G_KX
562 };
563
564 struct xgbe_phy {
565 struct ethtool_link_ksettings lks;
566
567 int address;
568
569 int autoneg;
570 int speed;
571 int duplex;
572
573 int link;
574
575 int pause_autoneg;
576 int tx_pause;
577 int rx_pause;
578 };
579
580 enum xgbe_i2c_cmd {
581 XGBE_I2C_CMD_READ = 0,
582 XGBE_I2C_CMD_WRITE,
583 };
584
585 struct xgbe_i2c_op {
586 enum xgbe_i2c_cmd cmd;
587
588 unsigned int target;
589
590 void *buf;
591 unsigned int len;
592 };
593
594 struct xgbe_i2c_op_state {
595 struct xgbe_i2c_op *op;
596
597 unsigned int tx_len;
598 unsigned char *tx_buf;
599
600 unsigned int rx_len;
601 unsigned char *rx_buf;
602
603 unsigned int tx_abort_source;
604
605 int ret;
606 };
607
608 struct xgbe_i2c {
609 unsigned int started;
610 unsigned int max_speed_mode;
611 unsigned int rx_fifo_size;
612 unsigned int tx_fifo_size;
613
614 struct xgbe_i2c_op_state op_state;
615 };
616
617 struct xgbe_mmc_stats {
618 /* Tx Stats */
619 u64 txoctetcount_gb;
620 u64 txframecount_gb;
621 u64 txbroadcastframes_g;
622 u64 txmulticastframes_g;
623 u64 tx64octets_gb;
624 u64 tx65to127octets_gb;
625 u64 tx128to255octets_gb;
626 u64 tx256to511octets_gb;
627 u64 tx512to1023octets_gb;
628 u64 tx1024tomaxoctets_gb;
629 u64 txunicastframes_gb;
630 u64 txmulticastframes_gb;
631 u64 txbroadcastframes_gb;
632 u64 txunderflowerror;
633 u64 txoctetcount_g;
634 u64 txframecount_g;
635 u64 txpauseframes;
636 u64 txvlanframes_g;
637
638 /* Rx Stats */
639 u64 rxframecount_gb;
640 u64 rxoctetcount_gb;
641 u64 rxoctetcount_g;
642 u64 rxbroadcastframes_g;
643 u64 rxmulticastframes_g;
644 u64 rxcrcerror;
645 u64 rxrunterror;
646 u64 rxjabbererror;
647 u64 rxundersize_g;
648 u64 rxoversize_g;
649 u64 rx64octets_gb;
650 u64 rx65to127octets_gb;
651 u64 rx128to255octets_gb;
652 u64 rx256to511octets_gb;
653 u64 rx512to1023octets_gb;
654 u64 rx1024tomaxoctets_gb;
655 u64 rxunicastframes_g;
656 u64 rxlengtherror;
657 u64 rxoutofrangetype;
658 u64 rxpauseframes;
659 u64 rxfifooverflow;
660 u64 rxvlanframes_gb;
661 u64 rxwatchdogerror;
662 u64 rxalignmenterror;
663 };
664
665 struct xgbe_ext_stats {
666 u64 tx_tso_packets;
667 u64 rx_split_header_packets;
668 u64 rx_buffer_unavailable;
669
670 u64 txq_packets[XGBE_MAX_DMA_CHANNELS];
671 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS];
672 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS];
673 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS];
674
675 u64 tx_vxlan_packets;
676 u64 rx_vxlan_packets;
677 u64 rx_csum_errors;
678 u64 rx_vxlan_csum_errors;
679 };
680
681 struct xgbe_pps_config {
682 struct timespec64 start;
683 struct timespec64 period;
684 };
685
686 struct xgbe_hw_if {
687 int (*tx_complete)(struct xgbe_ring_desc *);
688
689 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr);
690 int (*config_rx_mode)(struct xgbe_prv_data *);
691
692 int (*enable_rx_csum)(struct xgbe_prv_data *);
693 int (*disable_rx_csum)(struct xgbe_prv_data *);
694
695 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
696 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
697 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
698 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
699 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
700
701 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
702 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
703 int (*set_speed)(struct xgbe_prv_data *, int);
704
705 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
706 enum xgbe_mdio_mode);
707 int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int);
708 int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16);
709 int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int);
710 int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int,
711 u16);
712
713 int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
714 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
715
716 void (*enable_tx)(struct xgbe_prv_data *);
717 void (*disable_tx)(struct xgbe_prv_data *);
718 void (*enable_rx)(struct xgbe_prv_data *);
719 void (*disable_rx)(struct xgbe_prv_data *);
720
721 void (*powerup_tx)(struct xgbe_prv_data *);
722 void (*powerdown_tx)(struct xgbe_prv_data *);
723 void (*powerup_rx)(struct xgbe_prv_data *);
724 void (*powerdown_rx)(struct xgbe_prv_data *);
725
726 int (*init)(struct xgbe_prv_data *);
727 int (*exit)(struct xgbe_prv_data *);
728
729 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
730 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
731 void (*dev_xmit)(struct xgbe_channel *);
732 int (*dev_read)(struct xgbe_channel *);
733 void (*tx_desc_init)(struct xgbe_channel *);
734 void (*rx_desc_init)(struct xgbe_channel *);
735 void (*tx_desc_reset)(struct xgbe_ring_data *);
736 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
737 unsigned int);
738 int (*is_last_desc)(struct xgbe_ring_desc *);
739 int (*is_context_desc)(struct xgbe_ring_desc *);
740 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
741
742 /* For FLOW ctrl */
743 int (*config_tx_flow_control)(struct xgbe_prv_data *);
744 int (*config_rx_flow_control)(struct xgbe_prv_data *);
745
746 /* For RX coalescing */
747 int (*config_rx_coalesce)(struct xgbe_prv_data *);
748 int (*config_tx_coalesce)(struct xgbe_prv_data *);
749 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
750 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
751
752 /* For RX and TX threshold config */
753 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
754 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
755
756 /* For RX and TX Store and Forward Mode config */
757 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
758 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
759
760 /* For TX DMA Operate on Second Frame config */
761 int (*config_osp_mode)(struct xgbe_prv_data *);
762
763 /* For MMC statistics */
764 void (*rx_mmc_int)(struct xgbe_prv_data *);
765 void (*tx_mmc_int)(struct xgbe_prv_data *);
766 void (*read_mmc_stats)(struct xgbe_prv_data *);
767
768 /* For Data Center Bridging config */
769 void (*config_tc)(struct xgbe_prv_data *);
770 void (*config_dcb_tc)(struct xgbe_prv_data *);
771 void (*config_dcb_pfc)(struct xgbe_prv_data *);
772
773 /* For Receive Side Scaling */
774 int (*enable_rss)(struct xgbe_prv_data *);
775 int (*disable_rss)(struct xgbe_prv_data *);
776 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
777 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
778
779 /* For ECC */
780 void (*disable_ecc_ded)(struct xgbe_prv_data *);
781 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
782
783 /* For VXLAN */
784 void (*enable_vxlan)(struct xgbe_prv_data *);
785 void (*disable_vxlan)(struct xgbe_prv_data *);
786 void (*set_vxlan_id)(struct xgbe_prv_data *);
787
788 /* For Split Header */
789 void (*enable_sph)(struct xgbe_prv_data *pdata);
790 void (*disable_sph)(struct xgbe_prv_data *pdata);
791 };
792
793 /* This structure represents implementation specific routines for an
794 * implementation of a PHY. All routines are required unless noted below.
795 * Optional routines:
796 * an_pre, an_post
797 * kr_training_pre, kr_training_post
798 * module_info, module_eeprom
799 */
800 struct xgbe_phy_impl_if {
801 /* Perform Setup/teardown actions */
802 int (*init)(struct xgbe_prv_data *);
803 void (*exit)(struct xgbe_prv_data *);
804
805 /* Perform start/stop specific actions */
806 int (*reset)(struct xgbe_prv_data *);
807 int (*start)(struct xgbe_prv_data *);
808 void (*stop)(struct xgbe_prv_data *);
809
810 /* Return the link status */
811 int (*link_status)(struct xgbe_prv_data *, int *);
812
813 /* Indicate if a particular speed is valid */
814 bool (*valid_speed)(struct xgbe_prv_data *, int);
815
816 /* Check if the specified mode can/should be used */
817 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
818 /* Switch the PHY into various modes */
819 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
820 /* Retrieve mode needed for a specific speed */
821 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
822 /* Retrieve new/next mode when trying to auto-negotiate */
823 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
824 /* Retrieve current mode */
825 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
826
827 /* Retrieve current auto-negotiation mode */
828 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
829
830 /* Configure auto-negotiation settings */
831 int (*an_config)(struct xgbe_prv_data *);
832
833 /* Set/override auto-negotiation advertisement settings */
834 void (*an_advertising)(struct xgbe_prv_data *,
835 struct ethtool_link_ksettings *);
836
837 /* Process results of auto-negotiation */
838 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
839
840 /* Pre/Post auto-negotiation support */
841 void (*an_pre)(struct xgbe_prv_data *);
842 void (*an_post)(struct xgbe_prv_data *);
843
844 /* Pre/Post KR training enablement support */
845 void (*kr_training_pre)(struct xgbe_prv_data *);
846 void (*kr_training_post)(struct xgbe_prv_data *);
847
848 /* SFP module related info */
849 int (*module_info)(struct xgbe_prv_data *pdata,
850 struct ethtool_modinfo *modinfo);
851 int (*module_eeprom)(struct xgbe_prv_data *pdata,
852 struct ethtool_eeprom *eeprom, u8 *data);
853 };
854
855 struct xgbe_phy_if {
856 /* For PHY setup/teardown */
857 int (*phy_init)(struct xgbe_prv_data *);
858 void (*phy_exit)(struct xgbe_prv_data *);
859
860 /* For PHY support when setting device up/down */
861 int (*phy_reset)(struct xgbe_prv_data *);
862 int (*phy_start)(struct xgbe_prv_data *);
863 void (*phy_stop)(struct xgbe_prv_data *);
864
865 /* For PHY support while device is up */
866 void (*phy_status)(struct xgbe_prv_data *);
867 int (*phy_config_aneg)(struct xgbe_prv_data *);
868
869 /* For PHY settings validation */
870 bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
871
872 /* For single interrupt support */
873 irqreturn_t (*an_isr)(struct xgbe_prv_data *);
874
875 /* For ethtool PHY support */
876 int (*module_info)(struct xgbe_prv_data *pdata,
877 struct ethtool_modinfo *modinfo);
878 int (*module_eeprom)(struct xgbe_prv_data *pdata,
879 struct ethtool_eeprom *eeprom, u8 *data);
880
881 /* PHY implementation specific services */
882 struct xgbe_phy_impl_if phy_impl;
883 };
884
885 struct xgbe_i2c_if {
886 /* For initial I2C setup */
887 int (*i2c_init)(struct xgbe_prv_data *);
888
889 /* For I2C support when setting device up/down */
890 int (*i2c_start)(struct xgbe_prv_data *);
891 void (*i2c_stop)(struct xgbe_prv_data *);
892
893 /* For performing I2C operations */
894 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
895
896 /* For single interrupt support */
897 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *);
898 };
899
900 struct xgbe_desc_if {
901 int (*alloc_ring_resources)(struct xgbe_prv_data *);
902 void (*free_ring_resources)(struct xgbe_prv_data *);
903 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
904 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
905 struct xgbe_ring_data *);
906 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
907 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
908 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
909 };
910
911 /* This structure contains flags that indicate what hardware features
912 * or configurations are present in the device.
913 */
914 struct xgbe_hw_features {
915 /* HW Version */
916 unsigned int version;
917
918 /* HW Feature Register0 */
919 unsigned int gmii; /* 1000 Mbps support */
920 unsigned int vlhash; /* VLAN Hash Filter */
921 unsigned int sma; /* SMA(MDIO) Interface */
922 unsigned int rwk; /* PMT remote wake-up packet */
923 unsigned int mgk; /* PMT magic packet */
924 unsigned int mmc; /* RMON module */
925 unsigned int aoe; /* ARP Offload */
926 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
927 unsigned int eee; /* Energy Efficient Ethernet */
928 unsigned int tx_coe; /* Tx Checksum Offload */
929 unsigned int rx_coe; /* Rx Checksum Offload */
930 unsigned int addn_mac; /* Additional MAC Addresses */
931 unsigned int ts_src; /* Timestamp Source */
932 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
933 unsigned int vxn; /* VXLAN/NVGRE */
934
935 /* HW Feature Register1 */
936 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
937 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
938 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
939 unsigned int dma_width; /* DMA width */
940 unsigned int dcb; /* DCB Feature */
941 unsigned int sph; /* Split Header Feature */
942 unsigned int tso; /* TCP Segmentation Offload */
943 unsigned int dma_debug; /* DMA Debug Registers */
944 unsigned int rss; /* Receive Side Scaling */
945 unsigned int tc_cnt; /* Number of Traffic Classes */
946 unsigned int hash_table_size; /* Hash Table Size */
947 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
948
949 /* HW Feature Register2 */
950 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
951 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
952 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
953 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
954 unsigned int pps_out_num; /* Number of PPS outputs */
955 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
956 };
957
958 struct xgbe_version_data {
959 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
960 enum xgbe_xpcs_access xpcs_access;
961 unsigned int mmc_64bit;
962 unsigned int tx_max_fifo_size;
963 unsigned int rx_max_fifo_size;
964 unsigned int tx_tstamp_workaround;
965 unsigned int tstamp_ptp_clock_freq;
966 unsigned int ecc_support;
967 unsigned int i2c_support;
968 unsigned int irq_reissue_support;
969 unsigned int tx_desc_prefetch;
970 unsigned int rx_desc_prefetch;
971 unsigned int an_cdr_workaround;
972 unsigned int enable_rrc;
973 };
974
975 struct xgbe_prv_data {
976 struct net_device *netdev;
977 struct pci_dev *pcidev;
978 struct platform_device *platdev;
979 struct acpi_device *adev;
980 struct device *dev;
981 struct platform_device *phy_platdev;
982 struct device *phy_dev;
983 unsigned int smn_base;
984
985 /* Version related data */
986 struct xgbe_version_data *vdata;
987
988 /* ACPI or DT flag */
989 unsigned int use_acpi;
990
991 /* XGMAC/XPCS related mmio registers */
992 void __iomem *xgmac_regs; /* XGMAC CSRs */
993 void __iomem *xpcs_regs; /* XPCS MMD registers */
994 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
995 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
996 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
997 void __iomem *xprop_regs; /* XGBE property registers */
998 void __iomem *xi2c_regs; /* XGBE I2C CSRs */
999
1000 /* Port property registers */
1001 unsigned int pp0;
1002 unsigned int pp1;
1003 unsigned int pp2;
1004 unsigned int pp3;
1005 unsigned int pp4;
1006
1007 /* XPCS indirect addressing lock */
1008 spinlock_t xpcs_lock;
1009 unsigned int xpcs_window_def_reg;
1010 unsigned int xpcs_window_sel_reg;
1011 unsigned int xpcs_window;
1012 unsigned int xpcs_window_size;
1013 unsigned int xpcs_window_mask;
1014
1015 /* RSS addressing mutex */
1016 struct mutex rss_mutex;
1017
1018 /* Flags representing xgbe_state */
1019 unsigned long dev_state;
1020
1021 /* ECC support */
1022 unsigned long tx_sec_period;
1023 unsigned long tx_ded_period;
1024 unsigned long rx_sec_period;
1025 unsigned long rx_ded_period;
1026 unsigned long desc_sec_period;
1027 unsigned long desc_ded_period;
1028
1029 unsigned int tx_sec_count;
1030 unsigned int tx_ded_count;
1031 unsigned int rx_sec_count;
1032 unsigned int rx_ded_count;
1033 unsigned int desc_ded_count;
1034 unsigned int desc_sec_count;
1035
1036 int dev_irq;
1037 int ecc_irq;
1038 int i2c_irq;
1039 int channel_irq[XGBE_MAX_DMA_CHANNELS];
1040
1041 unsigned int per_channel_irq;
1042 unsigned int irq_count;
1043 unsigned int channel_irq_count;
1044 unsigned int channel_irq_mode;
1045
1046 char ecc_name[IFNAMSIZ + 32];
1047
1048 struct xgbe_hw_if hw_if;
1049 struct xgbe_phy_if phy_if;
1050 struct xgbe_desc_if desc_if;
1051 struct xgbe_i2c_if i2c_if;
1052
1053 /* AXI DMA settings */
1054 unsigned int coherent;
1055 unsigned int arcr;
1056 unsigned int awcr;
1057 unsigned int awarcr;
1058
1059 /* Service routine support */
1060 struct workqueue_struct *dev_workqueue;
1061 struct work_struct service_work;
1062 struct timer_list service_timer;
1063
1064 /* Rings for Tx/Rx on a DMA channel */
1065 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS];
1066 unsigned int tx_max_channel_count;
1067 unsigned int rx_max_channel_count;
1068 unsigned int channel_count;
1069 unsigned int tx_ring_count;
1070 unsigned int tx_desc_count;
1071 unsigned int rx_ring_count;
1072 unsigned int rx_desc_count;
1073
1074 unsigned int new_tx_ring_count;
1075 unsigned int new_rx_ring_count;
1076
1077 unsigned int tx_max_q_count;
1078 unsigned int rx_max_q_count;
1079 unsigned int tx_q_count;
1080 unsigned int rx_q_count;
1081
1082 /* Tx/Rx common settings */
1083 unsigned int blen;
1084 unsigned int pbl;
1085 unsigned int aal;
1086 unsigned int rd_osr_limit;
1087 unsigned int wr_osr_limit;
1088
1089 /* Tx settings */
1090 unsigned int tx_sf_mode;
1091 unsigned int tx_threshold;
1092 unsigned int tx_osp_mode;
1093 unsigned int tx_max_fifo_size;
1094
1095 /* Rx settings */
1096 unsigned int rx_sf_mode;
1097 unsigned int rx_threshold;
1098 unsigned int rx_max_fifo_size;
1099
1100 /* Tx coalescing settings */
1101 unsigned int tx_usecs;
1102 unsigned int tx_frames;
1103
1104 /* Rx coalescing settings */
1105 unsigned int rx_riwt;
1106 unsigned int rx_usecs;
1107 unsigned int rx_frames;
1108
1109 /* Current Rx buffer size */
1110 unsigned int rx_buf_size;
1111
1112 /* Flow control settings */
1113 unsigned int pause_autoneg;
1114 unsigned int tx_pause;
1115 unsigned int rx_pause;
1116 unsigned int rx_rfa[XGBE_MAX_QUEUES];
1117 unsigned int rx_rfd[XGBE_MAX_QUEUES];
1118
1119 /* Receive Side Scaling settings */
1120 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
1121 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
1122 u32 rss_options;
1123
1124 /* VXLAN settings */
1125 u16 vxlan_port;
1126
1127 /* Netdev related settings */
1128 unsigned char mac_addr[ETH_ALEN];
1129 netdev_features_t netdev_features;
1130 struct napi_struct napi;
1131 struct xgbe_mmc_stats mmc_stats;
1132 struct xgbe_ext_stats ext_stats;
1133
1134 /* Filtering support */
1135 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1136
1137 /* Device clocks */
1138 struct clk *sysclk;
1139 unsigned long sysclk_rate;
1140 struct clk *ptpclk;
1141 unsigned long ptpclk_rate;
1142
1143 /* Timestamp support */
1144 spinlock_t tstamp_lock;
1145 struct ptp_clock_info ptp_clock_info;
1146 struct ptp_clock *ptp_clock;
1147 struct kernel_hwtstamp_config tstamp_config;
1148 unsigned int tstamp_addend;
1149 struct work_struct tx_tstamp_work;
1150 struct sk_buff *tx_tstamp_skb;
1151 u64 tx_tstamp;
1152
1153 /* Pulse Per Second output */
1154 struct xgbe_pps_config pps[XGBE_MAX_PPS_OUT];
1155
1156 /* DCB support */
1157 struct ieee_ets *ets;
1158 struct ieee_pfc *pfc;
1159 unsigned int q2tc_map[XGBE_MAX_QUEUES];
1160 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
1161 unsigned int pfcq[XGBE_MAX_QUEUES];
1162 unsigned int pfc_rfa;
1163 u8 num_tcs;
1164
1165 /* Hardware features of the device */
1166 struct xgbe_hw_features hw_feat;
1167
1168 /* Device work structures */
1169 struct work_struct restart_work;
1170 struct work_struct stopdev_work;
1171
1172 /* Keeps track of power mode */
1173 unsigned int power_down;
1174
1175 /* Network interface message level setting */
1176 u32 msg_enable;
1177
1178 /* Current PHY settings */
1179 phy_interface_t phy_mode;
1180 int phy_link;
1181 int phy_speed;
1182
1183 /* MDIO/PHY related settings */
1184 unsigned int phy_started;
1185 void *phy_data;
1186 struct xgbe_phy phy;
1187 int mdio_mmd;
1188 unsigned long link_check;
1189 struct completion mdio_complete;
1190
1191 unsigned int kr_redrv;
1192
1193 char an_name[IFNAMSIZ + 32];
1194 struct workqueue_struct *an_workqueue;
1195
1196 int an_irq;
1197 struct work_struct an_irq_work;
1198
1199 /* Auto-negotiation state machine support */
1200 unsigned int an_int;
1201 unsigned int an_status;
1202 struct mutex an_mutex;
1203 enum xgbe_an an_result;
1204 enum xgbe_an an_state;
1205 enum xgbe_rx kr_state;
1206 enum xgbe_rx kx_state;
1207 struct work_struct an_work;
1208 unsigned int an_again;
1209 unsigned int an_supported;
1210 unsigned int parallel_detect;
1211 unsigned int fec_ability;
1212 unsigned long an_start;
1213 unsigned long kr_start_time;
1214 enum xgbe_an_mode an_mode;
1215
1216 /* I2C support */
1217 struct xgbe_i2c i2c;
1218 struct mutex i2c_mutex;
1219 struct completion i2c_complete;
1220 char i2c_name[IFNAMSIZ + 32];
1221
1222 unsigned int lpm_ctrl; /* CTRL1 for resume */
1223
1224 unsigned int isr_as_bh_work;
1225 struct work_struct dev_bh_work;
1226 struct work_struct ecc_bh_work;
1227 struct work_struct i2c_bh_work;
1228 struct work_struct an_bh_work;
1229
1230 struct dentry *xgbe_debugfs;
1231
1232 unsigned int debugfs_xgmac_reg;
1233
1234 unsigned int debugfs_xpcs_mmd;
1235 unsigned int debugfs_xpcs_reg;
1236
1237 unsigned int debugfs_xprop_reg;
1238
1239 unsigned int debugfs_xi2c_reg;
1240
1241 bool debugfs_an_cdr_workaround;
1242 bool debugfs_an_cdr_track_early;
1243 bool en_rx_adap;
1244 int rx_adapt_retries;
1245 bool rx_adapt_done;
1246 bool mode_set;
1247 bool sph;
1248 };
1249
1250 /* Function prototypes*/
1251 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *);
1252 void xgbe_free_pdata(struct xgbe_prv_data *);
1253 void xgbe_set_counts(struct xgbe_prv_data *);
1254 int xgbe_config_netdev(struct xgbe_prv_data *);
1255 void xgbe_deconfig_netdev(struct xgbe_prv_data *);
1256
1257 int xgbe_platform_init(void);
1258 void xgbe_platform_exit(void);
1259 #ifdef CONFIG_PCI
1260 int xgbe_pci_init(void);
1261 void xgbe_pci_exit(void);
1262 #else
xgbe_pci_init(void)1263 static inline int xgbe_pci_init(void) { return 0; }
xgbe_pci_exit(void)1264 static inline void xgbe_pci_exit(void) { }
1265 #endif
1266
1267 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
1268 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
1269 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
1270 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
1271 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
1272 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
1273 const struct net_device_ops *xgbe_get_netdev_ops(void);
1274 const struct ethtool_ops *xgbe_get_ethtool_ops(void);
1275 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void);
1276
1277 #ifdef CONFIG_AMD_XGBE_DCB
1278 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
1279 #endif
1280
1281 void xgbe_ptp_register(struct xgbe_prv_data *);
1282 void xgbe_ptp_unregister(struct xgbe_prv_data *);
1283 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1284 unsigned int, unsigned int, unsigned int);
1285 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1286 unsigned int);
1287 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
1288 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
1289 int xgbe_powerup(struct net_device *, unsigned int);
1290 int xgbe_powerdown(struct net_device *, unsigned int);
1291 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
1292 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
1293 void xgbe_restart_dev(struct xgbe_prv_data *pdata);
1294 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata);
1295
1296 /* For Timestamp config */
1297 void xgbe_config_tstamp(struct xgbe_prv_data *pdata, unsigned int mac_tscr);
1298 u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata);
1299 u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata);
1300 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1301 struct xgbe_ring_desc *rdesc);
1302 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1303 struct xgbe_ring_desc *rdesc);
1304 void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1305 unsigned int addend);
1306 void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1307 unsigned int nsec);
1308 void xgbe_tx_tstamp(struct work_struct *work);
1309 int xgbe_get_hwtstamp_settings(struct net_device *netdev,
1310 struct kernel_hwtstamp_config *config);
1311 int xgbe_set_hwtstamp_settings(struct net_device *netdev,
1312 struct kernel_hwtstamp_config *config,
1313 struct netlink_ext_ack *extack);
1314 void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1315 struct sk_buff *skb,
1316 struct xgbe_packet_data *packet);
1317 int xgbe_init_ptp(struct xgbe_prv_data *pdata);
1318 void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1319 unsigned int nsec);
1320
1321 int xgbe_pps_config(struct xgbe_prv_data *pdata, struct xgbe_pps_config *cfg,
1322 int index, bool on);
1323
1324 /* Selftest functions */
1325 void xgbe_selftest_run(struct net_device *dev,
1326 struct ethtool_test *etest, u64 *buf);
1327 void xgbe_selftest_get_strings(struct xgbe_prv_data *pdata, u8 *data);
1328 int xgbe_selftest_get_count(struct xgbe_prv_data *pdata);
1329
1330 /* Loopback control */
1331 int xgbe_enable_mac_loopback(struct xgbe_prv_data *pdata);
1332 void xgbe_disable_mac_loopback(struct xgbe_prv_data *pdata);
1333
1334 #ifdef CONFIG_DEBUG_FS
1335 void xgbe_debugfs_init(struct xgbe_prv_data *);
1336 void xgbe_debugfs_exit(struct xgbe_prv_data *);
1337 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata);
1338 #else
xgbe_debugfs_init(struct xgbe_prv_data * pdata)1339 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_exit(struct xgbe_prv_data * pdata)1340 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_rename(struct xgbe_prv_data * pdata)1341 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {}
1342 #endif /* CONFIG_DEBUG_FS */
1343
1344 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
1345 #if 0
1346 #define YDEBUG
1347 #define YDEBUG_MDIO
1348 #endif
1349
1350 /* For debug prints */
1351 #ifdef YDEBUG
1352 #define DBGPR(x...) pr_alert(x)
1353 #else
1354 #define DBGPR(x...) do { } while (0)
1355 #endif
1356
1357 #ifdef YDEBUG_MDIO
1358 #define DBGPR_MDIO(x...) pr_alert(x)
1359 #else
1360 #define DBGPR_MDIO(x...) do { } while (0)
1361 #endif
1362
1363 #endif
1364