1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver 4 * 5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 6 * Copyright (c) 2025 Collabora Ltd. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/delay.h> 12 #include <linux/of_device.h> 13 #include <linux/clk.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 #include <linux/spinlock.h> 19 #include <sound/pcm_params.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/tlv.h> 22 23 #include "rockchip_sai.h" 24 25 #define DRV_NAME "rockchip-sai" 26 27 #define CLK_SHIFT_RATE_HZ_MAX 5 28 #define FW_RATIO_MAX 8 29 #define FW_RATIO_MIN 1 30 #define MAXBURST_PER_FIFO 8 31 32 #define TIMEOUT_US 1000 33 #define WAIT_TIME_MS_MAX 10000 34 35 #define MAX_LANES 4 36 37 enum fpw_mode { 38 FPW_ONE_BCLK_WIDTH, 39 FPW_ONE_SLOT_WIDTH, 40 FPW_HALF_FRAME_WIDTH, 41 }; 42 43 struct rk_sai_dev { 44 struct device *dev; 45 struct clk *hclk; 46 struct clk *mclk; 47 struct regmap *regmap; 48 struct reset_control *rst_h; 49 struct reset_control *rst_m; 50 struct snd_dmaengine_dai_dma_data capture_dma_data; 51 struct snd_dmaengine_dai_dma_data playback_dma_data; 52 struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1]; 53 unsigned int mclk_rate; 54 unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1]; 55 unsigned int tx_lanes; 56 unsigned int rx_lanes; 57 unsigned int sdi[MAX_LANES]; 58 unsigned int sdo[MAX_LANES]; 59 unsigned int version; 60 enum fpw_mode fpw; 61 int fw_ratio; 62 bool has_capture; 63 bool has_playback; 64 bool is_master_mode; 65 bool is_tdm; 66 bool initialized; 67 /* protects register writes that depend on the state of XFER[1:0] */ 68 spinlock_t xfer_lock; 69 }; 70 71 static bool rockchip_sai_stream_valid(struct snd_pcm_substream *substream, 72 struct snd_soc_dai *dai) 73 { 74 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 75 76 if (!substream) 77 return false; 78 79 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 80 sai->has_playback) 81 return true; 82 83 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 84 sai->has_capture) 85 return true; 86 87 return false; 88 } 89 90 static int rockchip_sai_fsync_lost_detect(struct rk_sai_dev *sai, bool en) 91 { 92 unsigned int fw, cnt; 93 94 if (sai->is_master_mode || sai->version < SAI_VER_2311) 95 return 0; 96 97 regmap_read(sai->regmap, SAI_FSCR, &fw); 98 cnt = SAI_FSCR_FW_V(fw) << 1; /* two fsync lost */ 99 100 regmap_update_bits(sai->regmap, SAI_INTCR, 101 SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC); 102 regmap_update_bits(sai->regmap, SAI_INTCR, 103 SAI_INTCR_FSLOST_MASK, 104 SAI_INTCR_FSLOST(en)); 105 /* 106 * The `cnt` is the number of SCLK cycles of the CRU's SCLK signal that 107 * should be used as timeout. Consequently, in slave mode, this value 108 * is only correct if the CRU SCLK is equal to the external SCLK. 109 */ 110 regmap_update_bits(sai->regmap, SAI_FS_TIMEOUT, 111 SAI_FS_TIMEOUT_VAL_MASK | SAI_FS_TIMEOUT_EN_MASK, 112 SAI_FS_TIMEOUT_VAL(cnt) | SAI_FS_TIMEOUT_EN(en)); 113 114 return 0; 115 } 116 117 static int rockchip_sai_fsync_err_detect(struct rk_sai_dev *sai, 118 bool en) 119 { 120 if (sai->is_master_mode || sai->version < SAI_VER_2311) 121 return 0; 122 123 regmap_update_bits(sai->regmap, SAI_INTCR, 124 SAI_INTCR_FSERRC, SAI_INTCR_FSERRC); 125 regmap_update_bits(sai->regmap, SAI_INTCR, 126 SAI_INTCR_FSERR_MASK, 127 SAI_INTCR_FSERR(en)); 128 129 return 0; 130 } 131 132 static int rockchip_sai_poll_clk_idle(struct rk_sai_dev *sai) 133 { 134 unsigned int reg, idle, val; 135 int ret; 136 137 if (sai->version >= SAI_VER_2307) { 138 reg = SAI_STATUS; 139 idle = SAI_STATUS_FS_IDLE; 140 idle = sai->version >= SAI_VER_2311 ? idle >> 1 : idle; 141 } else { 142 reg = SAI_XFER; 143 idle = SAI_XFER_FS_IDLE; 144 } 145 146 ret = regmap_read_poll_timeout_atomic(sai->regmap, reg, val, 147 (val & idle), 10, TIMEOUT_US); 148 if (ret < 0) 149 dev_warn(sai->dev, "Failed to idle FS\n"); 150 151 return ret; 152 } 153 154 static int rockchip_sai_poll_stream_idle(struct rk_sai_dev *sai, bool playback, bool capture) 155 { 156 unsigned int reg, val; 157 unsigned int idle = 0; 158 int ret; 159 160 if (sai->version >= SAI_VER_2307) { 161 reg = SAI_STATUS; 162 if (playback) 163 idle |= SAI_STATUS_TX_IDLE; 164 if (capture) 165 idle |= SAI_STATUS_RX_IDLE; 166 idle = sai->version >= SAI_VER_2311 ? idle >> 1 : idle; 167 } else { 168 reg = SAI_XFER; 169 if (playback) 170 idle |= SAI_XFER_TX_IDLE; 171 if (capture) 172 idle |= SAI_XFER_RX_IDLE; 173 } 174 175 ret = regmap_read_poll_timeout_atomic(sai->regmap, reg, val, 176 (val & idle), 10, TIMEOUT_US); 177 if (ret < 0) 178 dev_warn(sai->dev, "Failed to idle stream\n"); 179 180 return ret; 181 } 182 183 /** 184 * rockchip_sai_xfer_clk_stop_and_wait() - stop the xfer clock and wait for it to be idle 185 * @sai: pointer to the driver instance's rk_sai_dev struct 186 * @to_restore: pointer to store the CLK/FSS register values in as they were 187 * found before they were cleared, or NULL. 188 * 189 * Clear the XFER_CLK and XFER_FSS registers if needed, then busy-waits for the 190 * XFER clocks to be idle. Before clearing the bits, it stores the state of the 191 * registers as it encountered them in to_restore if it isn't NULL. 192 * 193 * Context: Any context. Expects sai->xfer_lock to be held by caller. 194 */ 195 static void rockchip_sai_xfer_clk_stop_and_wait(struct rk_sai_dev *sai, unsigned int *to_restore) 196 { 197 unsigned int mask = SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK; 198 unsigned int disable = SAI_XFER_CLK_DIS | SAI_XFER_FSS_DIS; 199 unsigned int val; 200 201 assert_spin_locked(&sai->xfer_lock); 202 203 regmap_read(sai->regmap, SAI_XFER, &val); 204 if ((val & mask) == disable) 205 goto wait_for_idle; 206 207 if (sai->is_master_mode) 208 regmap_update_bits(sai->regmap, SAI_XFER, mask, disable); 209 210 wait_for_idle: 211 rockchip_sai_poll_clk_idle(sai); 212 213 if (to_restore) 214 *to_restore = val; 215 } 216 217 static int rockchip_sai_runtime_suspend(struct device *dev) 218 { 219 struct rk_sai_dev *sai = dev_get_drvdata(dev); 220 unsigned long flags; 221 222 rockchip_sai_fsync_lost_detect(sai, 0); 223 rockchip_sai_fsync_err_detect(sai, 0); 224 225 spin_lock_irqsave(&sai->xfer_lock, flags); 226 rockchip_sai_xfer_clk_stop_and_wait(sai, NULL); 227 spin_unlock_irqrestore(&sai->xfer_lock, flags); 228 229 regcache_cache_only(sai->regmap, true); 230 /* 231 * After FS is idle, we should wait at least 2 BCLK cycles to make sure 232 * the CLK gate operation has completed, and only then disable mclk. 233 * 234 * Otherwise, the BCLK is still ungated, and once the mclk is enabled, 235 * there is a risk that a few BCLK cycles leak. This is true especially 236 * at low speeds, such as with a samplerate of 8k. 237 * 238 * Ideally we'd adjust the delay based on the samplerate, but it's such 239 * a tiny value that we can just delay for the maximum clock period 240 * for the sake of simplicity. 241 * 242 * The maximum BCLK period is 31us @ 8K-8Bit (64kHz BCLK). We wait for 243 * 40us to give ourselves a safety margin in case udelay falls short. 244 */ 245 udelay(40); 246 clk_disable_unprepare(sai->mclk); 247 clk_disable_unprepare(sai->hclk); 248 249 return 0; 250 } 251 252 static int rockchip_sai_runtime_resume(struct device *dev) 253 { 254 struct rk_sai_dev *sai = dev_get_drvdata(dev); 255 int ret; 256 257 ret = clk_prepare_enable(sai->hclk); 258 if (ret) 259 goto err_hclk; 260 261 ret = clk_prepare_enable(sai->mclk); 262 if (ret) 263 goto err_mclk; 264 265 regcache_cache_only(sai->regmap, false); 266 regcache_mark_dirty(sai->regmap); 267 ret = regcache_sync(sai->regmap); 268 if (ret) 269 goto err_regmap; 270 271 return 0; 272 273 err_regmap: 274 clk_disable_unprepare(sai->mclk); 275 err_mclk: 276 clk_disable_unprepare(sai->hclk); 277 err_hclk: 278 return ret; 279 } 280 281 static void rockchip_sai_fifo_xrun_detect(struct rk_sai_dev *sai, 282 int stream, bool en) 283 { 284 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 285 /* clear irq status which was asserted before TXUIE enabled */ 286 regmap_update_bits(sai->regmap, SAI_INTCR, 287 SAI_INTCR_TXUIC, SAI_INTCR_TXUIC); 288 regmap_update_bits(sai->regmap, SAI_INTCR, 289 SAI_INTCR_TXUIE_MASK, 290 SAI_INTCR_TXUIE(en)); 291 } else { 292 /* clear irq status which was asserted before RXOIE enabled */ 293 regmap_update_bits(sai->regmap, SAI_INTCR, 294 SAI_INTCR_RXOIC, SAI_INTCR_RXOIC); 295 regmap_update_bits(sai->regmap, SAI_INTCR, 296 SAI_INTCR_RXOIE_MASK, 297 SAI_INTCR_RXOIE(en)); 298 } 299 } 300 301 static void rockchip_sai_dma_ctrl(struct rk_sai_dev *sai, 302 int stream, bool en) 303 { 304 if (!en) 305 rockchip_sai_fifo_xrun_detect(sai, stream, 0); 306 307 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 308 regmap_update_bits(sai->regmap, SAI_DMACR, 309 SAI_DMACR_TDE_MASK, 310 SAI_DMACR_TDE(en)); 311 } else { 312 regmap_update_bits(sai->regmap, SAI_DMACR, 313 SAI_DMACR_RDE_MASK, 314 SAI_DMACR_RDE(en)); 315 } 316 317 if (en) 318 rockchip_sai_fifo_xrun_detect(sai, stream, 1); 319 } 320 321 static void rockchip_sai_reset(struct rk_sai_dev *sai) 322 { 323 /* 324 * It is advised to reset the hclk domain before resetting the mclk 325 * domain, especially in slave mode without a clock input. 326 * 327 * To deal with the aforementioned case of slave mode without a clock 328 * input, we work around a potential issue by resetting the whole 329 * controller, bringing it back into master mode, and then recovering 330 * the controller configuration in the regmap. 331 */ 332 reset_control_assert(sai->rst_h); 333 udelay(10); 334 reset_control_deassert(sai->rst_h); 335 udelay(10); 336 reset_control_assert(sai->rst_m); 337 udelay(10); 338 reset_control_deassert(sai->rst_m); 339 udelay(10); 340 341 /* recover regmap config */ 342 regcache_mark_dirty(sai->regmap); 343 regcache_sync(sai->regmap); 344 } 345 346 static int rockchip_sai_clear(struct rk_sai_dev *sai, unsigned int clr) 347 { 348 unsigned int val = 0; 349 int ret = 0; 350 351 regmap_update_bits(sai->regmap, SAI_CLR, clr, clr); 352 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val, 353 !(val & clr), 10, TIMEOUT_US); 354 if (ret < 0) { 355 dev_warn(sai->dev, "Failed to clear %u\n", clr); 356 rockchip_sai_reset(sai); 357 } 358 359 return ret; 360 } 361 362 static void rockchip_sai_xfer_start(struct rk_sai_dev *sai, int stream) 363 { 364 unsigned int msk, val; 365 366 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 367 msk = SAI_XFER_TXS_MASK; 368 val = SAI_XFER_TXS_EN; 369 370 } else { 371 msk = SAI_XFER_RXS_MASK; 372 val = SAI_XFER_RXS_EN; 373 } 374 375 regmap_update_bits(sai->regmap, SAI_XFER, msk, val); 376 } 377 378 static void rockchip_sai_xfer_stop(struct rk_sai_dev *sai, int stream) 379 { 380 unsigned int msk = 0, val = 0, clr = 0; 381 bool capture = stream == SNDRV_PCM_STREAM_CAPTURE || stream < 0; 382 bool playback = stream == SNDRV_PCM_STREAM_PLAYBACK || stream < 0; 383 /* could be <= 0 but we don't want to depend on enum values */ 384 385 if (playback) { 386 msk |= SAI_XFER_TXS_MASK; 387 val |= SAI_XFER_TXS_DIS; 388 clr |= SAI_CLR_TXC; 389 } 390 if (capture) { 391 msk |= SAI_XFER_RXS_MASK; 392 val |= SAI_XFER_RXS_DIS; 393 clr |= SAI_CLR_RXC; 394 } 395 396 regmap_update_bits(sai->regmap, SAI_XFER, msk, val); 397 rockchip_sai_poll_stream_idle(sai, playback, capture); 398 399 rockchip_sai_clear(sai, clr); 400 } 401 402 static void rockchip_sai_start(struct rk_sai_dev *sai, int stream) 403 { 404 rockchip_sai_dma_ctrl(sai, stream, 1); 405 rockchip_sai_xfer_start(sai, stream); 406 } 407 408 static void rockchip_sai_stop(struct rk_sai_dev *sai, int stream) 409 { 410 rockchip_sai_dma_ctrl(sai, stream, 0); 411 rockchip_sai_xfer_stop(sai, stream); 412 } 413 414 static void rockchip_sai_fmt_create(struct rk_sai_dev *sai, unsigned int fmt) 415 { 416 unsigned int xcr_mask = 0, xcr_val = 0, xsft_mask = 0, xsft_val = 0; 417 unsigned int fscr_mask = 0, fscr_val = 0; 418 419 assert_spin_locked(&sai->xfer_lock); 420 421 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 422 case SND_SOC_DAIFMT_RIGHT_J: 423 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 424 xcr_val = SAI_XCR_VDJ_R | SAI_XCR_EDGE_SHIFT_0; 425 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 426 xsft_val = SAI_XSHIFT_RIGHT(0); 427 fscr_mask = SAI_FSCR_EDGE_MASK; 428 fscr_val = SAI_FSCR_EDGE_DUAL; 429 sai->fpw = FPW_HALF_FRAME_WIDTH; 430 break; 431 case SND_SOC_DAIFMT_LEFT_J: 432 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 433 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0; 434 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 435 xsft_val = SAI_XSHIFT_RIGHT(0); 436 fscr_mask = SAI_FSCR_EDGE_MASK; 437 fscr_val = SAI_FSCR_EDGE_DUAL; 438 sai->fpw = FPW_HALF_FRAME_WIDTH; 439 break; 440 case SND_SOC_DAIFMT_I2S: 441 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 442 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_1; 443 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 444 if (sai->is_tdm) 445 xsft_val = SAI_XSHIFT_RIGHT(1); 446 else 447 xsft_val = SAI_XSHIFT_RIGHT(2); 448 fscr_mask = SAI_FSCR_EDGE_MASK; 449 fscr_val = SAI_FSCR_EDGE_DUAL; 450 sai->fpw = FPW_HALF_FRAME_WIDTH; 451 break; 452 case SND_SOC_DAIFMT_DSP_A: 453 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 454 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0; 455 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 456 xsft_val = SAI_XSHIFT_RIGHT(2); 457 fscr_mask = SAI_FSCR_EDGE_MASK; 458 fscr_val = SAI_FSCR_EDGE_RISING; 459 sai->fpw = FPW_ONE_BCLK_WIDTH; 460 break; 461 case SND_SOC_DAIFMT_DSP_B: 462 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 463 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0; 464 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 465 xsft_val = SAI_XSHIFT_RIGHT(0); 466 fscr_mask = SAI_FSCR_EDGE_MASK; 467 fscr_val = SAI_FSCR_EDGE_RISING; 468 sai->fpw = FPW_ONE_BCLK_WIDTH; 469 break; 470 default: 471 dev_err(sai->dev, "Unsupported fmt %u\n", fmt); 472 break; 473 } 474 475 regmap_update_bits(sai->regmap, SAI_TXCR, xcr_mask, xcr_val); 476 regmap_update_bits(sai->regmap, SAI_RXCR, xcr_mask, xcr_val); 477 regmap_update_bits(sai->regmap, SAI_TX_SHIFT, xsft_mask, xsft_val); 478 regmap_update_bits(sai->regmap, SAI_RX_SHIFT, xsft_mask, xsft_val); 479 regmap_update_bits(sai->regmap, SAI_FSCR, fscr_mask, fscr_val); 480 } 481 482 static int rockchip_sai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 483 { 484 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 485 unsigned int mask = 0, val = 0; 486 unsigned int clk_gates; 487 unsigned long flags; 488 int ret = 0; 489 490 pm_runtime_get_sync(dai->dev); 491 492 mask = SAI_CKR_MSS_MASK; 493 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 494 case SND_SOC_DAIFMT_BP_FP: 495 val = SAI_CKR_MSS_MASTER; 496 sai->is_master_mode = true; 497 break; 498 case SND_SOC_DAIFMT_BC_FC: 499 val = SAI_CKR_MSS_SLAVE; 500 sai->is_master_mode = false; 501 break; 502 default: 503 ret = -EINVAL; 504 goto err_pm_put; 505 } 506 507 spin_lock_irqsave(&sai->xfer_lock, flags); 508 rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates); 509 if (sai->initialized) { 510 if (sai->has_capture && sai->has_playback) 511 rockchip_sai_xfer_stop(sai, -1); 512 else if (sai->has_capture) 513 rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_CAPTURE); 514 else 515 rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_PLAYBACK); 516 } else { 517 rockchip_sai_clear(sai, 0); 518 sai->initialized = true; 519 } 520 521 regmap_update_bits(sai->regmap, SAI_CKR, mask, val); 522 523 mask = SAI_CKR_CKP_MASK | SAI_CKR_FSP_MASK; 524 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 525 case SND_SOC_DAIFMT_NB_NF: 526 val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_NORMAL; 527 break; 528 case SND_SOC_DAIFMT_NB_IF: 529 val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_INVERTED; 530 break; 531 case SND_SOC_DAIFMT_IB_NF: 532 val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_NORMAL; 533 break; 534 case SND_SOC_DAIFMT_IB_IF: 535 val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_INVERTED; 536 break; 537 default: 538 ret = -EINVAL; 539 goto err_xfer_unlock; 540 } 541 542 regmap_update_bits(sai->regmap, SAI_CKR, mask, val); 543 544 rockchip_sai_fmt_create(sai, fmt); 545 546 err_xfer_unlock: 547 if (clk_gates) 548 regmap_update_bits(sai->regmap, SAI_XFER, 549 SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK, 550 clk_gates); 551 spin_unlock_irqrestore(&sai->xfer_lock, flags); 552 err_pm_put: 553 pm_runtime_put(dai->dev); 554 555 return ret; 556 } 557 558 static int rockchip_sai_hw_params(struct snd_pcm_substream *substream, 559 struct snd_pcm_hw_params *params, 560 struct snd_soc_dai *dai) 561 { 562 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 563 struct snd_dmaengine_dai_dma_data *dma_data; 564 unsigned int mclk_rate, mclk_req_rate, bclk_rate, div_bclk; 565 unsigned int ch_per_lane, slot_width; 566 unsigned int val, fscr, reg; 567 unsigned int lanes, req_lanes; 568 unsigned long flags; 569 int ret = 0; 570 571 if (!rockchip_sai_stream_valid(substream, dai)) 572 return 0; 573 574 dma_data = snd_soc_dai_get_dma_data(dai, substream); 575 dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2; 576 577 pm_runtime_get_sync(sai->dev); 578 579 regmap_read(sai->regmap, SAI_DMACR, &val); 580 581 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 582 reg = SAI_TXCR; 583 lanes = sai->tx_lanes; 584 } else { 585 reg = SAI_RXCR; 586 lanes = sai->rx_lanes; 587 } 588 589 if (!sai->is_tdm) { 590 req_lanes = DIV_ROUND_UP(params_channels(params), 2); 591 if (lanes < req_lanes) { 592 dev_err(sai->dev, "not enough lanes (%d) for requested number of %s channels (%d)\n", 593 lanes, reg == SAI_TXCR ? "playback" : "capture", 594 params_channels(params)); 595 ret = -EINVAL; 596 goto err_pm_put; 597 } else { 598 lanes = req_lanes; 599 } 600 } 601 602 dev_dbg(sai->dev, "using %d lanes totalling %d%s channels for %s\n", 603 lanes, params_channels(params), sai->is_tdm ? " (TDM)" : "", 604 reg == SAI_TXCR ? "playback" : "capture"); 605 606 switch (params_format(params)) { 607 case SNDRV_PCM_FORMAT_S8: 608 case SNDRV_PCM_FORMAT_U8: 609 val = SAI_XCR_VDW(8); 610 break; 611 case SNDRV_PCM_FORMAT_S16_LE: 612 val = SAI_XCR_VDW(16); 613 break; 614 case SNDRV_PCM_FORMAT_S24_LE: 615 val = SAI_XCR_VDW(24); 616 break; 617 case SNDRV_PCM_FORMAT_S32_LE: 618 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 619 val = SAI_XCR_VDW(32); 620 break; 621 default: 622 ret = -EINVAL; 623 goto err_pm_put; 624 } 625 626 val |= SAI_XCR_CSR(lanes); 627 628 spin_lock_irqsave(&sai->xfer_lock, flags); 629 630 regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK | SAI_XCR_CSR_MASK, val); 631 632 if (!sai->is_tdm) 633 regmap_update_bits(sai->regmap, reg, SAI_XCR_SBW_MASK, 634 SAI_XCR_SBW(params_physical_width(params))); 635 636 regmap_read(sai->regmap, reg, &val); 637 638 slot_width = SAI_XCR_SBW_V(val); 639 ch_per_lane = params_channels(params) / lanes; 640 641 regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK, 642 SAI_XCR_SNB(ch_per_lane)); 643 644 fscr = SAI_FSCR_FW(sai->fw_ratio * slot_width * ch_per_lane); 645 646 switch (sai->fpw) { 647 case FPW_ONE_BCLK_WIDTH: 648 fscr |= SAI_FSCR_FPW(1); 649 break; 650 case FPW_ONE_SLOT_WIDTH: 651 fscr |= SAI_FSCR_FPW(slot_width); 652 break; 653 case FPW_HALF_FRAME_WIDTH: 654 fscr |= SAI_FSCR_FPW(sai->fw_ratio * slot_width * ch_per_lane / 2); 655 break; 656 default: 657 dev_err(sai->dev, "Invalid Frame Pulse Width %d\n", sai->fpw); 658 ret = -EINVAL; 659 goto err_xfer_unlock; 660 } 661 662 regmap_update_bits(sai->regmap, SAI_FSCR, 663 SAI_FSCR_FW_MASK | SAI_FSCR_FPW_MASK, fscr); 664 665 if (sai->is_master_mode) { 666 bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params); 667 ret = clk_set_rate(sai->mclk, sai->mclk_rate); 668 if (ret) { 669 dev_err(sai->dev, "Failed to set mclk to %u: %pe\n", 670 sai->mclk_rate, ERR_PTR(ret)); 671 goto err_xfer_unlock; 672 } 673 674 mclk_rate = clk_get_rate(sai->mclk); 675 if (mclk_rate < bclk_rate) { 676 dev_err(sai->dev, "Mismatch mclk: %u, at least %u\n", 677 mclk_rate, bclk_rate); 678 ret = -EINVAL; 679 goto err_xfer_unlock; 680 } 681 682 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 683 mclk_req_rate = bclk_rate * div_bclk; 684 685 if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX || 686 mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) { 687 dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n", 688 mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX); 689 ret = -EINVAL; 690 goto err_xfer_unlock; 691 } 692 693 regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK, 694 SAI_CKR_MDIV(div_bclk)); 695 } 696 697 err_xfer_unlock: 698 spin_unlock_irqrestore(&sai->xfer_lock, flags); 699 err_pm_put: 700 pm_runtime_put(sai->dev); 701 702 return ret; 703 } 704 705 static int rockchip_sai_prepare(struct snd_pcm_substream *substream, 706 struct snd_soc_dai *dai) 707 { 708 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 709 unsigned long flags; 710 711 if (!rockchip_sai_stream_valid(substream, dai)) 712 return 0; 713 714 if (sai->is_master_mode) { 715 /* 716 * We should wait for the first BCLK pulse to have definitely 717 * occurred after any DIV settings have potentially been 718 * changed in order to guarantee a clean clock signal once we 719 * ungate the clock. 720 * 721 * Ideally, this would be done depending on the samplerate, but 722 * for the sake of simplicity, we'll just delay for the maximum 723 * possible clock offset time, which is quite a small value. 724 * 725 * The maximum BCLK offset is 15.6us @ 8K-8Bit (64kHz BCLK). We 726 * wait for 20us in order to give us a safety margin in case 727 * udelay falls short. 728 */ 729 udelay(20); 730 spin_lock_irqsave(&sai->xfer_lock, flags); 731 regmap_update_bits(sai->regmap, SAI_XFER, 732 SAI_XFER_CLK_MASK | 733 SAI_XFER_FSS_MASK, 734 SAI_XFER_CLK_EN | 735 SAI_XFER_FSS_EN); 736 spin_unlock_irqrestore(&sai->xfer_lock, flags); 737 } 738 739 rockchip_sai_fsync_lost_detect(sai, 1); 740 rockchip_sai_fsync_err_detect(sai, 1); 741 742 return 0; 743 } 744 745 static void rockchip_sai_path_config(struct rk_sai_dev *sai, 746 int num, bool is_rx) 747 { 748 int i; 749 750 if (is_rx) 751 for (i = 0; i < num; i++) 752 regmap_update_bits(sai->regmap, SAI_PATH_SEL, 753 SAI_RX_PATH_MASK(i), 754 SAI_RX_PATH(i, sai->sdi[i])); 755 else 756 for (i = 0; i < num; i++) 757 regmap_update_bits(sai->regmap, SAI_PATH_SEL, 758 SAI_TX_PATH_MASK(i), 759 SAI_TX_PATH(i, sai->sdo[i])); 760 } 761 762 static int rockchip_sai_path_prepare(struct rk_sai_dev *sai, 763 struct device_node *np, 764 bool is_rx) 765 { 766 const char *path_prop; 767 unsigned int *data; 768 unsigned int *lanes; 769 int i, num, ret; 770 771 if (is_rx) { 772 path_prop = "rockchip,sai-rx-route"; 773 data = sai->sdi; 774 lanes = &sai->rx_lanes; 775 } else { 776 path_prop = "rockchip,sai-tx-route"; 777 data = sai->sdo; 778 lanes = &sai->tx_lanes; 779 } 780 781 num = of_count_phandle_with_args(np, path_prop, NULL); 782 if (num == -ENOENT) { 783 return 0; 784 } else if (num > MAX_LANES || num == 0) { 785 dev_err(sai->dev, "found %d entries in %s, outside of range 1 to %d\n", 786 num, path_prop, MAX_LANES); 787 return -EINVAL; 788 } else if (num < 0) { 789 dev_err(sai->dev, "error in %s property: %pe\n", path_prop, 790 ERR_PTR(num)); 791 return num; 792 } 793 794 *lanes = num; 795 ret = device_property_read_u32_array(sai->dev, path_prop, data, num); 796 if (ret < 0) { 797 dev_err(sai->dev, "failed to read property '%s': %pe\n", 798 path_prop, ERR_PTR(ret)); 799 return ret; 800 } 801 802 for (i = 0; i < num; i++) { 803 if (data[i] >= MAX_LANES) { 804 dev_err(sai->dev, "%s[%d] is %d, should be less than %d\n", 805 path_prop, i, data[i], MAX_LANES); 806 return -EINVAL; 807 } 808 } 809 810 rockchip_sai_path_config(sai, num, is_rx); 811 812 return 0; 813 } 814 815 static int rockchip_sai_parse_paths(struct rk_sai_dev *sai, 816 struct device_node *np) 817 { 818 int ret; 819 820 if (sai->has_playback) { 821 sai->tx_lanes = 1; 822 ret = rockchip_sai_path_prepare(sai, np, false); 823 if (ret < 0) { 824 dev_err(sai->dev, "Failed to prepare TX path: %pe\n", 825 ERR_PTR(ret)); 826 return ret; 827 } 828 } 829 830 if (sai->has_capture) { 831 sai->rx_lanes = 1; 832 ret = rockchip_sai_path_prepare(sai, np, true); 833 if (ret < 0) { 834 dev_err(sai->dev, "Failed to prepare RX path: %pe\n", 835 ERR_PTR(ret)); 836 return ret; 837 } 838 } 839 840 return 0; 841 } 842 843 static int rockchip_sai_trigger(struct snd_pcm_substream *substream, 844 int cmd, struct snd_soc_dai *dai) 845 { 846 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 847 int ret = 0; 848 849 if (!rockchip_sai_stream_valid(substream, dai)) 850 return 0; 851 852 switch (cmd) { 853 case SNDRV_PCM_TRIGGER_START: 854 case SNDRV_PCM_TRIGGER_RESUME: 855 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 856 rockchip_sai_start(sai, substream->stream); 857 break; 858 case SNDRV_PCM_TRIGGER_SUSPEND: 859 case SNDRV_PCM_TRIGGER_STOP: 860 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 861 rockchip_sai_stop(sai, substream->stream); 862 break; 863 default: 864 ret = -EINVAL; 865 break; 866 } 867 868 return ret; 869 } 870 871 872 static int rockchip_sai_dai_probe(struct snd_soc_dai *dai) 873 { 874 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 875 876 snd_soc_dai_init_dma_data(dai, 877 sai->has_playback ? &sai->playback_dma_data : NULL, 878 sai->has_capture ? &sai->capture_dma_data : NULL); 879 880 return 0; 881 } 882 883 static int rockchip_sai_startup(struct snd_pcm_substream *substream, 884 struct snd_soc_dai *dai) 885 { 886 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 887 int stream = substream->stream; 888 889 if (!rockchip_sai_stream_valid(substream, dai)) 890 return 0; 891 892 if (sai->substreams[stream]) 893 return -EBUSY; 894 895 if (sai->wait_time[stream]) 896 substream->wait_time = sai->wait_time[stream]; 897 898 sai->substreams[stream] = substream; 899 900 return 0; 901 } 902 903 static void rockchip_sai_shutdown(struct snd_pcm_substream *substream, 904 struct snd_soc_dai *dai) 905 { 906 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 907 908 if (!rockchip_sai_stream_valid(substream, dai)) 909 return; 910 911 sai->substreams[substream->stream] = NULL; 912 } 913 914 static int rockchip_sai_set_tdm_slot(struct snd_soc_dai *dai, 915 unsigned int tx_mask, unsigned int rx_mask, 916 int slots, int slot_width) 917 { 918 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 919 unsigned long flags; 920 unsigned int clk_gates; 921 int sw = slot_width; 922 923 if (!slots) { 924 /* Disabling TDM, set slot width back to 32 bits */ 925 sai->is_tdm = false; 926 sw = 32; 927 } else { 928 sai->is_tdm = true; 929 } 930 931 if (sw < 16 || sw > 32) 932 return -EINVAL; 933 934 pm_runtime_get_sync(dai->dev); 935 spin_lock_irqsave(&sai->xfer_lock, flags); 936 rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates); 937 regmap_update_bits(sai->regmap, SAI_TXCR, SAI_XCR_SBW_MASK, 938 SAI_XCR_SBW(sw)); 939 regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK, 940 SAI_XCR_SBW(sw)); 941 regmap_update_bits(sai->regmap, SAI_XFER, 942 SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK, 943 clk_gates); 944 spin_unlock_irqrestore(&sai->xfer_lock, flags); 945 pm_runtime_put(dai->dev); 946 947 return 0; 948 } 949 950 static int rockchip_sai_set_sysclk(struct snd_soc_dai *dai, int stream, 951 unsigned int freq, int dir) 952 { 953 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 954 955 sai->mclk_rate = freq; 956 957 return 0; 958 } 959 960 static const struct snd_soc_dai_ops rockchip_sai_dai_ops = { 961 .probe = rockchip_sai_dai_probe, 962 .startup = rockchip_sai_startup, 963 .shutdown = rockchip_sai_shutdown, 964 .hw_params = rockchip_sai_hw_params, 965 .set_fmt = rockchip_sai_set_fmt, 966 .set_sysclk = rockchip_sai_set_sysclk, 967 .prepare = rockchip_sai_prepare, 968 .trigger = rockchip_sai_trigger, 969 .set_tdm_slot = rockchip_sai_set_tdm_slot, 970 }; 971 972 static const struct snd_soc_dai_driver rockchip_sai_dai = { 973 .ops = &rockchip_sai_dai_ops, 974 .symmetric_rate = 1, 975 }; 976 977 static bool rockchip_sai_wr_reg(struct device *dev, unsigned int reg) 978 { 979 switch (reg) { 980 case SAI_TXCR: 981 case SAI_FSCR: 982 case SAI_RXCR: 983 case SAI_MONO_CR: 984 case SAI_XFER: 985 case SAI_CLR: 986 case SAI_CKR: 987 case SAI_DMACR: 988 case SAI_INTCR: 989 case SAI_TXDR: 990 case SAI_PATH_SEL: 991 case SAI_TX_SLOT_MASK0: 992 case SAI_TX_SLOT_MASK1: 993 case SAI_TX_SLOT_MASK2: 994 case SAI_TX_SLOT_MASK3: 995 case SAI_RX_SLOT_MASK0: 996 case SAI_RX_SLOT_MASK1: 997 case SAI_RX_SLOT_MASK2: 998 case SAI_RX_SLOT_MASK3: 999 case SAI_TX_SHIFT: 1000 case SAI_RX_SHIFT: 1001 case SAI_FSXN: 1002 case SAI_FS_TIMEOUT: 1003 case SAI_LOOPBACK_LR: 1004 return true; 1005 default: 1006 return false; 1007 } 1008 } 1009 1010 static bool rockchip_sai_rd_reg(struct device *dev, unsigned int reg) 1011 { 1012 switch (reg) { 1013 case SAI_TXCR: 1014 case SAI_FSCR: 1015 case SAI_RXCR: 1016 case SAI_MONO_CR: 1017 case SAI_XFER: 1018 case SAI_CLR: 1019 case SAI_CKR: 1020 case SAI_TXFIFOLR: 1021 case SAI_RXFIFOLR: 1022 case SAI_DMACR: 1023 case SAI_INTCR: 1024 case SAI_INTSR: 1025 case SAI_TXDR: 1026 case SAI_RXDR: 1027 case SAI_PATH_SEL: 1028 case SAI_TX_SLOT_MASK0: 1029 case SAI_TX_SLOT_MASK1: 1030 case SAI_TX_SLOT_MASK2: 1031 case SAI_TX_SLOT_MASK3: 1032 case SAI_RX_SLOT_MASK0: 1033 case SAI_RX_SLOT_MASK1: 1034 case SAI_RX_SLOT_MASK2: 1035 case SAI_RX_SLOT_MASK3: 1036 case SAI_TX_DATA_CNT: 1037 case SAI_RX_DATA_CNT: 1038 case SAI_TX_SHIFT: 1039 case SAI_RX_SHIFT: 1040 case SAI_STATUS: 1041 case SAI_VERSION: 1042 case SAI_FSXN: 1043 case SAI_FS_TIMEOUT: 1044 case SAI_LOOPBACK_LR: 1045 return true; 1046 default: 1047 return false; 1048 } 1049 } 1050 1051 static bool rockchip_sai_volatile_reg(struct device *dev, unsigned int reg) 1052 { 1053 switch (reg) { 1054 case SAI_XFER: 1055 case SAI_INTCR: 1056 case SAI_INTSR: 1057 case SAI_CLR: 1058 case SAI_TXFIFOLR: 1059 case SAI_RXFIFOLR: 1060 case SAI_TXDR: 1061 case SAI_RXDR: 1062 case SAI_TX_DATA_CNT: 1063 case SAI_RX_DATA_CNT: 1064 case SAI_STATUS: 1065 case SAI_VERSION: 1066 return true; 1067 default: 1068 return false; 1069 } 1070 } 1071 1072 static bool rockchip_sai_precious_reg(struct device *dev, unsigned int reg) 1073 { 1074 switch (reg) { 1075 case SAI_RXDR: 1076 return true; 1077 default: 1078 return false; 1079 } 1080 } 1081 1082 static const struct reg_default rockchip_sai_reg_defaults[] = { 1083 { SAI_TXCR, 0x00000bff }, 1084 { SAI_FSCR, 0x0001f03f }, 1085 { SAI_RXCR, 0x00000bff }, 1086 { SAI_PATH_SEL, 0x0000e4e4 }, 1087 }; 1088 1089 static const struct regmap_config rockchip_sai_regmap_config = { 1090 .reg_bits = 32, 1091 .reg_stride = 4, 1092 .val_bits = 32, 1093 .max_register = SAI_LOOPBACK_LR, 1094 .reg_defaults = rockchip_sai_reg_defaults, 1095 .num_reg_defaults = ARRAY_SIZE(rockchip_sai_reg_defaults), 1096 .writeable_reg = rockchip_sai_wr_reg, 1097 .readable_reg = rockchip_sai_rd_reg, 1098 .volatile_reg = rockchip_sai_volatile_reg, 1099 .precious_reg = rockchip_sai_precious_reg, 1100 .cache_type = REGCACHE_FLAT, 1101 }; 1102 1103 static int rockchip_sai_init_dai(struct rk_sai_dev *sai, struct resource *res, 1104 struct snd_soc_dai_driver **dp) 1105 { 1106 struct device_node *node = sai->dev->of_node; 1107 struct snd_soc_dai_driver *dai; 1108 struct property *dma_names; 1109 const char *dma_name; 1110 1111 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 1112 if (!strcmp(dma_name, "tx")) 1113 sai->has_playback = true; 1114 if (!strcmp(dma_name, "rx")) 1115 sai->has_capture = true; 1116 } 1117 1118 dai = devm_kmemdup(sai->dev, &rockchip_sai_dai, 1119 sizeof(*dai), GFP_KERNEL); 1120 if (!dai) 1121 return -ENOMEM; 1122 1123 if (sai->has_playback) { 1124 dai->playback.stream_name = "Playback"; 1125 dai->playback.channels_min = 1; 1126 dai->playback.channels_max = 512; 1127 dai->playback.rates = SNDRV_PCM_RATE_8000_384000; 1128 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 | 1129 SNDRV_PCM_FMTBIT_S16_LE | 1130 SNDRV_PCM_FMTBIT_S24_LE | 1131 SNDRV_PCM_FMTBIT_S32_LE | 1132 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 1133 1134 sai->playback_dma_data.addr = res->start + SAI_TXDR; 1135 sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1136 sai->playback_dma_data.maxburst = MAXBURST_PER_FIFO; 1137 } 1138 1139 if (sai->has_capture) { 1140 dai->capture.stream_name = "Capture"; 1141 dai->capture.channels_min = 1; 1142 dai->capture.channels_max = 512; 1143 dai->capture.rates = SNDRV_PCM_RATE_8000_384000; 1144 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 | 1145 SNDRV_PCM_FMTBIT_S16_LE | 1146 SNDRV_PCM_FMTBIT_S24_LE | 1147 SNDRV_PCM_FMTBIT_S32_LE | 1148 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 1149 1150 sai->capture_dma_data.addr = res->start + SAI_RXDR; 1151 sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1152 sai->capture_dma_data.maxburst = MAXBURST_PER_FIFO; 1153 } 1154 1155 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_TDL_MASK, 1156 SAI_DMACR_TDL(16)); 1157 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_RDL_MASK, 1158 SAI_DMACR_RDL(16)); 1159 1160 if (dp) 1161 *dp = dai; 1162 1163 return 0; 1164 } 1165 1166 static const char * const mono_text[] = { "Disable", "Enable" }; 1167 1168 static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0); 1169 1170 static const char * const lplrc_text[] = { "L:MIC R:LP", "L:LP R:MIC" }; 1171 static const char * const lplr_text[] = { "Disable", "Enable" }; 1172 1173 static const char * const lpx_text[] = { 1174 "From SDO0", "From SDO1", "From SDO2", "From SDO3" }; 1175 1176 static const char * const lps_text[] = { "Disable", "Enable" }; 1177 static const char * const sync_out_text[] = { "From CRU", "From IO" }; 1178 static const char * const sync_in_text[] = { "From IO", "From Sync Port" }; 1179 1180 static const char * const rpaths_text[] = { 1181 "From SDI0", "From SDI1", "From SDI2", "From SDI3" }; 1182 1183 static const char * const tpaths_text[] = { 1184 "From PATH0", "From PATH1", "From PATH2", "From PATH3" }; 1185 1186 /* MONO_CR */ 1187 static SOC_ENUM_SINGLE_DECL(rmono_switch, SAI_MONO_CR, 1, mono_text); 1188 static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text); 1189 1190 /* PATH_SEL */ 1191 static SOC_ENUM_SINGLE_DECL(lp3_enum, SAI_PATH_SEL, 28, lpx_text); 1192 static SOC_ENUM_SINGLE_DECL(lp2_enum, SAI_PATH_SEL, 26, lpx_text); 1193 static SOC_ENUM_SINGLE_DECL(lp1_enum, SAI_PATH_SEL, 24, lpx_text); 1194 static SOC_ENUM_SINGLE_DECL(lp0_enum, SAI_PATH_SEL, 22, lpx_text); 1195 static SOC_ENUM_SINGLE_DECL(lp3_switch, SAI_PATH_SEL, 21, lps_text); 1196 static SOC_ENUM_SINGLE_DECL(lp2_switch, SAI_PATH_SEL, 20, lps_text); 1197 static SOC_ENUM_SINGLE_DECL(lp1_switch, SAI_PATH_SEL, 19, lps_text); 1198 static SOC_ENUM_SINGLE_DECL(lp0_switch, SAI_PATH_SEL, 18, lps_text); 1199 static SOC_ENUM_SINGLE_DECL(sync_out_switch, SAI_PATH_SEL, 17, sync_out_text); 1200 static SOC_ENUM_SINGLE_DECL(sync_in_switch, SAI_PATH_SEL, 16, sync_in_text); 1201 static SOC_ENUM_SINGLE_DECL(rpath3_enum, SAI_PATH_SEL, 14, rpaths_text); 1202 static SOC_ENUM_SINGLE_DECL(rpath2_enum, SAI_PATH_SEL, 12, rpaths_text); 1203 static SOC_ENUM_SINGLE_DECL(rpath1_enum, SAI_PATH_SEL, 10, rpaths_text); 1204 static SOC_ENUM_SINGLE_DECL(rpath0_enum, SAI_PATH_SEL, 8, rpaths_text); 1205 static SOC_ENUM_SINGLE_DECL(tpath3_enum, SAI_PATH_SEL, 6, tpaths_text); 1206 static SOC_ENUM_SINGLE_DECL(tpath2_enum, SAI_PATH_SEL, 4, tpaths_text); 1207 static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text); 1208 static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text); 1209 1210 /* LOOPBACK_LR */ 1211 static SOC_ENUM_SINGLE_DECL(lp3lrc_enum, SAI_LOOPBACK_LR, 7, lplrc_text); 1212 static SOC_ENUM_SINGLE_DECL(lp2lrc_enum, SAI_LOOPBACK_LR, 6, lplrc_text); 1213 static SOC_ENUM_SINGLE_DECL(lp1lrc_enum, SAI_LOOPBACK_LR, 5, lplrc_text); 1214 static SOC_ENUM_SINGLE_DECL(lp0lrc_enum, SAI_LOOPBACK_LR, 4, lplrc_text); 1215 static SOC_ENUM_SINGLE_DECL(lp3lr_switch, SAI_LOOPBACK_LR, 3, lplr_text); 1216 static SOC_ENUM_SINGLE_DECL(lp2lr_switch, SAI_LOOPBACK_LR, 2, lplr_text); 1217 static SOC_ENUM_SINGLE_DECL(lp1lr_switch, SAI_LOOPBACK_LR, 1, lplr_text); 1218 static SOC_ENUM_SINGLE_DECL(lp0lr_switch, SAI_LOOPBACK_LR, 0, lplr_text); 1219 1220 static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol, 1221 struct snd_ctl_elem_info *uinfo) 1222 { 1223 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1224 uinfo->count = 1; 1225 uinfo->value.integer.min = 0; 1226 uinfo->value.integer.max = WAIT_TIME_MS_MAX; 1227 uinfo->value.integer.step = 1; 1228 1229 return 0; 1230 } 1231 1232 static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol, 1233 struct snd_ctl_elem_value *ucontrol) 1234 { 1235 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1236 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component); 1237 1238 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE]; 1239 1240 return 0; 1241 } 1242 1243 static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol, 1244 struct snd_ctl_elem_value *ucontrol) 1245 { 1246 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1247 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component); 1248 1249 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX) 1250 return -EINVAL; 1251 1252 sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0]; 1253 1254 return 1; 1255 } 1256 1257 static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol, 1258 struct snd_ctl_elem_value *ucontrol) 1259 { 1260 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1261 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component); 1262 1263 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK]; 1264 1265 return 0; 1266 } 1267 1268 static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol, 1269 struct snd_ctl_elem_value *ucontrol) 1270 { 1271 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1272 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component); 1273 1274 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX) 1275 return -EINVAL; 1276 1277 sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0]; 1278 1279 return 1; 1280 } 1281 1282 #define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put) \ 1283 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, \ 1284 .info = rockchip_sai_wait_time_info, \ 1285 .get = xhandler_get, .put = xhandler_put } 1286 1287 static const struct snd_kcontrol_new rockchip_sai_controls[] = { 1288 SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR, 1289 2, 128, 0, rmss_tlv), 1290 SOC_ENUM("Receive Mono Switch", rmono_switch), 1291 SOC_ENUM("Transmit Mono Switch", tmono_switch), 1292 1293 SOC_ENUM("SDI3 Loopback I2S LR Channel Sel", lp3lrc_enum), 1294 SOC_ENUM("SDI2 Loopback I2S LR Channel Sel", lp2lrc_enum), 1295 SOC_ENUM("SDI1 Loopback I2S LR Channel Sel", lp1lrc_enum), 1296 SOC_ENUM("SDI0 Loopback I2S LR Channel Sel", lp0lrc_enum), 1297 SOC_ENUM("SDI3 Loopback I2S LR Switch", lp3lr_switch), 1298 SOC_ENUM("SDI2 Loopback I2S LR Switch", lp2lr_switch), 1299 SOC_ENUM("SDI1 Loopback I2S LR Switch", lp1lr_switch), 1300 SOC_ENUM("SDI0 Loopback I2S LR Switch", lp0lr_switch), 1301 1302 SOC_ENUM("SDI3 Loopback Src Select", lp3_enum), 1303 SOC_ENUM("SDI2 Loopback Src Select", lp2_enum), 1304 SOC_ENUM("SDI1 Loopback Src Select", lp1_enum), 1305 SOC_ENUM("SDI0 Loopback Src Select", lp0_enum), 1306 SOC_ENUM("SDI3 Loopback Switch", lp3_switch), 1307 SOC_ENUM("SDI2 Loopback Switch", lp2_switch), 1308 SOC_ENUM("SDI1 Loopback Switch", lp1_switch), 1309 SOC_ENUM("SDI0 Loopback Switch", lp0_switch), 1310 SOC_ENUM("Sync Out Switch", sync_out_switch), 1311 SOC_ENUM("Sync In Switch", sync_in_switch), 1312 SOC_ENUM("Receive PATH3 Source Select", rpath3_enum), 1313 SOC_ENUM("Receive PATH2 Source Select", rpath2_enum), 1314 SOC_ENUM("Receive PATH1 Source Select", rpath1_enum), 1315 SOC_ENUM("Receive PATH0 Source Select", rpath0_enum), 1316 SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum), 1317 SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum), 1318 SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum), 1319 SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum), 1320 1321 SAI_PCM_WAIT_TIME("PCM Read Wait Time MS", 1322 rockchip_sai_rd_wait_time_get, 1323 rockchip_sai_rd_wait_time_put), 1324 SAI_PCM_WAIT_TIME("PCM Write Wait Time MS", 1325 rockchip_sai_wr_wait_time_get, 1326 rockchip_sai_wr_wait_time_put), 1327 }; 1328 1329 static const struct snd_soc_component_driver rockchip_sai_component = { 1330 .name = DRV_NAME, 1331 .controls = rockchip_sai_controls, 1332 .num_controls = ARRAY_SIZE(rockchip_sai_controls), 1333 .legacy_dai_naming = 1, 1334 }; 1335 1336 static irqreturn_t rockchip_sai_isr(int irq, void *devid) 1337 { 1338 struct rk_sai_dev *sai = (struct rk_sai_dev *)devid; 1339 struct snd_pcm_substream *substream; 1340 u32 val; 1341 1342 regmap_read(sai->regmap, SAI_INTSR, &val); 1343 if (val & SAI_INTSR_TXUI_ACT) { 1344 dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n"); 1345 regmap_update_bits(sai->regmap, SAI_INTCR, 1346 SAI_INTCR_TXUIC, SAI_INTCR_TXUIC); 1347 regmap_update_bits(sai->regmap, SAI_INTCR, 1348 SAI_INTCR_TXUIE_MASK, 1349 SAI_INTCR_TXUIE(0)); 1350 substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 1351 if (substream) 1352 snd_pcm_stop_xrun(substream); 1353 } 1354 1355 if (val & SAI_INTSR_RXOI_ACT) { 1356 dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n"); 1357 regmap_update_bits(sai->regmap, SAI_INTCR, 1358 SAI_INTCR_RXOIC, SAI_INTCR_RXOIC); 1359 regmap_update_bits(sai->regmap, SAI_INTCR, 1360 SAI_INTCR_RXOIE_MASK, 1361 SAI_INTCR_RXOIE(0)); 1362 substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE]; 1363 if (substream) 1364 snd_pcm_stop_xrun(substream); 1365 } 1366 1367 if (val & SAI_INTSR_FSERRI_ACT) { 1368 dev_warn_ratelimited(sai->dev, "Frame Sync Error\n"); 1369 regmap_update_bits(sai->regmap, SAI_INTCR, 1370 SAI_INTCR_FSERRC, SAI_INTCR_FSERRC); 1371 regmap_update_bits(sai->regmap, SAI_INTCR, 1372 SAI_INTCR_FSERR_MASK, 1373 SAI_INTCR_FSERR(0)); 1374 } 1375 1376 if (val & SAI_INTSR_FSLOSTI_ACT) { 1377 dev_warn_ratelimited(sai->dev, "Frame Sync Lost\n"); 1378 regmap_update_bits(sai->regmap, SAI_INTCR, 1379 SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC); 1380 regmap_update_bits(sai->regmap, SAI_INTCR, 1381 SAI_INTCR_FSLOST_MASK, 1382 SAI_INTCR_FSLOST(0)); 1383 } 1384 1385 return IRQ_HANDLED; 1386 } 1387 1388 static int rockchip_sai_probe(struct platform_device *pdev) 1389 { 1390 struct device_node *node = pdev->dev.of_node; 1391 struct rk_sai_dev *sai; 1392 struct snd_soc_dai_driver *dai; 1393 struct resource *res; 1394 void __iomem *regs; 1395 int ret, irq; 1396 1397 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1398 if (!sai) 1399 return -ENOMEM; 1400 1401 sai->dev = &pdev->dev; 1402 sai->fw_ratio = 1; 1403 /* match to register default */ 1404 sai->is_master_mode = true; 1405 dev_set_drvdata(&pdev->dev, sai); 1406 1407 spin_lock_init(&sai->xfer_lock); 1408 1409 sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h"); 1410 if (IS_ERR(sai->rst_h)) 1411 return dev_err_probe(&pdev->dev, PTR_ERR(sai->rst_h), 1412 "Error in 'h' reset control\n"); 1413 1414 sai->rst_m = devm_reset_control_get_optional_exclusive(&pdev->dev, "m"); 1415 if (IS_ERR(sai->rst_m)) 1416 return dev_err_probe(&pdev->dev, PTR_ERR(sai->rst_m), 1417 "Error in 'm' reset control\n"); 1418 1419 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1420 if (IS_ERR(regs)) 1421 return dev_err_probe(&pdev->dev, PTR_ERR(regs), 1422 "Failed to get and ioremap resource\n"); 1423 1424 sai->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1425 &rockchip_sai_regmap_config); 1426 if (IS_ERR(sai->regmap)) 1427 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap), 1428 "Failed to initialize regmap\n"); 1429 1430 irq = platform_get_irq_optional(pdev, 0); 1431 if (irq > 0) { 1432 ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr, 1433 IRQF_SHARED, node->name, sai); 1434 if (ret) 1435 return dev_err_probe(&pdev->dev, ret, 1436 "Failed to request irq %d\n", irq); 1437 } else { 1438 dev_dbg(&pdev->dev, "Asked for an IRQ but got %d\n", irq); 1439 } 1440 1441 sai->mclk = devm_clk_get(&pdev->dev, "mclk"); 1442 if (IS_ERR(sai->mclk)) 1443 return dev_err_probe(&pdev->dev, PTR_ERR(sai->mclk), 1444 "Failed to get mclk\n"); 1445 1446 sai->hclk = devm_clk_get_enabled(&pdev->dev, "hclk"); 1447 if (IS_ERR(sai->hclk)) 1448 return dev_err_probe(&pdev->dev, PTR_ERR(sai->hclk), 1449 "Failed to get hclk\n"); 1450 1451 regmap_read(sai->regmap, SAI_VERSION, &sai->version); 1452 1453 ret = rockchip_sai_init_dai(sai, res, &dai); 1454 if (ret) 1455 return dev_err_probe(&pdev->dev, ret, "Failed to initialize DAI\n"); 1456 1457 ret = rockchip_sai_parse_paths(sai, node); 1458 if (ret) 1459 return dev_err_probe(&pdev->dev, ret, "Failed to parse paths\n"); 1460 1461 /* 1462 * From here on, all register accesses need to be wrapped in 1463 * pm_runtime_get_sync/pm_runtime_put calls 1464 * 1465 * NB: we don't rely on _resume_and_get in case of !CONFIG_PM 1466 */ 1467 devm_pm_runtime_enable(&pdev->dev); 1468 pm_runtime_get_noresume(&pdev->dev); 1469 ret = rockchip_sai_runtime_resume(&pdev->dev); 1470 if (ret) 1471 return dev_err_probe(&pdev->dev, ret, "Failed to resume device\n"); 1472 1473 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1474 if (ret) { 1475 dev_err(&pdev->dev, "Failed to register PCM: %d\n", ret); 1476 goto err_runtime_suspend; 1477 } 1478 1479 ret = devm_snd_soc_register_component(&pdev->dev, 1480 &rockchip_sai_component, 1481 dai, 1); 1482 if (ret) { 1483 dev_err(&pdev->dev, "Failed to register component: %d\n", ret); 1484 goto err_runtime_suspend; 1485 } 1486 1487 pm_runtime_use_autosuspend(&pdev->dev); 1488 pm_runtime_put(&pdev->dev); 1489 1490 clk_disable_unprepare(sai->hclk); 1491 1492 return 0; 1493 1494 err_runtime_suspend: 1495 if (IS_ENABLED(CONFIG_PM)) 1496 pm_runtime_put(&pdev->dev); 1497 else 1498 rockchip_sai_runtime_suspend(&pdev->dev); 1499 1500 return ret; 1501 } 1502 1503 static void rockchip_sai_remove(struct platform_device *pdev) 1504 { 1505 #ifndef CONFIG_PM 1506 rockchip_sai_runtime_suspend(&pdev->dev); 1507 #endif 1508 } 1509 1510 static const struct dev_pm_ops rockchip_sai_pm_ops = { 1511 SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL) 1512 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1513 }; 1514 1515 static const struct of_device_id rockchip_sai_match[] = { 1516 { .compatible = "rockchip,rk3576-sai", }, 1517 {}, 1518 }; 1519 MODULE_DEVICE_TABLE(of, rockchip_sai_match); 1520 1521 static struct platform_driver rockchip_sai_driver = { 1522 .probe = rockchip_sai_probe, 1523 .remove = rockchip_sai_remove, 1524 .driver = { 1525 .name = DRV_NAME, 1526 .of_match_table = rockchip_sai_match, 1527 .pm = &rockchip_sai_pm_ops, 1528 }, 1529 }; 1530 module_platform_driver(rockchip_sai_driver); 1531 1532 MODULE_DESCRIPTION("Rockchip SAI ASoC Interface"); 1533 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>"); 1534 MODULE_AUTHOR("Nicolas Frattaroli <nicolas.frattaroli@collabora.com>"); 1535 MODULE_LICENSE("GPL"); 1536