1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2024 Intel Corporation 4 */ 5 6 #include <kunit/visibility.h> 7 #include <linux/pci.h> 8 9 #include <drm/drm_managed.h> 10 #include <drm/drm_print.h> 11 12 #include "regs/xe_bars.h" 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_regs.h" 15 #include "xe_assert.h" 16 #include "xe_device.h" 17 #include "xe_force_wake.h" 18 #include "xe_gt_mcr.h" 19 #include "xe_mmio.h" 20 #include "xe_sriov.h" 21 #include "xe_tile_sriov_vf.h" 22 #include "xe_ttm_vram_mgr.h" 23 #include "xe_vram.h" 24 #include "xe_vram_types.h" 25 26 static bool resource_is_valid(struct pci_dev *pdev, int bar) 27 { 28 if (!pci_resource_flags(pdev, bar)) 29 return false; 30 31 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 32 return false; 33 34 if (!pci_resource_len(pdev, bar)) 35 return false; 36 37 return true; 38 } 39 40 static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region *lmem_bar) 41 { 42 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 43 44 if (!resource_is_valid(pdev, LMEM_BAR)) { 45 drm_err(&xe->drm, "pci resource is not valid\n"); 46 return -ENXIO; 47 } 48 49 lmem_bar->io_start = pci_resource_start(pdev, LMEM_BAR); 50 lmem_bar->io_size = pci_resource_len(pdev, LMEM_BAR); 51 if (!lmem_bar->io_size) 52 return -EIO; 53 54 /* XXX: Need to change when xe link code is ready */ 55 lmem_bar->dpa_base = 0; 56 57 /* set up a map to the total memory area. */ 58 lmem_bar->mapping = devm_ioremap_wc(&pdev->dev, lmem_bar->io_start, lmem_bar->io_size); 59 60 return 0; 61 } 62 63 static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset) 64 { 65 struct xe_device *xe = gt_to_xe(gt); 66 u64 offset; 67 u32 reg; 68 69 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 70 if (!fw_ref.domains) 71 return -ETIMEDOUT; 72 73 if (GRAPHICS_VER(xe) >= 20) { 74 u64 ccs_size = tile_size / 512; 75 u64 offset_hi, offset_lo; 76 u32 nodes, num_enabled; 77 78 reg = xe_mmio_read32(>->mmio, MIRROR_FUSE3); 79 nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg); 80 num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */ 81 82 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 83 offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg); 84 85 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER); 86 offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg); 87 88 offset = offset_hi << 32; /* HW view bits 39:32 */ 89 offset |= offset_lo << 6; /* HW view bits 31:6 */ 90 offset *= num_enabled; /* convert to SW view */ 91 offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */ 92 93 /* We don't expect any holes */ 94 xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE) - 95 ccs_size), 96 "Hole between CCS and GSM.\n"); 97 } else { 98 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR); 99 offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; 100 } 101 102 *poffset = offset; 103 104 return 0; 105 } 106 107 /* 108 * tile_vram_size() - Collect vram size and offset information 109 * @tile: tile to get info for 110 * @vram_size: available vram (size - device reserved portions) 111 * @tile_size: actual vram size 112 * @tile_offset: physical start point in the vram address space 113 * 114 * There are 4 places for size information: 115 * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1) 116 * - TILEx size (actual vram size) 117 * - GSMBASE offset (TILEx - "stolen") 118 * - CSSBASE offset (TILEx - CSS space necessary) 119 * 120 * CSSBASE is always a lower/smaller offset then GSMBASE. 121 * 122 * The actual available size of memory is to the CCS or GSM base. 123 * NOTE: multi-tile bases will include the tile offset. 124 * 125 */ 126 static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 127 u64 *tile_size, u64 *tile_offset) 128 { 129 struct xe_device *xe = tile_to_xe(tile); 130 struct xe_gt *gt = tile->primary_gt; 131 u64 offset; 132 u32 reg; 133 134 if (IS_SRIOV_VF(xe)) { 135 struct xe_tile *t; 136 int id; 137 138 offset = 0; 139 for_each_tile(t, xe, id) 140 for_each_if(t->id < tile->id) 141 offset += xe_tile_sriov_vf_lmem(t); 142 143 *tile_size = xe_tile_sriov_vf_lmem(tile); 144 *vram_size = *tile_size; 145 *tile_offset = offset; 146 147 return 0; 148 } 149 150 /* actual size */ 151 if (unlikely(xe->info.platform == XE_DG1)) { 152 *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR); 153 *tile_offset = 0; 154 } else { 155 reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id)); 156 *tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G; 157 *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; 158 } 159 160 /* minus device usage */ 161 if (xe->info.has_flat_ccs) { 162 int ret = get_flat_ccs_offset(gt, *tile_size, &offset); 163 164 if (ret) 165 return ret; 166 } else { 167 offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE); 168 } 169 170 /* remove the tile offset so we have just the available size */ 171 *vram_size = offset - *tile_offset; 172 173 return 0; 174 } 175 176 static void vram_fini(void *arg) 177 { 178 struct xe_device *xe = arg; 179 struct xe_tile *tile; 180 int id; 181 182 xe->mem.vram->mapping = NULL; 183 184 for_each_tile(tile, xe, id) { 185 tile->mem.vram->mapping = NULL; 186 if (tile->mem.kernel_vram) 187 tile->mem.kernel_vram->mapping = NULL; 188 } 189 } 190 191 struct xe_vram_region *xe_vram_region_alloc(struct xe_device *xe, u8 id, u32 placement) 192 { 193 struct xe_vram_region *vram; 194 struct drm_device *drm = &xe->drm; 195 196 xe_assert(xe, id < xe->info.tile_count); 197 198 vram = drmm_kzalloc(drm, sizeof(*vram), GFP_KERNEL); 199 if (!vram) 200 return NULL; 201 202 vram->xe = xe; 203 vram->id = id; 204 vram->placement = placement; 205 #if defined(CONFIG_DRM_XE_PAGEMAP) 206 vram->migrate = xe->tiles[id].migrate; 207 #endif 208 return vram; 209 } 210 211 static void print_vram_region_info(struct xe_device *xe, struct xe_vram_region *vram) 212 { 213 struct drm_device *drm = &xe->drm; 214 215 if (vram->io_size < vram->usable_size) 216 drm_info(drm, "Small BAR device\n"); 217 218 drm_info(drm, 219 "VRAM[%u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", 220 vram->id, &vram->actual_physical_size, &vram->usable_size, &vram->io_size); 221 drm_info(drm, "VRAM[%u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", 222 vram->id, &vram->dpa_base, vram->dpa_base + (u64)vram->actual_physical_size, 223 &vram->io_start, vram->io_start + (u64)vram->io_size); 224 } 225 226 static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram, 227 struct xe_vram_region *lmem_bar, u64 offset, u64 usable_size, 228 u64 region_size, resource_size_t remain_io_size) 229 { 230 /* Check if VRAM region is already initialized */ 231 if (vram->mapping) 232 return 0; 233 234 vram->actual_physical_size = region_size; 235 vram->io_start = lmem_bar->io_start + offset; 236 vram->io_size = min_t(u64, usable_size, remain_io_size); 237 238 if (!vram->io_size) { 239 drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n"); 240 return -ENODEV; 241 } 242 243 vram->dpa_base = lmem_bar->dpa_base + offset; 244 vram->mapping = lmem_bar->mapping + offset; 245 vram->usable_size = usable_size; 246 247 print_vram_region_info(xe, vram); 248 249 return 0; 250 } 251 252 /** 253 * xe_vram_probe() - Probe VRAM configuration 254 * @xe: the &xe_device 255 * 256 * Collect VRAM size and offset information for all tiles. 257 * 258 * Return: 0 on success, error code on failure 259 */ 260 int xe_vram_probe(struct xe_device *xe) 261 { 262 struct xe_tile *tile; 263 struct xe_vram_region lmem_bar; 264 resource_size_t remain_io_size; 265 u64 available_size = 0; 266 u64 total_size = 0; 267 int err; 268 u8 id; 269 270 if (!IS_DGFX(xe)) 271 return 0; 272 273 err = determine_lmem_bar_size(xe, &lmem_bar); 274 if (err) 275 return err; 276 drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &lmem_bar.io_start, &lmem_bar.io_size); 277 278 remain_io_size = lmem_bar.io_size; 279 280 for_each_tile(tile, xe, id) { 281 u64 region_size; 282 u64 usable_size; 283 u64 tile_offset; 284 285 err = tile_vram_size(tile, &usable_size, ®ion_size, &tile_offset); 286 if (err) 287 return err; 288 289 total_size += region_size; 290 available_size += usable_size; 291 292 err = vram_region_init(xe, tile->mem.vram, &lmem_bar, tile_offset, usable_size, 293 region_size, remain_io_size); 294 if (err) 295 return err; 296 297 if (total_size > lmem_bar.io_size) { 298 drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n", 299 &total_size, &lmem_bar.io_size); 300 } 301 302 remain_io_size -= min_t(u64, tile->mem.vram->actual_physical_size, remain_io_size); 303 } 304 305 err = vram_region_init(xe, xe->mem.vram, &lmem_bar, 0, available_size, total_size, 306 lmem_bar.io_size); 307 if (err) 308 return err; 309 310 return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe); 311 } 312 313 /** 314 * xe_vram_region_io_start - Get the IO start of a VRAM region 315 * @vram: the VRAM region 316 * 317 * Return: the IO start of the VRAM region, or 0 if not valid 318 */ 319 resource_size_t xe_vram_region_io_start(const struct xe_vram_region *vram) 320 { 321 return vram ? vram->io_start : 0; 322 } 323 324 /** 325 * xe_vram_region_io_size - Get the IO size of a VRAM region 326 * @vram: the VRAM region 327 * 328 * Return: the IO size of the VRAM region, or 0 if not valid 329 */ 330 resource_size_t xe_vram_region_io_size(const struct xe_vram_region *vram) 331 { 332 return vram ? vram->io_size : 0; 333 } 334 335 /** 336 * xe_vram_region_dpa_base - Get the DPA base of a VRAM region 337 * @vram: the VRAM region 338 * 339 * Return: the DPA base of the VRAM region, or 0 if not valid 340 */ 341 resource_size_t xe_vram_region_dpa_base(const struct xe_vram_region *vram) 342 { 343 return vram ? vram->dpa_base : 0; 344 } 345 346 /** 347 * xe_vram_region_usable_size - Get the usable size of a VRAM region 348 * @vram: the VRAM region 349 * 350 * Return: the usable size of the VRAM region, or 0 if not valid 351 */ 352 resource_size_t xe_vram_region_usable_size(const struct xe_vram_region *vram) 353 { 354 return vram ? vram->usable_size : 0; 355 } 356 357 /** 358 * xe_vram_region_actual_physical_size - Get the actual physical size of a VRAM region 359 * @vram: the VRAM region 360 * 361 * Return: the actual physical size of the VRAM region, or 0 if not valid 362 */ 363 resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region *vram) 364 { 365 return vram ? vram->actual_physical_size : 0; 366 } 367 EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size); 368