xref: /linux/drivers/gpu/drm/xe/xe_hw_engine.h (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #ifndef _XE_HW_ENGINE_H_
7 #define _XE_HW_ENGINE_H_
8 
9 #include "xe_hw_engine_types.h"
10 
11 struct drm_printer;
12 struct drm_xe_engine_class_instance;
13 struct xe_device;
14 
15 #ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MIN
16 #define XE_HW_ENGINE_JOB_TIMEOUT_MIN CONFIG_DRM_XE_JOB_TIMEOUT_MIN
17 #else
18 #define XE_HW_ENGINE_JOB_TIMEOUT_MIN 1
19 #endif
20 #ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MAX
21 #define XE_HW_ENGINE_JOB_TIMEOUT_MAX CONFIG_DRM_XE_JOB_TIMEOUT_MAX
22 #else
23 #define XE_HW_ENGINE_JOB_TIMEOUT_MAX (10 * 1000)
24 #endif
25 #ifdef CONFIG_DRM_XE_TIMESLICE_MIN
26 #define XE_HW_ENGINE_TIMESLICE_MIN CONFIG_DRM_XE_TIMESLICE_MIN
27 #else
28 #define XE_HW_ENGINE_TIMESLICE_MIN 1
29 #endif
30 #ifdef CONFIG_DRM_XE_TIMESLICE_MAX
31 #define XE_HW_ENGINE_TIMESLICE_MAX CONFIG_DRM_XE_TIMESLICE_MAX
32 #else
33 #define XE_HW_ENGINE_TIMESLICE_MAX (10 * 1000 * 1000)
34 #endif
35 #ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT
36 #define XE_HW_ENGINE_PREEMPT_TIMEOUT CONFIG_DRM_XE_PREEMPT_TIMEOUT
37 #else
38 #define XE_HW_ENGINE_PREEMPT_TIMEOUT (640 * 1000)
39 #endif
40 #ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN
41 #define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN
42 #else
43 #define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN 1
44 #endif
45 #ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX
46 #define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX
47 #else
48 #define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX (10 * 1000 * 1000)
49 #endif
50 
51 int xe_hw_engines_init_early(struct xe_gt *gt);
52 int xe_hw_engines_init(struct xe_gt *gt);
53 void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec);
54 void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe);
55 u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,
56 				enum xe_engine_class engine_class);
57 
58 struct xe_hw_engine_snapshot *
59 xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe);
60 void xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot *snapshot);
61 void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,
62 				 struct drm_printer *p);
63 void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p);
64 void xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe);
65 
66 bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe);
67 
68 struct xe_hw_engine *
69 xe_hw_engine_lookup(struct xe_device *xe,
70 		    struct drm_xe_engine_class_instance eci);
71 
xe_hw_engine_is_valid(struct xe_hw_engine * hwe)72 static inline bool xe_hw_engine_is_valid(struct xe_hw_engine *hwe)
73 {
74 	return hwe->name;
75 }
76 
77 const char *xe_hw_engine_class_to_str(enum xe_engine_class class);
78 u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe);
79 enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe);
80 
81 void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val);
82 u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);
83 
84 #endif
85