1 /*
2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/bpf_trace.h>
34 #include <net/xdp_sock_drv.h>
35 #include "en/xdp.h"
36 #include "en/params.h"
37 #include <linux/bitfield.h>
38 #include <net/page_pool/helpers.h>
39
mlx5e_xdp_max_mtu(struct mlx5e_params * params,struct mlx5e_rq_opt_param * rqo)40 int mlx5e_xdp_max_mtu(struct mlx5e_params *params,
41 struct mlx5e_rq_opt_param *rqo)
42 {
43 int hr = mlx5e_get_linear_rq_headroom(params, rqo);
44
45 /* Let S := SKB_DATA_ALIGN(sizeof(struct skb_shared_info)).
46 * The condition checked in mlx5e_rx_is_linear_skb is:
47 * SKB_DATA_ALIGN(sw_mtu + hard_mtu + hr) + S <= PAGE_SIZE (1)
48 * (Note that hw_mtu == sw_mtu + hard_mtu.)
49 * What is returned from this function is:
50 * max_mtu = PAGE_SIZE - S - hr - hard_mtu (2)
51 * After assigning sw_mtu := max_mtu, the left side of (1) turns to
52 * SKB_DATA_ALIGN(PAGE_SIZE - S) + S, which is equal to PAGE_SIZE,
53 * because both PAGE_SIZE and S are already aligned. Any number greater
54 * than max_mtu would make the left side of (1) greater than PAGE_SIZE,
55 * so max_mtu is the maximum MTU allowed.
56 */
57
58 return MLX5E_HW2SW_MTU(params, SKB_MAX_HEAD(hr));
59 }
60
61 static inline bool
mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq * sq,struct mlx5e_rq * rq,struct xdp_buff * xdp)62 mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq,
63 struct xdp_buff *xdp)
64 {
65 struct page *page = virt_to_page(xdp->data);
66 struct mlx5e_xmit_data_frags xdptxdf = {};
67 struct mlx5e_xmit_data *xdptxd;
68 struct xdp_frame *xdpf;
69 dma_addr_t dma_addr;
70 int i;
71
72 xdpf = xdp_convert_buff_to_frame(xdp);
73 if (unlikely(!xdpf))
74 return false;
75
76 xdptxd = &xdptxdf.xd;
77 xdptxd->data = xdpf->data;
78 xdptxd->len = xdpf->len;
79 xdptxd->has_frags = xdp_frame_has_frags(xdpf);
80
81 if (xdp->rxq->mem.type == MEM_TYPE_XSK_BUFF_POOL) {
82 /* The xdp_buff was in the UMEM and was copied into a newly
83 * allocated page. The UMEM page was returned via the ZCA, and
84 * this new page has to be mapped at this point and has to be
85 * unmapped and returned via xdp_return_frame on completion.
86 */
87
88 /* Prevent double recycling of the UMEM page. Even in case this
89 * function returns false, the xdp_buff shouldn't be recycled,
90 * as it was already done in xdp_convert_zc_to_xdp_frame.
91 */
92 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
93
94 if (unlikely(xdptxd->has_frags))
95 return false;
96
97 dma_addr = dma_map_single(sq->pdev, xdptxd->data, xdptxd->len,
98 DMA_TO_DEVICE);
99 if (dma_mapping_error(sq->pdev, dma_addr)) {
100 xdp_return_frame(xdpf);
101 return false;
102 }
103
104 xdptxd->dma_addr = dma_addr;
105
106 if (unlikely(!INDIRECT_CALL_2(sq->xmit_xdp_frame,
107 mlx5e_xmit_xdp_frame_mpwqe,
108 mlx5e_xmit_xdp_frame,
109 sq, xdptxd, 0, NULL))) {
110 dma_unmap_single(sq->pdev, dma_addr, xdptxd->len,
111 DMA_TO_DEVICE);
112 xdp_return_frame(xdpf);
113 return false;
114 }
115
116 /* xmit_mode == MLX5E_XDP_XMIT_MODE_FRAME */
117 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
118 (union mlx5e_xdp_info) { .mode = MLX5E_XDP_XMIT_MODE_FRAME });
119 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
120 (union mlx5e_xdp_info) { .frame.xdpf = xdpf });
121 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
122 (union mlx5e_xdp_info) { .frame.dma_addr = dma_addr });
123 return true;
124 }
125
126 /* Driver assumes that xdp_convert_buff_to_frame returns an xdp_frame
127 * that points to the same memory region as the original xdp_buff. It
128 * allows to map the memory only once and to use the DMA_BIDIRECTIONAL
129 * mode.
130 */
131
132 dma_addr = page_pool_get_dma_addr(page) + offset_in_page(xdpf->data);
133 dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd->len, DMA_BIDIRECTIONAL);
134
135 if (xdptxd->has_frags) {
136 xdptxdf.sinfo = xdp_get_shared_info_from_frame(xdpf);
137 xdptxdf.dma_arr = NULL;
138
139 for (i = 0; i < xdptxdf.sinfo->nr_frags; i++) {
140 skb_frag_t *frag = &xdptxdf.sinfo->frags[i];
141 dma_addr_t addr;
142 u32 len;
143
144 addr = page_pool_get_dma_addr(skb_frag_page(frag)) +
145 skb_frag_off(frag);
146 len = skb_frag_size(frag);
147 dma_sync_single_for_device(sq->pdev, addr, len,
148 DMA_BIDIRECTIONAL);
149 }
150 }
151
152 xdptxd->dma_addr = dma_addr;
153
154 if (unlikely(!INDIRECT_CALL_2(sq->xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,
155 mlx5e_xmit_xdp_frame, sq, xdptxd, 0, NULL)))
156 return false;
157
158 /* xmit_mode == MLX5E_XDP_XMIT_MODE_PAGE */
159 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
160 (union mlx5e_xdp_info) { .mode = MLX5E_XDP_XMIT_MODE_PAGE });
161
162 if (xdptxd->has_frags) {
163 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
164 (union mlx5e_xdp_info)
165 { .page.num = 1 + xdptxdf.sinfo->nr_frags });
166 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
167 (union mlx5e_xdp_info) { .page.page = page });
168 for (i = 0; i < xdptxdf.sinfo->nr_frags; i++) {
169 skb_frag_t *frag = &xdptxdf.sinfo->frags[i];
170
171 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
172 (union mlx5e_xdp_info)
173 { .page.page = skb_frag_page(frag) });
174 }
175 } else {
176 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
177 (union mlx5e_xdp_info) { .page.num = 1 });
178 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
179 (union mlx5e_xdp_info) { .page.page = page });
180 }
181
182 return true;
183 }
184
mlx5e_xdp_rx_timestamp(const struct xdp_md * ctx,u64 * timestamp)185 static int mlx5e_xdp_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp)
186 {
187 const struct mlx5e_xdp_buff *_ctx = (void *)ctx;
188
189 if (unlikely(!mlx5e_rx_hw_stamp(_ctx->rq->hwtstamp_config)))
190 return -ENODATA;
191
192 *timestamp = mlx5e_cqe_ts_to_ns(_ctx->rq->ptp_cyc2time,
193 _ctx->rq->clock, get_cqe_ts(_ctx->cqe));
194 return 0;
195 }
196
197 /* Mapping HW RSS Type bits CQE_RSS_HTYPE_IP + CQE_RSS_HTYPE_L4 into 4-bits*/
198 #define RSS_TYPE_MAX_TABLE 16 /* 4-bits max 16 entries */
199 #define RSS_L4 GENMASK(1, 0)
200 #define RSS_L3 GENMASK(3, 2) /* Same as CQE_RSS_HTYPE_IP */
201
202 /* Valid combinations of CQE_RSS_HTYPE_IP + CQE_RSS_HTYPE_L4 sorted numerical */
203 enum mlx5_rss_hash_type {
204 RSS_TYPE_NO_HASH = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IP_NONE) |
205 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_NONE)),
206 RSS_TYPE_L3_IPV4 = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV4) |
207 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_NONE)),
208 RSS_TYPE_L4_IPV4_TCP = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV4) |
209 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_TCP)),
210 RSS_TYPE_L4_IPV4_UDP = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV4) |
211 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_UDP)),
212 RSS_TYPE_L4_IPV4_IPSEC = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV4) |
213 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_IPSEC)),
214 RSS_TYPE_L3_IPV6 = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV6) |
215 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_NONE)),
216 RSS_TYPE_L4_IPV6_TCP = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV6) |
217 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_TCP)),
218 RSS_TYPE_L4_IPV6_UDP = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV6) |
219 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_UDP)),
220 RSS_TYPE_L4_IPV6_IPSEC = (FIELD_PREP_CONST(RSS_L3, CQE_RSS_IPV6) |
221 FIELD_PREP_CONST(RSS_L4, CQE_RSS_L4_IPSEC)),
222 };
223
224 /* Invalid combinations will simply return zero, allows no boundary checks */
225 static const enum xdp_rss_hash_type mlx5_xdp_rss_type[RSS_TYPE_MAX_TABLE] = {
226 [RSS_TYPE_NO_HASH] = XDP_RSS_TYPE_NONE,
227 [1] = XDP_RSS_TYPE_NONE, /* Implicit zero */
228 [2] = XDP_RSS_TYPE_NONE, /* Implicit zero */
229 [3] = XDP_RSS_TYPE_NONE, /* Implicit zero */
230 [RSS_TYPE_L3_IPV4] = XDP_RSS_TYPE_L3_IPV4,
231 [RSS_TYPE_L4_IPV4_TCP] = XDP_RSS_TYPE_L4_IPV4_TCP,
232 [RSS_TYPE_L4_IPV4_UDP] = XDP_RSS_TYPE_L4_IPV4_UDP,
233 [RSS_TYPE_L4_IPV4_IPSEC] = XDP_RSS_TYPE_L4_IPV4_IPSEC,
234 [RSS_TYPE_L3_IPV6] = XDP_RSS_TYPE_L3_IPV6,
235 [RSS_TYPE_L4_IPV6_TCP] = XDP_RSS_TYPE_L4_IPV6_TCP,
236 [RSS_TYPE_L4_IPV6_UDP] = XDP_RSS_TYPE_L4_IPV6_UDP,
237 [RSS_TYPE_L4_IPV6_IPSEC] = XDP_RSS_TYPE_L4_IPV6_IPSEC,
238 [12] = XDP_RSS_TYPE_NONE, /* Implicit zero */
239 [13] = XDP_RSS_TYPE_NONE, /* Implicit zero */
240 [14] = XDP_RSS_TYPE_NONE, /* Implicit zero */
241 [15] = XDP_RSS_TYPE_NONE, /* Implicit zero */
242 };
243
mlx5e_xdp_rx_hash(const struct xdp_md * ctx,u32 * hash,enum xdp_rss_hash_type * rss_type)244 static int mlx5e_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,
245 enum xdp_rss_hash_type *rss_type)
246 {
247 const struct mlx5e_xdp_buff *_ctx = (void *)ctx;
248 const struct mlx5_cqe64 *cqe = _ctx->cqe;
249 u32 hash_type, l4_type, ip_type, lookup;
250
251 if (unlikely(!(_ctx->xdp.rxq->dev->features & NETIF_F_RXHASH)))
252 return -ENODATA;
253
254 *hash = be32_to_cpu(cqe->rss_hash_result);
255
256 hash_type = cqe->rss_hash_type;
257 BUILD_BUG_ON(CQE_RSS_HTYPE_IP != RSS_L3); /* same mask */
258 ip_type = hash_type & CQE_RSS_HTYPE_IP;
259 l4_type = FIELD_GET(CQE_RSS_HTYPE_L4, hash_type);
260 lookup = ip_type | l4_type;
261 *rss_type = mlx5_xdp_rss_type[lookup];
262
263 return 0;
264 }
265
mlx5e_xdp_rx_vlan_tag(const struct xdp_md * ctx,__be16 * vlan_proto,u16 * vlan_tci)266 static int mlx5e_xdp_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto,
267 u16 *vlan_tci)
268 {
269 const struct mlx5e_xdp_buff *_ctx = (void *)ctx;
270 const struct mlx5_cqe64 *cqe = _ctx->cqe;
271
272 if (!cqe_has_vlan(cqe))
273 return -ENODATA;
274
275 *vlan_proto = htons(ETH_P_8021Q);
276 *vlan_tci = be16_to_cpu(cqe->vlan_info);
277 return 0;
278 }
279
280 const struct xdp_metadata_ops mlx5e_xdp_metadata_ops = {
281 .xmo_rx_timestamp = mlx5e_xdp_rx_timestamp,
282 .xmo_rx_hash = mlx5e_xdp_rx_hash,
283 .xmo_rx_vlan_tag = mlx5e_xdp_rx_vlan_tag,
284 };
285
286 struct mlx5e_xsk_tx_complete {
287 struct mlx5_cqe64 *cqe;
288 struct mlx5e_cq *cq;
289 };
290
mlx5e_xsk_fill_timestamp(void * _priv)291 static u64 mlx5e_xsk_fill_timestamp(void *_priv)
292 {
293 struct mlx5e_xsk_tx_complete *priv = _priv;
294 u64 ts;
295
296 ts = get_cqe_ts(priv->cqe);
297
298 if (mlx5_is_real_time_rq(priv->cq->mdev) || mlx5_is_real_time_sq(priv->cq->mdev))
299 return mlx5_real_time_cyc2time(priv->cq->mdev->clock, ts);
300
301 return mlx5_timecounter_cyc2time(priv->cq->mdev->clock, ts);
302 }
303
mlx5e_xsk_request_checksum(u16 csum_start,u16 csum_offset,void * priv)304 static void mlx5e_xsk_request_checksum(u16 csum_start, u16 csum_offset, void *priv)
305 {
306 struct mlx5_wqe_eth_seg *eseg = priv;
307
308 /* HW/FW is doing parsing, so offsets are largely ignored. */
309 eseg->cs_flags |= MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
310 }
311
312 const struct xsk_tx_metadata_ops mlx5e_xsk_tx_metadata_ops = {
313 .tmo_fill_timestamp = mlx5e_xsk_fill_timestamp,
314 .tmo_request_checksum = mlx5e_xsk_request_checksum,
315 };
316
317 /* returns true if packet was consumed by xdp */
mlx5e_xdp_handle(struct mlx5e_rq * rq,struct bpf_prog * prog,struct mlx5e_xdp_buff * mxbuf)318 bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
319 struct bpf_prog *prog, struct mlx5e_xdp_buff *mxbuf)
320 {
321 struct xdp_buff *xdp = &mxbuf->xdp;
322 u32 act;
323 int err;
324
325 act = bpf_prog_run_xdp(prog, xdp);
326 switch (act) {
327 case XDP_PASS:
328 return false;
329 case XDP_TX:
330 if (unlikely(!mlx5e_xmit_xdp_buff(rq->xdpsq, rq, xdp)))
331 goto xdp_abort;
332 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
333 return true;
334 case XDP_REDIRECT:
335 /* When XDP enabled then page-refcnt==1 here */
336 err = xdp_do_redirect(rq->netdev, xdp, prog);
337 if (unlikely(err))
338 goto xdp_abort;
339 __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
340 __set_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
341 rq->stats->xdp_redirect++;
342 return true;
343 default:
344 bpf_warn_invalid_xdp_action(rq->netdev, prog, act);
345 fallthrough;
346 case XDP_ABORTED:
347 xdp_abort:
348 trace_xdp_exception(rq->netdev, prog, act);
349 fallthrough;
350 case XDP_DROP:
351 rq->stats->xdp_drop++;
352 return true;
353 }
354 }
355
mlx5e_xdpsq_get_next_pi(struct mlx5e_xdpsq * sq,u16 size)356 static u16 mlx5e_xdpsq_get_next_pi(struct mlx5e_xdpsq *sq, u16 size)
357 {
358 struct mlx5_wq_cyc *wq = &sq->wq;
359 u16 pi, contig_wqebbs;
360
361 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
362 contig_wqebbs = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
363 if (unlikely(contig_wqebbs < size)) {
364 struct mlx5e_xdp_wqe_info *wi, *edge_wi;
365
366 wi = &sq->db.wqe_info[pi];
367 edge_wi = wi + contig_wqebbs;
368
369 /* Fill SQ frag edge with NOPs to avoid WQE wrapping two pages. */
370 for (; wi < edge_wi; wi++) {
371 *wi = (struct mlx5e_xdp_wqe_info) {
372 .num_wqebbs = 1,
373 .num_pkts = 0,
374 };
375 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
376 }
377 sq->stats->nops += contig_wqebbs;
378
379 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
380 }
381
382 return pi;
383 }
384
mlx5e_xdp_mpwqe_session_start(struct mlx5e_xdpsq * sq)385 static void mlx5e_xdp_mpwqe_session_start(struct mlx5e_xdpsq *sq)
386 {
387 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
388 struct mlx5e_xdpsq_stats *stats = sq->stats;
389 struct mlx5e_tx_wqe *wqe;
390 u16 pi;
391
392 pi = mlx5e_xdpsq_get_next_pi(sq, sq->max_sq_mpw_wqebbs);
393 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
394 net_prefetchw(wqe->data);
395
396 *session = (struct mlx5e_tx_mpwqe) {
397 .wqe = wqe,
398 .bytes_count = 0,
399 .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT,
400 .ds_count_max = sq->max_sq_mpw_wqebbs * MLX5_SEND_WQEBB_NUM_DS,
401 .pkt_count = 0,
402 .inline_on = mlx5e_xdp_get_inline_state(sq, session->inline_on),
403 };
404
405 stats->mpwqe++;
406 }
407
mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq * sq)408 void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq)
409 {
410 struct mlx5_wq_cyc *wq = &sq->wq;
411 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
412 struct mlx5_wqe_ctrl_seg *cseg = &session->wqe->ctrl;
413 u16 ds_count = session->ds_count;
414 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
415 struct mlx5e_xdp_wqe_info *wi = &sq->db.wqe_info[pi];
416
417 cseg->opmod_idx_opcode =
418 cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
419 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
420
421 wi->num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS);
422 wi->num_pkts = session->pkt_count;
423
424 sq->pc += wi->num_wqebbs;
425
426 sq->doorbell_cseg = cseg;
427
428 session->wqe = NULL; /* Close session */
429 }
430
431 enum {
432 MLX5E_XDP_CHECK_OK = 1,
433 MLX5E_XDP_CHECK_START_MPWQE = 2,
434 };
435
mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq * sq)436 INDIRECT_CALLABLE_SCOPE int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq)
437 {
438 if (unlikely(!sq->mpwqe.wqe)) {
439 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc,
440 sq->stop_room))) {
441 /* SQ is full, ring doorbell */
442 mlx5e_xmit_xdp_doorbell(sq);
443 sq->stats->full++;
444 return -EBUSY;
445 }
446
447 return MLX5E_XDP_CHECK_START_MPWQE;
448 }
449
450 return MLX5E_XDP_CHECK_OK;
451 }
452
453 INDIRECT_CALLABLE_SCOPE bool
454 mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
455 int check_result, struct xsk_tx_metadata **meta);
456
457 INDIRECT_CALLABLE_SCOPE bool
mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq * sq,struct mlx5e_xmit_data * xdptxd,int check_result,struct xsk_tx_metadata ** meta)458 mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
459 int check_result, struct xsk_tx_metadata **meta)
460 {
461 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
462 struct mlx5e_xdpsq_stats *stats = sq->stats;
463 struct mlx5e_xmit_data *p = xdptxd;
464 struct mlx5e_xmit_data tmp;
465
466 if (xdptxd->has_frags) {
467 struct mlx5e_xmit_data_frags *xdptxdf =
468 container_of(xdptxd, struct mlx5e_xmit_data_frags, xd);
469
470 if (!!xdptxd->len + xdptxdf->sinfo->nr_frags > 1) {
471 /* MPWQE is enabled, but a multi-buffer packet is queued for
472 * transmission. MPWQE can't send fragmented packets, so close
473 * the current session and fall back to a regular WQE.
474 */
475 if (unlikely(sq->mpwqe.wqe))
476 mlx5e_xdp_mpwqe_complete(sq);
477 return mlx5e_xmit_xdp_frame(sq, xdptxd, 0, meta);
478 }
479 if (!xdptxd->len) {
480 skb_frag_t *frag = &xdptxdf->sinfo->frags[0];
481
482 tmp.data = skb_frag_address(frag);
483 tmp.len = skb_frag_size(frag);
484 tmp.dma_addr = xdptxdf->dma_arr ? xdptxdf->dma_arr[0] :
485 page_pool_get_dma_addr(skb_frag_page(frag)) +
486 skb_frag_off(frag);
487 p = &tmp;
488 }
489 }
490
491 if (unlikely(p->len > sq->hw_mtu)) {
492 stats->err++;
493 return false;
494 }
495
496 if (!check_result)
497 check_result = mlx5e_xmit_xdp_frame_check_mpwqe(sq);
498 if (unlikely(check_result < 0))
499 return false;
500
501 if (check_result == MLX5E_XDP_CHECK_START_MPWQE) {
502 /* Start the session when nothing can fail, so it's guaranteed
503 * that if there is an active session, it has at least one dseg,
504 * and it's safe to complete it at any time.
505 */
506 mlx5e_xdp_mpwqe_session_start(sq);
507 if (meta)
508 xsk_tx_metadata_request(sq->xsk_pool, meta,
509 &mlx5e_xsk_tx_metadata_ops,
510 &session->wqe->eth);
511 }
512
513 mlx5e_xdp_mpwqe_add_dseg(sq, p, stats);
514
515 if (unlikely(mlx5e_xdp_mpwqe_is_full(session)))
516 mlx5e_xdp_mpwqe_complete(sq);
517
518 stats->xmit++;
519 return true;
520 }
521
mlx5e_xmit_xdp_frame_check_stop_room(struct mlx5e_xdpsq * sq,int stop_room)522 static int mlx5e_xmit_xdp_frame_check_stop_room(struct mlx5e_xdpsq *sq, int stop_room)
523 {
524 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, stop_room))) {
525 /* SQ is full, ring doorbell */
526 mlx5e_xmit_xdp_doorbell(sq);
527 sq->stats->full++;
528 return -EBUSY;
529 }
530
531 return MLX5E_XDP_CHECK_OK;
532 }
533
mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq * sq)534 INDIRECT_CALLABLE_SCOPE int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq)
535 {
536 return mlx5e_xmit_xdp_frame_check_stop_room(sq, 1);
537 }
538
539 INDIRECT_CALLABLE_SCOPE bool
mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq * sq,struct mlx5e_xmit_data * xdptxd,int check_result,struct xsk_tx_metadata ** meta)540 mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,
541 int check_result, struct xsk_tx_metadata **meta)
542 {
543 struct mlx5e_xmit_data_frags *xdptxdf =
544 container_of(xdptxd, struct mlx5e_xmit_data_frags, xd);
545 struct mlx5_wq_cyc *wq = &sq->wq;
546 struct mlx5_wqe_ctrl_seg *cseg;
547 struct mlx5_wqe_data_seg *dseg;
548 struct mlx5_wqe_eth_seg *eseg;
549 struct mlx5e_tx_wqe *wqe;
550
551 dma_addr_t dma_addr = xdptxd->dma_addr;
552 u32 dma_len = xdptxd->len;
553 u16 ds_cnt, inline_hdr_sz;
554 unsigned int frags_size;
555 u8 num_wqebbs = 1;
556 int num_frags = 0;
557 bool inline_ok;
558 bool linear;
559 u16 pi;
560 int i;
561
562 struct mlx5e_xdpsq_stats *stats = sq->stats;
563
564 inline_ok = sq->min_inline_mode == MLX5_INLINE_MODE_NONE ||
565 dma_len >= MLX5E_XDP_MIN_INLINE;
566 frags_size = xdptxd->has_frags ? xdptxdf->sinfo->xdp_frags_size : 0;
567
568 if (unlikely(!inline_ok || sq->hw_mtu < dma_len + frags_size)) {
569 stats->err++;
570 return false;
571 }
572
573 inline_hdr_sz = 0;
574 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE)
575 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
576
577 linear = !!(dma_len - inline_hdr_sz);
578 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + linear + !!inline_hdr_sz;
579
580 /* check_result must be 0 if xdptxd->has_frags is true. */
581 if (!check_result) {
582 int stop_room = 1;
583
584 if (xdptxd->has_frags) {
585 ds_cnt += xdptxdf->sinfo->nr_frags;
586 num_frags = xdptxdf->sinfo->nr_frags;
587 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
588 /* Assuming MLX5_CAP_GEN(mdev, max_wqe_sz_sq) is big
589 * enough to hold all fragments.
590 */
591 stop_room = MLX5E_STOP_ROOM(num_wqebbs);
592 }
593
594 check_result = mlx5e_xmit_xdp_frame_check_stop_room(sq, stop_room);
595 }
596 if (unlikely(check_result < 0))
597 return false;
598
599 pi = mlx5e_xdpsq_get_next_pi(sq, num_wqebbs);
600 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
601 net_prefetchw(wqe);
602
603 cseg = &wqe->ctrl;
604 eseg = &wqe->eth;
605 dseg = wqe->data;
606
607 /* copy the inline part if required */
608 if (inline_hdr_sz) {
609 memcpy(eseg->inline_hdr.start, xdptxd->data, sizeof(eseg->inline_hdr.start));
610 memcpy(dseg, xdptxd->data + sizeof(eseg->inline_hdr.start),
611 inline_hdr_sz - sizeof(eseg->inline_hdr.start));
612 dma_len -= inline_hdr_sz;
613 dma_addr += inline_hdr_sz;
614 dseg++;
615 }
616
617 /* write the dma part */
618 if (linear) {
619 dseg->addr = cpu_to_be64(dma_addr);
620 dseg->byte_count = cpu_to_be32(dma_len);
621 dseg->lkey = sq->mkey_be;
622 dseg++;
623 }
624
625 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
626
627 memset(&cseg->trailer, 0, sizeof(cseg->trailer));
628 memset(eseg, 0, sizeof(*eseg) - sizeof(eseg->trailer));
629
630 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
631
632 for (i = 0; i < num_frags; i++) {
633 skb_frag_t *frag = &xdptxdf->sinfo->frags[i];
634 dma_addr_t addr;
635
636 addr = xdptxdf->dma_arr ? xdptxdf->dma_arr[i] :
637 page_pool_get_dma_addr(skb_frag_page(frag)) +
638 skb_frag_off(frag);
639
640 dseg->addr = cpu_to_be64(addr);
641 dseg->byte_count = cpu_to_be32(skb_frag_size(frag));
642 dseg->lkey = sq->mkey_be;
643 dseg++;
644 }
645
646 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
647
648 sq->db.wqe_info[pi] = (struct mlx5e_xdp_wqe_info) {
649 .num_wqebbs = num_wqebbs,
650 .num_pkts = 1,
651 };
652
653 sq->pc += num_wqebbs;
654
655 if (meta)
656 xsk_tx_metadata_request(sq->xsk_pool, meta,
657 &mlx5e_xsk_tx_metadata_ops, eseg);
658
659 sq->doorbell_cseg = cseg;
660
661 stats->xmit++;
662 return true;
663 }
664
mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq * sq,struct mlx5e_xdp_wqe_info * wi,u32 * xsk_frames,struct xdp_frame_bulk * bq,struct mlx5e_cq * cq,struct mlx5_cqe64 * cqe)665 static void mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq *sq,
666 struct mlx5e_xdp_wqe_info *wi,
667 u32 *xsk_frames,
668 struct xdp_frame_bulk *bq,
669 struct mlx5e_cq *cq,
670 struct mlx5_cqe64 *cqe)
671 {
672 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
673 u16 i;
674
675 for (i = 0; i < wi->num_pkts; i++) {
676 union mlx5e_xdp_info xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
677
678 switch (xdpi.mode) {
679 case MLX5E_XDP_XMIT_MODE_FRAME: {
680 /* XDP_TX from the XSK RQ and XDP_REDIRECT */
681 struct xdp_frame *xdpf;
682 dma_addr_t dma_addr;
683
684 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
685 xdpf = xdpi.frame.xdpf;
686 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
687 dma_addr = xdpi.frame.dma_addr;
688
689 dma_unmap_single(sq->pdev, dma_addr,
690 xdpf->len, DMA_TO_DEVICE);
691 if (xdp_frame_has_frags(xdpf)) {
692 struct skb_shared_info *sinfo;
693 int j;
694
695 sinfo = xdp_get_shared_info_from_frame(xdpf);
696 for (j = 0; j < sinfo->nr_frags; j++) {
697 skb_frag_t *frag = &sinfo->frags[j];
698
699 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
700 dma_addr = xdpi.frame.dma_addr;
701
702 dma_unmap_single(sq->pdev, dma_addr,
703 skb_frag_size(frag), DMA_TO_DEVICE);
704 }
705 }
706 xdp_return_frame_bulk(xdpf, bq);
707 break;
708 }
709 case MLX5E_XDP_XMIT_MODE_PAGE: {
710 /* XDP_TX from the regular RQ */
711 u8 num, n = 0;
712
713 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
714 num = xdpi.page.num;
715
716 do {
717 struct page *page;
718
719 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
720 page = xdpi.page.page;
721
722 /* No need to check page_pool_page_is_pp() as we
723 * know this is a page_pool page.
724 */
725 page_pool_recycle_direct(pp_page_to_nmdesc(page)->pp,
726 page);
727 } while (++n < num);
728
729 break;
730 }
731 case MLX5E_XDP_XMIT_MODE_XSK: {
732 /* AF_XDP send */
733 struct xsk_tx_metadata_compl *compl = NULL;
734 struct mlx5e_xsk_tx_complete priv = {
735 .cqe = cqe,
736 .cq = cq,
737 };
738
739 if (xp_tx_metadata_enabled(sq->xsk_pool)) {
740 xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);
741 compl = &xdpi.xsk_meta;
742
743 xsk_tx_metadata_complete(compl, &mlx5e_xsk_tx_metadata_ops, &priv);
744 }
745
746 (*xsk_frames)++;
747 break;
748 }
749 default:
750 WARN_ON_ONCE(true);
751 }
752 }
753 }
754
mlx5e_poll_xdpsq_cq(struct mlx5e_cq * cq)755 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
756 {
757 struct xdp_frame_bulk bq;
758 struct mlx5e_xdpsq *sq;
759 struct mlx5_cqe64 *cqe;
760 u32 xsk_frames = 0;
761 u16 sqcc;
762 int i;
763
764 xdp_frame_bulk_init(&bq);
765
766 sq = container_of(cq, struct mlx5e_xdpsq, cq);
767
768 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
769 return false;
770
771 cqe = mlx5_cqwq_get_cqe(&cq->wq);
772 if (!cqe)
773 return false;
774
775 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
776 * otherwise a cq overrun may occur
777 */
778 sqcc = sq->cc;
779
780 i = 0;
781 do {
782 struct mlx5e_xdp_wqe_info *wi;
783 u16 wqe_counter, ci;
784 bool last_wqe;
785
786 mlx5_cqwq_pop(&cq->wq);
787
788 wqe_counter = be16_to_cpu(cqe->wqe_counter);
789
790 do {
791 last_wqe = (sqcc == wqe_counter);
792 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
793 wi = &sq->db.wqe_info[ci];
794
795 sqcc += wi->num_wqebbs;
796
797 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, &bq, cq, cqe);
798 } while (!last_wqe);
799
800 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
801 netdev_WARN_ONCE(sq->channel->netdev,
802 "Bad OP in XDPSQ CQE: 0x%x\n",
803 get_cqe_opcode(cqe));
804 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
805 (struct mlx5_err_cqe *)cqe);
806 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
807 }
808 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
809
810 xdp_flush_frame_bulk(&bq);
811
812 if (xsk_frames)
813 xsk_tx_completed(sq->xsk_pool, xsk_frames);
814
815 sq->stats->cqes += i;
816
817 mlx5_cqwq_update_db_record(&cq->wq);
818
819 /* ensure cq space is freed before enabling more cqes */
820 wmb();
821
822 sq->cc = sqcc;
823 return (i == MLX5E_TX_CQ_POLL_BUDGET);
824 }
825
mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq * sq)826 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
827 {
828 struct xdp_frame_bulk bq;
829 u32 xsk_frames = 0;
830
831 xdp_frame_bulk_init(&bq);
832
833 rcu_read_lock(); /* need for xdp_return_frame_bulk */
834
835 while (sq->cc != sq->pc) {
836 struct mlx5e_xdp_wqe_info *wi;
837 u16 ci;
838
839 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
840 wi = &sq->db.wqe_info[ci];
841
842 sq->cc += wi->num_wqebbs;
843
844 mlx5e_free_xdpsq_desc(sq, wi, &xsk_frames, &bq, NULL, NULL);
845 }
846
847 xdp_flush_frame_bulk(&bq);
848 rcu_read_unlock();
849
850 if (xsk_frames)
851 xsk_tx_completed(sq->xsk_pool, xsk_frames);
852 }
853
mlx5e_xdp_xmit(struct net_device * dev,int n,struct xdp_frame ** frames,u32 flags)854 int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
855 u32 flags)
856 {
857 struct mlx5e_priv *priv = netdev_priv(dev);
858 struct mlx5e_xdpsq *sq;
859 int nxmit = 0;
860 int sq_num;
861 int i;
862
863 /* this flag is sufficient, no need to test internal sq state */
864 if (unlikely(!mlx5e_xdp_tx_is_enabled(priv)))
865 return -ENETDOWN;
866
867 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
868 return -EINVAL;
869
870 sq_num = smp_processor_id();
871
872 if (unlikely(sq_num >= priv->channels.num))
873 return -ENXIO;
874
875 sq = priv->channels.c[sq_num]->xdpsq;
876
877 for (i = 0; i < n; i++) {
878 struct mlx5e_xmit_data_frags xdptxdf = {};
879 struct xdp_frame *xdpf = frames[i];
880 dma_addr_t dma_arr[MAX_SKB_FRAGS];
881 struct mlx5e_xmit_data *xdptxd;
882 bool ret;
883
884 xdptxd = &xdptxdf.xd;
885 xdptxd->data = xdpf->data;
886 xdptxd->len = xdpf->len;
887 xdptxd->has_frags = xdp_frame_has_frags(xdpf);
888 xdptxd->dma_addr = dma_map_single(sq->pdev, xdptxd->data,
889 xdptxd->len, DMA_TO_DEVICE);
890
891 if (unlikely(dma_mapping_error(sq->pdev, xdptxd->dma_addr)))
892 break;
893
894 if (xdptxd->has_frags) {
895 int j;
896
897 xdptxdf.sinfo = xdp_get_shared_info_from_frame(xdpf);
898 xdptxdf.dma_arr = dma_arr;
899 for (j = 0; j < xdptxdf.sinfo->nr_frags; j++) {
900 skb_frag_t *frag = &xdptxdf.sinfo->frags[j];
901
902 dma_arr[j] = dma_map_single(sq->pdev, skb_frag_address(frag),
903 skb_frag_size(frag), DMA_TO_DEVICE);
904
905 if (!dma_mapping_error(sq->pdev, dma_arr[j]))
906 continue;
907 /* mapping error */
908 while (--j >= 0)
909 dma_unmap_single(sq->pdev, dma_arr[j],
910 skb_frag_size(&xdptxdf.sinfo->frags[j]),
911 DMA_TO_DEVICE);
912 goto out;
913 }
914 }
915
916 ret = INDIRECT_CALL_2(sq->xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,
917 mlx5e_xmit_xdp_frame, sq, xdptxd, 0, NULL);
918 if (unlikely(!ret)) {
919 int j;
920
921 dma_unmap_single(sq->pdev, xdptxd->dma_addr,
922 xdptxd->len, DMA_TO_DEVICE);
923 if (!xdptxd->has_frags)
924 break;
925 for (j = 0; j < xdptxdf.sinfo->nr_frags; j++)
926 dma_unmap_single(sq->pdev, dma_arr[j],
927 skb_frag_size(&xdptxdf.sinfo->frags[j]),
928 DMA_TO_DEVICE);
929 break;
930 }
931
932 /* xmit_mode == MLX5E_XDP_XMIT_MODE_FRAME */
933 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
934 (union mlx5e_xdp_info) { .mode = MLX5E_XDP_XMIT_MODE_FRAME });
935 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
936 (union mlx5e_xdp_info) { .frame.xdpf = xdpf });
937 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
938 (union mlx5e_xdp_info) { .frame.dma_addr = xdptxd->dma_addr });
939 if (xdptxd->has_frags) {
940 int j;
941
942 for (j = 0; j < xdptxdf.sinfo->nr_frags; j++)
943 mlx5e_xdpi_fifo_push(&sq->db.xdpi_fifo,
944 (union mlx5e_xdp_info)
945 { .frame.dma_addr = dma_arr[j] });
946 }
947 nxmit++;
948 }
949
950 out:
951 if (sq->mpwqe.wqe)
952 mlx5e_xdp_mpwqe_complete(sq);
953
954 if (flags & XDP_XMIT_FLUSH)
955 mlx5e_xmit_xdp_doorbell(sq);
956
957 return nxmit;
958 }
959
mlx5e_xdp_rx_poll_complete(struct mlx5e_rq * rq)960 void mlx5e_xdp_rx_poll_complete(struct mlx5e_rq *rq)
961 {
962 struct mlx5e_xdpsq *xdpsq = rq->xdpsq;
963
964 if (xdpsq->mpwqe.wqe)
965 mlx5e_xdp_mpwqe_complete(xdpsq);
966
967 mlx5e_xmit_xdp_doorbell(xdpsq);
968
969 if (test_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags)) {
970 xdp_do_flush();
971 __clear_bit(MLX5E_RQ_FLAG_XDP_REDIRECT, rq->flags);
972 }
973 }
974
mlx5e_set_xmit_fp(struct mlx5e_xdpsq * sq,bool is_mpw)975 void mlx5e_set_xmit_fp(struct mlx5e_xdpsq *sq, bool is_mpw)
976 {
977 sq->xmit_xdp_frame_check = is_mpw ?
978 mlx5e_xmit_xdp_frame_check_mpwqe : mlx5e_xmit_xdp_frame_check;
979 sq->xmit_xdp_frame = is_mpw ?
980 mlx5e_xmit_xdp_frame_mpwqe : mlx5e_xmit_xdp_frame;
981 }
982