1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/phy/pcie.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
24
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
26
27 #include "phy-qcom-qmp-common.h"
28
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
35 #include "phy-qcom-qmp-pcs-pcie-v6.h"
36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h"
38 #include "phy-qcom-qmp-pcs-v6_30.h"
39 #include "phy-qcom-qmp-pcie-qhp.h"
40
41 #define PHY_INIT_COMPLETE_TIMEOUT 10000
42
43 /* set of registers with offsets different per-PHY */
44 enum qphy_reg_layout {
45 /* PCS registers */
46 QPHY_SW_RESET,
47 QPHY_START_CTRL,
48 QPHY_PCS_STATUS,
49 QPHY_PCS_POWER_DOWN_CONTROL,
50 /* Keep last to ensure regs_layout arrays are properly initialized */
51 QPHY_LAYOUT_SIZE
52 };
53
54 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
55 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
56 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
57 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
58 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
59 };
60
61 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
62 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
63 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
64 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
65 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
66 };
67
68 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
69 [QPHY_SW_RESET] = 0x00,
70 [QPHY_START_CTRL] = 0x08,
71 [QPHY_PCS_STATUS] = 0x2ac,
72 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
73 };
74
75 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
76 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
77 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
78 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
79 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
80 };
81
82 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
83 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
84 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
85 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
86 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
87 };
88
89 static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
90 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
91 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
92 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
93 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
94 };
95
96 static const unsigned int pciephy_v7_regs_layout[QPHY_LAYOUT_SIZE] = {
97 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET,
98 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL,
99 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1,
100 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL,
101 };
102
103 static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] = {
104 [QPHY_START_CTRL] = QPHY_V8_50_PCS_START_CONTROL,
105 [QPHY_PCS_STATUS] = QPHY_V8_50_PCS_STATUS1,
106 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_50_PCS_POWER_DOWN_CONTROL,
107 };
108
109 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
152 };
153
154 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
155 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
156 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
157 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
158 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
159 };
160
161 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
162 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
163 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
164 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
165 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
166 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
167 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
170 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
171 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
172 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
176 };
177
178 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
189 };
190
191 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
192 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
193 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
194 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
195 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
196 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
197 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
198 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
199 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
200 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
201 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
202 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
203 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
204 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
205 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
206 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
207 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
208 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
209 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
210 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
211 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
212 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
213 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
214 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
215 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
216 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
217 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
218 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
219 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
220 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
221 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
222 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
223 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
224 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
225 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
226 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
227 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
228 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
229 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
230 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
231 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
232 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
233 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
234 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
235 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
236 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
237 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
238 };
239
240 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
241 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
242 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
243 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
244 };
245
246 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
277 };
278
279 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
280 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
281 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
282 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
287 };
288
289 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
290 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
291 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
292 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
293 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
294 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
298 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
299 };
300
301 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
302 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
303 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
304 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
305 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
306 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
307 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
308 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
309 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
310 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
311 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
312 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
313 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
314 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
315 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
316 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
317 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
318 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
319 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
320 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
321 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
322 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
323 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
324 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
325 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
326 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
327 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
328 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
329 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
330 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
331 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
332 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
333 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
334 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
335 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
336 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
337 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
338 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
339 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
340 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
341 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
342 };
343
344 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
345 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
346 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
347 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
348 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
349 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
350 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
351 };
352
353 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
354 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
355 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
356 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
357 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
358 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
359 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
360 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
361 };
362
363 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
364 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
365 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
366 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
367 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
368 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
369 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
370 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
371 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
372 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
373 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
374 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
375 };
376
377 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
378 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
379 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
380 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
381 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
382 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
383 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
384 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
385 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
386 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
387 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
388 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
389 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
390 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
391 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
392 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
393 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
394 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
395 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
396 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
397 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
398 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
399 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
400 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
401 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
402 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
403 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
404 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
405 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
406 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
407 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
408 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
409 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
410 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
411 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
412 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
413 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
414 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
415 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
416 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
417 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
418 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
419 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
420 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
421 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
422 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
423 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
424 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
425 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
426 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
427 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
428 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
429 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
430 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
431 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
432 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
433 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
434 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
435 };
436
437 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
438 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
439 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
440 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
441 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
442 };
443
444 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe),
449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4),
450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2),
468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
475 };
476
477 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
478 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),
479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),
480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),
481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),
482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
489 };
490
491 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),
499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
505 };
506
507 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = {
508 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
509 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
510 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
511 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
512 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
513 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
514 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
515 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
516 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
517 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
518 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
519 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
520 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
521 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
522 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
523 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
524 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
525 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
526 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
527 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
528 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
529 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
530 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
531 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
532 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
533 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
534 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
535 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
536 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
537 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
538 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
539 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
540 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
541 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
542 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
543 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
544 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
545 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
546 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
547 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
548 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
549 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
550 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
551 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
552 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
553 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
554 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
555 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
556 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
557 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
558 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
559 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
560 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
561 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
562 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
563 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
564 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
565 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
566 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
567 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
568 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
569 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
570 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
571 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
572 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
573 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
574 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
575 };
576
577 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
578 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
579 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
580 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
581 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
582 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
583 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
584 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
585 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
586 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
587 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
588 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
589 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
590 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
591 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
592 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
593 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
594 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
595 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
596 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
597 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
598 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
599 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
600 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
601 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
602 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
603 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
604 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
605 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
606 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
607 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
608 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
609 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
610 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
611 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
612 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
613 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
614 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
615 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
616 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
617 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
618 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
619 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
620 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
621 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
622 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
623 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
624 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
625 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
626 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
627 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
628 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
629 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
630 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
631 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
632 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
633 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
634 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
635 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
636 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
637 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
638 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
639 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
640 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
641 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
642 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
643 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
644 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
645 };
646
647 static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = {
648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73),
660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80),
661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00),
667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02),
673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
678 };
679
680 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = {
681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
687 };
688
689 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = {
690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
694 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
696 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14),
697 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10),
698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b),
699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
701 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
703 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
705 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
706 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06),
707 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
709 };
710
711 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = {
712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
718 };
719
720 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
721 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
722 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
724 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
725 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
726 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),
730 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
731 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
732 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
733 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
734 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
735 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
736 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
737 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
738 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),
739 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
740 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
741 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
742 };
743
744 static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = {
745 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
746 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
747 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
748 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
749 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
750 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
751 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
752 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
753 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
754 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
755 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
756 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
757 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
758 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
759 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9),
760 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4),
761 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
762 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
763 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
764 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
765 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
766 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xd),
767 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04),
768 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35),
769 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
770 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
771 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4),
772 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
773 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30),
774 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
775 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
776 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
777 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
778 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
779 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
780 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
781 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
782 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
783 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
784 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
785 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
786 };
787
788 static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] = {
789 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
790 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
791 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
792 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
793 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
794 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
795 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
796 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
797 };
798
799 static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] = {
800 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
801 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
802 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
803 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
804 };
805
806 static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = {
807 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
808 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
809 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
810 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
811 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
812 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
813 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
814 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
815 QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7),
816 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
817 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
818 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
819 };
820
821 static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x2_pcie_rx_alt_tbl[] = {
822 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
823 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
824 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
825 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
826 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
827 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
828 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
829 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
830 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
831 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
832 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
833 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
834 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
835 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
836 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
837 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
838 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
839 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
840 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
841 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
842 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
843 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
844 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
845 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
846 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
847 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
848 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
849 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
850 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
851 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
852 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
853 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
854 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
855 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
856 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
857 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
858 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
859 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
860 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
861 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
862 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
863 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
864 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
865 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
866 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
867 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
868 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
869 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
870 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
871 };
872
873 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
874 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
875 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
876 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
877 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
878 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
879 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
880 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
881 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
882 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
883 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
884 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
885 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
886 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
887 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
888 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
889 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
890 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
891 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
892 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
893 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
894 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
895 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
896 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
897 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
898 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
899 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
900 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
901 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
902 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
903 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
904 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
905 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
906 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
907 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
908 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
909 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
910 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
911 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
912 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
913 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
914 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
915 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
916 };
917
918 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
919 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
920 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
921 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
922 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
923 };
924
925 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
926 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
927 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
928 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
929 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
930 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
931 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
932 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
933 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
934 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
935 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
936 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
937 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
938 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
939 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
940 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
941 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
942 };
943
944 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
945 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
946
947 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
948 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
949 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
950 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
951 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
952
953 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
954 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
955 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
956 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
957 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
958 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
959 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
960
961 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
962 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
963 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
964
965 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
966 };
967
968 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
969 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
970 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
971 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
972 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
973 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
974 };
975
976 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
977 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
978 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
979 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
980 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
981 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
982 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
983 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
984 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
985 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
986 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
987 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
988 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
989 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
990 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
991 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
992 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
993 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
994 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
995 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
996 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
997 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
998 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
999 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
1000 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
1001 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
1002 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
1003 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
1004 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
1005 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
1006 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
1007 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1008 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1009 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
1010 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
1011 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
1012 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
1013 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
1014 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
1015 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
1016 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
1017 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
1018 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
1019 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
1020 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
1021 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
1022 };
1023
1024 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
1025 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
1026 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
1027 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
1028 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
1029 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
1030 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
1031 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
1032 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
1033 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
1034 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
1035 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
1036 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
1037 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
1038 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
1039 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
1040 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
1041 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
1042 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
1043 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
1044 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
1045 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
1046 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
1047 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
1048 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
1049 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
1050 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
1051 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
1052 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
1053 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
1054 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
1055 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
1056 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
1057 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
1058 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
1059 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
1060 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
1061 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
1062 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
1063 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
1064 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
1065 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
1066 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
1067 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
1068 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
1069 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
1070 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
1071 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
1072 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
1073 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
1074 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
1075 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
1076 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
1077 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
1078 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
1079 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
1080 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
1081 };
1082
1083 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
1084 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
1085 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
1086 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
1087 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
1088 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
1089 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
1090 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
1091 };
1092
1093 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
1094 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1095 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1096 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1097 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1098 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
1099 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1100 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
1101 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
1102 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1103 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1104 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1105 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
1106 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
1107 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1108 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1109 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1110 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1111 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1112 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1113 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1114 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1115 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1116 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1117 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1118 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1119 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1120 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1121 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1122 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1123 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1124 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1125 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1126 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1127 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1128 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1129 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1130 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1131 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1132 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1136 };
1137
1138 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
1139 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1140 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
1141 };
1142
1143 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
1144 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1145 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1146 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
1147 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
1148 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
1149 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
1150 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
1151 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1152 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1153 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1154 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1155 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1156 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
1157 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1158 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1159 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1160 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
1161 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1162 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1163 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1164 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1165 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
1166 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1167 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1168 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
1169 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1170 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
1171 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
1172 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1173 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1174 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1175 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
1176 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1177 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
1178 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1179 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1180 };
1181
1182 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
1183 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1184 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1185 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1186 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1187 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
1188 };
1189
1190 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
1191 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1192 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1193 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1194 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1195 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1196 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1197 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1198 };
1199
1200 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {
1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
1229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
1233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
1234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1235 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1236 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1237 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),
1238 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1239 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),
1240 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1241 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1242 };
1243
1244 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
1245 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1246 };
1247
1248 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
1249 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1250 };
1251
1252 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = {
1253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
1254 };
1255
1256 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {
1257 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1258 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1259 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1260 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1261 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1262 };
1263
1264 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {
1265 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1266 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1267 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1268 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1269 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1270 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1271 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1272 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1273 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1274 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1275 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1276 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1277 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1278 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1279 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1280 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1281 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1282 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1283 };
1284
1285 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {
1286 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1287 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1288 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1289 };
1290
1291 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1292 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1293 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1294 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
1295 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1296 };
1297
1298 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {
1299 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1300 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1301 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1302 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1303 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1304 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1305 };
1306
1307 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {
1308 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1309 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1310 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1311 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1312 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1313 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1314 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1315 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1316 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1317 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1318 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1319 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1320 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1321 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1322 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1323 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1324 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1325 };
1326
1327 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {
1328 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1329 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),
1330 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1331 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),
1332 };
1333
1334 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1335 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
1336 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1337 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1338 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1339 };
1340
1341 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = {
1342 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1343 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1344 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1345 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1346 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1347 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1348 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1349 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1350 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1351 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1352 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1353 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1354 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1355 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1356 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1357 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1358 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1361 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1362 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1363 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1367 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1368 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1369 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1370 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
1374 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1375 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1376 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1377 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1378 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1379 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1380 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1381 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1382 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1383 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1384 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1385 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1386 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1387 };
1388
1389 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = {
1390 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),
1391 };
1392
1393 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1394 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1395 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1396 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
1397 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
1398 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),
1399 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1400 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1401 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1402 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32),
1403 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1404 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1405 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1406 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1407 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1408 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1409 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1410 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1411 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1412 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1413 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1414 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
1415 };
1416
1417 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {
1418 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1419 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
1420 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1421 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
1422 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1423 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1424 };
1425
1426 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = {
1427 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
1428 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
1429 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1430 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1431 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1432 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1433 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
1434 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
1435 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),
1436 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),
1437 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1438 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1),
1439 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2),
1440 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
1441 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1442 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1443 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1444 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1445 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1),
1446 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2),
1447 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
1448 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1449 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
1450 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1451 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1452 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
1453 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1454 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1455 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4),
1456 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4),
1457 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
1458 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1459 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),
1460 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1461 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1462 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
1463 };
1464
1465 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {
1466 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
1467 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
1468 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1469 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1470 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
1471 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
1472 };
1473
1474 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1475 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1476 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
1477 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1478 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
1479 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1480 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1481 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1482 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
1483 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
1484 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1485 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1486 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18),
1487 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
1488 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
1489 };
1490
1491 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_serdes_tbl[] = {
1492 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1493 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1494 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1495 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1496 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1497 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x08),
1498 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x04),
1499 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0d),
1500 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1501 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1502 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1503 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1504 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1505 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1506 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1507 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1508 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1509 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1510 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1511 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1512 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1513 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1514 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1515 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1516 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1517 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1518 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1519 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1520 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1521 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1522 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1523 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),
1524 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1525 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1526 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1527 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1528 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1529 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1530 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1531 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1532 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
1533 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1534 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1535 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1536 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1537 };
1538
1539 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl[] = {
1540 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1541 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
1542 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1543 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
1544 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
1545 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
1546 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1547 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1548 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1549 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
1550 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1551 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1552 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1553 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1554 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1555 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1556 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1557 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1558 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1559 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1560 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1561 };
1562
1563 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_txz_tbl[] = {
1564 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1565 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x05),
1566 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1567 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
1568 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1569 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1570 };
1571
1572 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rxz_tbl[] = {
1573 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
1574 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
1575 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1576 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1577 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1578 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1579 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
1580 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
1581 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1582 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0c),
1583 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
1584 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1585 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1586 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1587 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1588 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1589 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
1590 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd4),
1591 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0x23),
1592 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1593 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1594 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x38),
1595 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1596 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1597 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x1c),
1598 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xe4),
1599 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
1600 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1601 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x69),
1602 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1603 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1604 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
1605 };
1606
1607 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rx_tbl[] = {
1608 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, BIT(0)),
1609 };
1610
1611 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_tbl[] = {
1612 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2, 0x00),
1613 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_G3S2_PRE_GAIN, 0x2e),
1614 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_RX_SIGDET_LVL, 0x99),
1615 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7, 0x00),
1616 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG4, 0x00),
1617 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG5, 0x22),
1618 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG, 0x04),
1619 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG2, 0x02),
1620 };
1621
1622 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl[] = {
1623 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1624 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS, 0x00),
1625 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_EQ_CONFIG1, 0x16),
1626 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5, 0x02),
1627 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN, 0x2e),
1628 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1, 0x03),
1629 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3, 0x28),
1630 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5, 0x18),
1631 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
1632 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
1633 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME, 0x27),
1634 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME, 0x27),
1635 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG, 0xc0),
1636 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2, 0x1d),
1637 };
1638
1639 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
1640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
1645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
1647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
1648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
1652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
1653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1655 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1656 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1657 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1659 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1660 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1661 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1662 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1663 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1664 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1665 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1666 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1667 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1668 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1669 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1670 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1671 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1672 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1673 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1674 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1675 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1676 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1677 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1678 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1679 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1680 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1681 };
1682
1683 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
1684 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1685 };
1686
1687 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
1688 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1689 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
1690 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1691 };
1692
1693 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
1694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
1697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
1700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
1701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
1702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1713 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1714 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1715 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1716 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1717 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1718 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1719 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1720 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1721 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1722 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1723 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1724 };
1725
1726 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
1727 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
1728 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
1729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
1731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
1732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1733 };
1734
1735 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
1736 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1737 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
1738 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1739 };
1740
1741 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
1742 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1743 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
1744 };
1745
1746 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
1747 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1748 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1749 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1750 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
1751 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1752 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1753 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1754 };
1755
1756 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1757 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1758 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
1759 };
1760
1761 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
1762 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1763 };
1764
1765 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
1766 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
1767 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1768 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
1769 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1770 };
1771
1772 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
1773 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
1774 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
1775 };
1776
1777 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1778 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
1779 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1780 };
1781
1782 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
1783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
1784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
1786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
1787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
1789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
1791 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
1792 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
1793 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
1794 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
1795 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
1796 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
1797 };
1798
1799 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {
1800 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1801 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1802 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1803 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),
1804 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),
1805 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1806 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1807 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1808 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),
1809 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),
1810 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),
1818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),
1819 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),
1820 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),
1821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),
1822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),
1823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),
1824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
1825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
1826 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
1827 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1828 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1829 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1830 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),
1831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),
1832 };
1833
1834 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
1835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
1836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
1837 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
1838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
1839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
1840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
1841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
1842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
1843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
1844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
1845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
1846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
1847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
1848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
1849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
1850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
1851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
1856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
1857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
1858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
1859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
1860 };
1861
1862 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
1863 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
1864 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
1865 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
1866 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
1867 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
1868 };
1869
1870 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
1871 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
1872 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
1873 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
1874 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
1875 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
1876 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
1877 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
1878 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1879 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
1880 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
1881 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
1882 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
1883 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
1884 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
1885 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
1886 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
1887 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
1888 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
1889 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
1890 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
1891 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
1892 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
1893 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
1894 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1895 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
1896 };
1897
1898 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
1899 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
1900 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
1901 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
1902 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
1903 };
1904
1905 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
1906 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
1907 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
1908 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
1909 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
1910 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1911 };
1912
1913 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
1914 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1915 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1916 };
1917
1918 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = {
1919 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1920 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1921 };
1922
1923 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = {
1924 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
1925 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1926 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
1927 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1928 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
1929 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
1930 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
1931 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
1932 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
1933 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
1934 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
1935 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1936 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1937 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
1938 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
1939 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
1940 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
1941 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
1942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
1943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1944 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1945 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1946 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1947 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1948 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1949 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1950 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1951 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1952 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1953 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1954 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1955 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1956 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00),
1957 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1958 };
1959
1960 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = {
1961 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1962 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1963 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00),
1964 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00),
1965 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00),
1966 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1967 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1968 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12),
1969 };
1970
1971 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = {
1972 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1973 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06),
1974 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06),
1975 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e),
1976 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e),
1977 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1978 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1979 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02),
1980 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d),
1981 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44),
1982 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00),
1983 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
1984 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1985 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74),
1986 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1987 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c),
1988 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03),
1989 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
1990 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04),
1991 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1992 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1993 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1994 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64),
1995 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1996 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1997 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1998 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c),
1999 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2000 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2001 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2002 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2003 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2004 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2005 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2006 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2007 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2008 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2009 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
2010 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2011 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2012 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2013 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
2014 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2015 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00),
2016 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2017 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
2018 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2019 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
2020 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac),
2021 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
2022 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
2023 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07),
2024 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
2025 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2026 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5),
2027 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee),
2028 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
2029 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
2030 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
2031 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
2032 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
2033 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28),
2034 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2035 };
2036
2037 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = {
2038 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2039 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa),
2040 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d),
2041 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2042 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2043 };
2044
2045 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {
2046 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2047 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
2048 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
2049 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),
2050 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2051 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
2052 };
2053
2054 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = {
2055 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2056 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2057 };
2058
2059 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
2060 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2061 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2062 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
2063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
2066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
2067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
2068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
2077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
2078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
2079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
2080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
2083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
2094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2101 };
2102
2103 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
2104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
2105 };
2106
2107 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
2108 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
2109 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
2110 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2111 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2112 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
2113 };
2114
2115 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
2116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
2117 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
2118 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
2119 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
2120 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
2121 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
2122 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
2123 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
2124 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
2125 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2126 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2127 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2128 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2129 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
2130 };
2131
2132 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
2133 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
2134 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
2135 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
2136 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
2137 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
2138 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
2139 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
2140 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2141 };
2142
2143 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
2144 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
2145 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
2146 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
2147 };
2148
2149 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2150 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2151 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2152 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
2153 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2154 };
2155
2156 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
2157 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
2158 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
2159 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2160 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
2161 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
2162 };
2163
2164 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
2165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
2166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
2167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
2168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
2169 };
2170
2171 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
2172 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
2173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
2174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2175 };
2176
2177 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
2178 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
2179 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
2180 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
2181 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2182 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
2183 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
2184 };
2185
2186 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
2187 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
2188 };
2189
2190 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
2191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
2192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2204 };
2205
2206 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = {
2207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
2235 };
2236
2237 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
2238 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
2239 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
2240 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
2241 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
2242 };
2243
2244 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
2245 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2247 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
2248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
2249 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
2250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
2251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
2252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
2253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
2254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
2255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
2256 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
2257 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
2258 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
2259 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
2260 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
2261 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
2262 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
2263 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
2264 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
2265 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
2266 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2267 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2268 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2269
2270 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
2271
2272 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2273
2274 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2275 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2276 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2277 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2278 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2279 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2280 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2281 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2282
2283 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2284 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
2285 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2286 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2287 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2288 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2289 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
2290 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2291 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2292 };
2293
2294 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
2295 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2296 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2297 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2298 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99),
2299 };
2300
2301 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
2302 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2303 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2304 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
2305 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
2306 };
2307
2308 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = {
2309 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2310 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2311 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00),
2312 };
2313
2314 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {
2315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
2316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
2317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
2318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
2319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
2320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
2321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
2322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
2323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
2324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
2326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
2327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
2328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
2329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
2330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2335 };
2336
2337 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = {
2338 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
2339 };
2340
2341 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
2342 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2343 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
2344 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
2345 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
2346 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
2347 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
2348 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
2349 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2350 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2351 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
2352 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
2353 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
2354 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2355 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2356 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2357 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2358 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
2360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
2361 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
2362 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
2363 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
2364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
2365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
2366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
2367 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
2368 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
2369 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
2370 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
2371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
2372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
2373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2374 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
2375 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
2376 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2377 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
2378 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
2379 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2380 };
2381
2382 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
2383 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
2384 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
2385 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
2386 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
2387 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
2388 };
2389
2390 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
2391 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2392 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
2393 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
2394 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
2395 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
2396 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
2397 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
2398 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
2399 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
2400 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
2401 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
2402 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
2403 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
2404 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
2405 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
2406 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
2407 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00),
2408 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
2409 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
2410 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
2411 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
2412 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
2413 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
2414 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
2415 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
2416 };
2417
2418 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
2419 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
2420 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
2421 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
2422 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
2423 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
2424 };
2425
2426 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2427 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
2428 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),
2429 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
2430 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2431 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2432 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2433 };
2434
2435 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
2436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
2437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
2438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
2439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
2443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
2444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
2445 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
2446 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
2447 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
2448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
2449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
2450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
2451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
2452 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2453 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2454 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
2455 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
2456 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
2457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
2458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
2459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
2460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
2461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
2462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
2463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
2465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
2466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
2467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
2468 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2469 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2470 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
2471 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2472 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
2473 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
2474 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2475 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
2476 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2477 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
2478 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
2479 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
2480 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
2481 };
2482
2483 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
2484 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
2485 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
2486 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
2487 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
2488 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
2489 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
2490 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
2491 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
2492 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
2493 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
2494 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
2495 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2496 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2497 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2498 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2499 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2500 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2501 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2502 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2503 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2504 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
2505 };
2506
2507 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
2508 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
2509 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
2510 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
2511 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
2512 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
2513 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
2514 };
2515
2516 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
2517 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
2518 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
2519 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
2520 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
2521 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
2522 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
2523 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
2524 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
2525 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
2526 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2527 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
2528 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2529 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
2530 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
2531 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2532 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2533 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
2534 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
2535 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
2536 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
2537 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
2538 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
2539 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
2540 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
2541 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
2542 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
2543 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
2544 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
2545 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
2546 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
2547 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
2548 };
2549
2550 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
2551 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2552 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
2553 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
2554 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
2555 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
2556 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
2557 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
2558 };
2559
2560 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
2561 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
2562 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
2563 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
2564 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
2565 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
2566 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
2567 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
2568 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
2569 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
2570 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
2571 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
2572 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
2573 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
2574 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
2575 };
2576
2577 static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = {
2578 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
2579 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
2580 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
2581 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
2582 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82),
2583 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
2584 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2585 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
2586 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2587 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
2588 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
2589 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2590 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3),
2591 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3),
2592 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00),
2593 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
2594 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06),
2595 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
2596 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
2597 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23),
2598 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b),
2599 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
2600 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
2601 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43),
2602 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
2603 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
2604 };
2605
2606 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_serdes_tbl[] = {
2607 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x1),
2608 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),
2609 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),
2610 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
2611 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),
2612 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0x93),
2613 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),
2614 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_ENABLE1, 0x90),
2615 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYS_CLK_CTRL, 0x82),
2616 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_IVCO, 0x07),
2617 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),
2618 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),
2619 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),
2620 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),
2621 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),
2622 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),
2623 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x08),
2624 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),
2625 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_EN, 0x42),
2626 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x04),
2627 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x0d),
2628 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x0a),
2629 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x1a),
2630 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),
2631 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x34),
2632 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0xab),
2633 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0xaa),
2634 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),
2635 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),
2636 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x55),
2637 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),
2638 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x14),
2639 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_SELECT, 0x34),
2640 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),
2641 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),
2642 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),
2643 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC_3, 0x0F),
2644 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0xA0),
2645 };
2646
2647 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_rx_tbl[] = {
2648 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2649 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x11),
2650 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xBF),
2651 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xBF),
2652 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xB7),
2653 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xEA),
2654 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3F),
2655 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x09),
2656 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x49),
2657 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1B),
2658 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x9C),
2659 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xD1),
2660 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH, 0x09),
2661 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH2, 0x49),
2662 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH3, 0x1B),
2663 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH4, 0x9C),
2664 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_LOW, 0xD1),
2665 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH1, 0x3E),
2666 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH2, 0x1E),
2667 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_POST_THRESH, 0xD2),
2668 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x09),
2669 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x05),
2670 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),
2671 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),
2672 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x09),
2673 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_ENABLES, 0x1C),
2674 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x60),
2675 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),
2676 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),
2677 };
2678
2679 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_tx_tbl[] = {
2680 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0x35),
2681 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x10),
2682 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x31),
2683 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x7F),
2684 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x02),
2685 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x08),
2686 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x14),
2687 };
2688
2689 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_tbl[] = {
2690 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x05),
2691 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0x77),
2692 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RATE_SLEW_CNTRL1, 0x0B),
2693 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG2, 0x0F),
2694 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x8C),
2695 QMP_PHY_INIT_CFG(QPHY_V7_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2696 QMP_PHY_INIT_CFG(QPHY_V7_PCS_G3S2_PRE_GAIN, 0x2E),
2697 };
2698
2699 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2700 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1E),
2701 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),
2702 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1D),
2703 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2704 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xC1),
2705 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2706 };
2707
2708 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {
2709 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
2710 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2711 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2712 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2713 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2714 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2715 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2716 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2717 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2718 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2719 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2720 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2721 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2722 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2723 };
2724
2725 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = {
2726 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
2727 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2728 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2729 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2730 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2731 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2732 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2733 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2734 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2735 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2736 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2737 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2738 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2739 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2740 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2741 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2742 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2743 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2744 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2745 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2746 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2747 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2748 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2749 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2750 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2751 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2752 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2753 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2754 };
2755
2756 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {
2757 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x07),
2758 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2759 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
2760 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2761 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xe4),
2762 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2763 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2764 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
2765 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
2766 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
2767 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
2768 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xe4),
2769 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
2770 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2771 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2772 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2773 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3),
2774 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
2775 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xed),
2776 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe5),
2777 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x8d),
2778 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6),
2779 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e),
2780 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2781 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2782 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2783 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
2784 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2785 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2786 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2787 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2788 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2789 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2790 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2791 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2792 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2793 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2794 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2795 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2796 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2797 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2798 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x03),
2799 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x08),
2800 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2801 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2802 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2803 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x01),
2804 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2805 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2806 };
2807
2808 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = {
2809 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
2810 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
2811 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
2812 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
2813 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f),
2814 };
2815
2816 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = {
2817 QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME, 0x27),
2818 QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME, 0x27),
2819 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2820 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2821 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
2822 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
2823 };
2824
2825 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {
2826 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
2827 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2828 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2829 };
2830
2831 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_alt_tbl[] = {
2832 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2833 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2834 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2835 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2836 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1, 0xff),
2837 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2, 0x89),
2838 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1, 0x00),
2839 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2, 0x50),
2840 };
2841
2842 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
2843 QMP_PHY_INIT_CFG(QSERDES_v5_LN_SHRD_UCDR_PI_CTRL2, 0x00),
2844 };
2845
2846 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
2847 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2848 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2849 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
2850 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2851 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2852 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
2853 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2854 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2855 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2856 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2857 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2858 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2859 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2860 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2861 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2862 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2863 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2864 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2865 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2866 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2867 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
2868 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2869 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
2870 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2871 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2872 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
2873 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
2874 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
2875 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6),
2876 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
2877 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0),
2878 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2879 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2880 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2881 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3),
2882 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6),
2883 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xe4),
2884 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe6),
2885 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
2886 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6),
2887 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e),
2888 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2889 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2890 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2891 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2892 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2893 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2894 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2895 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x06),
2896 };
2897
2898 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
2899 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
2900 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2901 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2902 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2903 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2904 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2905 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2906 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2907 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2908 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2909 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2910 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2911 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2912 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2913 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2914 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2915 };
2916
2917
2918 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = {
2919 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
2920 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2921 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2922 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2923 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2924 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2925 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2926 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2927 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2928 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2929 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2930 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2931 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2932 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2933 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2934 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2935 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2936 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2937 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2938 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2939 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2940 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2941 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2944 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2945 };
2946
2947 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = {
2948 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
2949 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
2950 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
2951 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
2952 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
2953 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
2954 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
2955 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
2956 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
2957 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2958 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2959 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2960 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2961 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2962 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2963 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
2964 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
2965 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
2966 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
2967 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
2968 };
2969
2970 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = {
2971 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00),
2972 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00),
2973 };
2974
2975 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
2976 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2977 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
2978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
2979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff),
2980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),
2981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
2986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
2987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
2988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2989 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2990 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2991 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2992 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2993 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
2994 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
2995 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
2996 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
2997 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14),
2998 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34),
2999 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
3000 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
3001 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
3002 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),
3003 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),
3004 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
3005 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
3006 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
3007 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
3008 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
3009 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
3010 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
3011 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
3012 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
3013 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
3014 };
3015
3016 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl[] = {
3017 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2, 0x01),
3018 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2, 0x01),
3019 };
3020
3021 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_tx_tbl[] = {
3022 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_BIST_MODE_LANENO, 0x00, 2),
3023 };
3024
3025 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
3026 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
3027 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e),
3028 };
3029
3030 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl[] = {
3031 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x00),
3032 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x06),
3033 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x07),
3034 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
3035 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x28),
3036 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x28),
3037 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x0d),
3038 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x0d),
3039 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x00),
3040 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x00),
3041 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
3042 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
3043 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
3044 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0xff),
3045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x09),
3046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x19),
3047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x14),
3048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
3049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x03),
3050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
3051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1, 0x03),
3052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
3053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
3054 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
3055 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
3056 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
3057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
3058 };
3059
3060 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl[] = {
3061 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
3062 };
3063
3064 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl[] = {
3065 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
3066 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x14),
3067 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
3068 };
3069
3070 struct qmp_pcie_offsets {
3071 u16 serdes;
3072 u16 pcs;
3073 u16 pcs_misc;
3074 u16 pcs_lane1;
3075 u16 tx;
3076 u16 rx;
3077 u16 tx2;
3078 u16 rx2;
3079 u16 txz;
3080 u16 rxz;
3081 u16 txrxz;
3082 u16 ln_shrd;
3083 };
3084
3085 struct qmp_phy_cfg_tbls {
3086 const struct qmp_phy_init_tbl *serdes;
3087 int serdes_num;
3088 const struct qmp_phy_init_tbl *tx;
3089 int tx_num;
3090 const struct qmp_phy_init_tbl *rx;
3091 int rx_num;
3092 const struct qmp_phy_init_tbl *txz;
3093 int txz_num;
3094 const struct qmp_phy_init_tbl *rxz;
3095 int rxz_num;
3096 const struct qmp_phy_init_tbl *pcs;
3097 int pcs_num;
3098 const struct qmp_phy_init_tbl *pcs_misc;
3099 int pcs_misc_num;
3100 const struct qmp_phy_init_tbl *pcs_lane1;
3101 int pcs_lane1_num;
3102 const struct qmp_phy_init_tbl *ln_shrd;
3103 int ln_shrd_num;
3104 };
3105
3106 /* struct qmp_phy_cfg - per-PHY initialization config */
3107 struct qmp_phy_cfg {
3108 int lanes;
3109
3110 const struct qmp_pcie_offsets *offsets;
3111
3112 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
3113 const struct qmp_phy_cfg_tbls tbls;
3114 /*
3115 * Additional init sequences for PHY blocks, providing additional
3116 * register programming. They are used for providing separate sequences
3117 * for the Root Complex and End Point use cases.
3118 *
3119 * If EP mode is not supported, both tables can be left unset.
3120 */
3121 const struct qmp_phy_cfg_tbls *tbls_rc;
3122 const struct qmp_phy_cfg_tbls *tbls_ep;
3123
3124 const struct qmp_phy_init_tbl *serdes_4ln_tbl;
3125 int serdes_4ln_num;
3126
3127 /* resets to be requested */
3128 const char * const *reset_list;
3129 int num_resets;
3130 /* regulators to be requested */
3131 const char * const *vreg_list;
3132 int num_vregs;
3133
3134 /* array of registers with different offsets */
3135 const unsigned int *regs;
3136
3137 unsigned int pwrdn_ctrl;
3138 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
3139 unsigned int phy_status;
3140
3141 bool skip_start_delay;
3142
3143 /* QMP PHY pipe clock interface rate */
3144 unsigned long pipe_clock_rate;
3145
3146 /* QMP PHY AUX clock interface rate */
3147 unsigned long aux_clock_rate;
3148 };
3149
3150 struct qmp_pcie {
3151 struct device *dev;
3152
3153 const struct qmp_phy_cfg *cfg;
3154 bool tcsr_4ln_config;
3155 bool skip_init;
3156
3157 void __iomem *serdes;
3158 void __iomem *pcs;
3159 void __iomem *pcs_misc;
3160 void __iomem *pcs_lane1;
3161 void __iomem *tx;
3162 void __iomem *rx;
3163 void __iomem *tx2;
3164 void __iomem *rx2;
3165 void __iomem *txz;
3166 void __iomem *rxz;
3167 void __iomem *ln_shrd;
3168
3169 void __iomem *port_b;
3170
3171 struct clk_bulk_data *clks;
3172 struct clk_bulk_data pipe_clks[2];
3173 int num_pipe_clks;
3174
3175 struct reset_control_bulk_data *resets;
3176 struct reset_control *nocsr_reset;
3177 struct regulator_bulk_data *vregs;
3178
3179 struct phy *phy;
3180 int mode;
3181
3182 struct clk_fixed_rate pipe_clk_fixed;
3183 struct clk_fixed_rate aux_clk_fixed;
3184 };
3185
qphy_checkbits(const void __iomem * base,u32 offset,u32 val)3186 static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val)
3187 {
3188 u32 reg;
3189
3190 reg = readl(base + offset);
3191 return (reg & val) == val;
3192 }
3193
qphy_setbits(void __iomem * base,u32 offset,u32 val)3194 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
3195 {
3196 u32 reg;
3197
3198 reg = readl(base + offset);
3199 reg |= val;
3200 writel(reg, base + offset);
3201
3202 /* ensure that above write is through */
3203 readl(base + offset);
3204 }
3205
qphy_clrbits(void __iomem * base,u32 offset,u32 val)3206 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
3207 {
3208 u32 reg;
3209
3210 reg = readl(base + offset);
3211 reg &= ~val;
3212 writel(reg, base + offset);
3213
3214 /* ensure that above write is through */
3215 readl(base + offset);
3216 }
3217
3218 /* list of clocks required by phy */
3219 static const char * const qmp_pciephy_clk_l[] = {
3220 "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
3221 };
3222
3223 /* list of regulators */
3224 static const char * const qmp_phy_vreg_l[] = {
3225 "vdda-phy", "vdda-pll",
3226 };
3227
3228 static const char * const sm8550_qmp_phy_vreg_l[] = {
3229 "vdda-phy", "vdda-pll", "vdda-qref",
3230 };
3231
3232 /* list of resets */
3233 static const char * const ipq8074_pciephy_reset_l[] = {
3234 "phy", "common",
3235 };
3236
3237 static const char * const sdm845_pciephy_reset_l[] = {
3238 "phy",
3239 };
3240
3241 static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = {
3242 .serdes = 0,
3243 .pcs = 0x1800,
3244 .tx = 0x0800,
3245 /* no .rx for QHP */
3246 };
3247
3248 static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = {
3249 .serdes = 0,
3250 .pcs = 0x0800,
3251 .tx = 0x0200,
3252 .rx = 0x0400,
3253 };
3254
3255 static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = {
3256 .serdes = 0,
3257 .pcs = 0x0800,
3258 .pcs_misc = 0x0600,
3259 .tx = 0x0200,
3260 .rx = 0x0400,
3261 };
3262
3263 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
3264 .serdes = 0,
3265 .pcs = 0x0800,
3266 .pcs_misc = 0x0c00,
3267 .tx = 0x0200,
3268 .rx = 0x0400,
3269 };
3270
3271 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
3272 .serdes = 0,
3273 .pcs = 0x0a00,
3274 .pcs_misc = 0x0e00,
3275 .tx = 0x0200,
3276 .rx = 0x0400,
3277 .tx2 = 0x0600,
3278 .rx2 = 0x0800,
3279 };
3280
3281 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
3282 .serdes = 0x1000,
3283 .pcs = 0x1200,
3284 .pcs_misc = 0x1600,
3285 .pcs_lane1 = 0x1e00,
3286 .tx = 0x0000,
3287 .rx = 0x0200,
3288 .tx2 = 0x0800,
3289 .rx2 = 0x0a00,
3290 };
3291
3292 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
3293 .serdes = 0,
3294 .pcs = 0x0200,
3295 .pcs_misc = 0x0600,
3296 .tx = 0x0e00,
3297 .rx = 0x1000,
3298 .tx2 = 0x1600,
3299 .rx2 = 0x1800,
3300 };
3301
3302 static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
3303 .serdes = 0,
3304 .pcs = 0x1000,
3305 .pcs_misc = 0x1400,
3306 .tx = 0x0200,
3307 .rx = 0x0400,
3308 .tx2 = 0x0600,
3309 .rx2 = 0x0800,
3310 };
3311
3312 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
3313 .serdes = 0x1000,
3314 .pcs = 0x1200,
3315 .pcs_misc = 0x1400,
3316 .pcs_lane1 = 0x1e00,
3317 .tx = 0x0000,
3318 .rx = 0x0200,
3319 .tx2 = 0x0800,
3320 .rx2 = 0x0a00,
3321 .ln_shrd = 0x0e00,
3322 };
3323
3324 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
3325 .serdes = 0x2000,
3326 .pcs = 0x2200,
3327 .pcs_misc = 0x2400,
3328 .tx = 0x0,
3329 .rx = 0x0200,
3330 .tx2 = 0x3800,
3331 .rx2 = 0x3a00,
3332 };
3333
3334 static const struct qmp_pcie_offsets qmp_pcie_offsets_v7 = {
3335 .serdes = 0x0,
3336 .pcs = 0x400,
3337 .pcs_misc = 0x800,
3338 .tx = 0x1000,
3339 .rx = 0x1200,
3340 .tx2 = 0x1800,
3341 .rx2 = 0x1a00,
3342 };
3343
3344 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
3345 .serdes = 0x1000,
3346 .pcs = 0x1200,
3347 .pcs_misc = 0x1400,
3348 .tx = 0x0000,
3349 .rx = 0x0200,
3350 .tx2 = 0x0800,
3351 .rx2 = 0x0a00,
3352 .ln_shrd = 0x0e00,
3353 };
3354
3355 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = {
3356 .serdes = 0x8800,
3357 .pcs = 0x9000,
3358 .pcs_misc = 0x9800,
3359 .tx = 0x0000,
3360 .rx = 0x0200,
3361 .txz = 0xe000,
3362 .rxz = 0xe200,
3363 .ln_shrd = 0x8000,
3364 };
3365
3366 static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 = {
3367 .serdes = 0x8000,
3368 .pcs = 0x9000,
3369 .txrxz = 0xd000,
3370 };
3371
3372 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
3373 .lanes = 1,
3374
3375 .offsets = &qmp_pcie_offsets_v2,
3376
3377 .tbls = {
3378 .serdes = ipq8074_pcie_serdes_tbl,
3379 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
3380 .tx = ipq8074_pcie_tx_tbl,
3381 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
3382 .rx = ipq8074_pcie_rx_tbl,
3383 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
3384 .pcs = ipq8074_pcie_pcs_tbl,
3385 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
3386 },
3387 .reset_list = ipq8074_pciephy_reset_l,
3388 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3389 .vreg_list = NULL,
3390 .num_vregs = 0,
3391 .regs = pciephy_v2_regs_layout,
3392
3393 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3394 .phy_status = PHYSTATUS,
3395 };
3396
3397 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
3398 .lanes = 1,
3399
3400 .offsets = &qmp_pcie_offsets_v4x1,
3401
3402 .tbls = {
3403 .serdes = ipq8074_pcie_gen3_serdes_tbl,
3404 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
3405 .tx = ipq8074_pcie_gen3_tx_tbl,
3406 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
3407 .rx = ipq8074_pcie_gen3_rx_tbl,
3408 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
3409 .pcs = ipq8074_pcie_gen3_pcs_tbl,
3410 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
3411 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl,
3412 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl),
3413 },
3414 .reset_list = ipq8074_pciephy_reset_l,
3415 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3416 .vreg_list = NULL,
3417 .num_vregs = 0,
3418 .regs = pciephy_v4_regs_layout,
3419
3420 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3421 .phy_status = PHYSTATUS,
3422
3423 .pipe_clock_rate = 250000000,
3424 };
3425
3426 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
3427 .lanes = 1,
3428
3429 .offsets = &qmp_pcie_offsets_v4x1,
3430
3431 .tbls = {
3432 .serdes = ipq6018_pcie_serdes_tbl,
3433 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
3434 .tx = ipq6018_pcie_tx_tbl,
3435 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
3436 .rx = ipq6018_pcie_rx_tbl,
3437 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
3438 .pcs = ipq6018_pcie_pcs_tbl,
3439 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
3440 .pcs_misc = ipq6018_pcie_pcs_misc_tbl,
3441 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
3442 },
3443 .reset_list = ipq8074_pciephy_reset_l,
3444 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3445 .vreg_list = NULL,
3446 .num_vregs = 0,
3447 .regs = pciephy_v4_regs_layout,
3448
3449 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3450 .phy_status = PHYSTATUS,
3451 };
3452
3453 static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = {
3454 .lanes = 1,
3455
3456 .offsets = &qmp_pcie_offsets_v4x1,
3457
3458 .tbls = {
3459 .serdes = ipq9574_gen3x1_pcie_serdes_tbl,
3460 .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl),
3461 .tx = ipq8074_pcie_gen3_tx_tbl,
3462 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
3463 .rx = ipq9574_pcie_rx_tbl,
3464 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
3465 .pcs = ipq9574_gen3x1_pcie_pcs_tbl,
3466 .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl),
3467 .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl,
3468 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl),
3469 },
3470 .reset_list = ipq8074_pciephy_reset_l,
3471 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3472 .vreg_list = NULL,
3473 .num_vregs = 0,
3474 .regs = pciephy_v4_regs_layout,
3475
3476 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3477 .phy_status = PHYSTATUS,
3478 .pipe_clock_rate = 250000000,
3479 };
3480
3481 static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {
3482 .lanes = 2,
3483
3484 .offsets = &qmp_pcie_offsets_ipq9574,
3485
3486 .tbls = {
3487 .serdes = ipq9574_gen3x2_pcie_serdes_tbl,
3488 .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
3489 .tx = ipq8074_pcie_gen3_tx_tbl,
3490 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
3491 .rx = ipq9574_pcie_rx_tbl,
3492 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
3493 .pcs = ipq9574_gen3x2_pcie_pcs_tbl,
3494 .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl),
3495 .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
3496 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
3497 },
3498 .reset_list = ipq8074_pciephy_reset_l,
3499 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3500 .vreg_list = NULL,
3501 .num_vregs = 0,
3502 .regs = pciephy_v5_regs_layout,
3503
3504 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3505 .phy_status = PHYSTATUS,
3506 .pipe_clock_rate = 250000000,
3507 };
3508
3509 static const struct qmp_phy_cfg qcs615_pciephy_cfg = {
3510 .lanes = 1,
3511
3512 .offsets = &qmp_pcie_offsets_v2,
3513
3514 .tbls = {
3515 .serdes = qcs615_pcie_serdes_tbl,
3516 .serdes_num = ARRAY_SIZE(qcs615_pcie_serdes_tbl),
3517 .tx = qcs615_pcie_tx_tbl,
3518 .tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl),
3519 .rx = qcs615_pcie_rx_tbl,
3520 .rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl),
3521 .pcs = qcs615_pcie_pcs_tbl,
3522 .pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl),
3523 },
3524 .reset_list = sdm845_pciephy_reset_l,
3525 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3526 .vreg_list = qmp_phy_vreg_l,
3527 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3528 .regs = pciephy_v2_regs_layout,
3529
3530 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3531 .phy_status = PHYSTATUS,
3532 };
3533
3534 static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = {
3535 .lanes = 2,
3536 .offsets = &qmp_pcie_offsets_v5_20,
3537
3538 .tbls = {
3539 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
3540 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
3541 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3542 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
3543 .rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl,
3544 .rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl),
3545 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
3546 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
3547 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
3548 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3549 },
3550
3551 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3552 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
3553 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
3554 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
3555 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
3556 },
3557
3558 .reset_list = sdm845_pciephy_reset_l,
3559 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3560 .vreg_list = qmp_phy_vreg_l,
3561 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3562 .regs = pciephy_v5_regs_layout,
3563
3564 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3565 .phy_status = PHYSTATUS_4_20,
3566 };
3567
3568 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
3569 .lanes = 1,
3570
3571 .offsets = &qmp_pcie_offsets_v3,
3572
3573 .tbls = {
3574 .serdes = sdm845_qmp_pcie_serdes_tbl,
3575 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
3576 .tx = sdm845_qmp_pcie_tx_tbl,
3577 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
3578 .rx = sdm845_qmp_pcie_rx_tbl,
3579 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
3580 .pcs = sdm845_qmp_pcie_pcs_tbl,
3581 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
3582 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl,
3583 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
3584 },
3585 .reset_list = sdm845_pciephy_reset_l,
3586 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3587 .vreg_list = qmp_phy_vreg_l,
3588 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3589 .regs = pciephy_v3_regs_layout,
3590
3591 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3592 .phy_status = PHYSTATUS,
3593 };
3594
3595 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
3596 .lanes = 1,
3597
3598 .offsets = &qmp_pcie_offsets_qhp,
3599
3600 .tbls = {
3601 .serdes = sdm845_qhp_pcie_serdes_tbl,
3602 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
3603 .tx = sdm845_qhp_pcie_tx_tbl,
3604 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
3605 .pcs = sdm845_qhp_pcie_pcs_tbl,
3606 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
3607 },
3608 .reset_list = sdm845_pciephy_reset_l,
3609 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3610 .vreg_list = qmp_phy_vreg_l,
3611 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3612 .regs = sdm845_qhp_pciephy_regs_layout,
3613
3614 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3615 .phy_status = PHYSTATUS,
3616 };
3617
3618 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3619 .lanes = 1,
3620
3621 .offsets = &qmp_pcie_offsets_v4x1,
3622
3623 .tbls = {
3624 .serdes = sm8250_qmp_pcie_serdes_tbl,
3625 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3626 .tx = sm8250_qmp_pcie_tx_tbl,
3627 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3628 .rx = sm8250_qmp_pcie_rx_tbl,
3629 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3630 .pcs = sm8250_qmp_pcie_pcs_tbl,
3631 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3632 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
3633 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3634 },
3635 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3636 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3637 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3638 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl,
3639 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3640 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3641 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3642 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3643 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3644 },
3645 .reset_list = sdm845_pciephy_reset_l,
3646 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3647 .vreg_list = qmp_phy_vreg_l,
3648 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3649 .regs = pciephy_v4_regs_layout,
3650
3651 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3652 .phy_status = PHYSTATUS,
3653 };
3654
3655 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3656 .lanes = 2,
3657
3658 .offsets = &qmp_pcie_offsets_v4x2,
3659
3660 .tbls = {
3661 .serdes = sm8250_qmp_pcie_serdes_tbl,
3662 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3663 .tx = sm8250_qmp_pcie_tx_tbl,
3664 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3665 .rx = sm8250_qmp_pcie_rx_tbl,
3666 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3667 .pcs = sm8250_qmp_pcie_pcs_tbl,
3668 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3669 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
3670 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3671 },
3672 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3673 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl,
3674 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3675 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl,
3676 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3677 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3678 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3679 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3680 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3681 },
3682 .reset_list = sdm845_pciephy_reset_l,
3683 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3684 .vreg_list = qmp_phy_vreg_l,
3685 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3686 .regs = pciephy_v4_regs_layout,
3687
3688 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3689 .phy_status = PHYSTATUS,
3690 };
3691
3692 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3693 .lanes = 1,
3694
3695 .offsets = &qmp_pcie_offsets_v3,
3696
3697 .tbls = {
3698 .serdes = msm8998_pcie_serdes_tbl,
3699 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3700 .tx = msm8998_pcie_tx_tbl,
3701 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3702 .rx = msm8998_pcie_rx_tbl,
3703 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3704 .pcs = msm8998_pcie_pcs_tbl,
3705 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3706 },
3707 .reset_list = ipq8074_pciephy_reset_l,
3708 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3709 .vreg_list = qmp_phy_vreg_l,
3710 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3711 .regs = pciephy_v3_regs_layout,
3712
3713 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3714 .phy_status = PHYSTATUS,
3715
3716 .skip_start_delay = true,
3717 };
3718
3719 static const struct qmp_phy_cfg sar2130p_qmp_gen3x2_pciephy_cfg = {
3720 .lanes = 2,
3721
3722 .offsets = &qmp_pcie_offsets_v5,
3723
3724 .tbls = {
3725 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
3726 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
3727 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
3728 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
3729 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
3730 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
3731 .pcs_lane1 = sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl,
3732 .pcs_lane1_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl),
3733 },
3734 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3735 .serdes = sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl,
3736 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl),
3737 .tx = sar2130p_qmp_gen3x2_pcie_rc_tx_tbl,
3738 .tx_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_tx_tbl),
3739 .pcs = sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl,
3740 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl),
3741 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
3742 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
3743 },
3744 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3745 .serdes = sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl,
3746 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl),
3747 .pcs = sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl,
3748 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl),
3749 .pcs_misc = sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl,
3750 .pcs_misc_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl),
3751 },
3752 .reset_list = sdm845_pciephy_reset_l,
3753 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3754 .vreg_list = qmp_phy_vreg_l,
3755 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3756 .regs = pciephy_v5_regs_layout,
3757
3758 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3759 .phy_status = PHYSTATUS,
3760 };
3761
3762 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
3763 .lanes = 2,
3764
3765 .offsets = &qmp_pcie_offsets_v4x2,
3766
3767 .tbls = {
3768 .serdes = sc8180x_qmp_pcie_serdes_tbl,
3769 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
3770 .tx = sc8180x_qmp_pcie_tx_tbl,
3771 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
3772 .rx = sc8180x_qmp_pcie_rx_tbl,
3773 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
3774 .pcs = sc8180x_qmp_pcie_pcs_tbl,
3775 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
3776 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl,
3777 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
3778 },
3779 .reset_list = sdm845_pciephy_reset_l,
3780 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3781 .vreg_list = qmp_phy_vreg_l,
3782 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3783 .regs = pciephy_v4_regs_layout,
3784
3785 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3786 .phy_status = PHYSTATUS,
3787 };
3788
3789 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
3790 .lanes = 1,
3791
3792 .offsets = &qmp_pcie_offsets_v5,
3793
3794 .tbls = {
3795 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
3796 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3797 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
3798 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),
3799 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl,
3800 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),
3801 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
3802 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),
3803 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,
3804 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),
3805 },
3806
3807 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3808 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,
3809 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
3810 },
3811
3812 .reset_list = sdm845_pciephy_reset_l,
3813 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3814 .vreg_list = qmp_phy_vreg_l,
3815 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3816 .regs = pciephy_v5_regs_layout,
3817
3818 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3819 .phy_status = PHYSTATUS,
3820 };
3821
3822 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
3823 .lanes = 2,
3824
3825 .offsets = &qmp_pcie_offsets_v5,
3826
3827 .tbls = {
3828 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
3829 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3830 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
3831 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
3832 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
3833 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
3834 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
3835 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
3836 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3837 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3838 },
3839
3840 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3841 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
3842 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
3843 },
3844
3845 .reset_list = sdm845_pciephy_reset_l,
3846 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3847 .vreg_list = qmp_phy_vreg_l,
3848 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3849 .regs = pciephy_v5_regs_layout,
3850
3851 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3852 .phy_status = PHYSTATUS,
3853 };
3854
3855 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
3856 .lanes = 4,
3857
3858 .offsets = &qmp_pcie_offsets_v5,
3859
3860 .tbls = {
3861 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
3862 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3863 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
3864 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
3865 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
3866 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
3867 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
3868 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
3869 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3870 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3871 },
3872
3873 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3874 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
3875 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
3876 },
3877
3878 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,
3879 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),
3880
3881 .reset_list = sdm845_pciephy_reset_l,
3882 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3883 .vreg_list = qmp_phy_vreg_l,
3884 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3885 .regs = pciephy_v5_regs_layout,
3886
3887 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3888 .phy_status = PHYSTATUS,
3889 };
3890
3891 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
3892 .lanes = 2,
3893
3894 .offsets = &qmp_pcie_offsets_v4_20,
3895
3896 .tbls = {
3897 .serdes = sdx55_qmp_pcie_serdes_tbl,
3898 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
3899 .tx = sdx55_qmp_pcie_tx_tbl,
3900 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
3901 .rx = sdx55_qmp_pcie_rx_tbl,
3902 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
3903 .pcs = sdx55_qmp_pcie_pcs_tbl,
3904 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
3905 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl,
3906 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
3907 },
3908
3909 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3910 .serdes = sdx55_qmp_pcie_rc_serdes_tbl,
3911 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),
3912 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl,
3913 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),
3914 },
3915
3916 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3917 .serdes = sdx55_qmp_pcie_ep_serdes_tbl,
3918 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
3919 .pcs_lane1 = sdx55_qmp_pcie_ep_pcs_lane1_tbl,
3920 .pcs_lane1_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl),
3921 },
3922
3923 .reset_list = sdm845_pciephy_reset_l,
3924 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3925 .vreg_list = qmp_phy_vreg_l,
3926 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3927 .regs = pciephy_v4_regs_layout,
3928
3929 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3930 .phy_status = PHYSTATUS_4_20,
3931 };
3932
3933 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
3934 .lanes = 1,
3935
3936 .offsets = &qmp_pcie_offsets_v5,
3937
3938 .tbls = {
3939 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
3940 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
3941 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
3942 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
3943 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
3944 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
3945 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
3946 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
3947 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
3948 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
3949 },
3950
3951 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3952 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
3953 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
3954 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
3955 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
3956 },
3957
3958 .reset_list = sdm845_pciephy_reset_l,
3959 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3960 .vreg_list = qmp_phy_vreg_l,
3961 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3962 .regs = pciephy_v5_regs_layout,
3963
3964 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3965 .phy_status = PHYSTATUS,
3966 };
3967
3968 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
3969 .lanes = 2,
3970
3971 .offsets = &qmp_pcie_offsets_v5,
3972
3973 .tbls = {
3974 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
3975 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
3976 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
3977 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
3978 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
3979 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
3980 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
3981 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
3982 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3983 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3984 },
3985
3986 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3987 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
3988 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
3989 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
3990 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
3991 },
3992
3993 .reset_list = sdm845_pciephy_reset_l,
3994 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3995 .vreg_list = qmp_phy_vreg_l,
3996 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3997 .regs = pciephy_v5_regs_layout,
3998
3999 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4000 .phy_status = PHYSTATUS,
4001 };
4002
4003 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
4004 .lanes = 2,
4005
4006 .offsets = &qmp_pcie_offsets_v6_20,
4007
4008 .tbls = {
4009 .serdes = sdx65_qmp_pcie_serdes_tbl,
4010 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl),
4011 .tx = sdx65_qmp_pcie_tx_tbl,
4012 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl),
4013 .rx = sdx65_qmp_pcie_rx_tbl,
4014 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl),
4015 .pcs = sdx65_qmp_pcie_pcs_tbl,
4016 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),
4017 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl,
4018 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
4019 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
4020 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
4021 },
4022 .reset_list = sdm845_pciephy_reset_l,
4023 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4024 .vreg_list = qmp_phy_vreg_l,
4025 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4026 .regs = pciephy_v6_regs_layout,
4027
4028 .pwrdn_ctrl = SW_PWRDN,
4029 .phy_status = PHYSTATUS_4_20,
4030 };
4031
4032 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
4033 .lanes = 1,
4034
4035 .offsets = &qmp_pcie_offsets_v5,
4036
4037 .tbls = {
4038 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
4039 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
4040 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
4041 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
4042 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
4043 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
4044 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
4045 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
4046 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
4047 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
4048 },
4049
4050 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
4051 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
4052 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
4053 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
4054 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
4055 },
4056
4057 .reset_list = sdm845_pciephy_reset_l,
4058 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4059 .vreg_list = qmp_phy_vreg_l,
4060 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4061 .regs = pciephy_v5_regs_layout,
4062
4063 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4064 .phy_status = PHYSTATUS,
4065 };
4066
4067 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
4068 .lanes = 2,
4069
4070 .offsets = &qmp_pcie_offsets_v5_20,
4071
4072 .tbls = {
4073 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl,
4074 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
4075 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl,
4076 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
4077 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl,
4078 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
4079 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl,
4080 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
4081 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
4082 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
4083 },
4084
4085 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
4086 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl,
4087 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl),
4088 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl,
4089 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl),
4090 },
4091
4092 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
4093 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl,
4094 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl),
4095 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
4096 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
4097 },
4098
4099 .reset_list = sdm845_pciephy_reset_l,
4100 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4101 .vreg_list = qmp_phy_vreg_l,
4102 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4103 .regs = pciephy_v5_regs_layout,
4104
4105 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4106 .phy_status = PHYSTATUS_4_20,
4107
4108 /* 20MHz PHY AUX Clock */
4109 .aux_clock_rate = 20000000,
4110 };
4111
4112 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
4113 .lanes = 2,
4114
4115 .offsets = &qmp_pcie_offsets_v5,
4116
4117 .tbls = {
4118 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl,
4119 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
4120 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
4121 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
4122 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
4123 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
4124 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
4125 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
4126 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
4127 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
4128 },
4129 .reset_list = sdm845_pciephy_reset_l,
4130 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4131 .vreg_list = qmp_phy_vreg_l,
4132 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4133 .regs = pciephy_v5_regs_layout,
4134
4135 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4136 .phy_status = PHYSTATUS,
4137 };
4138
4139 static const struct qmp_phy_cfg sm8750_qmp_gen3x2_pciephy_cfg = {
4140 .lanes = 2,
4141
4142 .offsets = &qmp_pcie_offsets_v7,
4143
4144 .tbls = {
4145 .serdes = sm8750_qmp_gen3x2_pcie_serdes_tbl,
4146 .serdes_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_serdes_tbl),
4147 .tx = sm8750_qmp_gen3x2_pcie_tx_tbl,
4148 .tx_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_tx_tbl),
4149 .rx = sm8750_qmp_gen3x2_pcie_rx_tbl,
4150 .rx_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_rx_tbl),
4151 .pcs = sm8750_qmp_gen3x2_pcie_pcs_tbl,
4152 .pcs_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_tbl),
4153 .pcs_misc = sm8750_qmp_gen3x2_pcie_pcs_misc_tbl,
4154 .pcs_misc_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_misc_tbl),
4155 },
4156 .reset_list = sdm845_pciephy_reset_l,
4157 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4158 .vreg_list = qmp_phy_vreg_l,
4159 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4160 .regs = pciephy_v7_regs_layout,
4161
4162 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4163 .phy_status = PHYSTATUS,
4164 };
4165
4166 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
4167 .lanes = 2,
4168
4169 .offsets = &qmp_pcie_offsets_v6_20,
4170
4171 .tbls = {
4172 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
4173 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
4174 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
4175 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
4176 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl,
4177 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
4178 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
4179 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
4180 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
4181 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
4182 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
4183 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
4184 },
4185 .reset_list = sdm845_pciephy_reset_l,
4186 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4187 .vreg_list = sm8550_qmp_phy_vreg_l,
4188 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
4189 .regs = pciephy_v6_regs_layout,
4190
4191 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4192 .phy_status = PHYSTATUS_4_20,
4193
4194 /* 20MHz PHY AUX Clock */
4195 .aux_clock_rate = 20000000,
4196 };
4197
4198 static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {
4199 .lanes = 2,
4200
4201 .offsets = &qmp_pcie_offsets_v6_20,
4202
4203 .tbls = {
4204 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
4205 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
4206 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
4207 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
4208 .rx = sm8650_qmp_gen4x2_pcie_rx_tbl,
4209 .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl),
4210 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
4211 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
4212 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
4213 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
4214 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
4215 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
4216 },
4217 .reset_list = sdm845_pciephy_reset_l,
4218 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4219 .vreg_list = sm8550_qmp_phy_vreg_l,
4220 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
4221 .regs = pciephy_v6_regs_layout,
4222
4223 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4224 .phy_status = PHYSTATUS_4_20,
4225
4226 /* 20MHz PHY AUX Clock */
4227 .aux_clock_rate = 20000000,
4228 };
4229
4230 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
4231 .lanes = 2,
4232 .offsets = &qmp_pcie_offsets_v5_20,
4233
4234 .tbls = {
4235 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
4236 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
4237 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
4238 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
4239 .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl,
4240 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl),
4241 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
4242 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
4243 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
4244 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
4245 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
4246 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
4247 .ln_shrd = sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl,
4248 .ln_shrd_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl),
4249
4250 },
4251
4252 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
4253 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
4254 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
4255 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
4256 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
4257 },
4258
4259 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
4260 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
4261 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
4262 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
4263 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
4264 .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,
4265 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl),
4266 },
4267
4268 .reset_list = sdm845_pciephy_reset_l,
4269 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4270 .vreg_list = qmp_phy_vreg_l,
4271 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4272 .regs = pciephy_v5_regs_layout,
4273
4274 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4275 .phy_status = PHYSTATUS_4_20,
4276 };
4277
4278 static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
4279 .lanes = 4,
4280 .offsets = &qmp_pcie_offsets_v5_30,
4281
4282 .tbls = {
4283 .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl,
4284 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl),
4285 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
4286 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
4287 .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl,
4288 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl),
4289 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
4290 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
4291 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
4292 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
4293 },
4294
4295 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
4296 .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl,
4297 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl),
4298 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
4299 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
4300 },
4301
4302 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
4303 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
4304 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
4305 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
4306 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
4307 },
4308
4309 .reset_list = sdm845_pciephy_reset_l,
4310 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4311 .vreg_list = qmp_phy_vreg_l,
4312 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4313 .regs = pciephy_v5_regs_layout,
4314
4315 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4316 .phy_status = PHYSTATUS_4_20,
4317 };
4318
4319 static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
4320 .lanes = 2,
4321
4322 .offsets = &qmp_pcie_offsets_v6_20,
4323
4324 .tbls = {
4325 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl,
4326 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),
4327 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
4328 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),
4329 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl,
4330 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),
4331 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
4332 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),
4333 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,
4334 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),
4335 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,
4336 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),
4337 },
4338
4339 .reset_list = sdm845_pciephy_reset_l,
4340 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4341 .vreg_list = qmp_phy_vreg_l,
4342 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4343 .regs = pciephy_v6_regs_layout,
4344
4345 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4346 .phy_status = PHYSTATUS_4_20,
4347 };
4348
4349 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
4350 .lanes = 4,
4351
4352 .offsets = &qmp_pcie_offsets_v6_20,
4353
4354 .tbls = {
4355 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl,
4356 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),
4357 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
4358 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),
4359 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl,
4360 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),
4361 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
4362 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),
4363 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,
4364 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),
4365 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,
4366 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),
4367 },
4368
4369 .serdes_4ln_tbl = x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl,
4370 .serdes_4ln_num = ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl),
4371
4372 .reset_list = sdm845_pciephy_reset_l,
4373 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4374 .vreg_list = qmp_phy_vreg_l,
4375 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4376 .regs = pciephy_v6_regs_layout,
4377
4378 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4379 .phy_status = PHYSTATUS_4_20,
4380 };
4381
4382 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
4383 .lanes = 8,
4384
4385 .offsets = &qmp_pcie_offsets_v6_30,
4386 .tbls = {
4387 .serdes = x1e80100_qmp_gen4x8_pcie_serdes_tbl,
4388 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_serdes_tbl),
4389 .rx = x1e80100_qmp_gen4x8_pcie_rx_tbl,
4390 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rx_tbl),
4391 .txz = x1e80100_qmp_gen4x8_pcie_txz_tbl,
4392 .txz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_txz_tbl),
4393 .rxz = x1e80100_qmp_gen4x8_pcie_rxz_tbl,
4394 .rxz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rxz_tbl),
4395 .pcs = x1e80100_qmp_gen4x8_pcie_pcs_tbl,
4396 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_tbl),
4397 .pcs_misc = x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl,
4398 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl),
4399 .ln_shrd = x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl,
4400 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl),
4401 },
4402
4403 .reset_list = sdm845_pciephy_reset_l,
4404 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4405 .vreg_list = qmp_phy_vreg_l,
4406 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4407 .regs = pciephy_v6_regs_layout,
4408
4409 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4410 .phy_status = PHYSTATUS_4_20,
4411 };
4412
4413 static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = {
4414 .lanes = 4,
4415
4416 .offsets = &qmp_pcie_offsets_v6_20,
4417
4418 .reset_list = sdm845_pciephy_reset_l,
4419 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4420 .vreg_list = qmp_phy_vreg_l,
4421 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4422 .regs = pciephy_v6_regs_layout,
4423
4424 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4425 .phy_status = PHYSTATUS_4_20,
4426 };
4427
4428 static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = {
4429 .lanes = 4,
4430
4431 .offsets = &qmp_pcie_offsets_v8_50,
4432
4433 .reset_list = sdm845_pciephy_reset_l,
4434 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4435 .vreg_list = qmp_phy_vreg_l,
4436 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4437
4438 .regs = pciephy_v8_50_regs_layout,
4439
4440 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4441 .phy_status = PHYSTATUS_4_20,
4442 };
4443
qmp_pcie_init_port_b(struct qmp_pcie * qmp,const struct qmp_phy_cfg_tbls * tbls)4444 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
4445 {
4446 const struct qmp_phy_cfg *cfg = qmp->cfg;
4447 const struct qmp_pcie_offsets *offs = cfg->offsets;
4448 void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd;
4449
4450 serdes = qmp->port_b + offs->serdes;
4451 tx3 = qmp->port_b + offs->tx;
4452 rx3 = qmp->port_b + offs->rx;
4453 tx4 = qmp->port_b + offs->tx2;
4454 rx4 = qmp->port_b + offs->rx2;
4455 pcs = qmp->port_b + offs->pcs;
4456 pcs_misc = qmp->port_b + offs->pcs_misc;
4457 ln_shrd = qmp->port_b + offs->ln_shrd;
4458
4459 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
4460 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
4461
4462 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1);
4463 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1);
4464
4465 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2);
4466 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2);
4467
4468 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
4469 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
4470
4471 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
4472 }
4473
qmp_pcie_init_registers(struct qmp_pcie * qmp,const struct qmp_phy_cfg_tbls * tbls)4474 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
4475 {
4476 const struct qmp_phy_cfg *cfg = qmp->cfg;
4477 void __iomem *serdes = qmp->serdes;
4478 void __iomem *tx = qmp->tx;
4479 void __iomem *rx = qmp->rx;
4480 void __iomem *tx2 = qmp->tx2;
4481 void __iomem *rx2 = qmp->rx2;
4482 void __iomem *pcs = qmp->pcs;
4483 void __iomem *pcs_misc = qmp->pcs_misc;
4484 void __iomem *pcs_lane1 = qmp->pcs_lane1;
4485 void __iomem *ln_shrd = qmp->ln_shrd;
4486
4487 if (!tbls)
4488 return;
4489
4490 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
4491
4492 /*
4493 * Tx/Rx registers that require different settings than
4494 * txz/rxz must be programmed after txz/rxz.
4495 */
4496 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num);
4497 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num);
4498
4499 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);
4500 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);
4501
4502 if (cfg->lanes >= 2) {
4503 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2);
4504 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2);
4505 }
4506
4507 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
4508 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
4509 qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num);
4510
4511 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
4512 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl,
4513 cfg->serdes_4ln_num);
4514 qmp_pcie_init_port_b(qmp, tbls);
4515 }
4516
4517 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
4518 }
4519
qmp_pcie_init(struct phy * phy)4520 static int qmp_pcie_init(struct phy *phy)
4521 {
4522 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4523 const struct qmp_phy_cfg *cfg = qmp->cfg;
4524 void __iomem *pcs = qmp->pcs;
4525 int ret;
4526
4527 /*
4528 * We can skip PHY initialization if all of the following conditions
4529 * are met:
4530 * 1. The PHY supports the nocsr_reset that preserves the PHY config.
4531 * 2. The PHY was started (and not powered down again) by the
4532 * bootloader, with all of the expected bits set correctly.
4533 * In this case, we can continue without having the init sequence
4534 * defined in the driver.
4535 */
4536 qmp->skip_init = qmp->nocsr_reset &&
4537 qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START) &&
4538 qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl);
4539
4540 if (!qmp->skip_init && !cfg->tbls.serdes_num) {
4541 dev_err(qmp->dev, "Init sequence not available\n");
4542 return -ENODATA;
4543 }
4544
4545 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
4546 if (ret) {
4547 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
4548 return ret;
4549 }
4550
4551 /*
4552 * Toggle BCR reset for PHY that doesn't support no_csr reset or has not
4553 * been initialized.
4554 */
4555 if (!qmp->skip_init) {
4556 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
4557 if (ret) {
4558 dev_err(qmp->dev, "reset assert failed\n");
4559 goto err_disable_regulators;
4560 }
4561 }
4562
4563 ret = reset_control_assert(qmp->nocsr_reset);
4564 if (ret) {
4565 dev_err(qmp->dev, "no-csr reset assert failed\n");
4566 goto err_assert_reset;
4567 }
4568
4569 usleep_range(200, 300);
4570
4571 if (!qmp->skip_init) {
4572 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
4573 if (ret) {
4574 dev_err(qmp->dev, "reset deassert failed\n");
4575 goto err_assert_reset;
4576 }
4577 }
4578
4579 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
4580 if (ret)
4581 goto err_assert_reset;
4582
4583 return 0;
4584
4585 err_assert_reset:
4586 if (!qmp->skip_init)
4587 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
4588 err_disable_regulators:
4589 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4590
4591 return ret;
4592 }
4593
qmp_pcie_exit(struct phy * phy)4594 static int qmp_pcie_exit(struct phy *phy)
4595 {
4596 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4597 const struct qmp_phy_cfg *cfg = qmp->cfg;
4598
4599 if (qmp->nocsr_reset)
4600 reset_control_assert(qmp->nocsr_reset);
4601 else
4602 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
4603
4604 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
4605
4606 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4607
4608 return 0;
4609 }
4610
qmp_pcie_power_on(struct phy * phy)4611 static int qmp_pcie_power_on(struct phy *phy)
4612 {
4613 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4614 const struct qmp_phy_cfg *cfg = qmp->cfg;
4615 const struct qmp_phy_cfg_tbls *mode_tbls;
4616 void __iomem *pcs = qmp->pcs;
4617 void __iomem *status;
4618 unsigned int mask, val;
4619 int ret;
4620
4621 /*
4622 * Write CSR register for PHY that doesn't support no_csr reset or has not
4623 * been initialized.
4624 */
4625 if (qmp->skip_init)
4626 goto skip_tbls_init;
4627
4628 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4629 cfg->pwrdn_ctrl);
4630
4631 if (qmp->mode == PHY_MODE_PCIE_RC)
4632 mode_tbls = cfg->tbls_rc;
4633 else
4634 mode_tbls = cfg->tbls_ep;
4635
4636 qmp_pcie_init_registers(qmp, &cfg->tbls);
4637 qmp_pcie_init_registers(qmp, mode_tbls);
4638
4639 skip_tbls_init:
4640 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
4641 if (ret)
4642 return ret;
4643
4644 ret = reset_control_deassert(qmp->nocsr_reset);
4645 if (ret) {
4646 dev_err(qmp->dev, "no-csr reset deassert failed\n");
4647 goto err_disable_pipe_clk;
4648 }
4649
4650 if (qmp->skip_init)
4651 goto skip_serdes_start;
4652
4653 /* Pull PHY out of reset state */
4654 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4655
4656 /* start SerDes and Phy-Coding-Sublayer */
4657 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
4658
4659 if (!cfg->skip_start_delay)
4660 usleep_range(1000, 1200);
4661
4662 skip_serdes_start:
4663 status = pcs + cfg->regs[QPHY_PCS_STATUS];
4664 mask = cfg->phy_status;
4665 ret = readl_poll_timeout(status, val, !(val & mask), 200,
4666 PHY_INIT_COMPLETE_TIMEOUT);
4667 if (ret) {
4668 dev_err(qmp->dev, "phy initialization timed-out\n");
4669 goto err_disable_pipe_clk;
4670 }
4671
4672 return 0;
4673
4674 err_disable_pipe_clk:
4675 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
4676
4677 return ret;
4678 }
4679
qmp_pcie_power_off(struct phy * phy)4680 static int qmp_pcie_power_off(struct phy *phy)
4681 {
4682 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4683 const struct qmp_phy_cfg *cfg = qmp->cfg;
4684
4685 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
4686
4687 /*
4688 * While powering off the PHY, only qmp->nocsr_reset needs to be checked. In
4689 * this way, no matter whether the PHY settings were initially programmed by
4690 * bootloader or PHY driver itself, we can reuse them when PHY is powered on
4691 * next time.
4692 */
4693 if (qmp->nocsr_reset)
4694 goto skip_phy_deinit;
4695
4696 /* PHY reset */
4697 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4698
4699 /* stop SerDes and Phy-Coding-Sublayer */
4700 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
4701 SERDES_START | PCS_START);
4702
4703 /* Put PHY into POWER DOWN state: active low */
4704 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4705 cfg->pwrdn_ctrl);
4706
4707 skip_phy_deinit:
4708 return 0;
4709 }
4710
qmp_pcie_enable(struct phy * phy)4711 static int qmp_pcie_enable(struct phy *phy)
4712 {
4713 int ret;
4714
4715 ret = qmp_pcie_init(phy);
4716 if (ret)
4717 return ret;
4718
4719 ret = qmp_pcie_power_on(phy);
4720 if (ret)
4721 qmp_pcie_exit(phy);
4722
4723 return ret;
4724 }
4725
qmp_pcie_disable(struct phy * phy)4726 static int qmp_pcie_disable(struct phy *phy)
4727 {
4728 int ret;
4729
4730 ret = qmp_pcie_power_off(phy);
4731 if (ret)
4732 return ret;
4733
4734 return qmp_pcie_exit(phy);
4735 }
4736
qmp_pcie_set_mode(struct phy * phy,enum phy_mode mode,int submode)4737 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
4738 {
4739 struct qmp_pcie *qmp = phy_get_drvdata(phy);
4740
4741 switch (submode) {
4742 case PHY_MODE_PCIE_RC:
4743 case PHY_MODE_PCIE_EP:
4744 qmp->mode = submode;
4745 break;
4746 default:
4747 dev_err(&phy->dev, "Unsupported submode %d\n", submode);
4748 return -EINVAL;
4749 }
4750
4751 return 0;
4752 }
4753
4754 static const struct phy_ops qmp_pcie_phy_ops = {
4755 .power_on = qmp_pcie_enable,
4756 .power_off = qmp_pcie_disable,
4757 .set_mode = qmp_pcie_set_mode,
4758 .owner = THIS_MODULE,
4759 };
4760
qmp_pcie_vreg_init(struct qmp_pcie * qmp)4761 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
4762 {
4763 const struct qmp_phy_cfg *cfg = qmp->cfg;
4764 struct device *dev = qmp->dev;
4765 int num = cfg->num_vregs;
4766 int i;
4767
4768 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
4769 if (!qmp->vregs)
4770 return -ENOMEM;
4771
4772 for (i = 0; i < num; i++)
4773 qmp->vregs[i].supply = cfg->vreg_list[i];
4774
4775 return devm_regulator_bulk_get(dev, num, qmp->vregs);
4776 }
4777
qmp_pcie_reset_init(struct qmp_pcie * qmp)4778 static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
4779 {
4780 const struct qmp_phy_cfg *cfg = qmp->cfg;
4781 struct device *dev = qmp->dev;
4782 int i;
4783 int ret;
4784
4785 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
4786 sizeof(*qmp->resets), GFP_KERNEL);
4787 if (!qmp->resets)
4788 return -ENOMEM;
4789
4790 for (i = 0; i < cfg->num_resets; i++)
4791 qmp->resets[i].id = cfg->reset_list[i];
4792
4793 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
4794 if (ret)
4795 return dev_err_probe(dev, ret, "failed to get resets\n");
4796
4797 qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr");
4798 if (IS_ERR(qmp->nocsr_reset))
4799 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
4800 "failed to get no-csr reset\n");
4801
4802 return 0;
4803 }
4804
qmp_pcie_clk_init(struct qmp_pcie * qmp)4805 static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
4806 {
4807 struct device *dev = qmp->dev;
4808 int num = ARRAY_SIZE(qmp_pciephy_clk_l);
4809 int i;
4810
4811 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
4812 if (!qmp->clks)
4813 return -ENOMEM;
4814
4815 for (i = 0; i < num; i++)
4816 qmp->clks[i].id = qmp_pciephy_clk_l[i];
4817
4818 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
4819 }
4820
phy_clk_release_provider(void * res)4821 static void phy_clk_release_provider(void *res)
4822 {
4823 of_clk_del_provider(res);
4824 }
4825
4826 /*
4827 * Register a fixed rate pipe clock.
4828 *
4829 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
4830 * controls it. The <s>_pipe_clk coming out of the GCC is requested
4831 * by the PHY driver for its operations.
4832 * We register the <s>_pipe_clksrc here. The gcc driver takes care
4833 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
4834 * Below picture shows this relationship.
4835 *
4836 * +---------------+
4837 * | PHY block |<<---------------------------------------+
4838 * | | |
4839 * | +-------+ | +-----+ |
4840 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
4841 * clk | +-------+ | +-----+
4842 * +---------------+
4843 */
phy_pipe_clk_register(struct qmp_pcie * qmp,struct device_node * np)4844 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
4845 {
4846 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
4847 struct clk_init_data init = { };
4848 int ret;
4849
4850 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name);
4851 if (ret) {
4852 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
4853 return ret;
4854 }
4855
4856 init.ops = &clk_fixed_rate_ops;
4857
4858 /*
4859 * Controllers using QMP PHY-s use 125MHz pipe clock interface
4860 * unless other frequency is specified in the PHY config.
4861 */
4862 if (qmp->cfg->pipe_clock_rate)
4863 fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
4864 else
4865 fixed->fixed_rate = 125000000;
4866
4867 fixed->hw.init = &init;
4868
4869 return devm_clk_hw_register(qmp->dev, &fixed->hw);
4870 }
4871
4872 /*
4873 * Register a fixed rate PHY aux clock.
4874 *
4875 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate
4876 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested
4877 * by the PHY driver for its operations.
4878 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care
4879 * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk.
4880 * Below picture shows this relationship.
4881 *
4882 * +---------------+
4883 * | PHY block |<<---------------------------------------------+
4884 * | | |
4885 * | +-------+ | +-----+ |
4886 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+
4887 * clk | +-------+ | +-----+
4888 * +---------------+
4889 */
phy_aux_clk_register(struct qmp_pcie * qmp,struct device_node * np)4890 static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)
4891 {
4892 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;
4893 struct clk_init_data init = { };
4894 char name[64];
4895
4896 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev));
4897
4898 init.name = name;
4899 init.ops = &clk_fixed_rate_ops;
4900
4901 fixed->fixed_rate = qmp->cfg->aux_clock_rate;
4902 fixed->hw.init = &init;
4903
4904 return devm_clk_hw_register(qmp->dev, &fixed->hw);
4905 }
4906
qmp_pcie_clk_hw_get(struct of_phandle_args * clkspec,void * data)4907 static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data)
4908 {
4909 struct qmp_pcie *qmp = data;
4910
4911 /* Support legacy bindings */
4912 if (!clkspec->args_count)
4913 return &qmp->pipe_clk_fixed.hw;
4914
4915 switch (clkspec->args[0]) {
4916 case QMP_PCIE_PIPE_CLK:
4917 return &qmp->pipe_clk_fixed.hw;
4918 case QMP_PCIE_PHY_AUX_CLK:
4919 return &qmp->aux_clk_fixed.hw;
4920 }
4921
4922 return ERR_PTR(-EINVAL);
4923 }
4924
qmp_pcie_register_clocks(struct qmp_pcie * qmp,struct device_node * np)4925 static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np)
4926 {
4927 int ret;
4928
4929 ret = phy_pipe_clk_register(qmp, np);
4930 if (ret)
4931 return ret;
4932
4933 if (qmp->cfg->aux_clock_rate) {
4934 ret = phy_aux_clk_register(qmp, np);
4935 if (ret)
4936 return ret;
4937
4938 ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp);
4939 if (ret)
4940 return ret;
4941 } else {
4942 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw);
4943 if (ret)
4944 return ret;
4945 }
4946
4947 /*
4948 * Roll a devm action because the clock provider is the child node, but
4949 * the child node is not actually a device.
4950 */
4951 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
4952 }
4953
qmp_pcie_parse_dt_legacy(struct qmp_pcie * qmp,struct device_node * np)4954 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)
4955 {
4956 struct platform_device *pdev = to_platform_device(qmp->dev);
4957 const struct qmp_phy_cfg *cfg = qmp->cfg;
4958 struct device *dev = qmp->dev;
4959 struct clk *clk;
4960
4961 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
4962 if (IS_ERR(qmp->serdes))
4963 return PTR_ERR(qmp->serdes);
4964
4965 /*
4966 * Get memory resources for the PHY:
4967 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
4968 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
4969 * For single lane PHYs: pcs_misc (optional) -> 3.
4970 */
4971 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
4972 if (IS_ERR(qmp->tx))
4973 return PTR_ERR(qmp->tx);
4974
4975 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
4976 qmp->rx = qmp->tx;
4977 else
4978 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
4979 if (IS_ERR(qmp->rx))
4980 return PTR_ERR(qmp->rx);
4981
4982 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
4983 if (IS_ERR(qmp->pcs))
4984 return PTR_ERR(qmp->pcs);
4985
4986 if (cfg->lanes >= 2) {
4987 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
4988 if (IS_ERR(qmp->tx2))
4989 return PTR_ERR(qmp->tx2);
4990
4991 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
4992 if (IS_ERR(qmp->rx2))
4993 return PTR_ERR(qmp->rx2);
4994
4995 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
4996 } else {
4997 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
4998 }
4999
5000 if (IS_ERR(qmp->pcs_misc) &&
5001 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
5002 qmp->pcs_misc = qmp->pcs + 0x400;
5003
5004 if (IS_ERR(qmp->pcs_misc)) {
5005 if (cfg->tbls.pcs_misc ||
5006 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) ||
5007 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) {
5008 return PTR_ERR(qmp->pcs_misc);
5009 }
5010 }
5011
5012 /*
5013 * For all platforms where legacy bindings existed, PCS_LANE1 was
5014 * mapped as a part of the PCS_MISC region.
5015 */
5016 if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0)
5017 qmp->pcs_lane1 = qmp->pcs_misc +
5018 (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc);
5019
5020 clk = devm_get_clk_from_child(dev, np, NULL);
5021 if (IS_ERR(clk)) {
5022 return dev_err_probe(dev, PTR_ERR(clk),
5023 "failed to get pipe clock\n");
5024 }
5025
5026 qmp->num_pipe_clks = 1;
5027 qmp->pipe_clks[0].id = "pipe";
5028 qmp->pipe_clks[0].clk = clk;
5029
5030 return 0;
5031 }
5032
qmp_pcie_get_4ln_config(struct qmp_pcie * qmp)5033 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)
5034 {
5035 struct regmap *tcsr;
5036 unsigned int args[2];
5037 int ret;
5038
5039 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,
5040 "qcom,4ln-config-sel",
5041 ARRAY_SIZE(args), args);
5042 if (IS_ERR(tcsr)) {
5043 ret = PTR_ERR(tcsr);
5044 if (ret == -ENOENT)
5045 return 0;
5046
5047 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);
5048 return ret;
5049 }
5050
5051 ret = regmap_test_bits(tcsr, args[0], BIT(args[1]));
5052 if (ret < 0) {
5053 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);
5054 return ret;
5055 }
5056
5057 qmp->tcsr_4ln_config = ret;
5058
5059 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);
5060
5061 return 0;
5062 }
5063
qmp_pcie_parse_dt(struct qmp_pcie * qmp)5064 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
5065 {
5066 struct platform_device *pdev = to_platform_device(qmp->dev);
5067 const struct qmp_phy_cfg *cfg = qmp->cfg;
5068 const struct qmp_pcie_offsets *offs = cfg->offsets;
5069 struct device *dev = qmp->dev;
5070 void __iomem *base;
5071 int ret;
5072
5073 if (!offs)
5074 return -EINVAL;
5075
5076 ret = qmp_pcie_get_4ln_config(qmp);
5077 if (ret)
5078 return ret;
5079
5080 base = devm_platform_ioremap_resource(pdev, 0);
5081 if (IS_ERR(base))
5082 return PTR_ERR(base);
5083
5084 qmp->serdes = base + offs->serdes;
5085 qmp->pcs = base + offs->pcs;
5086 qmp->pcs_misc = base + offs->pcs_misc;
5087 qmp->pcs_lane1 = base + offs->pcs_lane1;
5088 qmp->tx = base + offs->tx;
5089 qmp->rx = base + offs->rx;
5090
5091 if (cfg->lanes >= 2) {
5092 qmp->tx2 = base + offs->tx2;
5093 qmp->rx2 = base + offs->rx2;
5094 }
5095
5096 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
5097 qmp->port_b = devm_platform_ioremap_resource(pdev, 1);
5098 if (IS_ERR(qmp->port_b))
5099 return PTR_ERR(qmp->port_b);
5100 }
5101
5102 qmp->txz = base + offs->txz;
5103 qmp->rxz = base + offs->rxz;
5104
5105 if (cfg->tbls.ln_shrd)
5106 qmp->ln_shrd = base + offs->ln_shrd;
5107
5108 qmp->num_pipe_clks = 2;
5109 qmp->pipe_clks[0].id = "pipe";
5110 qmp->pipe_clks[1].id = "pipediv2";
5111
5112 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
5113 if (ret)
5114 return ret;
5115
5116 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
5117 if (ret)
5118 return ret;
5119
5120 return 0;
5121 }
5122
qmp_pcie_probe(struct platform_device * pdev)5123 static int qmp_pcie_probe(struct platform_device *pdev)
5124 {
5125 struct device *dev = &pdev->dev;
5126 struct phy_provider *phy_provider;
5127 struct device_node *np;
5128 struct qmp_pcie *qmp;
5129 int ret;
5130
5131 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
5132 if (!qmp)
5133 return -ENOMEM;
5134
5135 qmp->dev = dev;
5136
5137 qmp->cfg = of_device_get_match_data(dev);
5138 if (!qmp->cfg)
5139 return -EINVAL;
5140
5141 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
5142 WARN_ON_ONCE(!qmp->cfg->phy_status);
5143
5144 ret = qmp_pcie_clk_init(qmp);
5145 if (ret)
5146 return ret;
5147
5148 ret = qmp_pcie_reset_init(qmp);
5149 if (ret)
5150 return ret;
5151
5152 ret = qmp_pcie_vreg_init(qmp);
5153 if (ret)
5154 return ret;
5155
5156 /* Check for legacy binding with child node. */
5157 np = of_get_next_available_child(dev->of_node, NULL);
5158 if (np) {
5159 ret = qmp_pcie_parse_dt_legacy(qmp, np);
5160 } else {
5161 np = of_node_get(dev->of_node);
5162 ret = qmp_pcie_parse_dt(qmp);
5163 }
5164 if (ret)
5165 goto err_node_put;
5166
5167 ret = qmp_pcie_register_clocks(qmp, np);
5168 if (ret)
5169 goto err_node_put;
5170
5171 qmp->mode = PHY_MODE_PCIE_RC;
5172
5173 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
5174 if (IS_ERR(qmp->phy)) {
5175 ret = PTR_ERR(qmp->phy);
5176 dev_err(dev, "failed to create PHY: %d\n", ret);
5177 goto err_node_put;
5178 }
5179
5180 phy_set_drvdata(qmp->phy, qmp);
5181
5182 of_node_put(np);
5183
5184 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
5185
5186 return PTR_ERR_OR_ZERO(phy_provider);
5187
5188 err_node_put:
5189 of_node_put(np);
5190 return ret;
5191 }
5192
5193 static const struct of_device_id qmp_pcie_of_match_table[] = {
5194 {
5195 .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
5196 .data = &glymur_qmp_gen5x4_pciephy_cfg,
5197 }, {
5198 .compatible = "qcom,ipq6018-qmp-pcie-phy",
5199 .data = &ipq6018_pciephy_cfg,
5200 }, {
5201 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
5202 .data = &ipq8074_pciephy_gen3_cfg,
5203 }, {
5204 .compatible = "qcom,ipq8074-qmp-pcie-phy",
5205 .data = &ipq8074_pciephy_cfg,
5206 }, {
5207 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
5208 .data = &ipq9574_gen3x1_pciephy_cfg,
5209 }, {
5210 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
5211 .data = &ipq9574_gen3x2_pciephy_cfg,
5212 }, {
5213 .compatible = "qcom,msm8998-qmp-pcie-phy",
5214 .data = &msm8998_pciephy_cfg,
5215 }, {
5216 .compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
5217 .data = &qcs615_pciephy_cfg,
5218 }, {
5219 .compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy",
5220 .data = &qcs8300_qmp_gen4x2_pciephy_cfg,
5221 }, {
5222 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
5223 .data = &sa8775p_qmp_gen4x2_pciephy_cfg,
5224 }, {
5225 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
5226 .data = &sa8775p_qmp_gen4x4_pciephy_cfg,
5227 }, {
5228 .compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy",
5229 .data = &sar2130p_qmp_gen3x2_pciephy_cfg,
5230 }, {
5231 .compatible = "qcom,sc8180x-qmp-pcie-phy",
5232 .data = &sc8180x_pciephy_cfg,
5233 }, {
5234 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
5235 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg,
5236 }, {
5237 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
5238 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg,
5239 }, {
5240 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
5241 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg,
5242 }, {
5243 .compatible = "qcom,sdm845-qhp-pcie-phy",
5244 .data = &sdm845_qhp_pciephy_cfg,
5245 }, {
5246 .compatible = "qcom,sdm845-qmp-pcie-phy",
5247 .data = &sdm845_qmp_pciephy_cfg,
5248 }, {
5249 .compatible = "qcom,sdx55-qmp-pcie-phy",
5250 .data = &sdx55_qmp_pciephy_cfg,
5251 }, {
5252 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
5253 .data = &sdx65_qmp_pciephy_cfg,
5254 }, {
5255 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
5256 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
5257 }, {
5258 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
5259 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5260 }, {
5261 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5262 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
5263 }, {
5264 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5265 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5266 }, {
5267 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5268 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5269 }, {
5270 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
5271 .data = &sm8350_qmp_gen3x1_pciephy_cfg,
5272 }, {
5273 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
5274 .data = &sm8350_qmp_gen3x2_pciephy_cfg,
5275 }, {
5276 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
5277 .data = &sm8450_qmp_gen3x1_pciephy_cfg,
5278 }, {
5279 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
5280 .data = &sm8450_qmp_gen4x2_pciephy_cfg,
5281 }, {
5282 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
5283 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
5284 }, {
5285 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
5286 .data = &sm8550_qmp_gen4x2_pciephy_cfg,
5287 }, {
5288 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
5289 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
5290 }, {
5291 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
5292 .data = &sm8650_qmp_gen4x2_pciephy_cfg,
5293 }, {
5294 .compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy",
5295 .data = &sm8750_qmp_gen3x2_pciephy_cfg,
5296 }, {
5297 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
5298 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
5299 }, {
5300 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
5301 .data = &x1e80100_qmp_gen4x2_pciephy_cfg,
5302 }, {
5303 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
5304 .data = &x1e80100_qmp_gen4x4_pciephy_cfg,
5305 }, {
5306 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
5307 .data = &x1e80100_qmp_gen4x8_pciephy_cfg,
5308 }, {
5309 .compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy",
5310 .data = &qmp_v6_gen4x4_pciephy_cfg,
5311 },
5312 { },
5313 };
5314 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table);
5315
5316 static struct platform_driver qmp_pcie_driver = {
5317 .probe = qmp_pcie_probe,
5318 .driver = {
5319 .name = "qcom-qmp-pcie-phy",
5320 .of_match_table = qmp_pcie_of_match_table,
5321 },
5322 };
5323
5324 module_platform_driver(qmp_pcie_driver);
5325
5326 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
5327 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");
5328 MODULE_LICENSE("GPL v2");
5329