1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/netdevice.h>
6 #include <linux/if_ether.h>
7 #include <linux/if_vlan.h>
8 #include <linux/iopoll.h>
9 #include <linux/pci.h>
10
11 #include "wx_type.h"
12 #include "wx_lib.h"
13 #include "wx_hw.h"
14
wx_phy_read_reg_mdi(struct mii_bus * bus,int phy_addr,int devnum,int regnum)15 static int wx_phy_read_reg_mdi(struct mii_bus *bus, int phy_addr, int devnum, int regnum)
16 {
17 struct wx *wx = bus->priv;
18 u32 command, val;
19 int ret;
20
21 /* setup and write the address cycle command */
22 command = WX_MSCA_RA(regnum) |
23 WX_MSCA_PA(phy_addr) |
24 WX_MSCA_DA(devnum);
25 wr32(wx, WX_MSCA, command);
26
27 command = WX_MSCC_CMD(WX_MSCA_CMD_READ) | WX_MSCC_BUSY;
28 if (wx->mac.type == wx_mac_em)
29 command |= WX_MDIO_CLK(6);
30 wr32(wx, WX_MSCC, command);
31
32 /* wait to complete */
33 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
34 100000, false, wx, WX_MSCC);
35 if (ret) {
36 wx_err(wx, "Mdio read c22 command did not complete.\n");
37 return ret;
38 }
39
40 return (u16)rd32(wx, WX_MSCC);
41 }
42
wx_phy_write_reg_mdi(struct mii_bus * bus,int phy_addr,int devnum,int regnum,u16 value)43 static int wx_phy_write_reg_mdi(struct mii_bus *bus, int phy_addr,
44 int devnum, int regnum, u16 value)
45 {
46 struct wx *wx = bus->priv;
47 u32 command, val;
48 int ret;
49
50 /* setup and write the address cycle command */
51 command = WX_MSCA_RA(regnum) |
52 WX_MSCA_PA(phy_addr) |
53 WX_MSCA_DA(devnum);
54 wr32(wx, WX_MSCA, command);
55
56 command = value | WX_MSCC_CMD(WX_MSCA_CMD_WRITE) | WX_MSCC_BUSY;
57 if (wx->mac.type == wx_mac_em)
58 command |= WX_MDIO_CLK(6);
59 wr32(wx, WX_MSCC, command);
60
61 /* wait to complete */
62 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
63 100000, false, wx, WX_MSCC);
64 if (ret)
65 wx_err(wx, "Mdio write c22 command did not complete.\n");
66
67 return ret;
68 }
69
wx_phy_read_reg_mdi_c22(struct mii_bus * bus,int phy_addr,int regnum)70 int wx_phy_read_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum)
71 {
72 struct wx *wx = bus->priv;
73
74 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF);
75 return wx_phy_read_reg_mdi(bus, phy_addr, 0, regnum);
76 }
77 EXPORT_SYMBOL(wx_phy_read_reg_mdi_c22);
78
wx_phy_write_reg_mdi_c22(struct mii_bus * bus,int phy_addr,int regnum,u16 value)79 int wx_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
80 {
81 struct wx *wx = bus->priv;
82
83 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF);
84 return wx_phy_write_reg_mdi(bus, phy_addr, 0, regnum, value);
85 }
86 EXPORT_SYMBOL(wx_phy_write_reg_mdi_c22);
87
wx_phy_read_reg_mdi_c45(struct mii_bus * bus,int phy_addr,int devnum,int regnum)88 int wx_phy_read_reg_mdi_c45(struct mii_bus *bus, int phy_addr, int devnum, int regnum)
89 {
90 struct wx *wx = bus->priv;
91
92 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0);
93 return wx_phy_read_reg_mdi(bus, phy_addr, devnum, regnum);
94 }
95 EXPORT_SYMBOL(wx_phy_read_reg_mdi_c45);
96
wx_phy_write_reg_mdi_c45(struct mii_bus * bus,int phy_addr,int devnum,int regnum,u16 value)97 int wx_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr,
98 int devnum, int regnum, u16 value)
99 {
100 struct wx *wx = bus->priv;
101
102 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0);
103 return wx_phy_write_reg_mdi(bus, phy_addr, devnum, regnum, value);
104 }
105 EXPORT_SYMBOL(wx_phy_write_reg_mdi_c45);
106
wx_intr_disable(struct wx * wx,u64 qmask)107 static void wx_intr_disable(struct wx *wx, u64 qmask)
108 {
109 u32 mask;
110
111 mask = (qmask & U32_MAX);
112 if (mask)
113 wr32(wx, WX_PX_IMS(0), mask);
114
115 if (wx->mac.type == wx_mac_sp) {
116 mask = (qmask >> 32);
117 if (mask)
118 wr32(wx, WX_PX_IMS(1), mask);
119 }
120 }
121
wx_intr_enable(struct wx * wx,u64 qmask)122 void wx_intr_enable(struct wx *wx, u64 qmask)
123 {
124 u32 mask;
125
126 mask = (qmask & U32_MAX);
127 if (mask)
128 wr32(wx, WX_PX_IMC(0), mask);
129 if (wx->mac.type == wx_mac_sp) {
130 mask = (qmask >> 32);
131 if (mask)
132 wr32(wx, WX_PX_IMC(1), mask);
133 }
134 }
135 EXPORT_SYMBOL(wx_intr_enable);
136
137 /**
138 * wx_irq_disable - Mask off interrupt generation on the NIC
139 * @wx: board private structure
140 **/
wx_irq_disable(struct wx * wx)141 void wx_irq_disable(struct wx *wx)
142 {
143 struct pci_dev *pdev = wx->pdev;
144
145 wr32(wx, WX_PX_MISC_IEN, 0);
146 wx_intr_disable(wx, WX_INTR_ALL);
147
148 if (pdev->msix_enabled) {
149 int vector;
150
151 for (vector = 0; vector < wx->num_q_vectors; vector++)
152 synchronize_irq(wx->msix_q_entries[vector].vector);
153
154 synchronize_irq(wx->msix_entry->vector);
155 } else {
156 synchronize_irq(pdev->irq);
157 }
158 }
159 EXPORT_SYMBOL(wx_irq_disable);
160
161 /* cmd_addr is used for some special command:
162 * 1. to be sector address, when implemented erase sector command
163 * 2. to be flash address when implemented read, write flash address
164 */
wx_fmgr_cmd_op(struct wx * wx,u32 cmd,u32 cmd_addr)165 static int wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr)
166 {
167 u32 cmd_val = 0, val = 0;
168
169 cmd_val = WX_SPI_CMD_CMD(cmd) |
170 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) |
171 cmd_addr;
172 wr32(wx, WX_SPI_CMD, cmd_val);
173
174 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000,
175 false, wx, WX_SPI_STATUS);
176 }
177
wx_flash_read_dword(struct wx * wx,u32 addr,u32 * data)178 static int wx_flash_read_dword(struct wx *wx, u32 addr, u32 *data)
179 {
180 int ret = 0;
181
182 ret = wx_fmgr_cmd_op(wx, WX_SPI_CMD_READ_DWORD, addr);
183 if (ret < 0)
184 return ret;
185
186 *data = rd32(wx, WX_SPI_DATA);
187
188 return ret;
189 }
190
wx_check_flash_load(struct wx * hw,u32 check_bit)191 int wx_check_flash_load(struct wx *hw, u32 check_bit)
192 {
193 u32 reg = 0;
194 int err = 0;
195
196 /* if there's flash existing */
197 if (!(rd32(hw, WX_SPI_STATUS) &
198 WX_SPI_STATUS_FLASH_BYPASS)) {
199 /* wait hw load flash done */
200 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000,
201 false, hw, WX_SPI_ILDR_STATUS);
202 if (err < 0)
203 wx_err(hw, "Check flash load timeout.\n");
204 }
205
206 return err;
207 }
208 EXPORT_SYMBOL(wx_check_flash_load);
209
wx_control_hw(struct wx * wx,bool drv)210 void wx_control_hw(struct wx *wx, bool drv)
211 {
212 /* True : Let firmware know the driver has taken over
213 * False : Let firmware take over control of hw
214 */
215 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD,
216 drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0);
217 }
218 EXPORT_SYMBOL(wx_control_hw);
219
220 /**
221 * wx_mng_present - returns 0 when management capability is present
222 * @wx: pointer to hardware structure
223 */
wx_mng_present(struct wx * wx)224 int wx_mng_present(struct wx *wx)
225 {
226 u32 fwsm;
227
228 fwsm = rd32(wx, WX_MIS_ST);
229 if (fwsm & WX_MIS_ST_MNG_INIT_DN)
230 return 0;
231 else
232 return -EACCES;
233 }
234 EXPORT_SYMBOL(wx_mng_present);
235
236 /* Software lock to be held while software semaphore is being accessed. */
237 static DEFINE_MUTEX(wx_sw_sync_lock);
238
239 /**
240 * wx_release_sw_sync - Release SW semaphore
241 * @wx: pointer to hardware structure
242 * @mask: Mask to specify which semaphore to release
243 *
244 * Releases the SW semaphore for the specified
245 * function (CSR, PHY0, PHY1, EEPROM, Flash)
246 **/
wx_release_sw_sync(struct wx * wx,u32 mask)247 static void wx_release_sw_sync(struct wx *wx, u32 mask)
248 {
249 mutex_lock(&wx_sw_sync_lock);
250 wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0);
251 mutex_unlock(&wx_sw_sync_lock);
252 }
253
254 /**
255 * wx_acquire_sw_sync - Acquire SW semaphore
256 * @wx: pointer to hardware structure
257 * @mask: Mask to specify which semaphore to acquire
258 *
259 * Acquires the SW semaphore for the specified
260 * function (CSR, PHY0, PHY1, EEPROM, Flash)
261 **/
wx_acquire_sw_sync(struct wx * wx,u32 mask)262 static int wx_acquire_sw_sync(struct wx *wx, u32 mask)
263 {
264 u32 sem = 0;
265 int ret = 0;
266
267 mutex_lock(&wx_sw_sync_lock);
268 ret = read_poll_timeout(rd32, sem, !(sem & mask),
269 5000, 2000000, false, wx, WX_MNG_SWFW_SYNC);
270 if (!ret) {
271 sem |= mask;
272 wr32(wx, WX_MNG_SWFW_SYNC, sem);
273 } else {
274 wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem);
275 }
276 mutex_unlock(&wx_sw_sync_lock);
277
278 return ret;
279 }
280
281 /**
282 * wx_host_interface_command - Issue command to manageability block
283 * @wx: pointer to the HW structure
284 * @buffer: contains the command to write and where the return status will
285 * be placed
286 * @length: length of buffer, must be multiple of 4 bytes
287 * @timeout: time in ms to wait for command completion
288 * @return_data: read and return data from the buffer (true) or not (false)
289 * Needed because FW structures are big endian and decoding of
290 * these fields can be 8 bit or 16 bit based on command. Decoding
291 * is not easily understood without making a table of commands.
292 * So we will leave this up to the caller to read back the data
293 * in these cases.
294 **/
wx_host_interface_command(struct wx * wx,u32 * buffer,u32 length,u32 timeout,bool return_data)295 int wx_host_interface_command(struct wx *wx, u32 *buffer,
296 u32 length, u32 timeout, bool return_data)
297 {
298 u32 hdr_size = sizeof(struct wx_hic_hdr);
299 u32 hicr, i, bi, buf[64] = {};
300 int status = 0;
301 u32 dword_len;
302 u16 buf_len;
303
304 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) {
305 wx_err(wx, "Buffer length failure buffersize=%d.\n", length);
306 return -EINVAL;
307 }
308
309 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB);
310 if (status != 0)
311 return status;
312
313 /* Calculate length in DWORDs. We must be DWORD aligned */
314 if ((length % (sizeof(u32))) != 0) {
315 wx_err(wx, "Buffer length failure, not aligned to dword");
316 status = -EINVAL;
317 goto rel_out;
318 }
319
320 dword_len = length >> 2;
321
322 /* The device driver writes the relevant command block
323 * into the ram area.
324 */
325 for (i = 0; i < dword_len; i++) {
326 wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i]));
327 /* write flush */
328 buf[i] = rd32a(wx, WX_MNG_MBOX, i);
329 }
330 /* Setting this bit tells the ARC that a new command is pending. */
331 wr32m(wx, WX_MNG_MBOX_CTL,
332 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY);
333
334 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000,
335 timeout * 1000, false, wx, WX_MNG_MBOX_CTL);
336
337 buf[0] = rd32(wx, WX_MNG_MBOX);
338 if ((buf[0] & 0xff0000) >> 16 == 0x80) {
339 wx_err(wx, "Unknown FW command: 0x%x\n", buffer[0] & 0xff);
340 status = -EINVAL;
341 goto rel_out;
342 }
343
344 /* Check command completion */
345 if (status) {
346 wx_err(wx, "Command has failed with no status valid.\n");
347 wx_dbg(wx, "write value:\n");
348 for (i = 0; i < dword_len; i++)
349 wx_dbg(wx, "%x ", buffer[i]);
350 wx_dbg(wx, "read value:\n");
351 for (i = 0; i < dword_len; i++)
352 wx_dbg(wx, "%x ", buf[i]);
353 wx_dbg(wx, "\ncheck: %x %x\n", buffer[0] & 0xff, ~buf[0] >> 24);
354
355 goto rel_out;
356 }
357
358 if (!return_data)
359 goto rel_out;
360
361 /* Calculate length in DWORDs */
362 dword_len = hdr_size >> 2;
363
364 /* first pull in the header so we know the buffer length */
365 for (bi = 0; bi < dword_len; bi++) {
366 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi);
367 le32_to_cpus(&buffer[bi]);
368 }
369
370 /* If there is any thing in data position pull it in */
371 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len;
372 if (buf_len == 0)
373 goto rel_out;
374
375 if (length < buf_len + hdr_size) {
376 wx_err(wx, "Buffer not large enough for reply message.\n");
377 status = -EFAULT;
378 goto rel_out;
379 }
380
381 /* Calculate length in DWORDs, add 3 for odd lengths */
382 dword_len = (buf_len + 3) >> 2;
383
384 /* Pull in the rest of the buffer (bi is where we left off) */
385 for (; bi <= dword_len; bi++) {
386 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi);
387 le32_to_cpus(&buffer[bi]);
388 }
389
390 rel_out:
391 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB);
392 return status;
393 }
394 EXPORT_SYMBOL(wx_host_interface_command);
395
396 /**
397 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd
398 * assuming that the semaphore is already obtained.
399 * @wx: pointer to hardware structure
400 * @offset: offset of word in the EEPROM to read
401 * @data: word read from the EEPROM
402 *
403 * Reads a 16 bit word from the EEPROM using the hostif.
404 **/
wx_read_ee_hostif_data(struct wx * wx,u16 offset,u16 * data)405 static int wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data)
406 {
407 struct wx_hic_read_shadow_ram buffer;
408 int status;
409
410 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
411 buffer.hdr.req.buf_lenh = 0;
412 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
413 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
414
415 /* convert offset from words to bytes */
416 buffer.address = (__force u32)cpu_to_be32(offset * 2);
417 /* one word */
418 buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
419
420 status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer),
421 WX_HI_COMMAND_TIMEOUT, false);
422
423 if (status != 0)
424 return status;
425
426 *data = (u16)rd32a(wx, WX_MNG_MBOX, FW_NVM_DATA_OFFSET);
427
428 return status;
429 }
430
431 /**
432 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd
433 * @wx: pointer to hardware structure
434 * @offset: offset of word in the EEPROM to read
435 * @data: word read from the EEPROM
436 *
437 * Reads a 16 bit word from the EEPROM using the hostif.
438 **/
wx_read_ee_hostif(struct wx * wx,u16 offset,u16 * data)439 int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data)
440 {
441 int status = 0;
442
443 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
444 if (status == 0) {
445 status = wx_read_ee_hostif_data(wx, offset, data);
446 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
447 }
448
449 return status;
450 }
451 EXPORT_SYMBOL(wx_read_ee_hostif);
452
453 /**
454 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif
455 * @wx: pointer to hardware structure
456 * @offset: offset of word in the EEPROM to read
457 * @words: number of words
458 * @data: word(s) read from the EEPROM
459 *
460 * Reads a 16 bit word(s) from the EEPROM using the hostif.
461 **/
wx_read_ee_hostif_buffer(struct wx * wx,u16 offset,u16 words,u16 * data)462 int wx_read_ee_hostif_buffer(struct wx *wx,
463 u16 offset, u16 words, u16 *data)
464 {
465 struct wx_hic_read_shadow_ram buffer;
466 u32 current_word = 0;
467 u16 words_to_read;
468 u32 value = 0;
469 int status;
470 u32 i;
471
472 /* Take semaphore for the entire operation. */
473 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
474 if (status != 0)
475 return status;
476
477 while (words) {
478 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
479 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
480 else
481 words_to_read = words;
482
483 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
484 buffer.hdr.req.buf_lenh = 0;
485 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
486 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
487
488 /* convert offset from words to bytes */
489 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2);
490 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
491
492 status = wx_host_interface_command(wx, (u32 *)&buffer,
493 sizeof(buffer),
494 WX_HI_COMMAND_TIMEOUT,
495 false);
496
497 if (status != 0) {
498 wx_err(wx, "Host interface command failed\n");
499 goto out;
500 }
501
502 for (i = 0; i < words_to_read; i++) {
503 u32 reg = WX_MNG_MBOX + (FW_NVM_DATA_OFFSET << 2) + 2 * i;
504
505 value = rd32(wx, reg);
506 data[current_word] = (u16)(value & 0xffff);
507 current_word++;
508 i++;
509 if (i < words_to_read) {
510 value >>= 16;
511 data[current_word] = (u16)(value & 0xffff);
512 current_word++;
513 }
514 }
515 words -= words_to_read;
516 }
517
518 out:
519 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
520 return status;
521 }
522 EXPORT_SYMBOL(wx_read_ee_hostif_buffer);
523
524 /**
525 * wx_init_eeprom_params - Initialize EEPROM params
526 * @wx: pointer to hardware structure
527 *
528 * Initializes the EEPROM parameters wx_eeprom_info within the
529 * wx_hw struct in order to set up EEPROM access.
530 **/
wx_init_eeprom_params(struct wx * wx)531 void wx_init_eeprom_params(struct wx *wx)
532 {
533 struct wx_eeprom_info *eeprom = &wx->eeprom;
534 u16 eeprom_size;
535 u16 data = 0x80;
536
537 if (eeprom->type == wx_eeprom_uninitialized) {
538 eeprom->semaphore_delay = 10;
539 eeprom->type = wx_eeprom_none;
540
541 if (!(rd32(wx, WX_SPI_STATUS) &
542 WX_SPI_STATUS_FLASH_BYPASS)) {
543 eeprom->type = wx_flash;
544
545 eeprom_size = 4096;
546 eeprom->word_size = eeprom_size >> 1;
547
548 wx_dbg(wx, "Eeprom params: type = %d, size = %d\n",
549 eeprom->type, eeprom->word_size);
550 }
551 }
552
553 if (wx->mac.type == wx_mac_sp) {
554 if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) {
555 wx_err(wx, "NVM Read Error\n");
556 return;
557 }
558 data = data >> 1;
559 }
560
561 eeprom->sw_region_offset = data;
562 }
563 EXPORT_SYMBOL(wx_init_eeprom_params);
564
565 /**
566 * wx_get_mac_addr - Generic get MAC address
567 * @wx: pointer to hardware structure
568 * @mac_addr: Adapter MAC address
569 *
570 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
571 * A reset of the adapter must be performed prior to calling this function
572 * in order for the MAC address to have been loaded from the EEPROM into RAR0
573 **/
wx_get_mac_addr(struct wx * wx,u8 * mac_addr)574 void wx_get_mac_addr(struct wx *wx, u8 *mac_addr)
575 {
576 u32 rar_high;
577 u32 rar_low;
578 u16 i;
579
580 wr32(wx, WX_PSR_MAC_SWC_IDX, 0);
581 rar_high = rd32(wx, WX_PSR_MAC_SWC_AD_H);
582 rar_low = rd32(wx, WX_PSR_MAC_SWC_AD_L);
583
584 for (i = 0; i < 2; i++)
585 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
586
587 for (i = 0; i < 4; i++)
588 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
589 }
590 EXPORT_SYMBOL(wx_get_mac_addr);
591
592 /**
593 * wx_set_rar - Set Rx address register
594 * @wx: pointer to hardware structure
595 * @index: Receive address register to write
596 * @addr: Address to put into receive address register
597 * @pools: VMDq "set" or "pool" index
598 * @enable_addr: set flag that address is active
599 *
600 * Puts an ethernet address into a receive address register.
601 **/
wx_set_rar(struct wx * wx,u32 index,u8 * addr,u64 pools,u32 enable_addr)602 static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools,
603 u32 enable_addr)
604 {
605 u32 rar_entries = wx->mac.num_rar_entries;
606 u32 rar_low, rar_high;
607
608 /* Make sure we are using a valid rar index range */
609 if (index >= rar_entries) {
610 wx_err(wx, "RAR index %d is out of range.\n", index);
611 return -EINVAL;
612 }
613
614 /* select the MAC address */
615 wr32(wx, WX_PSR_MAC_SWC_IDX, index);
616
617 /* setup VMDq pool mapping */
618 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF);
619 if (wx->mac.type == wx_mac_sp)
620 wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32);
621
622 /* HW expects these in little endian so we reverse the byte
623 * order from network order (big endian) to little endian
624 *
625 * Some parts put the VMDq setting in the extra RAH bits,
626 * so save everything except the lower 16 bits that hold part
627 * of the address and the address valid bit.
628 */
629 rar_low = ((u32)addr[5] |
630 ((u32)addr[4] << 8) |
631 ((u32)addr[3] << 16) |
632 ((u32)addr[2] << 24));
633 rar_high = ((u32)addr[1] |
634 ((u32)addr[0] << 8));
635 if (enable_addr != 0)
636 rar_high |= WX_PSR_MAC_SWC_AD_H_AV;
637
638 wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low);
639 wr32m(wx, WX_PSR_MAC_SWC_AD_H,
640 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) |
641 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) |
642 WX_PSR_MAC_SWC_AD_H_AV),
643 rar_high);
644
645 return 0;
646 }
647
648 /**
649 * wx_clear_rar - Remove Rx address register
650 * @wx: pointer to hardware structure
651 * @index: Receive address register to write
652 *
653 * Clears an ethernet address from a receive address register.
654 **/
wx_clear_rar(struct wx * wx,u32 index)655 static int wx_clear_rar(struct wx *wx, u32 index)
656 {
657 u32 rar_entries = wx->mac.num_rar_entries;
658
659 /* Make sure we are using a valid rar index range */
660 if (index >= rar_entries) {
661 wx_err(wx, "RAR index %d is out of range.\n", index);
662 return -EINVAL;
663 }
664
665 /* Some parts put the VMDq setting in the extra RAH bits,
666 * so save everything except the lower 16 bits that hold part
667 * of the address and the address valid bit.
668 */
669 wr32(wx, WX_PSR_MAC_SWC_IDX, index);
670
671 wr32(wx, WX_PSR_MAC_SWC_VM_L, 0);
672 wr32(wx, WX_PSR_MAC_SWC_VM_H, 0);
673
674 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0);
675 wr32m(wx, WX_PSR_MAC_SWC_AD_H,
676 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) |
677 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) |
678 WX_PSR_MAC_SWC_AD_H_AV),
679 0);
680
681 return 0;
682 }
683
684 /**
685 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address
686 * @wx: pointer to hardware struct
687 * @rar: receive address register index to disassociate
688 * @vmdq: VMDq pool index to remove from the rar
689 **/
wx_clear_vmdq(struct wx * wx,u32 rar,u32 __maybe_unused vmdq)690 static int wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq)
691 {
692 u32 rar_entries = wx->mac.num_rar_entries;
693 u32 mpsar_lo, mpsar_hi;
694
695 /* Make sure we are using a valid rar index range */
696 if (rar >= rar_entries) {
697 wx_err(wx, "RAR index %d is out of range.\n", rar);
698 return -EINVAL;
699 }
700
701 wr32(wx, WX_PSR_MAC_SWC_IDX, rar);
702 mpsar_lo = rd32(wx, WX_PSR_MAC_SWC_VM_L);
703 mpsar_hi = rd32(wx, WX_PSR_MAC_SWC_VM_H);
704
705 if (!mpsar_lo && !mpsar_hi)
706 return 0;
707
708 /* was that the last pool using this rar? */
709 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
710 wx_clear_rar(wx, rar);
711
712 return 0;
713 }
714
715 /**
716 * wx_init_uta_tables - Initialize the Unicast Table Array
717 * @wx: pointer to hardware structure
718 **/
wx_init_uta_tables(struct wx * wx)719 static void wx_init_uta_tables(struct wx *wx)
720 {
721 int i;
722
723 wx_dbg(wx, " Clearing UTA\n");
724
725 for (i = 0; i < 128; i++)
726 wr32(wx, WX_PSR_UC_TBL(i), 0);
727 }
728
729 /**
730 * wx_init_rx_addrs - Initializes receive address filters.
731 * @wx: pointer to hardware structure
732 *
733 * Places the MAC address in receive address register 0 and clears the rest
734 * of the receive address registers. Clears the multicast table. Assumes
735 * the receiver is in reset when the routine is called.
736 **/
wx_init_rx_addrs(struct wx * wx)737 void wx_init_rx_addrs(struct wx *wx)
738 {
739 u32 rar_entries = wx->mac.num_rar_entries;
740 u32 psrctl;
741 int i;
742
743 /* If the current mac address is valid, assume it is a software override
744 * to the permanent address.
745 * Otherwise, use the permanent address from the eeprom.
746 */
747 if (!is_valid_ether_addr(wx->mac.addr)) {
748 /* Get the MAC address from the RAR0 for later reference */
749 wx_get_mac_addr(wx, wx->mac.addr);
750 wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr);
751 } else {
752 /* Setup the receive address. */
753 wx_dbg(wx, "Overriding MAC Address in RAR[0]\n");
754 wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr);
755
756 wx_set_rar(wx, 0, wx->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV);
757
758 if (wx->mac.type == wx_mac_sp) {
759 /* clear VMDq pool/queue selection for RAR 0 */
760 wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL);
761 }
762 }
763
764 /* Zero out the other receive addresses. */
765 wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1);
766 for (i = 1; i < rar_entries; i++) {
767 wr32(wx, WX_PSR_MAC_SWC_IDX, i);
768 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0);
769 wr32(wx, WX_PSR_MAC_SWC_AD_H, 0);
770 }
771
772 /* Clear the MTA */
773 wx->addr_ctrl.mta_in_use = 0;
774 psrctl = rd32(wx, WX_PSR_CTL);
775 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE);
776 psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT;
777 wr32(wx, WX_PSR_CTL, psrctl);
778 wx_dbg(wx, " Clearing MTA\n");
779 for (i = 0; i < wx->mac.mcft_size; i++)
780 wr32(wx, WX_PSR_MC_TBL(i), 0);
781
782 wx_init_uta_tables(wx);
783 }
784 EXPORT_SYMBOL(wx_init_rx_addrs);
785
wx_sync_mac_table(struct wx * wx)786 static void wx_sync_mac_table(struct wx *wx)
787 {
788 int i;
789
790 for (i = 0; i < wx->mac.num_rar_entries; i++) {
791 if (wx->mac_table[i].state & WX_MAC_STATE_MODIFIED) {
792 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) {
793 wx_set_rar(wx, i,
794 wx->mac_table[i].addr,
795 wx->mac_table[i].pools,
796 WX_PSR_MAC_SWC_AD_H_AV);
797 } else {
798 wx_clear_rar(wx, i);
799 }
800 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED);
801 }
802 }
803 }
804
805 /* this function destroys the first RAR entry */
wx_mac_set_default_filter(struct wx * wx,u8 * addr)806 void wx_mac_set_default_filter(struct wx *wx, u8 *addr)
807 {
808 memcpy(&wx->mac_table[0].addr, addr, ETH_ALEN);
809 wx->mac_table[0].pools = 1ULL;
810 wx->mac_table[0].state = (WX_MAC_STATE_DEFAULT | WX_MAC_STATE_IN_USE);
811 wx_set_rar(wx, 0, wx->mac_table[0].addr,
812 wx->mac_table[0].pools,
813 WX_PSR_MAC_SWC_AD_H_AV);
814 }
815 EXPORT_SYMBOL(wx_mac_set_default_filter);
816
wx_flush_sw_mac_table(struct wx * wx)817 void wx_flush_sw_mac_table(struct wx *wx)
818 {
819 u32 i;
820
821 for (i = 0; i < wx->mac.num_rar_entries; i++) {
822 if (!(wx->mac_table[i].state & WX_MAC_STATE_IN_USE))
823 continue;
824
825 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED;
826 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE;
827 memset(wx->mac_table[i].addr, 0, ETH_ALEN);
828 wx->mac_table[i].pools = 0;
829 }
830 wx_sync_mac_table(wx);
831 }
832 EXPORT_SYMBOL(wx_flush_sw_mac_table);
833
wx_add_mac_filter(struct wx * wx,u8 * addr,u16 pool)834 static int wx_add_mac_filter(struct wx *wx, u8 *addr, u16 pool)
835 {
836 u32 i;
837
838 if (is_zero_ether_addr(addr))
839 return -EINVAL;
840
841 for (i = 0; i < wx->mac.num_rar_entries; i++) {
842 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) {
843 if (ether_addr_equal(addr, wx->mac_table[i].addr)) {
844 if (wx->mac_table[i].pools != (1ULL << pool)) {
845 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN);
846 wx->mac_table[i].pools |= (1ULL << pool);
847 wx_sync_mac_table(wx);
848 return i;
849 }
850 }
851 }
852
853 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE)
854 continue;
855 wx->mac_table[i].state |= (WX_MAC_STATE_MODIFIED |
856 WX_MAC_STATE_IN_USE);
857 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN);
858 wx->mac_table[i].pools |= (1ULL << pool);
859 wx_sync_mac_table(wx);
860 return i;
861 }
862 return -ENOMEM;
863 }
864
wx_del_mac_filter(struct wx * wx,u8 * addr,u16 pool)865 static int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool)
866 {
867 u32 i;
868
869 if (is_zero_ether_addr(addr))
870 return -EINVAL;
871
872 /* search table for addr, if found, set to 0 and sync */
873 for (i = 0; i < wx->mac.num_rar_entries; i++) {
874 if (!ether_addr_equal(addr, wx->mac_table[i].addr))
875 continue;
876
877 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED;
878 wx->mac_table[i].pools &= ~(1ULL << pool);
879 if (!wx->mac_table[i].pools) {
880 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE;
881 memset(wx->mac_table[i].addr, 0, ETH_ALEN);
882 }
883 wx_sync_mac_table(wx);
884 return 0;
885 }
886 return -ENOMEM;
887 }
888
wx_available_rars(struct wx * wx)889 static int wx_available_rars(struct wx *wx)
890 {
891 u32 i, count = 0;
892
893 for (i = 0; i < wx->mac.num_rar_entries; i++) {
894 if (wx->mac_table[i].state == 0)
895 count++;
896 }
897
898 return count;
899 }
900
901 /**
902 * wx_write_uc_addr_list - write unicast addresses to RAR table
903 * @netdev: network interface device structure
904 * @pool: index for mac table
905 *
906 * Writes unicast address list to the RAR table.
907 * Returns: -ENOMEM on failure/insufficient address space
908 * 0 on no addresses written
909 * X on writing X addresses to the RAR table
910 **/
wx_write_uc_addr_list(struct net_device * netdev,int pool)911 static int wx_write_uc_addr_list(struct net_device *netdev, int pool)
912 {
913 struct wx *wx = netdev_priv(netdev);
914 int count = 0;
915
916 /* return ENOMEM indicating insufficient memory for addresses */
917 if (netdev_uc_count(netdev) > wx_available_rars(wx))
918 return -ENOMEM;
919
920 if (!netdev_uc_empty(netdev)) {
921 struct netdev_hw_addr *ha;
922
923 netdev_for_each_uc_addr(ha, netdev) {
924 wx_del_mac_filter(wx, ha->addr, pool);
925 wx_add_mac_filter(wx, ha->addr, pool);
926 count++;
927 }
928 }
929 return count;
930 }
931
932 /**
933 * wx_mta_vector - Determines bit-vector in multicast table to set
934 * @wx: pointer to private structure
935 * @mc_addr: the multicast address
936 *
937 * Extracts the 12 bits, from a multicast address, to determine which
938 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
939 * incoming rx multicast addresses, to determine the bit-vector to check in
940 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
941 * by the MO field of the MCSTCTRL. The MO field is set during initialization
942 * to mc_filter_type.
943 **/
wx_mta_vector(struct wx * wx,u8 * mc_addr)944 static u32 wx_mta_vector(struct wx *wx, u8 *mc_addr)
945 {
946 u32 vector = 0;
947
948 switch (wx->mac.mc_filter_type) {
949 case 0: /* use bits [47:36] of the address */
950 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
951 break;
952 case 1: /* use bits [46:35] of the address */
953 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
954 break;
955 case 2: /* use bits [45:34] of the address */
956 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
957 break;
958 case 3: /* use bits [43:32] of the address */
959 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
960 break;
961 default: /* Invalid mc_filter_type */
962 wx_err(wx, "MC filter type param set incorrectly\n");
963 break;
964 }
965
966 /* vector can only be 12-bits or boundary will be exceeded */
967 vector &= 0xFFF;
968 return vector;
969 }
970
971 /**
972 * wx_set_mta - Set bit-vector in multicast table
973 * @wx: pointer to private structure
974 * @mc_addr: Multicast address
975 *
976 * Sets the bit-vector in the multicast table.
977 **/
wx_set_mta(struct wx * wx,u8 * mc_addr)978 static void wx_set_mta(struct wx *wx, u8 *mc_addr)
979 {
980 u32 vector, vector_bit, vector_reg;
981
982 wx->addr_ctrl.mta_in_use++;
983
984 vector = wx_mta_vector(wx, mc_addr);
985 wx_dbg(wx, " bit-vector = 0x%03X\n", vector);
986
987 /* The MTA is a register array of 128 32-bit registers. It is treated
988 * like an array of 4096 bits. We want to set bit
989 * BitArray[vector_value]. So we figure out what register the bit is
990 * in, read it, OR in the new bit, then write back the new value. The
991 * register is determined by the upper 7 bits of the vector value and
992 * the bit within that register are determined by the lower 5 bits of
993 * the value.
994 */
995 vector_reg = (vector >> 5) & 0x7F;
996 vector_bit = vector & 0x1F;
997 wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
998 }
999
1000 /**
1001 * wx_update_mc_addr_list - Updates MAC list of multicast addresses
1002 * @wx: pointer to private structure
1003 * @netdev: pointer to net device structure
1004 *
1005 * The given list replaces any existing list. Clears the MC addrs from receive
1006 * address registers and the multicast table. Uses unused receive address
1007 * registers for the first multicast addresses, and hashes the rest into the
1008 * multicast table.
1009 **/
wx_update_mc_addr_list(struct wx * wx,struct net_device * netdev)1010 static void wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev)
1011 {
1012 struct netdev_hw_addr *ha;
1013 u32 i, psrctl;
1014
1015 /* Set the new number of MC addresses that we are being requested to
1016 * use.
1017 */
1018 wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
1019 wx->addr_ctrl.mta_in_use = 0;
1020
1021 /* Clear mta_shadow */
1022 wx_dbg(wx, " Clearing MTA\n");
1023 memset(&wx->mac.mta_shadow, 0, sizeof(wx->mac.mta_shadow));
1024
1025 /* Update mta_shadow */
1026 netdev_for_each_mc_addr(ha, netdev) {
1027 wx_dbg(wx, " Adding the multicast addresses:\n");
1028 wx_set_mta(wx, ha->addr);
1029 }
1030
1031 /* Enable mta */
1032 for (i = 0; i < wx->mac.mcft_size; i++)
1033 wr32a(wx, WX_PSR_MC_TBL(0), i,
1034 wx->mac.mta_shadow[i]);
1035
1036 if (wx->addr_ctrl.mta_in_use > 0) {
1037 psrctl = rd32(wx, WX_PSR_CTL);
1038 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE);
1039 psrctl |= WX_PSR_CTL_MFE |
1040 (wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT);
1041 wr32(wx, WX_PSR_CTL, psrctl);
1042 }
1043
1044 wx_dbg(wx, "Update mc addr list Complete\n");
1045 }
1046
1047 /**
1048 * wx_write_mc_addr_list - write multicast addresses to MTA
1049 * @netdev: network interface device structure
1050 *
1051 * Writes multicast address list to the MTA hash table.
1052 * Returns: 0 on no addresses written
1053 * X on writing X addresses to MTA
1054 **/
wx_write_mc_addr_list(struct net_device * netdev)1055 static int wx_write_mc_addr_list(struct net_device *netdev)
1056 {
1057 struct wx *wx = netdev_priv(netdev);
1058
1059 if (!netif_running(netdev))
1060 return 0;
1061
1062 wx_update_mc_addr_list(wx, netdev);
1063
1064 return netdev_mc_count(netdev);
1065 }
1066
1067 /**
1068 * wx_set_mac - Change the Ethernet Address of the NIC
1069 * @netdev: network interface device structure
1070 * @p: pointer to an address structure
1071 *
1072 * Returns 0 on success, negative on failure
1073 **/
wx_set_mac(struct net_device * netdev,void * p)1074 int wx_set_mac(struct net_device *netdev, void *p)
1075 {
1076 struct wx *wx = netdev_priv(netdev);
1077 struct sockaddr *addr = p;
1078 int retval;
1079
1080 retval = eth_prepare_mac_addr_change(netdev, addr);
1081 if (retval)
1082 return retval;
1083
1084 wx_del_mac_filter(wx, wx->mac.addr, 0);
1085 eth_hw_addr_set(netdev, addr->sa_data);
1086 memcpy(wx->mac.addr, addr->sa_data, netdev->addr_len);
1087
1088 wx_mac_set_default_filter(wx, wx->mac.addr);
1089
1090 return 0;
1091 }
1092 EXPORT_SYMBOL(wx_set_mac);
1093
wx_disable_rx(struct wx * wx)1094 void wx_disable_rx(struct wx *wx)
1095 {
1096 u32 pfdtxgswc;
1097 u32 rxctrl;
1098
1099 rxctrl = rd32(wx, WX_RDB_PB_CTL);
1100 if (rxctrl & WX_RDB_PB_CTL_RXEN) {
1101 pfdtxgswc = rd32(wx, WX_PSR_CTL);
1102 if (pfdtxgswc & WX_PSR_CTL_SW_EN) {
1103 pfdtxgswc &= ~WX_PSR_CTL_SW_EN;
1104 wr32(wx, WX_PSR_CTL, pfdtxgswc);
1105 wx->mac.set_lben = true;
1106 } else {
1107 wx->mac.set_lben = false;
1108 }
1109 rxctrl &= ~WX_RDB_PB_CTL_RXEN;
1110 wr32(wx, WX_RDB_PB_CTL, rxctrl);
1111
1112 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) ||
1113 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) {
1114 /* disable mac receiver */
1115 wr32m(wx, WX_MAC_RX_CFG,
1116 WX_MAC_RX_CFG_RE, 0);
1117 }
1118 }
1119 }
1120 EXPORT_SYMBOL(wx_disable_rx);
1121
wx_enable_rx(struct wx * wx)1122 static void wx_enable_rx(struct wx *wx)
1123 {
1124 u32 psrctl;
1125
1126 /* enable mac receiver */
1127 wr32m(wx, WX_MAC_RX_CFG,
1128 WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
1129
1130 wr32m(wx, WX_RDB_PB_CTL,
1131 WX_RDB_PB_CTL_RXEN, WX_RDB_PB_CTL_RXEN);
1132
1133 if (wx->mac.set_lben) {
1134 psrctl = rd32(wx, WX_PSR_CTL);
1135 psrctl |= WX_PSR_CTL_SW_EN;
1136 wr32(wx, WX_PSR_CTL, psrctl);
1137 wx->mac.set_lben = false;
1138 }
1139 }
1140
1141 /**
1142 * wx_set_rxpba - Initialize Rx packet buffer
1143 * @wx: pointer to private structure
1144 **/
wx_set_rxpba(struct wx * wx)1145 static void wx_set_rxpba(struct wx *wx)
1146 {
1147 u32 rxpktsize, txpktsize, txpbthresh;
1148 u32 pbsize = wx->mac.rx_pb_size;
1149
1150 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) {
1151 if (test_bit(WX_FLAG_FDIR_HASH, wx->flags) ||
1152 test_bit(WX_FLAG_FDIR_PERFECT, wx->flags))
1153 pbsize -= 64; /* Default 64KB */
1154 }
1155
1156 rxpktsize = pbsize << WX_RDB_PB_SZ_SHIFT;
1157 wr32(wx, WX_RDB_PB_SZ(0), rxpktsize);
1158
1159 /* Only support an equally distributed Tx packet buffer strategy. */
1160 txpktsize = wx->mac.tx_pb_size;
1161 txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX;
1162 wr32(wx, WX_TDB_PB_SZ(0), txpktsize);
1163 wr32(wx, WX_TDM_PB_THRE(0), txpbthresh);
1164 }
1165
1166 #define WX_ETH_FRAMING 20
1167
1168 /**
1169 * wx_hpbthresh - calculate high water mark for flow control
1170 *
1171 * @wx: board private structure to calculate for
1172 **/
wx_hpbthresh(struct wx * wx)1173 static int wx_hpbthresh(struct wx *wx)
1174 {
1175 struct net_device *dev = wx->netdev;
1176 int link, tc, kb, marker;
1177 u32 dv_id, rx_pba;
1178
1179 /* Calculate max LAN frame size */
1180 link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + WX_ETH_FRAMING;
1181 tc = link;
1182
1183 /* Calculate delay value for device */
1184 dv_id = WX_DV(link, tc);
1185
1186 /* Delay value is calculated in bit times convert to KB */
1187 kb = WX_BT2KB(dv_id);
1188 rx_pba = rd32(wx, WX_RDB_PB_SZ(0)) >> WX_RDB_PB_SZ_SHIFT;
1189
1190 marker = rx_pba - kb;
1191
1192 /* It is possible that the packet buffer is not large enough
1193 * to provide required headroom. In this case throw an error
1194 * to user and a do the best we can.
1195 */
1196 if (marker < 0) {
1197 dev_warn(&wx->pdev->dev,
1198 "Packet Buffer can not provide enough headroom to support flow control. Decrease MTU or number of traffic classes\n");
1199 marker = tc + 1;
1200 }
1201
1202 return marker;
1203 }
1204
1205 /**
1206 * wx_lpbthresh - calculate low water mark for flow control
1207 *
1208 * @wx: board private structure to calculate for
1209 **/
wx_lpbthresh(struct wx * wx)1210 static int wx_lpbthresh(struct wx *wx)
1211 {
1212 struct net_device *dev = wx->netdev;
1213 u32 dv_id;
1214 int tc;
1215
1216 /* Calculate max LAN frame size */
1217 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
1218
1219 /* Calculate delay value for device */
1220 dv_id = WX_LOW_DV(tc);
1221
1222 /* Delay value is calculated in bit times convert to KB */
1223 return WX_BT2KB(dv_id);
1224 }
1225
1226 /**
1227 * wx_pbthresh_setup - calculate and setup high low water marks
1228 *
1229 * @wx: board private structure to calculate for
1230 **/
wx_pbthresh_setup(struct wx * wx)1231 static void wx_pbthresh_setup(struct wx *wx)
1232 {
1233 wx->fc.high_water = wx_hpbthresh(wx);
1234 wx->fc.low_water = wx_lpbthresh(wx);
1235
1236 /* Low water marks must not be larger than high water marks */
1237 if (wx->fc.low_water > wx->fc.high_water)
1238 wx->fc.low_water = 0;
1239 }
1240
wx_configure_port(struct wx * wx)1241 static void wx_configure_port(struct wx *wx)
1242 {
1243 u32 value, i;
1244
1245 value = WX_CFG_PORT_CTL_D_VLAN | WX_CFG_PORT_CTL_QINQ;
1246 wr32m(wx, WX_CFG_PORT_CTL,
1247 WX_CFG_PORT_CTL_D_VLAN |
1248 WX_CFG_PORT_CTL_QINQ,
1249 value);
1250
1251 wr32(wx, WX_CFG_TAG_TPID(0),
1252 ETH_P_8021Q | ETH_P_8021AD << 16);
1253 wx->tpid[0] = ETH_P_8021Q;
1254 wx->tpid[1] = ETH_P_8021AD;
1255 for (i = 1; i < 4; i++)
1256 wr32(wx, WX_CFG_TAG_TPID(i),
1257 ETH_P_8021Q | ETH_P_8021Q << 16);
1258 for (i = 2; i < 8; i++)
1259 wx->tpid[i] = ETH_P_8021Q;
1260 }
1261
1262 /**
1263 * wx_disable_sec_rx_path - Stops the receive data path
1264 * @wx: pointer to private structure
1265 *
1266 * Stops the receive data path and waits for the HW to internally empty
1267 * the Rx security block
1268 **/
wx_disable_sec_rx_path(struct wx * wx)1269 int wx_disable_sec_rx_path(struct wx *wx)
1270 {
1271 u32 secrx;
1272
1273 wr32m(wx, WX_RSC_CTL,
1274 WX_RSC_CTL_RX_DIS, WX_RSC_CTL_RX_DIS);
1275
1276 return read_poll_timeout(rd32, secrx, secrx & WX_RSC_ST_RSEC_RDY,
1277 1000, 40000, false, wx, WX_RSC_ST);
1278 }
1279 EXPORT_SYMBOL(wx_disable_sec_rx_path);
1280
1281 /**
1282 * wx_enable_sec_rx_path - Enables the receive data path
1283 * @wx: pointer to private structure
1284 *
1285 * Enables the receive data path.
1286 **/
wx_enable_sec_rx_path(struct wx * wx)1287 void wx_enable_sec_rx_path(struct wx *wx)
1288 {
1289 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_RX_DIS, 0);
1290 WX_WRITE_FLUSH(wx);
1291 }
1292 EXPORT_SYMBOL(wx_enable_sec_rx_path);
1293
wx_vlan_strip_control(struct wx * wx,bool enable)1294 static void wx_vlan_strip_control(struct wx *wx, bool enable)
1295 {
1296 int i, j;
1297
1298 for (i = 0; i < wx->num_rx_queues; i++) {
1299 struct wx_ring *ring = wx->rx_ring[i];
1300
1301 j = ring->reg_idx;
1302 wr32m(wx, WX_PX_RR_CFG(j), WX_PX_RR_CFG_VLAN,
1303 enable ? WX_PX_RR_CFG_VLAN : 0);
1304 }
1305 }
1306
wx_set_rx_mode(struct net_device * netdev)1307 void wx_set_rx_mode(struct net_device *netdev)
1308 {
1309 struct wx *wx = netdev_priv(netdev);
1310 netdev_features_t features;
1311 u32 fctrl, vmolr, vlnctrl;
1312 int count;
1313
1314 features = netdev->features;
1315
1316 /* Check for Promiscuous and All Multicast modes */
1317 fctrl = rd32(wx, WX_PSR_CTL);
1318 fctrl &= ~(WX_PSR_CTL_UPE | WX_PSR_CTL_MPE);
1319 vmolr = rd32(wx, WX_PSR_VM_L2CTL(0));
1320 vmolr &= ~(WX_PSR_VM_L2CTL_UPE |
1321 WX_PSR_VM_L2CTL_MPE |
1322 WX_PSR_VM_L2CTL_ROPE |
1323 WX_PSR_VM_L2CTL_ROMPE);
1324 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL);
1325 vlnctrl &= ~(WX_PSR_VLAN_CTL_VFE | WX_PSR_VLAN_CTL_CFIEN);
1326
1327 /* set all bits that we expect to always be set */
1328 fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE;
1329 vmolr |= WX_PSR_VM_L2CTL_BAM |
1330 WX_PSR_VM_L2CTL_AUPE |
1331 WX_PSR_VM_L2CTL_VACC;
1332 vlnctrl |= WX_PSR_VLAN_CTL_VFE;
1333
1334 wx->addr_ctrl.user_set_promisc = false;
1335 if (netdev->flags & IFF_PROMISC) {
1336 wx->addr_ctrl.user_set_promisc = true;
1337 fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE;
1338 /* pf don't want packets routing to vf, so clear UPE */
1339 vmolr |= WX_PSR_VM_L2CTL_MPE;
1340 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE;
1341 }
1342
1343 if (netdev->flags & IFF_ALLMULTI) {
1344 fctrl |= WX_PSR_CTL_MPE;
1345 vmolr |= WX_PSR_VM_L2CTL_MPE;
1346 }
1347
1348 if (netdev->features & NETIF_F_RXALL) {
1349 vmolr |= (WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_MPE);
1350 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE;
1351 /* receive bad packets */
1352 wr32m(wx, WX_RSC_CTL,
1353 WX_RSC_CTL_SAVE_MAC_ERR,
1354 WX_RSC_CTL_SAVE_MAC_ERR);
1355 } else {
1356 vmolr |= WX_PSR_VM_L2CTL_ROPE | WX_PSR_VM_L2CTL_ROMPE;
1357 }
1358
1359 /* Write addresses to available RAR registers, if there is not
1360 * sufficient space to store all the addresses then enable
1361 * unicast promiscuous mode
1362 */
1363 count = wx_write_uc_addr_list(netdev, 0);
1364 if (count < 0) {
1365 vmolr &= ~WX_PSR_VM_L2CTL_ROPE;
1366 vmolr |= WX_PSR_VM_L2CTL_UPE;
1367 }
1368
1369 /* Write addresses to the MTA, if the attempt fails
1370 * then we should just turn on promiscuous mode so
1371 * that we can at least receive multicast traffic
1372 */
1373 count = wx_write_mc_addr_list(netdev);
1374 if (count < 0) {
1375 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE;
1376 vmolr |= WX_PSR_VM_L2CTL_MPE;
1377 }
1378
1379 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl);
1380 wr32(wx, WX_PSR_CTL, fctrl);
1381 wr32(wx, WX_PSR_VM_L2CTL(0), vmolr);
1382
1383 if ((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1384 (features & NETIF_F_HW_VLAN_STAG_RX))
1385 wx_vlan_strip_control(wx, true);
1386 else
1387 wx_vlan_strip_control(wx, false);
1388
1389 }
1390 EXPORT_SYMBOL(wx_set_rx_mode);
1391
wx_set_rx_buffer_len(struct wx * wx)1392 static void wx_set_rx_buffer_len(struct wx *wx)
1393 {
1394 struct net_device *netdev = wx->netdev;
1395 u32 mhadd, max_frame;
1396
1397 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
1398 /* adjust max frame to be at least the size of a standard frame */
1399 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
1400 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
1401
1402 mhadd = rd32(wx, WX_PSR_MAX_SZ);
1403 if (max_frame != mhadd)
1404 wr32(wx, WX_PSR_MAX_SZ, max_frame);
1405 }
1406
1407 /**
1408 * wx_change_mtu - Change the Maximum Transfer Unit
1409 * @netdev: network interface device structure
1410 * @new_mtu: new value for maximum frame size
1411 *
1412 * Returns 0 on success, negative on failure
1413 **/
wx_change_mtu(struct net_device * netdev,int new_mtu)1414 int wx_change_mtu(struct net_device *netdev, int new_mtu)
1415 {
1416 struct wx *wx = netdev_priv(netdev);
1417
1418 WRITE_ONCE(netdev->mtu, new_mtu);
1419 wx_set_rx_buffer_len(wx);
1420
1421 return 0;
1422 }
1423 EXPORT_SYMBOL(wx_change_mtu);
1424
1425 /* Disable the specified rx queue */
wx_disable_rx_queue(struct wx * wx,struct wx_ring * ring)1426 void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring)
1427 {
1428 u8 reg_idx = ring->reg_idx;
1429 u32 rxdctl;
1430 int ret;
1431
1432 /* write value back with RRCFG.EN bit cleared */
1433 wr32m(wx, WX_PX_RR_CFG(reg_idx),
1434 WX_PX_RR_CFG_RR_EN, 0);
1435
1436 /* the hardware may take up to 100us to really disable the rx queue */
1437 ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN),
1438 10, 100, true, wx, WX_PX_RR_CFG(reg_idx));
1439
1440 if (ret == -ETIMEDOUT) {
1441 /* Just for information */
1442 wx_err(wx,
1443 "RRCFG.EN on Rx queue %d not cleared within the polling period\n",
1444 reg_idx);
1445 }
1446 }
1447 EXPORT_SYMBOL(wx_disable_rx_queue);
1448
wx_enable_rx_queue(struct wx * wx,struct wx_ring * ring)1449 static void wx_enable_rx_queue(struct wx *wx, struct wx_ring *ring)
1450 {
1451 u8 reg_idx = ring->reg_idx;
1452 u32 rxdctl;
1453 int ret;
1454
1455 ret = read_poll_timeout(rd32, rxdctl, rxdctl & WX_PX_RR_CFG_RR_EN,
1456 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx));
1457
1458 if (ret == -ETIMEDOUT) {
1459 /* Just for information */
1460 wx_err(wx,
1461 "RRCFG.EN on Rx queue %d not set within the polling period\n",
1462 reg_idx);
1463 }
1464 }
1465
wx_configure_srrctl(struct wx * wx,struct wx_ring * rx_ring)1466 static void wx_configure_srrctl(struct wx *wx,
1467 struct wx_ring *rx_ring)
1468 {
1469 u16 reg_idx = rx_ring->reg_idx;
1470 u32 srrctl;
1471
1472 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
1473 srrctl &= ~(WX_PX_RR_CFG_RR_HDR_SZ |
1474 WX_PX_RR_CFG_RR_BUF_SZ |
1475 WX_PX_RR_CFG_SPLIT_MODE);
1476 /* configure header buffer length, needed for RSC */
1477 srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT;
1478
1479 /* configure the packet buffer length */
1480 srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT;
1481
1482 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);
1483 }
1484
wx_configure_tx_ring(struct wx * wx,struct wx_ring * ring)1485 static void wx_configure_tx_ring(struct wx *wx,
1486 struct wx_ring *ring)
1487 {
1488 u32 txdctl = WX_PX_TR_CFG_ENABLE;
1489 u8 reg_idx = ring->reg_idx;
1490 u64 tdba = ring->dma;
1491 int ret;
1492
1493 /* disable queue to avoid issues while updating state */
1494 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH);
1495 WX_WRITE_FLUSH(wx);
1496
1497 wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32));
1498 wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba));
1499
1500 /* reset head and tail pointers */
1501 wr32(wx, WX_PX_TR_RP(reg_idx), 0);
1502 wr32(wx, WX_PX_TR_WP(reg_idx), 0);
1503 ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx);
1504
1505 if (ring->count < WX_MAX_TXD)
1506 txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT;
1507 txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT;
1508
1509 ring->atr_count = 0;
1510 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) &&
1511 test_bit(WX_FLAG_FDIR_HASH, wx->flags))
1512 ring->atr_sample_rate = wx->atr_sample_rate;
1513 else
1514 ring->atr_sample_rate = 0;
1515
1516 /* reinitialize tx_buffer_info */
1517 memset(ring->tx_buffer_info, 0,
1518 sizeof(struct wx_tx_buffer) * ring->count);
1519
1520 /* enable queue */
1521 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl);
1522
1523 /* poll to verify queue is enabled */
1524 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE,
1525 1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx));
1526 if (ret == -ETIMEDOUT)
1527 wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx);
1528 }
1529
wx_configure_rx_ring(struct wx * wx,struct wx_ring * ring)1530 static void wx_configure_rx_ring(struct wx *wx,
1531 struct wx_ring *ring)
1532 {
1533 u16 reg_idx = ring->reg_idx;
1534 union wx_rx_desc *rx_desc;
1535 u64 rdba = ring->dma;
1536 u32 rxdctl;
1537
1538 /* disable queue to avoid issues while updating state */
1539 rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
1540 wx_disable_rx_queue(wx, ring);
1541
1542 wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32));
1543 wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba));
1544
1545 if (ring->count == WX_MAX_RXD)
1546 rxdctl |= 0 << WX_PX_RR_CFG_RR_SIZE_SHIFT;
1547 else
1548 rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT;
1549
1550 rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT;
1551 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl);
1552
1553 /* reset head and tail pointers */
1554 wr32(wx, WX_PX_RR_RP(reg_idx), 0);
1555 wr32(wx, WX_PX_RR_WP(reg_idx), 0);
1556 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx);
1557
1558 wx_configure_srrctl(wx, ring);
1559
1560 /* initialize rx_buffer_info */
1561 memset(ring->rx_buffer_info, 0,
1562 sizeof(struct wx_rx_buffer) * ring->count);
1563
1564 /* initialize Rx descriptor 0 */
1565 rx_desc = WX_RX_DESC(ring, 0);
1566 rx_desc->wb.upper.length = 0;
1567
1568 /* enable receive descriptor ring */
1569 wr32m(wx, WX_PX_RR_CFG(reg_idx),
1570 WX_PX_RR_CFG_RR_EN, WX_PX_RR_CFG_RR_EN);
1571
1572 wx_enable_rx_queue(wx, ring);
1573 wx_alloc_rx_buffers(ring, wx_desc_unused(ring));
1574 }
1575
1576 /**
1577 * wx_configure_tx - Configure Transmit Unit after Reset
1578 * @wx: pointer to private structure
1579 *
1580 * Configure the Tx unit of the MAC after a reset.
1581 **/
wx_configure_tx(struct wx * wx)1582 static void wx_configure_tx(struct wx *wx)
1583 {
1584 u32 i;
1585
1586 /* TDM_CTL.TE must be before Tx queues are enabled */
1587 wr32m(wx, WX_TDM_CTL,
1588 WX_TDM_CTL_TE, WX_TDM_CTL_TE);
1589
1590 /* Setup the HW Tx Head and Tail descriptor pointers */
1591 for (i = 0; i < wx->num_tx_queues; i++)
1592 wx_configure_tx_ring(wx, wx->tx_ring[i]);
1593
1594 wr32m(wx, WX_TSC_BUF_AE, WX_TSC_BUF_AE_THR, 0x10);
1595
1596 if (wx->mac.type == wx_mac_em)
1597 wr32m(wx, WX_TSC_CTL, WX_TSC_CTL_TX_DIS | WX_TSC_CTL_TSEC_DIS, 0x1);
1598
1599 /* enable mac transmitter */
1600 wr32m(wx, WX_MAC_TX_CFG,
1601 WX_MAC_TX_CFG_TE, WX_MAC_TX_CFG_TE);
1602 }
1603
wx_restore_vlan(struct wx * wx)1604 static void wx_restore_vlan(struct wx *wx)
1605 {
1606 u16 vid = 1;
1607
1608 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), 0);
1609
1610 for_each_set_bit_from(vid, wx->active_vlans, VLAN_N_VID)
1611 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), vid);
1612 }
1613
wx_store_reta(struct wx * wx)1614 static void wx_store_reta(struct wx *wx)
1615 {
1616 u8 *indir_tbl = wx->rss_indir_tbl;
1617 u32 reta = 0;
1618 u32 i;
1619
1620 /* Fill out the redirection table as follows:
1621 * - 8 bit wide entries containing 4 bit RSS index
1622 */
1623 for (i = 0; i < WX_MAX_RETA_ENTRIES; i++) {
1624 reta |= indir_tbl[i] << (i & 0x3) * 8;
1625 if ((i & 3) == 3) {
1626 wr32(wx, WX_RDB_RSSTBL(i >> 2), reta);
1627 reta = 0;
1628 }
1629 }
1630 }
1631
wx_setup_reta(struct wx * wx)1632 static void wx_setup_reta(struct wx *wx)
1633 {
1634 u16 rss_i = wx->ring_feature[RING_F_RSS].indices;
1635 u32 random_key_size = WX_RSS_KEY_SIZE / 4;
1636 u32 i, j;
1637
1638 /* Fill out hash function seeds */
1639 for (i = 0; i < random_key_size; i++)
1640 wr32(wx, WX_RDB_RSSRK(i), wx->rss_key[i]);
1641
1642 /* Fill out redirection table */
1643 memset(wx->rss_indir_tbl, 0, sizeof(wx->rss_indir_tbl));
1644
1645 for (i = 0, j = 0; i < WX_MAX_RETA_ENTRIES; i++, j++) {
1646 if (j == rss_i)
1647 j = 0;
1648
1649 wx->rss_indir_tbl[i] = j;
1650 }
1651
1652 wx_store_reta(wx);
1653 }
1654
wx_setup_mrqc(struct wx * wx)1655 static void wx_setup_mrqc(struct wx *wx)
1656 {
1657 u32 rss_field = 0;
1658
1659 /* Disable indicating checksum in descriptor, enables RSS hash */
1660 wr32m(wx, WX_PSR_CTL, WX_PSR_CTL_PCSD, WX_PSR_CTL_PCSD);
1661
1662 /* Perform hash on these packet types */
1663 rss_field = WX_RDB_RA_CTL_RSS_IPV4 |
1664 WX_RDB_RA_CTL_RSS_IPV4_TCP |
1665 WX_RDB_RA_CTL_RSS_IPV4_UDP |
1666 WX_RDB_RA_CTL_RSS_IPV6 |
1667 WX_RDB_RA_CTL_RSS_IPV6_TCP |
1668 WX_RDB_RA_CTL_RSS_IPV6_UDP;
1669
1670 netdev_rss_key_fill(wx->rss_key, sizeof(wx->rss_key));
1671
1672 wx_setup_reta(wx);
1673
1674 if (wx->rss_enabled)
1675 rss_field |= WX_RDB_RA_CTL_RSS_EN;
1676
1677 wr32(wx, WX_RDB_RA_CTL, rss_field);
1678 }
1679
1680 /**
1681 * wx_configure_rx - Configure Receive Unit after Reset
1682 * @wx: pointer to private structure
1683 *
1684 * Configure the Rx unit of the MAC after a reset.
1685 **/
wx_configure_rx(struct wx * wx)1686 void wx_configure_rx(struct wx *wx)
1687 {
1688 u32 psrtype, i;
1689 int ret;
1690
1691 wx_disable_rx(wx);
1692
1693 psrtype = WX_RDB_PL_CFG_L4HDR |
1694 WX_RDB_PL_CFG_L3HDR |
1695 WX_RDB_PL_CFG_L2HDR |
1696 WX_RDB_PL_CFG_TUN_TUNHDR;
1697 wr32(wx, WX_RDB_PL_CFG(0), psrtype);
1698
1699 /* enable hw crc stripping */
1700 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_CRC_STRIP, WX_RSC_CTL_CRC_STRIP);
1701
1702 if (wx->mac.type == wx_mac_sp) {
1703 u32 psrctl;
1704
1705 /* RSC Setup */
1706 psrctl = rd32(wx, WX_PSR_CTL);
1707 psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */
1708 psrctl |= WX_PSR_CTL_RSC_DIS;
1709 wr32(wx, WX_PSR_CTL, psrctl);
1710 }
1711
1712 wx_setup_mrqc(wx);
1713
1714 /* set_rx_buffer_len must be called before ring initialization */
1715 wx_set_rx_buffer_len(wx);
1716
1717 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1718 * the Base and Length of the Rx Descriptor Ring
1719 */
1720 for (i = 0; i < wx->num_rx_queues; i++)
1721 wx_configure_rx_ring(wx, wx->rx_ring[i]);
1722
1723 /* Enable all receives, disable security engine prior to block traffic */
1724 ret = wx_disable_sec_rx_path(wx);
1725 if (ret < 0)
1726 wx_err(wx, "The register status is abnormal, please check device.");
1727
1728 wx_enable_rx(wx);
1729 wx_enable_sec_rx_path(wx);
1730 }
1731 EXPORT_SYMBOL(wx_configure_rx);
1732
wx_configure_isb(struct wx * wx)1733 static void wx_configure_isb(struct wx *wx)
1734 {
1735 /* set ISB Address */
1736 wr32(wx, WX_PX_ISB_ADDR_L, wx->isb_dma & DMA_BIT_MASK(32));
1737 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
1738 wr32(wx, WX_PX_ISB_ADDR_H, upper_32_bits(wx->isb_dma));
1739 }
1740
wx_configure(struct wx * wx)1741 void wx_configure(struct wx *wx)
1742 {
1743 wx_set_rxpba(wx);
1744 wx_pbthresh_setup(wx);
1745 wx_configure_port(wx);
1746
1747 wx_set_rx_mode(wx->netdev);
1748 wx_restore_vlan(wx);
1749
1750 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))
1751 wx->configure_fdir(wx);
1752
1753 wx_configure_tx(wx);
1754 wx_configure_rx(wx);
1755 wx_configure_isb(wx);
1756 }
1757 EXPORT_SYMBOL(wx_configure);
1758
1759 /**
1760 * wx_disable_pcie_master - Disable PCI-express master access
1761 * @wx: pointer to hardware structure
1762 *
1763 * Disables PCI-Express master access and verifies there are no pending
1764 * requests.
1765 **/
wx_disable_pcie_master(struct wx * wx)1766 int wx_disable_pcie_master(struct wx *wx)
1767 {
1768 int status = 0;
1769 u32 val;
1770
1771 /* Always set this bit to ensure any future transactions are blocked */
1772 pci_clear_master(wx->pdev);
1773
1774 /* Exit if master requests are blocked */
1775 if (!(rd32(wx, WX_PX_TRANSACTION_PENDING)))
1776 return 0;
1777
1778 /* Poll for master request bit to clear */
1779 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT,
1780 false, wx, WX_PX_TRANSACTION_PENDING);
1781 if (status < 0)
1782 wx_err(wx, "PCIe transaction pending bit did not clear.\n");
1783
1784 return status;
1785 }
1786 EXPORT_SYMBOL(wx_disable_pcie_master);
1787
1788 /**
1789 * wx_stop_adapter - Generic stop Tx/Rx units
1790 * @wx: pointer to hardware structure
1791 *
1792 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts,
1793 * disables transmit and receive units. The adapter_stopped flag is used by
1794 * the shared code and drivers to determine if the adapter is in a stopped
1795 * state and should not touch the hardware.
1796 **/
wx_stop_adapter(struct wx * wx)1797 int wx_stop_adapter(struct wx *wx)
1798 {
1799 u16 i;
1800
1801 /* Set the adapter_stopped flag so other driver functions stop touching
1802 * the hardware
1803 */
1804 wx->adapter_stopped = true;
1805
1806 /* Disable the receive unit */
1807 wx_disable_rx(wx);
1808
1809 /* Set interrupt mask to stop interrupts from being generated */
1810 wx_intr_disable(wx, WX_INTR_ALL);
1811
1812 /* Clear any pending interrupts, flush previous writes */
1813 wr32(wx, WX_PX_MISC_IC, 0xffffffff);
1814 wr32(wx, WX_BME_CTL, 0x3);
1815
1816 /* Disable the transmit unit. Each queue must be disabled. */
1817 for (i = 0; i < wx->mac.max_tx_queues; i++) {
1818 wr32m(wx, WX_PX_TR_CFG(i),
1819 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE,
1820 WX_PX_TR_CFG_SWFLSH);
1821 }
1822
1823 /* Disable the receive unit by stopping each queue */
1824 for (i = 0; i < wx->mac.max_rx_queues; i++) {
1825 wr32m(wx, WX_PX_RR_CFG(i),
1826 WX_PX_RR_CFG_RR_EN, 0);
1827 }
1828
1829 /* flush all queues disables */
1830 WX_WRITE_FLUSH(wx);
1831
1832 /* Prevent the PCI-E bus from hanging by disabling PCI-E master
1833 * access and verify no pending requests
1834 */
1835 return wx_disable_pcie_master(wx);
1836 }
1837 EXPORT_SYMBOL(wx_stop_adapter);
1838
wx_reset_misc(struct wx * wx)1839 void wx_reset_misc(struct wx *wx)
1840 {
1841 int i;
1842
1843 /* receive packets that size > 2048 */
1844 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE);
1845
1846 /* clear counters on read */
1847 wr32m(wx, WX_MMC_CONTROL,
1848 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD);
1849
1850 wr32m(wx, WX_MAC_RX_FLOW_CTRL,
1851 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE);
1852
1853 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
1854
1855 wr32m(wx, WX_MIS_RST_ST,
1856 WX_MIS_RST_ST_RST_INIT, 0x1E00);
1857
1858 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
1859 wr32(wx, WX_PSR_MNG_FLEX_SEL, 0);
1860 for (i = 0; i < 16; i++) {
1861 wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0);
1862 wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0);
1863 wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0);
1864 }
1865 wr32(wx, WX_PSR_LAN_FLEX_SEL, 0);
1866 for (i = 0; i < 16; i++) {
1867 wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0);
1868 wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0);
1869 wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0);
1870 }
1871
1872 /* set pause frame dst mac addr */
1873 wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001);
1874 wr32(wx, WX_RDB_PFCMACDAH, 0x0180);
1875 }
1876 EXPORT_SYMBOL(wx_reset_misc);
1877
1878 /**
1879 * wx_get_pcie_msix_counts - Gets MSI-X vector count
1880 * @wx: pointer to hardware structure
1881 * @msix_count: number of MSI interrupts that can be obtained
1882 * @max_msix_count: number of MSI interrupts that mac need
1883 *
1884 * Read PCIe configuration space, and get the MSI-X vector count from
1885 * the capabilities table.
1886 **/
wx_get_pcie_msix_counts(struct wx * wx,u16 * msix_count,u16 max_msix_count)1887 int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count)
1888 {
1889 struct pci_dev *pdev = wx->pdev;
1890 struct device *dev = &pdev->dev;
1891 int pos;
1892
1893 *msix_count = 1;
1894 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
1895 if (!pos) {
1896 dev_err(dev, "Unable to find MSI-X Capabilities\n");
1897 return -EINVAL;
1898 }
1899 pci_read_config_word(pdev,
1900 pos + PCI_MSIX_FLAGS,
1901 msix_count);
1902 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK;
1903 /* MSI-X count is zero-based in HW */
1904 *msix_count += 1;
1905
1906 if (*msix_count > max_msix_count)
1907 *msix_count = max_msix_count;
1908
1909 return 0;
1910 }
1911 EXPORT_SYMBOL(wx_get_pcie_msix_counts);
1912
1913 /**
1914 * wx_init_rss_key - Initialize wx RSS key
1915 * @wx: device handle
1916 *
1917 * Allocates and initializes the RSS key if it is not allocated.
1918 **/
wx_init_rss_key(struct wx * wx)1919 static int wx_init_rss_key(struct wx *wx)
1920 {
1921 u32 *rss_key;
1922
1923 if (!wx->rss_key) {
1924 rss_key = kzalloc(WX_RSS_KEY_SIZE, GFP_KERNEL);
1925 if (unlikely(!rss_key))
1926 return -ENOMEM;
1927
1928 netdev_rss_key_fill(rss_key, WX_RSS_KEY_SIZE);
1929 wx->rss_key = rss_key;
1930 }
1931
1932 return 0;
1933 }
1934
wx_sw_init(struct wx * wx)1935 int wx_sw_init(struct wx *wx)
1936 {
1937 struct pci_dev *pdev = wx->pdev;
1938 u32 ssid = 0;
1939 int err = 0;
1940
1941 wx->vendor_id = pdev->vendor;
1942 wx->device_id = pdev->device;
1943 wx->revision_id = pdev->revision;
1944 wx->oem_svid = pdev->subsystem_vendor;
1945 wx->oem_ssid = pdev->subsystem_device;
1946 wx->bus.device = PCI_SLOT(pdev->devfn);
1947 wx->bus.func = PCI_FUNC(pdev->devfn);
1948
1949 if (wx->oem_svid == PCI_VENDOR_ID_WANGXUN) {
1950 wx->subsystem_vendor_id = pdev->subsystem_vendor;
1951 wx->subsystem_device_id = pdev->subsystem_device;
1952 } else {
1953 err = wx_flash_read_dword(wx, 0xfffdc, &ssid);
1954 if (err < 0) {
1955 wx_err(wx, "read of internal subsystem device id failed\n");
1956 return err;
1957 }
1958
1959 wx->subsystem_device_id = swab16((u16)ssid);
1960 }
1961
1962 err = wx_init_rss_key(wx);
1963 if (err < 0) {
1964 wx_err(wx, "rss key allocation failed\n");
1965 return err;
1966 }
1967
1968 wx->mac_table = kcalloc(wx->mac.num_rar_entries,
1969 sizeof(struct wx_mac_addr),
1970 GFP_KERNEL);
1971 if (!wx->mac_table) {
1972 wx_err(wx, "mac_table allocation failed\n");
1973 kfree(wx->rss_key);
1974 return -ENOMEM;
1975 }
1976
1977 bitmap_zero(wx->state, WX_STATE_NBITS);
1978 bitmap_zero(wx->flags, WX_PF_FLAGS_NBITS);
1979 wx->misc_irq_domain = false;
1980
1981 return 0;
1982 }
1983 EXPORT_SYMBOL(wx_sw_init);
1984
1985 /**
1986 * wx_find_vlvf_slot - find the vlanid or the first empty slot
1987 * @wx: pointer to hardware structure
1988 * @vlan: VLAN id to write to VLAN filter
1989 *
1990 * return the VLVF index where this VLAN id should be placed
1991 *
1992 **/
wx_find_vlvf_slot(struct wx * wx,u32 vlan)1993 static int wx_find_vlvf_slot(struct wx *wx, u32 vlan)
1994 {
1995 u32 bits = 0, first_empty_slot = 0;
1996 int regindex;
1997
1998 /* short cut the special case */
1999 if (vlan == 0)
2000 return 0;
2001
2002 /* Search for the vlan id in the VLVF entries. Save off the first empty
2003 * slot found along the way
2004 */
2005 for (regindex = 1; regindex < WX_PSR_VLAN_SWC_ENTRIES; regindex++) {
2006 wr32(wx, WX_PSR_VLAN_SWC_IDX, regindex);
2007 bits = rd32(wx, WX_PSR_VLAN_SWC);
2008 if (!bits && !(first_empty_slot))
2009 first_empty_slot = regindex;
2010 else if ((bits & 0x0FFF) == vlan)
2011 break;
2012 }
2013
2014 if (regindex >= WX_PSR_VLAN_SWC_ENTRIES) {
2015 if (first_empty_slot)
2016 regindex = first_empty_slot;
2017 else
2018 regindex = -ENOMEM;
2019 }
2020
2021 return regindex;
2022 }
2023
2024 /**
2025 * wx_set_vlvf - Set VLAN Pool Filter
2026 * @wx: pointer to hardware structure
2027 * @vlan: VLAN id to write to VLAN filter
2028 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2029 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2030 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
2031 * should be changed
2032 *
2033 * Turn on/off specified bit in VLVF table.
2034 **/
wx_set_vlvf(struct wx * wx,u32 vlan,u32 vind,bool vlan_on,bool * vfta_changed)2035 static int wx_set_vlvf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on,
2036 bool *vfta_changed)
2037 {
2038 int vlvf_index;
2039 u32 vt, bits;
2040
2041 /* If VT Mode is set
2042 * Either vlan_on
2043 * make sure the vlan is in VLVF
2044 * set the vind bit in the matching VLVFB
2045 * Or !vlan_on
2046 * clear the pool bit and possibly the vind
2047 */
2048 vt = rd32(wx, WX_CFG_PORT_CTL);
2049 if (!(vt & WX_CFG_PORT_CTL_NUM_VT_MASK))
2050 return 0;
2051
2052 vlvf_index = wx_find_vlvf_slot(wx, vlan);
2053 if (vlvf_index < 0)
2054 return vlvf_index;
2055
2056 wr32(wx, WX_PSR_VLAN_SWC_IDX, vlvf_index);
2057 if (vlan_on) {
2058 /* set the pool bit */
2059 if (vind < 32) {
2060 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L);
2061 bits |= (1 << vind);
2062 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits);
2063 } else {
2064 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H);
2065 bits |= (1 << (vind - 32));
2066 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits);
2067 }
2068 } else {
2069 /* clear the pool bit */
2070 if (vind < 32) {
2071 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L);
2072 bits &= ~(1 << vind);
2073 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits);
2074 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_H);
2075 } else {
2076 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H);
2077 bits &= ~(1 << (vind - 32));
2078 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits);
2079 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_L);
2080 }
2081 }
2082
2083 if (bits) {
2084 wr32(wx, WX_PSR_VLAN_SWC, (WX_PSR_VLAN_SWC_VIEN | vlan));
2085 if (!vlan_on && vfta_changed)
2086 *vfta_changed = false;
2087 } else {
2088 wr32(wx, WX_PSR_VLAN_SWC, 0);
2089 }
2090
2091 return 0;
2092 }
2093
2094 /**
2095 * wx_set_vfta - Set VLAN filter table
2096 * @wx: pointer to hardware structure
2097 * @vlan: VLAN id to write to VLAN filter
2098 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2099 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2100 *
2101 * Turn on/off specified VLAN in the VLAN filter table.
2102 **/
wx_set_vfta(struct wx * wx,u32 vlan,u32 vind,bool vlan_on)2103 static int wx_set_vfta(struct wx *wx, u32 vlan, u32 vind, bool vlan_on)
2104 {
2105 u32 bitindex, vfta, targetbit;
2106 bool vfta_changed = false;
2107 int regindex, ret;
2108
2109 /* this is a 2 part operation - first the VFTA, then the
2110 * VLVF and VLVFB if VT Mode is set
2111 * We don't write the VFTA until we know the VLVF part succeeded.
2112 */
2113
2114 /* Part 1
2115 * The VFTA is a bitstring made up of 128 32-bit registers
2116 * that enable the particular VLAN id, much like the MTA:
2117 * bits[11-5]: which register
2118 * bits[4-0]: which bit in the register
2119 */
2120 regindex = (vlan >> 5) & 0x7F;
2121 bitindex = vlan & 0x1F;
2122 targetbit = (1 << bitindex);
2123 /* errata 5 */
2124 vfta = wx->mac.vft_shadow[regindex];
2125 if (vlan_on) {
2126 if (!(vfta & targetbit)) {
2127 vfta |= targetbit;
2128 vfta_changed = true;
2129 }
2130 } else {
2131 if ((vfta & targetbit)) {
2132 vfta &= ~targetbit;
2133 vfta_changed = true;
2134 }
2135 }
2136 /* Part 2
2137 * Call wx_set_vlvf to set VLVFB and VLVF
2138 */
2139 ret = wx_set_vlvf(wx, vlan, vind, vlan_on, &vfta_changed);
2140 if (ret != 0)
2141 return ret;
2142
2143 if (vfta_changed)
2144 wr32(wx, WX_PSR_VLAN_TBL(regindex), vfta);
2145 wx->mac.vft_shadow[regindex] = vfta;
2146
2147 return 0;
2148 }
2149
2150 /**
2151 * wx_clear_vfta - Clear VLAN filter table
2152 * @wx: pointer to hardware structure
2153 *
2154 * Clears the VLAN filer table, and the VMDq index associated with the filter
2155 **/
wx_clear_vfta(struct wx * wx)2156 static void wx_clear_vfta(struct wx *wx)
2157 {
2158 u32 offset;
2159
2160 for (offset = 0; offset < wx->mac.vft_size; offset++) {
2161 wr32(wx, WX_PSR_VLAN_TBL(offset), 0);
2162 wx->mac.vft_shadow[offset] = 0;
2163 }
2164
2165 for (offset = 0; offset < WX_PSR_VLAN_SWC_ENTRIES; offset++) {
2166 wr32(wx, WX_PSR_VLAN_SWC_IDX, offset);
2167 wr32(wx, WX_PSR_VLAN_SWC, 0);
2168 wr32(wx, WX_PSR_VLAN_SWC_VM_L, 0);
2169 wr32(wx, WX_PSR_VLAN_SWC_VM_H, 0);
2170 }
2171 }
2172
wx_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2173 int wx_vlan_rx_add_vid(struct net_device *netdev,
2174 __be16 proto, u16 vid)
2175 {
2176 struct wx *wx = netdev_priv(netdev);
2177
2178 /* add VID to filter table */
2179 wx_set_vfta(wx, vid, VMDQ_P(0), true);
2180 set_bit(vid, wx->active_vlans);
2181
2182 return 0;
2183 }
2184 EXPORT_SYMBOL(wx_vlan_rx_add_vid);
2185
wx_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2186 int wx_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
2187 {
2188 struct wx *wx = netdev_priv(netdev);
2189
2190 /* remove VID from filter table */
2191 if (vid)
2192 wx_set_vfta(wx, vid, VMDQ_P(0), false);
2193 clear_bit(vid, wx->active_vlans);
2194
2195 return 0;
2196 }
2197 EXPORT_SYMBOL(wx_vlan_rx_kill_vid);
2198
wx_enable_rx_drop(struct wx * wx,struct wx_ring * ring)2199 static void wx_enable_rx_drop(struct wx *wx, struct wx_ring *ring)
2200 {
2201 u16 reg_idx = ring->reg_idx;
2202 u32 srrctl;
2203
2204 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
2205 srrctl |= WX_PX_RR_CFG_DROP_EN;
2206
2207 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);
2208 }
2209
wx_disable_rx_drop(struct wx * wx,struct wx_ring * ring)2210 static void wx_disable_rx_drop(struct wx *wx, struct wx_ring *ring)
2211 {
2212 u16 reg_idx = ring->reg_idx;
2213 u32 srrctl;
2214
2215 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
2216 srrctl &= ~WX_PX_RR_CFG_DROP_EN;
2217
2218 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);
2219 }
2220
wx_fc_enable(struct wx * wx,bool tx_pause,bool rx_pause)2221 int wx_fc_enable(struct wx *wx, bool tx_pause, bool rx_pause)
2222 {
2223 u16 pause_time = WX_DEFAULT_FCPAUSE;
2224 u32 mflcn_reg, fccfg_reg, reg;
2225 u32 fcrtl, fcrth;
2226 int i;
2227
2228 /* Low water mark of zero causes XOFF floods */
2229 if (tx_pause && wx->fc.high_water) {
2230 if (!wx->fc.low_water || wx->fc.low_water >= wx->fc.high_water) {
2231 wx_err(wx, "Invalid water mark configuration\n");
2232 return -EINVAL;
2233 }
2234 }
2235
2236 /* Disable any previous flow control settings */
2237 mflcn_reg = rd32(wx, WX_MAC_RX_FLOW_CTRL);
2238 mflcn_reg &= ~WX_MAC_RX_FLOW_CTRL_RFE;
2239
2240 fccfg_reg = rd32(wx, WX_RDB_RFCC);
2241 fccfg_reg &= ~WX_RDB_RFCC_RFCE_802_3X;
2242
2243 if (rx_pause)
2244 mflcn_reg |= WX_MAC_RX_FLOW_CTRL_RFE;
2245 if (tx_pause)
2246 fccfg_reg |= WX_RDB_RFCC_RFCE_802_3X;
2247
2248 /* Set 802.3x based flow control settings. */
2249 wr32(wx, WX_MAC_RX_FLOW_CTRL, mflcn_reg);
2250 wr32(wx, WX_RDB_RFCC, fccfg_reg);
2251
2252 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2253 if (tx_pause && wx->fc.high_water) {
2254 fcrtl = (wx->fc.low_water << 10) | WX_RDB_RFCL_XONE;
2255 wr32(wx, WX_RDB_RFCL, fcrtl);
2256 fcrth = (wx->fc.high_water << 10) | WX_RDB_RFCH_XOFFE;
2257 } else {
2258 wr32(wx, WX_RDB_RFCL, 0);
2259 /* In order to prevent Tx hangs when the internal Tx
2260 * switch is enabled we must set the high water mark
2261 * to the Rx packet buffer size - 24KB. This allows
2262 * the Tx switch to function even under heavy Rx
2263 * workloads.
2264 */
2265 fcrth = rd32(wx, WX_RDB_PB_SZ(0)) - 24576;
2266 }
2267
2268 wr32(wx, WX_RDB_RFCH, fcrth);
2269
2270 /* Configure pause time */
2271 reg = pause_time * 0x00010001;
2272 wr32(wx, WX_RDB_RFCV, reg);
2273
2274 /* Configure flow control refresh threshold value */
2275 wr32(wx, WX_RDB_RFCRT, pause_time / 2);
2276
2277 /* We should set the drop enable bit if:
2278 * Number of Rx queues > 1 and flow control is disabled
2279 *
2280 * This allows us to avoid head of line blocking for security
2281 * and performance reasons.
2282 */
2283 if (wx->num_rx_queues > 1 && !tx_pause) {
2284 for (i = 0; i < wx->num_rx_queues; i++)
2285 wx_enable_rx_drop(wx, wx->rx_ring[i]);
2286 } else {
2287 for (i = 0; i < wx->num_rx_queues; i++)
2288 wx_disable_rx_drop(wx, wx->rx_ring[i]);
2289 }
2290
2291 return 0;
2292 }
2293 EXPORT_SYMBOL(wx_fc_enable);
2294
2295 /**
2296 * wx_update_stats - Update the board statistics counters.
2297 * @wx: board private structure
2298 **/
wx_update_stats(struct wx * wx)2299 void wx_update_stats(struct wx *wx)
2300 {
2301 struct wx_hw_stats *hwstats = &wx->stats;
2302
2303 u64 non_eop_descs = 0, alloc_rx_buff_failed = 0;
2304 u64 hw_csum_rx_good = 0, hw_csum_rx_error = 0;
2305 u64 restart_queue = 0, tx_busy = 0;
2306 u32 i;
2307
2308 /* gather some stats to the wx struct that are per queue */
2309 for (i = 0; i < wx->num_rx_queues; i++) {
2310 struct wx_ring *rx_ring = wx->rx_ring[i];
2311
2312 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
2313 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
2314 hw_csum_rx_good += rx_ring->rx_stats.csum_good_cnt;
2315 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
2316 }
2317 wx->non_eop_descs = non_eop_descs;
2318 wx->alloc_rx_buff_failed = alloc_rx_buff_failed;
2319 wx->hw_csum_rx_error = hw_csum_rx_error;
2320 wx->hw_csum_rx_good = hw_csum_rx_good;
2321
2322 for (i = 0; i < wx->num_tx_queues; i++) {
2323 struct wx_ring *tx_ring = wx->tx_ring[i];
2324
2325 restart_queue += tx_ring->tx_stats.restart_queue;
2326 tx_busy += tx_ring->tx_stats.tx_busy;
2327 }
2328 wx->restart_queue = restart_queue;
2329 wx->tx_busy = tx_busy;
2330
2331 hwstats->gprc += rd32(wx, WX_RDM_PKT_CNT);
2332 hwstats->gptc += rd32(wx, WX_TDM_PKT_CNT);
2333 hwstats->gorc += rd64(wx, WX_RDM_BYTE_CNT_LSB);
2334 hwstats->gotc += rd64(wx, WX_TDM_BYTE_CNT_LSB);
2335 hwstats->tpr += rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L);
2336 hwstats->tpt += rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L);
2337 hwstats->crcerrs += rd64(wx, WX_RX_CRC_ERROR_FRAMES_L);
2338 hwstats->rlec += rd64(wx, WX_RX_LEN_ERROR_FRAMES_L);
2339 hwstats->bprc += rd64(wx, WX_RX_BC_FRAMES_GOOD_L);
2340 hwstats->bptc += rd64(wx, WX_TX_BC_FRAMES_GOOD_L);
2341 hwstats->mprc += rd64(wx, WX_RX_MC_FRAMES_GOOD_L);
2342 hwstats->mptc += rd64(wx, WX_TX_MC_FRAMES_GOOD_L);
2343 hwstats->roc += rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD);
2344 hwstats->ruc += rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD);
2345 hwstats->lxonoffrxc += rd32(wx, WX_MAC_LXONOFFRXC);
2346 hwstats->lxontxc += rd32(wx, WX_RDB_LXONTXC);
2347 hwstats->lxofftxc += rd32(wx, WX_RDB_LXOFFTXC);
2348 hwstats->o2bgptc += rd32(wx, WX_TDM_OS2BMC_CNT);
2349 hwstats->b2ospc += rd32(wx, WX_MNG_BMC2OS_CNT);
2350 hwstats->o2bspc += rd32(wx, WX_MNG_OS2BMC_CNT);
2351 hwstats->b2ogprc += rd32(wx, WX_RDM_BMC2OS_CNT);
2352 hwstats->rdmdrop += rd32(wx, WX_RDM_DRP_PKT);
2353
2354 if (wx->mac.type == wx_mac_sp) {
2355 hwstats->fdirmatch += rd32(wx, WX_RDB_FDIR_MATCH);
2356 hwstats->fdirmiss += rd32(wx, WX_RDB_FDIR_MISS);
2357 }
2358
2359 for (i = 0; i < wx->mac.max_rx_queues; i++)
2360 hwstats->qmprc += rd32(wx, WX_PX_MPRC(i));
2361 }
2362 EXPORT_SYMBOL(wx_update_stats);
2363
2364 /**
2365 * wx_clear_hw_cntrs - Generic clear hardware counters
2366 * @wx: board private structure
2367 *
2368 * Clears all hardware statistics counters by reading them from the hardware
2369 * Statistics counters are clear on read.
2370 **/
wx_clear_hw_cntrs(struct wx * wx)2371 void wx_clear_hw_cntrs(struct wx *wx)
2372 {
2373 u16 i = 0;
2374
2375 for (i = 0; i < wx->mac.max_rx_queues; i++)
2376 wr32(wx, WX_PX_MPRC(i), 0);
2377
2378 rd32(wx, WX_RDM_PKT_CNT);
2379 rd32(wx, WX_TDM_PKT_CNT);
2380 rd64(wx, WX_RDM_BYTE_CNT_LSB);
2381 rd32(wx, WX_TDM_BYTE_CNT_LSB);
2382 rd32(wx, WX_RDM_DRP_PKT);
2383 rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD);
2384 rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD);
2385 rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L);
2386 rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L);
2387 rd64(wx, WX_RX_MC_FRAMES_GOOD_L);
2388 rd64(wx, WX_TX_MC_FRAMES_GOOD_L);
2389 rd64(wx, WX_RX_BC_FRAMES_GOOD_L);
2390 rd64(wx, WX_TX_BC_FRAMES_GOOD_L);
2391 rd64(wx, WX_RX_CRC_ERROR_FRAMES_L);
2392 rd64(wx, WX_RX_LEN_ERROR_FRAMES_L);
2393 rd32(wx, WX_RDB_LXONTXC);
2394 rd32(wx, WX_RDB_LXOFFTXC);
2395 rd32(wx, WX_MAC_LXONOFFRXC);
2396 }
2397 EXPORT_SYMBOL(wx_clear_hw_cntrs);
2398
2399 /**
2400 * wx_start_hw - Prepare hardware for Tx/Rx
2401 * @wx: pointer to hardware structure
2402 *
2403 * Starts the hardware using the generic start_hw function
2404 * and the generation start_hw function.
2405 * Then performs revision-specific operations, if any.
2406 **/
wx_start_hw(struct wx * wx)2407 void wx_start_hw(struct wx *wx)
2408 {
2409 int i;
2410
2411 /* Clear the VLAN filter table */
2412 wx_clear_vfta(wx);
2413 WX_WRITE_FLUSH(wx);
2414 /* Clear the rate limiters */
2415 for (i = 0; i < wx->mac.max_tx_queues; i++) {
2416 wr32(wx, WX_TDM_RP_IDX, i);
2417 wr32(wx, WX_TDM_RP_RATE, 0);
2418 }
2419 }
2420 EXPORT_SYMBOL(wx_start_hw);
2421
2422 MODULE_LICENSE("GPL");
2423