1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #include <linux/etherdevice.h>
5 #include <net/ip6_checksum.h>
6 #include <net/page_pool/helpers.h>
7 #include <net/inet_ecn.h>
8 #include <linux/workqueue.h>
9 #include <linux/iopoll.h>
10 #include <linux/sctp.h>
11 #include <linux/pci.h>
12 #include <net/tcp.h>
13 #include <net/ip.h>
14
15 #include "wx_type.h"
16 #include "wx_lib.h"
17 #include "wx_ptp.h"
18 #include "wx_hw.h"
19
20 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
21 static struct wx_dec_ptype wx_ptype_lookup[256] = {
22 /* L2: mac */
23 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
24 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2),
25 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
26 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
27 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
28 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
29 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
30
31 /* L2: ethertype filter */
32 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
33
34 /* L3: ip non-tunnel */
35 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3),
36 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3),
37 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4),
38 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4),
39 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4),
40 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3),
41 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3),
42 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3),
43 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4),
44 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4),
45
46 /* L2: fcoe */
47 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
48 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
49
50 /* IPv4 --> IPv4/IPv6 */
51 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3),
52 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3),
53 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4),
54 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4),
55 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4),
56 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3),
57 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3),
58 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4),
59 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4),
60 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4),
61
62 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */
63 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3),
64 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3),
65 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3),
66 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4),
67 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4),
68 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4),
69 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3),
70 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3),
71 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4),
72 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4),
73 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4),
74
75 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */
76 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3),
77 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3),
78 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3),
79 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4),
80 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4),
81 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4),
82 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3),
83 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3),
84 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4),
85 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4),
86 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4),
87
88 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */
89 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3),
90 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3),
91 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3),
92 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4),
93 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4),
94 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4),
95 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3),
96 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3),
97 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4),
98 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4),
99 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4),
100
101 /* IPv6 --> IPv4/IPv6 */
102 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3),
103 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3),
104 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4),
105 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4),
106 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4),
107 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3),
108 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3),
109 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4),
110 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4),
111 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4),
112
113 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */
114 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3),
115 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3),
116 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3),
117 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4),
118 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4),
119 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4),
120 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3),
121 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3),
122 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4),
123 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4),
124 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4),
125
126 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */
127 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3),
128 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3),
129 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3),
130 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4),
131 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4),
132 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4),
133 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3),
134 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3),
135 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4),
136 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4),
137 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4),
138
139 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */
140 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3),
141 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3),
142 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3),
143 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4),
144 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4),
145 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4),
146 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3),
147 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3),
148 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4),
149 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4),
150 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4),
151 };
152
wx_decode_ptype(const u8 ptype)153 struct wx_dec_ptype wx_decode_ptype(const u8 ptype)
154 {
155 return wx_ptype_lookup[ptype];
156 }
157 EXPORT_SYMBOL(wx_decode_ptype);
158
159 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */
wx_test_staterr(union wx_rx_desc * rx_desc,const u32 stat_err_bits)160 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc,
161 const u32 stat_err_bits)
162 {
163 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
164 }
165
wx_dma_sync_frag(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer)166 static void wx_dma_sync_frag(struct wx_ring *rx_ring,
167 struct wx_rx_buffer *rx_buffer)
168 {
169 struct sk_buff *skb = rx_buffer->skb;
170 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
171
172 dma_sync_single_range_for_cpu(rx_ring->dev,
173 WX_CB(skb)->dma,
174 skb_frag_off(frag),
175 skb_frag_size(frag),
176 DMA_FROM_DEVICE);
177
178 /* If the page was released, just unmap it. */
179 if (unlikely(WX_CB(skb)->page_released))
180 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
181 }
182
wx_get_rx_buffer(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff ** skb,int * rx_buffer_pgcnt)183 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring,
184 union wx_rx_desc *rx_desc,
185 struct sk_buff **skb,
186 int *rx_buffer_pgcnt)
187 {
188 struct wx_rx_buffer *rx_buffer;
189 unsigned int size;
190
191 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
192 size = le16_to_cpu(rx_desc->wb.upper.length);
193
194 #if (PAGE_SIZE < 8192)
195 *rx_buffer_pgcnt = page_count(rx_buffer->page);
196 #else
197 *rx_buffer_pgcnt = 0;
198 #endif
199
200 prefetchw(rx_buffer->page);
201 *skb = rx_buffer->skb;
202
203 /* Delay unmapping of the first packet. It carries the header
204 * information, HW may still access the header after the writeback.
205 * Only unmap it when EOP is reached
206 */
207 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) {
208 if (!*skb)
209 goto skip_sync;
210 } else {
211 if (*skb)
212 wx_dma_sync_frag(rx_ring, rx_buffer);
213 }
214
215 /* we are reusing so sync this buffer for CPU use */
216 dma_sync_single_range_for_cpu(rx_ring->dev,
217 rx_buffer->dma,
218 rx_buffer->page_offset,
219 size,
220 DMA_FROM_DEVICE);
221 skip_sync:
222 return rx_buffer;
223 }
224
wx_put_rx_buffer(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer,struct sk_buff * skb,int rx_buffer_pgcnt)225 static void wx_put_rx_buffer(struct wx_ring *rx_ring,
226 struct wx_rx_buffer *rx_buffer,
227 struct sk_buff *skb,
228 int rx_buffer_pgcnt)
229 {
230 if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma)
231 /* the page has been released from the ring */
232 WX_CB(skb)->page_released = true;
233
234 /* clear contents of rx_buffer */
235 rx_buffer->page = NULL;
236 rx_buffer->skb = NULL;
237 }
238
wx_build_skb(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer,union wx_rx_desc * rx_desc)239 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring,
240 struct wx_rx_buffer *rx_buffer,
241 union wx_rx_desc *rx_desc)
242 {
243 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
244 #if (PAGE_SIZE < 8192)
245 unsigned int truesize = WX_RX_BUFSZ;
246 #else
247 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
248 #endif
249 struct sk_buff *skb = rx_buffer->skb;
250
251 if (!skb) {
252 void *page_addr = page_address(rx_buffer->page) +
253 rx_buffer->page_offset;
254
255 /* prefetch first cache line of first page */
256 net_prefetch(page_addr);
257
258 /* allocate a skb to store the frags */
259 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256);
260 if (unlikely(!skb))
261 return NULL;
262
263 /* we will be copying header into skb->data in
264 * pskb_may_pull so it is in our interest to prefetch
265 * it now to avoid a possible cache miss
266 */
267 prefetchw(skb->data);
268
269 if (size <= WX_RXBUFFER_256) {
270 memcpy(__skb_put(skb, size), page_addr,
271 ALIGN(size, sizeof(long)));
272 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true);
273 return skb;
274 }
275
276 skb_mark_for_recycle(skb);
277
278 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))
279 WX_CB(skb)->dma = rx_buffer->dma;
280
281 skb_add_rx_frag(skb, 0, rx_buffer->page,
282 rx_buffer->page_offset,
283 size, truesize);
284 goto out;
285
286 } else {
287 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
288 rx_buffer->page_offset, size, truesize);
289 }
290
291 out:
292 #if (PAGE_SIZE < 8192)
293 /* flip page offset to other buffer */
294 rx_buffer->page_offset ^= truesize;
295 #else
296 /* move offset up to the next cache line */
297 rx_buffer->page_offset += truesize;
298 #endif
299
300 return skb;
301 }
302
wx_alloc_mapped_page(struct wx_ring * rx_ring,struct wx_rx_buffer * bi)303 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring,
304 struct wx_rx_buffer *bi)
305 {
306 struct page *page = bi->page;
307 dma_addr_t dma;
308
309 /* since we are recycling buffers we should seldom need to alloc */
310 if (likely(page))
311 return true;
312
313 page = page_pool_dev_alloc_pages(rx_ring->page_pool);
314 if (unlikely(!page))
315 return false;
316 dma = page_pool_get_dma_addr(page);
317
318 bi->page_dma = dma;
319 bi->page = page;
320 bi->page_offset = 0;
321
322 return true;
323 }
324
325 /**
326 * wx_alloc_rx_buffers - Replace used receive buffers
327 * @rx_ring: ring to place buffers on
328 * @cleaned_count: number of buffers to replace
329 **/
wx_alloc_rx_buffers(struct wx_ring * rx_ring,u16 cleaned_count)330 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count)
331 {
332 u16 i = rx_ring->next_to_use;
333 union wx_rx_desc *rx_desc;
334 struct wx_rx_buffer *bi;
335
336 /* nothing to do */
337 if (!cleaned_count)
338 return;
339
340 rx_desc = WX_RX_DESC(rx_ring, i);
341 bi = &rx_ring->rx_buffer_info[i];
342 i -= rx_ring->count;
343
344 do {
345 if (!wx_alloc_mapped_page(rx_ring, bi))
346 break;
347
348 /* sync the buffer for use by the device */
349 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
350 bi->page_offset,
351 WX_RX_BUFSZ,
352 DMA_FROM_DEVICE);
353
354 rx_desc->read.pkt_addr =
355 cpu_to_le64(bi->page_dma + bi->page_offset);
356
357 rx_desc++;
358 bi++;
359 i++;
360 if (unlikely(!i)) {
361 rx_desc = WX_RX_DESC(rx_ring, 0);
362 bi = rx_ring->rx_buffer_info;
363 i -= rx_ring->count;
364 }
365
366 /* clear the status bits for the next_to_use descriptor */
367 rx_desc->wb.upper.status_error = 0;
368
369 cleaned_count--;
370 } while (cleaned_count);
371
372 i += rx_ring->count;
373
374 if (rx_ring->next_to_use != i) {
375 rx_ring->next_to_use = i;
376 /* update next to alloc since we have filled the ring */
377 rx_ring->next_to_alloc = i;
378
379 /* Force memory writes to complete before letting h/w
380 * know there are new descriptors to fetch. (Only
381 * applicable for weak-ordered memory model archs,
382 * such as IA-64).
383 */
384 wmb();
385 writel(i, rx_ring->tail);
386 }
387 }
388
wx_desc_unused(struct wx_ring * ring)389 u16 wx_desc_unused(struct wx_ring *ring)
390 {
391 u16 ntc = ring->next_to_clean;
392 u16 ntu = ring->next_to_use;
393
394 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
395 }
396
397 /**
398 * wx_is_non_eop - process handling of non-EOP buffers
399 * @rx_ring: Rx ring being processed
400 * @rx_desc: Rx descriptor for current buffer
401 * @skb: Current socket buffer containing buffer in progress
402 *
403 * This function updates next to clean. If the buffer is an EOP buffer
404 * this function exits returning false, otherwise it will place the
405 * sk_buff in the next buffer to be chained and return true indicating
406 * that this is in fact a non-EOP buffer.
407 **/
wx_is_non_eop(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)408 static bool wx_is_non_eop(struct wx_ring *rx_ring,
409 union wx_rx_desc *rx_desc,
410 struct sk_buff *skb)
411 {
412 u32 ntc = rx_ring->next_to_clean + 1;
413
414 /* fetch, update, and store next to clean */
415 ntc = (ntc < rx_ring->count) ? ntc : 0;
416 rx_ring->next_to_clean = ntc;
417
418 prefetch(WX_RX_DESC(rx_ring, ntc));
419
420 /* if we are the last buffer then there is nothing else to do */
421 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)))
422 return false;
423
424 rx_ring->rx_buffer_info[ntc].skb = skb;
425 rx_ring->rx_stats.non_eop_descs++;
426
427 return true;
428 }
429
wx_pull_tail(struct sk_buff * skb)430 static void wx_pull_tail(struct sk_buff *skb)
431 {
432 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
433 unsigned int pull_len;
434 unsigned char *va;
435
436 /* it is valid to use page_address instead of kmap since we are
437 * working with pages allocated out of the lomem pool per
438 * alloc_page(GFP_ATOMIC)
439 */
440 va = skb_frag_address(frag);
441
442 /* we need the header to contain the greater of either ETH_HLEN or
443 * 60 bytes if the skb->len is less than 60 for skb_pad.
444 */
445 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256);
446
447 /* align pull length to size of long to optimize memcpy performance */
448 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
449
450 /* update all of the pointers */
451 skb_frag_size_sub(frag, pull_len);
452 skb_frag_off_add(frag, pull_len);
453 skb->data_len -= pull_len;
454 skb->tail += pull_len;
455 }
456
457 /**
458 * wx_cleanup_headers - Correct corrupted or empty headers
459 * @rx_ring: rx descriptor ring packet is being transacted on
460 * @rx_desc: pointer to the EOP Rx descriptor
461 * @skb: pointer to current skb being fixed
462 *
463 * Check for corrupted packet headers caused by senders on the local L2
464 * embedded NIC switch not setting up their Tx Descriptors right. These
465 * should be very rare.
466 *
467 * Also address the case where we are pulling data in on pages only
468 * and as such no data is present in the skb header.
469 *
470 * In addition if skb is not at least 60 bytes we need to pad it so that
471 * it is large enough to qualify as a valid Ethernet frame.
472 *
473 * Returns true if an error was encountered and skb was freed.
474 **/
wx_cleanup_headers(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)475 static bool wx_cleanup_headers(struct wx_ring *rx_ring,
476 union wx_rx_desc *rx_desc,
477 struct sk_buff *skb)
478 {
479 struct net_device *netdev = rx_ring->netdev;
480
481 /* verify that the packet does not have any known errors */
482 if (!netdev ||
483 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) &&
484 !(netdev->features & NETIF_F_RXALL))) {
485 dev_kfree_skb_any(skb);
486 return true;
487 }
488
489 /* place header in linear portion of buffer */
490 if (!skb_headlen(skb))
491 wx_pull_tail(skb);
492
493 /* if eth_skb_pad returns an error the skb was freed */
494 if (eth_skb_pad(skb))
495 return true;
496
497 return false;
498 }
499
wx_rx_hash(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)500 static void wx_rx_hash(struct wx_ring *ring,
501 union wx_rx_desc *rx_desc,
502 struct sk_buff *skb)
503 {
504 u16 rss_type;
505
506 if (!(ring->netdev->features & NETIF_F_RXHASH))
507 return;
508
509 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
510 WX_RXD_RSSTYPE_MASK;
511
512 if (!rss_type)
513 return;
514
515 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
516 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
517 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
518 }
519
520 /**
521 * wx_rx_checksum - indicate in skb if hw indicated a good cksum
522 * @ring: structure containing ring specific data
523 * @rx_desc: current Rx descriptor being processed
524 * @skb: skb currently being received and modified
525 **/
wx_rx_checksum(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)526 static void wx_rx_checksum(struct wx_ring *ring,
527 union wx_rx_desc *rx_desc,
528 struct sk_buff *skb)
529 {
530 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc));
531
532 skb_checksum_none_assert(skb);
533 /* Rx csum disabled */
534 if (!(ring->netdev->features & NETIF_F_RXCSUM))
535 return;
536
537 /* if IPv4 header checksum error */
538 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) &&
539 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) ||
540 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) &&
541 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) {
542 ring->rx_stats.csum_err++;
543 return;
544 }
545
546 /* L4 checksum offload flag must set for the below code to work */
547 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS))
548 return;
549
550 /* Hardware can't guarantee csum if IPv6 Dest Header found */
551 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP &&
552 wx_test_staterr(rx_desc, WX_RXD_STAT_IPV6EX))
553 return;
554
555 /* if L4 checksum error */
556 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) {
557 ring->rx_stats.csum_err++;
558 return;
559 }
560
561 /* It must be a TCP or UDP or SCTP packet with a valid checksum */
562 skb->ip_summed = CHECKSUM_UNNECESSARY;
563
564 /* If there is an outer header present that might contain a checksum
565 * we need to bump the checksum level by 1 to reflect the fact that
566 * we are indicating we validated the inner checksum.
567 */
568 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG)
569 __skb_incr_checksum_unnecessary(skb);
570 ring->rx_stats.csum_good_cnt++;
571 }
572
wx_rx_vlan(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)573 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc,
574 struct sk_buff *skb)
575 {
576 u16 ethertype;
577 u8 idx = 0;
578
579 if ((ring->netdev->features &
580 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) &&
581 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) {
582 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
583 0x1c0) >> 6;
584 ethertype = ring->q_vector->wx->tpid[idx];
585 __vlan_hwaccel_put_tag(skb, htons(ethertype),
586 le16_to_cpu(rx_desc->wb.upper.vlan));
587 }
588 }
589
590 /**
591 * wx_process_skb_fields - Populate skb header fields from Rx descriptor
592 * @rx_ring: rx descriptor ring packet is being transacted on
593 * @rx_desc: pointer to the EOP Rx descriptor
594 * @skb: pointer to current skb being populated
595 *
596 * This function checks the ring, descriptor, and packet information in
597 * order to populate the hash, checksum, protocol, and
598 * other fields within the skb.
599 **/
wx_process_skb_fields(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)600 static void wx_process_skb_fields(struct wx_ring *rx_ring,
601 union wx_rx_desc *rx_desc,
602 struct sk_buff *skb)
603 {
604 struct wx *wx = netdev_priv(rx_ring->netdev);
605
606 wx_rx_hash(rx_ring, rx_desc, skb);
607 wx_rx_checksum(rx_ring, rx_desc, skb);
608
609 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, wx->flags)) &&
610 unlikely(wx_test_staterr(rx_desc, WX_RXD_STAT_TS))) {
611 wx_ptp_rx_hwtstamp(rx_ring->q_vector->wx, skb);
612 rx_ring->last_rx_timestamp = jiffies;
613 }
614
615 wx_rx_vlan(rx_ring, rx_desc, skb);
616 skb_record_rx_queue(skb, rx_ring->queue_index);
617 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
618 }
619
620 /**
621 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
622 * @q_vector: structure containing interrupt and ring information
623 * @rx_ring: rx descriptor ring to transact packets on
624 * @budget: Total limit on number of packets to process
625 *
626 * This function provides a "bounce buffer" approach to Rx interrupt
627 * processing. The advantage to this is that on systems that have
628 * expensive overhead for IOMMU access this provides a means of avoiding
629 * it by maintaining the mapping of the page to the system.
630 *
631 * Returns amount of work completed.
632 **/
wx_clean_rx_irq(struct wx_q_vector * q_vector,struct wx_ring * rx_ring,int budget)633 static int wx_clean_rx_irq(struct wx_q_vector *q_vector,
634 struct wx_ring *rx_ring,
635 int budget)
636 {
637 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
638 u16 cleaned_count = wx_desc_unused(rx_ring);
639
640 do {
641 struct wx_rx_buffer *rx_buffer;
642 union wx_rx_desc *rx_desc;
643 struct sk_buff *skb;
644 int rx_buffer_pgcnt;
645
646 /* return some buffers to hardware, one at a time is too slow */
647 if (cleaned_count >= WX_RX_BUFFER_WRITE) {
648 wx_alloc_rx_buffers(rx_ring, cleaned_count);
649 cleaned_count = 0;
650 }
651
652 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean);
653 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD))
654 break;
655
656 /* This memory barrier is needed to keep us from reading
657 * any other fields out of the rx_desc until we know the
658 * descriptor has been written back
659 */
660 dma_rmb();
661
662 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt);
663
664 /* retrieve a buffer from the ring */
665 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc);
666
667 /* exit if we failed to retrieve a buffer */
668 if (!skb) {
669 rx_ring->rx_stats.alloc_rx_buff_failed++;
670 break;
671 }
672
673 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
674 cleaned_count++;
675
676 /* place incomplete frames back on ring for completion */
677 if (wx_is_non_eop(rx_ring, rx_desc, skb))
678 continue;
679
680 /* verify the packet layout is correct */
681 if (wx_cleanup_headers(rx_ring, rx_desc, skb))
682 continue;
683
684 /* probably a little skewed due to removing CRC */
685 total_rx_bytes += skb->len;
686
687 /* populate checksum, timestamp, VLAN, and protocol */
688 wx_process_skb_fields(rx_ring, rx_desc, skb);
689 napi_gro_receive(&q_vector->napi, skb);
690
691 /* update budget accounting */
692 total_rx_packets++;
693 } while (likely(total_rx_packets < budget));
694
695 u64_stats_update_begin(&rx_ring->syncp);
696 rx_ring->stats.packets += total_rx_packets;
697 rx_ring->stats.bytes += total_rx_bytes;
698 u64_stats_update_end(&rx_ring->syncp);
699 q_vector->rx.total_packets += total_rx_packets;
700 q_vector->rx.total_bytes += total_rx_bytes;
701
702 return total_rx_packets;
703 }
704
wx_txring_txq(const struct wx_ring * ring)705 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring)
706 {
707 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
708 }
709
710 /**
711 * wx_clean_tx_irq - Reclaim resources after transmit completes
712 * @q_vector: structure containing interrupt and ring information
713 * @tx_ring: tx ring to clean
714 * @napi_budget: Used to determine if we are in netpoll
715 **/
wx_clean_tx_irq(struct wx_q_vector * q_vector,struct wx_ring * tx_ring,int napi_budget)716 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector,
717 struct wx_ring *tx_ring, int napi_budget)
718 {
719 unsigned int budget = q_vector->wx->tx_work_limit;
720 unsigned int total_bytes = 0, total_packets = 0;
721 struct wx *wx = netdev_priv(tx_ring->netdev);
722 unsigned int i = tx_ring->next_to_clean;
723 struct wx_tx_buffer *tx_buffer;
724 union wx_tx_desc *tx_desc;
725
726 if (!netif_carrier_ok(tx_ring->netdev))
727 return true;
728
729 tx_buffer = &tx_ring->tx_buffer_info[i];
730 tx_desc = WX_TX_DESC(tx_ring, i);
731 i -= tx_ring->count;
732
733 do {
734 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch;
735
736 /* if next_to_watch is not set then there is no work pending */
737 if (!eop_desc)
738 break;
739
740 /* prevent any other reads prior to eop_desc */
741 smp_rmb();
742
743 /* if DD is not set pending work has not been completed */
744 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD)))
745 break;
746
747 /* clear next_to_watch to prevent false hangs */
748 tx_buffer->next_to_watch = NULL;
749
750 /* update the statistics for this packet */
751 total_bytes += tx_buffer->bytecount;
752 total_packets += tx_buffer->gso_segs;
753
754 /* schedule check for Tx timestamp */
755 if (unlikely(test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state)) &&
756 skb_shinfo(tx_buffer->skb)->tx_flags & SKBTX_IN_PROGRESS)
757 ptp_schedule_worker(wx->ptp_clock, 0);
758
759 /* free the skb */
760 napi_consume_skb(tx_buffer->skb, napi_budget);
761
762 /* unmap skb header data */
763 dma_unmap_single(tx_ring->dev,
764 dma_unmap_addr(tx_buffer, dma),
765 dma_unmap_len(tx_buffer, len),
766 DMA_TO_DEVICE);
767
768 /* clear tx_buffer data */
769 dma_unmap_len_set(tx_buffer, len, 0);
770
771 /* unmap remaining buffers */
772 while (tx_desc != eop_desc) {
773 tx_buffer++;
774 tx_desc++;
775 i++;
776 if (unlikely(!i)) {
777 i -= tx_ring->count;
778 tx_buffer = tx_ring->tx_buffer_info;
779 tx_desc = WX_TX_DESC(tx_ring, 0);
780 }
781
782 /* unmap any remaining paged data */
783 if (dma_unmap_len(tx_buffer, len)) {
784 dma_unmap_page(tx_ring->dev,
785 dma_unmap_addr(tx_buffer, dma),
786 dma_unmap_len(tx_buffer, len),
787 DMA_TO_DEVICE);
788 dma_unmap_len_set(tx_buffer, len, 0);
789 }
790 }
791
792 /* move us one more past the eop_desc for start of next pkt */
793 tx_buffer++;
794 tx_desc++;
795 i++;
796 if (unlikely(!i)) {
797 i -= tx_ring->count;
798 tx_buffer = tx_ring->tx_buffer_info;
799 tx_desc = WX_TX_DESC(tx_ring, 0);
800 }
801
802 /* issue prefetch for next Tx descriptor */
803 prefetch(tx_desc);
804
805 /* update budget accounting */
806 budget--;
807 } while (likely(budget));
808
809 i += tx_ring->count;
810 tx_ring->next_to_clean = i;
811 u64_stats_update_begin(&tx_ring->syncp);
812 tx_ring->stats.bytes += total_bytes;
813 tx_ring->stats.packets += total_packets;
814 u64_stats_update_end(&tx_ring->syncp);
815 q_vector->tx.total_bytes += total_bytes;
816 q_vector->tx.total_packets += total_packets;
817
818 netdev_tx_completed_queue(wx_txring_txq(tx_ring),
819 total_packets, total_bytes);
820
821 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
822 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
823 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
824 /* Make sure that anybody stopping the queue after this
825 * sees the new next_to_clean.
826 */
827 smp_mb();
828
829 if (__netif_subqueue_stopped(tx_ring->netdev,
830 tx_ring->queue_index) &&
831 netif_running(tx_ring->netdev)) {
832 netif_wake_subqueue(tx_ring->netdev,
833 tx_ring->queue_index);
834 ++tx_ring->tx_stats.restart_queue;
835 }
836 }
837
838 return !!budget;
839 }
840
841 /**
842 * wx_poll - NAPI polling RX/TX cleanup routine
843 * @napi: napi struct with our devices info in it
844 * @budget: amount of work driver is allowed to do this pass, in packets
845 *
846 * This function will clean all queues associated with a q_vector.
847 **/
wx_poll(struct napi_struct * napi,int budget)848 static int wx_poll(struct napi_struct *napi, int budget)
849 {
850 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi);
851 int per_ring_budget, work_done = 0;
852 struct wx *wx = q_vector->wx;
853 bool clean_complete = true;
854 struct wx_ring *ring;
855
856 wx_for_each_ring(ring, q_vector->tx) {
857 if (!wx_clean_tx_irq(q_vector, ring, budget))
858 clean_complete = false;
859 }
860
861 /* Exit if we are called by netpoll */
862 if (budget <= 0)
863 return budget;
864
865 /* attempt to distribute budget to each queue fairly, but don't allow
866 * the budget to go below 1 because we'll exit polling
867 */
868 if (q_vector->rx.count > 1)
869 per_ring_budget = max(budget / q_vector->rx.count, 1);
870 else
871 per_ring_budget = budget;
872
873 wx_for_each_ring(ring, q_vector->rx) {
874 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget);
875
876 work_done += cleaned;
877 if (cleaned >= per_ring_budget)
878 clean_complete = false;
879 }
880
881 /* If all work not completed, return budget and keep polling */
882 if (!clean_complete)
883 return budget;
884
885 /* all work done, exit the polling mode */
886 if (likely(napi_complete_done(napi, work_done))) {
887 if (netif_running(wx->netdev))
888 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx));
889 }
890
891 return min(work_done, budget - 1);
892 }
893
wx_maybe_stop_tx(struct wx_ring * tx_ring,u16 size)894 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size)
895 {
896 if (likely(wx_desc_unused(tx_ring) >= size))
897 return 0;
898
899 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
900
901 /* For the next check */
902 smp_mb();
903
904 /* We need to check again in a case another CPU has just
905 * made room available.
906 */
907 if (likely(wx_desc_unused(tx_ring) < size))
908 return -EBUSY;
909
910 /* A reprieve! - use start_queue because it doesn't call schedule */
911 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
912 ++tx_ring->tx_stats.restart_queue;
913
914 return 0;
915 }
916
wx_tx_cmd_type(u32 tx_flags)917 static u32 wx_tx_cmd_type(u32 tx_flags)
918 {
919 /* set type for advanced descriptor with frame checksum insertion */
920 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS;
921
922 /* set HW vlan bit if vlan is present */
923 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE);
924 /* set segmentation enable bits for TSO/FSO */
925 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE);
926 /* set timestamp bit if present */
927 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP);
928 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC);
929
930 return cmd_type;
931 }
932
wx_tx_olinfo_status(union wx_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)933 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc,
934 u32 tx_flags, unsigned int paylen)
935 {
936 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT;
937
938 /* enable L4 checksum for TSO and TX checksum offload */
939 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS);
940 /* enable IPv4 checksum for TSO */
941 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS);
942 /* enable outer IPv4 checksum for TSO */
943 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4,
944 WX_TXD_EIPCS);
945 /* Check Context must be set if Tx switch is enabled, which it
946 * always is for case where virtual functions are running
947 */
948 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC);
949 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC,
950 WX_TXD_IPSEC);
951 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
952 }
953
wx_tx_map(struct wx_ring * tx_ring,struct wx_tx_buffer * first,const u8 hdr_len)954 static int wx_tx_map(struct wx_ring *tx_ring,
955 struct wx_tx_buffer *first,
956 const u8 hdr_len)
957 {
958 struct sk_buff *skb = first->skb;
959 struct wx_tx_buffer *tx_buffer;
960 u32 tx_flags = first->tx_flags;
961 u16 i = tx_ring->next_to_use;
962 unsigned int data_len, size;
963 union wx_tx_desc *tx_desc;
964 skb_frag_t *frag;
965 dma_addr_t dma;
966 u32 cmd_type;
967
968 cmd_type = wx_tx_cmd_type(tx_flags);
969 tx_desc = WX_TX_DESC(tx_ring, i);
970 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
971
972 size = skb_headlen(skb);
973 data_len = skb->data_len;
974 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
975
976 tx_buffer = first;
977
978 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
979 if (dma_mapping_error(tx_ring->dev, dma))
980 goto dma_error;
981
982 /* record length, and DMA address */
983 dma_unmap_len_set(tx_buffer, len, size);
984 dma_unmap_addr_set(tx_buffer, dma, dma);
985
986 tx_desc->read.buffer_addr = cpu_to_le64(dma);
987
988 while (unlikely(size > WX_MAX_DATA_PER_TXD)) {
989 tx_desc->read.cmd_type_len =
990 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD);
991
992 i++;
993 tx_desc++;
994 if (i == tx_ring->count) {
995 tx_desc = WX_TX_DESC(tx_ring, 0);
996 i = 0;
997 }
998 tx_desc->read.olinfo_status = 0;
999
1000 dma += WX_MAX_DATA_PER_TXD;
1001 size -= WX_MAX_DATA_PER_TXD;
1002
1003 tx_desc->read.buffer_addr = cpu_to_le64(dma);
1004 }
1005
1006 if (likely(!data_len))
1007 break;
1008
1009 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
1010
1011 i++;
1012 tx_desc++;
1013 if (i == tx_ring->count) {
1014 tx_desc = WX_TX_DESC(tx_ring, 0);
1015 i = 0;
1016 }
1017 tx_desc->read.olinfo_status = 0;
1018
1019 size = skb_frag_size(frag);
1020
1021 data_len -= size;
1022
1023 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1024 DMA_TO_DEVICE);
1025
1026 tx_buffer = &tx_ring->tx_buffer_info[i];
1027 }
1028
1029 /* write last descriptor with RS and EOP bits */
1030 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS;
1031 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1032
1033 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount);
1034
1035 /* set the timestamp */
1036 first->time_stamp = jiffies;
1037 skb_tx_timestamp(skb);
1038
1039 /* Force memory writes to complete before letting h/w know there
1040 * are new descriptors to fetch. (Only applicable for weak-ordered
1041 * memory model archs, such as IA-64).
1042 *
1043 * We also need this memory barrier to make certain all of the
1044 * status bits have been updated before next_to_watch is written.
1045 */
1046 wmb();
1047
1048 /* set next_to_watch value indicating a packet is present */
1049 first->next_to_watch = tx_desc;
1050
1051 i++;
1052 if (i == tx_ring->count)
1053 i = 0;
1054
1055 tx_ring->next_to_use = i;
1056
1057 wx_maybe_stop_tx(tx_ring, DESC_NEEDED);
1058
1059 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more())
1060 writel(i, tx_ring->tail);
1061
1062 return 0;
1063 dma_error:
1064 dev_err(tx_ring->dev, "TX DMA map failed\n");
1065
1066 /* clear dma mappings for failed tx_buffer_info map */
1067 for (;;) {
1068 tx_buffer = &tx_ring->tx_buffer_info[i];
1069 if (dma_unmap_len(tx_buffer, len))
1070 dma_unmap_page(tx_ring->dev,
1071 dma_unmap_addr(tx_buffer, dma),
1072 dma_unmap_len(tx_buffer, len),
1073 DMA_TO_DEVICE);
1074 dma_unmap_len_set(tx_buffer, len, 0);
1075 if (tx_buffer == first)
1076 break;
1077 if (i == 0)
1078 i += tx_ring->count;
1079 i--;
1080 }
1081
1082 dev_kfree_skb_any(first->skb);
1083 first->skb = NULL;
1084
1085 tx_ring->next_to_use = i;
1086
1087 return -ENOMEM;
1088 }
1089
wx_tx_ctxtdesc(struct wx_ring * tx_ring,u32 vlan_macip_lens,u32 fcoe_sof_eof,u32 type_tucmd,u32 mss_l4len_idx)1090 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens,
1091 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
1092 {
1093 struct wx_tx_context_desc *context_desc;
1094 u16 i = tx_ring->next_to_use;
1095
1096 context_desc = WX_TX_CTXTDESC(tx_ring, i);
1097 i++;
1098 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1099
1100 /* set bits to identify this as an advanced context descriptor */
1101 type_tucmd |= WX_TXD_DTYP_CTXT;
1102 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
1103 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
1104 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
1105 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
1106 }
1107
1108 union network_header {
1109 struct iphdr *ipv4;
1110 struct ipv6hdr *ipv6;
1111 void *raw;
1112 };
1113
wx_encode_tx_desc_ptype(const struct wx_tx_buffer * first)1114 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first)
1115 {
1116 u8 tun_prot = 0, l4_prot = 0, ptype = 0;
1117 struct sk_buff *skb = first->skb;
1118 unsigned char *exthdr, *l4_hdr;
1119 __be16 frag_off;
1120
1121 if (skb->encapsulation) {
1122 union network_header hdr;
1123
1124 switch (first->protocol) {
1125 case htons(ETH_P_IP):
1126 tun_prot = ip_hdr(skb)->protocol;
1127 ptype = WX_PTYPE_TUN_IPV4;
1128 break;
1129 case htons(ETH_P_IPV6):
1130 l4_hdr = skb_transport_header(skb);
1131 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr);
1132 tun_prot = ipv6_hdr(skb)->nexthdr;
1133 if (l4_hdr != exthdr)
1134 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off);
1135 ptype = WX_PTYPE_TUN_IPV6;
1136 break;
1137 default:
1138 return ptype;
1139 }
1140
1141 if (tun_prot == IPPROTO_IPIP || tun_prot == IPPROTO_IPV6) {
1142 hdr.raw = (void *)inner_ip_hdr(skb);
1143 ptype |= WX_PTYPE_PKT_IPIP;
1144 } else if (tun_prot == IPPROTO_UDP) {
1145 hdr.raw = (void *)inner_ip_hdr(skb);
1146 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1147 skb->inner_protocol != htons(ETH_P_TEB)) {
1148 ptype |= WX_PTYPE_PKT_IG;
1149 } else {
1150 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1151 == htons(ETH_P_8021Q))
1152 ptype |= WX_PTYPE_PKT_IGMV;
1153 else
1154 ptype |= WX_PTYPE_PKT_IGM;
1155 }
1156
1157 } else if (tun_prot == IPPROTO_GRE) {
1158 hdr.raw = (void *)inner_ip_hdr(skb);
1159 if (skb->inner_protocol == htons(ETH_P_IP) ||
1160 skb->inner_protocol == htons(ETH_P_IPV6)) {
1161 ptype |= WX_PTYPE_PKT_IG;
1162 } else {
1163 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1164 == htons(ETH_P_8021Q))
1165 ptype |= WX_PTYPE_PKT_IGMV;
1166 else
1167 ptype |= WX_PTYPE_PKT_IGM;
1168 }
1169 } else {
1170 return ptype;
1171 }
1172
1173 switch (hdr.ipv4->version) {
1174 case IPVERSION:
1175 l4_prot = hdr.ipv4->protocol;
1176 break;
1177 case 6:
1178 l4_hdr = skb_inner_transport_header(skb);
1179 exthdr = skb_inner_network_header(skb) + sizeof(struct ipv6hdr);
1180 l4_prot = inner_ipv6_hdr(skb)->nexthdr;
1181 if (l4_hdr != exthdr)
1182 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off);
1183 ptype |= WX_PTYPE_PKT_IPV6;
1184 break;
1185 default:
1186 return ptype;
1187 }
1188 } else {
1189 switch (first->protocol) {
1190 case htons(ETH_P_IP):
1191 l4_prot = ip_hdr(skb)->protocol;
1192 ptype = WX_PTYPE_PKT_IP;
1193 break;
1194 case htons(ETH_P_IPV6):
1195 l4_hdr = skb_transport_header(skb);
1196 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr);
1197 l4_prot = ipv6_hdr(skb)->nexthdr;
1198 if (l4_hdr != exthdr)
1199 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off);
1200 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6;
1201 break;
1202 default:
1203 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC;
1204 }
1205 }
1206 switch (l4_prot) {
1207 case IPPROTO_TCP:
1208 ptype |= WX_PTYPE_TYP_TCP;
1209 break;
1210 case IPPROTO_UDP:
1211 ptype |= WX_PTYPE_TYP_UDP;
1212 break;
1213 case IPPROTO_SCTP:
1214 ptype |= WX_PTYPE_TYP_SCTP;
1215 break;
1216 default:
1217 ptype |= WX_PTYPE_TYP_IP;
1218 break;
1219 }
1220
1221 return ptype;
1222 }
1223
wx_tso(struct wx_ring * tx_ring,struct wx_tx_buffer * first,u8 * hdr_len,u8 ptype)1224 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1225 u8 *hdr_len, u8 ptype)
1226 {
1227 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1228 struct net_device *netdev = tx_ring->netdev;
1229 u32 l4len, tunhdr_eiplen_tunlen = 0;
1230 struct sk_buff *skb = first->skb;
1231 bool enc = skb->encapsulation;
1232 struct ipv6hdr *ipv6h;
1233 struct tcphdr *tcph;
1234 struct iphdr *iph;
1235 u8 tun_prot = 0;
1236 int err;
1237
1238 if (skb->ip_summed != CHECKSUM_PARTIAL)
1239 return 0;
1240
1241 if (!skb_is_gso(skb))
1242 return 0;
1243
1244 err = skb_cow_head(skb, 0);
1245 if (err < 0)
1246 return err;
1247
1248 /* indicates the inner headers in the skbuff are valid. */
1249 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb);
1250 if (iph->version == 4) {
1251 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1252 iph->tot_len = 0;
1253 iph->check = 0;
1254 tcph->check = ~csum_tcpudp_magic(iph->saddr,
1255 iph->daddr, 0,
1256 IPPROTO_TCP, 0);
1257 first->tx_flags |= WX_TX_FLAGS_TSO |
1258 WX_TX_FLAGS_CSUM |
1259 WX_TX_FLAGS_IPV4 |
1260 WX_TX_FLAGS_CC;
1261 } else if (iph->version == 6 && skb_is_gso_v6(skb)) {
1262 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1263 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1264 ipv6h->payload_len = 0;
1265 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr,
1266 &ipv6h->daddr, 0,
1267 IPPROTO_TCP, 0);
1268 first->tx_flags |= WX_TX_FLAGS_TSO |
1269 WX_TX_FLAGS_CSUM |
1270 WX_TX_FLAGS_CC;
1271 }
1272
1273 /* compute header lengths */
1274 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1275 *hdr_len = enc ? skb_inner_transport_offset(skb) :
1276 skb_transport_offset(skb);
1277 *hdr_len += l4len;
1278
1279 /* update gso size and bytecount with header size */
1280 first->gso_segs = skb_shinfo(skb)->gso_segs;
1281 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1282
1283 /* mss_l4len_id: use 0 as index for TSO */
1284 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT;
1285 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT;
1286
1287 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
1288 if (enc) {
1289 unsigned char *exthdr, *l4_hdr;
1290 __be16 frag_off;
1291
1292 switch (first->protocol) {
1293 case htons(ETH_P_IP):
1294 tun_prot = ip_hdr(skb)->protocol;
1295 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4;
1296 break;
1297 case htons(ETH_P_IPV6):
1298 l4_hdr = skb_transport_header(skb);
1299 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr);
1300 tun_prot = ipv6_hdr(skb)->nexthdr;
1301 if (l4_hdr != exthdr)
1302 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off);
1303 break;
1304 default:
1305 break;
1306 }
1307 switch (tun_prot) {
1308 case IPPROTO_UDP:
1309 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1310 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1311 WX_TXD_OUTER_IPLEN_SHIFT) |
1312 (((skb_inner_mac_header(skb) -
1313 skb_transport_header(skb)) >> 1) <<
1314 WX_TXD_TUNNEL_LEN_SHIFT);
1315 break;
1316 case IPPROTO_GRE:
1317 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1318 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1319 WX_TXD_OUTER_IPLEN_SHIFT) |
1320 (((skb_inner_mac_header(skb) -
1321 skb_transport_header(skb)) >> 1) <<
1322 WX_TXD_TUNNEL_LEN_SHIFT);
1323 break;
1324 case IPPROTO_IPIP:
1325 case IPPROTO_IPV6:
1326 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1327 (char *)ip_hdr(skb)) >> 2) <<
1328 WX_TXD_OUTER_IPLEN_SHIFT;
1329 break;
1330 default:
1331 break;
1332 }
1333 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1;
1334 } else {
1335 vlan_macip_lens = skb_network_header_len(skb) >> 1;
1336 }
1337
1338 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT;
1339 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1340
1341 type_tucmd = ptype << 24;
1342 if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1343 netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1344 type_tucmd |= WX_SET_FLAG(first->tx_flags,
1345 WX_TX_FLAGS_HW_VLAN,
1346 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1347 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1348 type_tucmd, mss_l4len_idx);
1349
1350 return 1;
1351 }
1352
wx_tx_csum(struct wx_ring * tx_ring,struct wx_tx_buffer * first,u8 ptype)1353 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1354 u8 ptype)
1355 {
1356 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0;
1357 struct net_device *netdev = tx_ring->netdev;
1358 u32 mss_l4len_idx = 0, type_tucmd;
1359 struct sk_buff *skb = first->skb;
1360 u8 tun_prot = 0;
1361
1362 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1363 csum_failed:
1364 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) &&
1365 !(first->tx_flags & WX_TX_FLAGS_CC))
1366 return;
1367 vlan_macip_lens = skb_network_offset(skb) <<
1368 WX_TXD_MACLEN_SHIFT;
1369 } else {
1370 unsigned char *exthdr, *l4_hdr;
1371 __be16 frag_off;
1372 u8 l4_prot = 0;
1373 union {
1374 struct iphdr *ipv4;
1375 struct ipv6hdr *ipv6;
1376 u8 *raw;
1377 } network_hdr;
1378 union {
1379 struct tcphdr *tcphdr;
1380 u8 *raw;
1381 } transport_hdr;
1382
1383 if (skb->encapsulation) {
1384 network_hdr.raw = skb_inner_network_header(skb);
1385 transport_hdr.raw = skb_inner_transport_header(skb);
1386 vlan_macip_lens = skb_network_offset(skb) <<
1387 WX_TXD_MACLEN_SHIFT;
1388 switch (first->protocol) {
1389 case htons(ETH_P_IP):
1390 tun_prot = ip_hdr(skb)->protocol;
1391 break;
1392 case htons(ETH_P_IPV6):
1393 l4_hdr = skb_transport_header(skb);
1394 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr);
1395 tun_prot = ipv6_hdr(skb)->nexthdr;
1396 if (l4_hdr != exthdr)
1397 ipv6_skip_exthdr(skb, exthdr - skb->data,
1398 &tun_prot, &frag_off);
1399 break;
1400 default:
1401 return;
1402 }
1403 switch (tun_prot) {
1404 case IPPROTO_UDP:
1405 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1406 tunhdr_eiplen_tunlen |=
1407 ((skb_network_header_len(skb) >> 2) <<
1408 WX_TXD_OUTER_IPLEN_SHIFT) |
1409 (((skb_inner_mac_header(skb) -
1410 skb_transport_header(skb)) >> 1) <<
1411 WX_TXD_TUNNEL_LEN_SHIFT);
1412 break;
1413 case IPPROTO_GRE:
1414 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1415 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1416 WX_TXD_OUTER_IPLEN_SHIFT) |
1417 (((skb_inner_mac_header(skb) -
1418 skb_transport_header(skb)) >> 1) <<
1419 WX_TXD_TUNNEL_LEN_SHIFT);
1420 break;
1421 case IPPROTO_IPIP:
1422 case IPPROTO_IPV6:
1423 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1424 (char *)ip_hdr(skb)) >> 2) <<
1425 WX_TXD_OUTER_IPLEN_SHIFT;
1426 break;
1427 default:
1428 break;
1429 }
1430
1431 } else {
1432 network_hdr.raw = skb_network_header(skb);
1433 transport_hdr.raw = skb_transport_header(skb);
1434 vlan_macip_lens = skb_network_offset(skb) <<
1435 WX_TXD_MACLEN_SHIFT;
1436 }
1437
1438 switch (network_hdr.ipv4->version) {
1439 case IPVERSION:
1440 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1441 l4_prot = network_hdr.ipv4->protocol;
1442 break;
1443 case 6:
1444 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1445 exthdr = network_hdr.raw + sizeof(struct ipv6hdr);
1446 l4_prot = network_hdr.ipv6->nexthdr;
1447 if (transport_hdr.raw != exthdr)
1448 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off);
1449 break;
1450 default:
1451 break;
1452 }
1453
1454 switch (l4_prot) {
1455 case IPPROTO_TCP:
1456 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
1457 WX_TXD_L4LEN_SHIFT;
1458 break;
1459 case IPPROTO_SCTP:
1460 mss_l4len_idx = sizeof(struct sctphdr) <<
1461 WX_TXD_L4LEN_SHIFT;
1462 break;
1463 case IPPROTO_UDP:
1464 mss_l4len_idx = sizeof(struct udphdr) <<
1465 WX_TXD_L4LEN_SHIFT;
1466 break;
1467 default:
1468 skb_checksum_help(skb);
1469 goto csum_failed;
1470 }
1471
1472 /* update TX checksum flag */
1473 first->tx_flags |= WX_TX_FLAGS_CSUM;
1474 }
1475 first->tx_flags |= WX_TX_FLAGS_CC;
1476 /* vlan_macip_lens: MACLEN, VLAN tag */
1477 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1478
1479 type_tucmd = ptype << 24;
1480 if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1481 netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1482 type_tucmd |= WX_SET_FLAG(first->tx_flags,
1483 WX_TX_FLAGS_HW_VLAN,
1484 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1485 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1486 type_tucmd, mss_l4len_idx);
1487 }
1488
wx_xmit_frame_ring(struct sk_buff * skb,struct wx_ring * tx_ring)1489 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb,
1490 struct wx_ring *tx_ring)
1491 {
1492 struct wx *wx = netdev_priv(tx_ring->netdev);
1493 u16 count = TXD_USE_COUNT(skb_headlen(skb));
1494 struct wx_tx_buffer *first;
1495 u8 hdr_len = 0, ptype;
1496 unsigned short f;
1497 u32 tx_flags = 0;
1498 int tso;
1499
1500 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD,
1501 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD,
1502 * + 2 desc gap to keep tail from touching head,
1503 * + 1 desc for context descriptor,
1504 * otherwise try next time
1505 */
1506 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1507 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->
1508 frags[f]));
1509
1510 if (wx_maybe_stop_tx(tx_ring, count + 3)) {
1511 tx_ring->tx_stats.tx_busy++;
1512 return NETDEV_TX_BUSY;
1513 }
1514
1515 /* record the location of the first descriptor for this packet */
1516 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1517 first->skb = skb;
1518 first->bytecount = skb->len;
1519 first->gso_segs = 1;
1520
1521 /* if we have a HW VLAN tag being added default to the HW one */
1522 if (skb_vlan_tag_present(skb)) {
1523 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT;
1524 tx_flags |= WX_TX_FLAGS_HW_VLAN;
1525 }
1526
1527 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1528 wx->ptp_clock) {
1529 if (wx->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
1530 !test_and_set_bit_lock(WX_STATE_PTP_TX_IN_PROGRESS,
1531 wx->state)) {
1532 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1533 tx_flags |= WX_TX_FLAGS_TSTAMP;
1534 wx->ptp_tx_skb = skb_get(skb);
1535 wx->ptp_tx_start = jiffies;
1536 } else {
1537 wx->tx_hwtstamp_skipped++;
1538 }
1539 }
1540
1541 /* record initial flags and protocol */
1542 first->tx_flags = tx_flags;
1543 first->protocol = vlan_get_protocol(skb);
1544
1545 ptype = wx_encode_tx_desc_ptype(first);
1546
1547 tso = wx_tso(tx_ring, first, &hdr_len, ptype);
1548 if (tso < 0)
1549 goto out_drop;
1550 else if (!tso)
1551 wx_tx_csum(tx_ring, first, ptype);
1552
1553 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate)
1554 wx->atr(tx_ring, first, ptype);
1555
1556 if (wx_tx_map(tx_ring, first, hdr_len))
1557 goto cleanup_tx_tstamp;
1558
1559 return NETDEV_TX_OK;
1560 out_drop:
1561 dev_kfree_skb_any(first->skb);
1562 first->skb = NULL;
1563 cleanup_tx_tstamp:
1564 if (unlikely(tx_flags & WX_TX_FLAGS_TSTAMP)) {
1565 dev_kfree_skb_any(wx->ptp_tx_skb);
1566 wx->ptp_tx_skb = NULL;
1567 wx->tx_hwtstamp_errors++;
1568 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state);
1569 }
1570
1571 return NETDEV_TX_OK;
1572 }
1573
wx_xmit_frame(struct sk_buff * skb,struct net_device * netdev)1574 netdev_tx_t wx_xmit_frame(struct sk_buff *skb,
1575 struct net_device *netdev)
1576 {
1577 unsigned int r_idx = skb->queue_mapping;
1578 struct wx *wx = netdev_priv(netdev);
1579 struct wx_ring *tx_ring;
1580
1581 if (!netif_carrier_ok(netdev)) {
1582 dev_kfree_skb_any(skb);
1583 return NETDEV_TX_OK;
1584 }
1585
1586 /* The minimum packet size for olinfo paylen is 17 so pad the skb
1587 * in order to meet this minimum size requirement.
1588 */
1589 if (skb_put_padto(skb, 17))
1590 return NETDEV_TX_OK;
1591
1592 if (r_idx >= wx->num_tx_queues)
1593 r_idx = r_idx % wx->num_tx_queues;
1594 tx_ring = wx->tx_ring[r_idx];
1595
1596 return wx_xmit_frame_ring(skb, tx_ring);
1597 }
1598 EXPORT_SYMBOL(wx_xmit_frame);
1599
wx_napi_enable_all(struct wx * wx)1600 void wx_napi_enable_all(struct wx *wx)
1601 {
1602 struct wx_q_vector *q_vector;
1603 int q_idx;
1604
1605 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1606 q_vector = wx->q_vector[q_idx];
1607 napi_enable(&q_vector->napi);
1608 }
1609 }
1610 EXPORT_SYMBOL(wx_napi_enable_all);
1611
wx_napi_disable_all(struct wx * wx)1612 void wx_napi_disable_all(struct wx *wx)
1613 {
1614 struct wx_q_vector *q_vector;
1615 int q_idx;
1616
1617 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1618 q_vector = wx->q_vector[q_idx];
1619 napi_disable(&q_vector->napi);
1620 }
1621 }
1622 EXPORT_SYMBOL(wx_napi_disable_all);
1623
wx_set_vmdq_queues(struct wx * wx)1624 static bool wx_set_vmdq_queues(struct wx *wx)
1625 {
1626 u16 vmdq_i = wx->ring_feature[RING_F_VMDQ].limit;
1627 u16 rss_i = wx->ring_feature[RING_F_RSS].limit;
1628 u16 rss_m = WX_RSS_DISABLED_MASK;
1629 u16 vmdq_m = 0;
1630
1631 /* only proceed if VMDq is enabled */
1632 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags))
1633 return false;
1634 /* Add starting offset to total pool count */
1635 vmdq_i += wx->ring_feature[RING_F_VMDQ].offset;
1636
1637 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) {
1638 /* double check we are limited to maximum pools */
1639 vmdq_i = min_t(u16, 64, vmdq_i);
1640
1641 /* 64 pool mode with 2 queues per pool, or
1642 * 16/32/64 pool mode with 1 queue per pool
1643 */
1644 if (vmdq_i > 32 || rss_i < 4) {
1645 vmdq_m = WX_VMDQ_2Q_MASK;
1646 rss_m = WX_RSS_2Q_MASK;
1647 rss_i = min_t(u16, rss_i, 2);
1648 /* 32 pool mode with 4 queues per pool */
1649 } else {
1650 vmdq_m = WX_VMDQ_4Q_MASK;
1651 rss_m = WX_RSS_4Q_MASK;
1652 rss_i = 4;
1653 }
1654 } else {
1655 /* double check we are limited to maximum pools */
1656 vmdq_i = min_t(u16, 8, vmdq_i);
1657
1658 /* when VMDQ on, disable RSS */
1659 rss_i = 1;
1660 }
1661
1662 /* remove the starting offset from the pool count */
1663 vmdq_i -= wx->ring_feature[RING_F_VMDQ].offset;
1664
1665 /* save features for later use */
1666 wx->ring_feature[RING_F_VMDQ].indices = vmdq_i;
1667 wx->ring_feature[RING_F_VMDQ].mask = vmdq_m;
1668
1669 /* limit RSS based on user input and save for later use */
1670 wx->ring_feature[RING_F_RSS].indices = rss_i;
1671 wx->ring_feature[RING_F_RSS].mask = rss_m;
1672
1673 wx->queues_per_pool = rss_i;/*maybe same to num_rx_queues_per_pool*/
1674 wx->num_rx_pools = vmdq_i;
1675 wx->num_rx_queues_per_pool = rss_i;
1676
1677 wx->num_rx_queues = vmdq_i * rss_i;
1678 wx->num_tx_queues = vmdq_i * rss_i;
1679
1680 return true;
1681 }
1682
1683 /**
1684 * wx_set_rss_queues: Allocate queues for RSS
1685 * @wx: board private structure to initialize
1686 *
1687 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
1688 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
1689 *
1690 **/
wx_set_rss_queues(struct wx * wx)1691 static void wx_set_rss_queues(struct wx *wx)
1692 {
1693 struct wx_ring_feature *f;
1694
1695 /* set mask for 16 queue limit of RSS */
1696 f = &wx->ring_feature[RING_F_RSS];
1697 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags))
1698 f->mask = WX_RSS_64Q_MASK;
1699 else
1700 f->mask = WX_RSS_8Q_MASK;
1701 f->indices = f->limit;
1702
1703 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)))
1704 goto out;
1705
1706 clear_bit(WX_FLAG_FDIR_HASH, wx->flags);
1707
1708 wx->ring_feature[RING_F_FDIR].indices = 1;
1709 /* Use Flow Director in addition to RSS to ensure the best
1710 * distribution of flows across cores, even when an FDIR flow
1711 * isn't matched.
1712 */
1713 if (f->indices > 1) {
1714 f = &wx->ring_feature[RING_F_FDIR];
1715
1716 f->indices = f->limit;
1717
1718 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags)))
1719 set_bit(WX_FLAG_FDIR_HASH, wx->flags);
1720 }
1721
1722 out:
1723 wx->num_rx_queues = f->indices;
1724 wx->num_tx_queues = f->indices;
1725 }
1726
wx_set_num_queues(struct wx * wx)1727 static void wx_set_num_queues(struct wx *wx)
1728 {
1729 /* Start with base case */
1730 wx->num_rx_queues = 1;
1731 wx->num_tx_queues = 1;
1732 wx->queues_per_pool = 1;
1733
1734 if (wx_set_vmdq_queues(wx))
1735 return;
1736
1737 wx_set_rss_queues(wx);
1738 }
1739
1740 /**
1741 * wx_acquire_msix_vectors - acquire MSI-X vectors
1742 * @wx: board private structure
1743 *
1744 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
1745 * return a negative error code if unable to acquire MSI-X vectors for any
1746 * reason.
1747 */
wx_acquire_msix_vectors(struct wx * wx)1748 static int wx_acquire_msix_vectors(struct wx *wx)
1749 {
1750 struct irq_affinity affd = { .post_vectors = 1 };
1751 int nvecs, i;
1752
1753 /* We start by asking for one vector per queue pair */
1754 nvecs = max(wx->num_rx_queues, wx->num_tx_queues);
1755 nvecs = min_t(int, nvecs, num_online_cpus());
1756 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors);
1757
1758 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry),
1759 GFP_KERNEL);
1760 if (!wx->msix_q_entries)
1761 return -ENOMEM;
1762
1763 /* One for non-queue interrupts */
1764 nvecs += 1;
1765
1766 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry),
1767 GFP_KERNEL);
1768 if (!wx->msix_entry) {
1769 kfree(wx->msix_q_entries);
1770 wx->msix_q_entries = NULL;
1771 return -ENOMEM;
1772 }
1773
1774 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs,
1775 nvecs,
1776 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
1777 &affd);
1778 if (nvecs < 0) {
1779 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs);
1780 kfree(wx->msix_q_entries);
1781 wx->msix_q_entries = NULL;
1782 kfree(wx->msix_entry);
1783 wx->msix_entry = NULL;
1784 return nvecs;
1785 }
1786
1787 nvecs -= 1;
1788 for (i = 0; i < nvecs; i++) {
1789 wx->msix_q_entries[i].entry = i;
1790 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i);
1791 }
1792
1793 wx->num_q_vectors = nvecs;
1794
1795 wx->msix_entry->entry = nvecs;
1796 wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs);
1797
1798 if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) {
1799 wx->msix_entry->entry = 0;
1800 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0);
1801 wx->msix_q_entries[0].entry = 0;
1802 wx->msix_q_entries[0].vector = pci_irq_vector(wx->pdev, 1);
1803 }
1804
1805 return 0;
1806 }
1807
1808 /**
1809 * wx_set_interrupt_capability - set MSI-X or MSI if supported
1810 * @wx: board private structure to initialize
1811 *
1812 * Attempt to configure the interrupts using the best available
1813 * capabilities of the hardware and the kernel.
1814 **/
wx_set_interrupt_capability(struct wx * wx)1815 static int wx_set_interrupt_capability(struct wx *wx)
1816 {
1817 struct pci_dev *pdev = wx->pdev;
1818 int nvecs, ret;
1819
1820 /* We will try to get MSI-X interrupts first */
1821 ret = wx_acquire_msix_vectors(wx);
1822 if (ret == 0 || (ret == -ENOMEM))
1823 return ret;
1824
1825 /* Disable VMDq support */
1826 dev_warn(&wx->pdev->dev, "Disabling VMQQ support\n");
1827 clear_bit(WX_FLAG_VMDQ_ENABLED, wx->flags);
1828
1829 /* Disable RSS */
1830 dev_warn(&wx->pdev->dev, "Disabling RSS support\n");
1831 wx->ring_feature[RING_F_RSS].limit = 1;
1832
1833 wx_set_num_queues(wx);
1834
1835 /* minmum one for queue, one for misc*/
1836 nvecs = 1;
1837 nvecs = pci_alloc_irq_vectors(pdev, nvecs,
1838 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX);
1839 if (nvecs == 1) {
1840 if (pdev->msi_enabled)
1841 wx_err(wx, "Fallback to MSI.\n");
1842 else
1843 wx_err(wx, "Fallback to INTx.\n");
1844 } else {
1845 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs);
1846 return nvecs;
1847 }
1848
1849 pdev->irq = pci_irq_vector(pdev, 0);
1850 wx->num_q_vectors = 1;
1851
1852 return 0;
1853 }
1854
wx_cache_ring_vmdq(struct wx * wx)1855 static bool wx_cache_ring_vmdq(struct wx *wx)
1856 {
1857 struct wx_ring_feature *vmdq = &wx->ring_feature[RING_F_VMDQ];
1858 struct wx_ring_feature *rss = &wx->ring_feature[RING_F_RSS];
1859 u16 reg_idx;
1860 int i;
1861
1862 /* only proceed if VMDq is enabled */
1863 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags))
1864 return false;
1865
1866 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) {
1867 /* start at VMDq register offset for SR-IOV enabled setups */
1868 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
1869 for (i = 0; i < wx->num_rx_queues; i++, reg_idx++) {
1870 /* If we are greater than indices move to next pool */
1871 if ((reg_idx & ~vmdq->mask) >= rss->indices)
1872 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
1873 wx->rx_ring[i]->reg_idx = reg_idx;
1874 }
1875 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
1876 for (i = 0; i < wx->num_tx_queues; i++, reg_idx++) {
1877 /* If we are greater than indices move to next pool */
1878 if ((reg_idx & rss->mask) >= rss->indices)
1879 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
1880 wx->tx_ring[i]->reg_idx = reg_idx;
1881 }
1882 } else {
1883 /* start at VMDq register offset for SR-IOV enabled setups */
1884 reg_idx = vmdq->offset;
1885 for (i = 0; i < wx->num_rx_queues; i++)
1886 /* If we are greater than indices move to next pool */
1887 wx->rx_ring[i]->reg_idx = reg_idx + i;
1888
1889 reg_idx = vmdq->offset;
1890 for (i = 0; i < wx->num_tx_queues; i++)
1891 /* If we are greater than indices move to next pool */
1892 wx->tx_ring[i]->reg_idx = reg_idx + i;
1893 }
1894
1895 return true;
1896 }
1897
1898 /**
1899 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS
1900 * @wx: board private structure to initialize
1901 *
1902 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV.
1903 *
1904 **/
wx_cache_ring_rss(struct wx * wx)1905 static void wx_cache_ring_rss(struct wx *wx)
1906 {
1907 u16 i;
1908
1909 if (wx_cache_ring_vmdq(wx))
1910 return;
1911
1912 for (i = 0; i < wx->num_rx_queues; i++)
1913 wx->rx_ring[i]->reg_idx = i;
1914
1915 for (i = 0; i < wx->num_tx_queues; i++)
1916 wx->tx_ring[i]->reg_idx = i;
1917 }
1918
wx_add_ring(struct wx_ring * ring,struct wx_ring_container * head)1919 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head)
1920 {
1921 ring->next = head->ring;
1922 head->ring = ring;
1923 head->count++;
1924 }
1925
1926 /**
1927 * wx_alloc_q_vector - Allocate memory for a single interrupt vector
1928 * @wx: board private structure to initialize
1929 * @v_count: q_vectors allocated on wx, used for ring interleaving
1930 * @v_idx: index of vector in wx struct
1931 * @txr_count: total number of Tx rings to allocate
1932 * @txr_idx: index of first Tx ring to allocate
1933 * @rxr_count: total number of Rx rings to allocate
1934 * @rxr_idx: index of first Rx ring to allocate
1935 *
1936 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1937 **/
wx_alloc_q_vector(struct wx * wx,unsigned int v_count,unsigned int v_idx,unsigned int txr_count,unsigned int txr_idx,unsigned int rxr_count,unsigned int rxr_idx)1938 static int wx_alloc_q_vector(struct wx *wx,
1939 unsigned int v_count, unsigned int v_idx,
1940 unsigned int txr_count, unsigned int txr_idx,
1941 unsigned int rxr_count, unsigned int rxr_idx)
1942 {
1943 struct wx_q_vector *q_vector;
1944 int ring_count, default_itr;
1945 struct wx_ring *ring;
1946
1947 /* note this will allocate space for the ring structure as well! */
1948 ring_count = txr_count + rxr_count;
1949
1950 q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
1951 GFP_KERNEL);
1952 if (!q_vector)
1953 return -ENOMEM;
1954
1955 /* initialize NAPI */
1956 netif_napi_add(wx->netdev, &q_vector->napi,
1957 wx_poll);
1958
1959 /* tie q_vector and wx together */
1960 wx->q_vector[v_idx] = q_vector;
1961 q_vector->wx = wx;
1962 q_vector->v_idx = v_idx;
1963 if (cpu_online(v_idx))
1964 q_vector->numa_node = cpu_to_node(v_idx);
1965
1966 /* initialize pointer to rings */
1967 ring = q_vector->ring;
1968
1969 switch (wx->mac.type) {
1970 case wx_mac_sp:
1971 case wx_mac_aml:
1972 case wx_mac_aml40:
1973 default_itr = WX_12K_ITR;
1974 break;
1975 default:
1976 default_itr = WX_7K_ITR;
1977 break;
1978 }
1979
1980 /* initialize ITR */
1981 if (txr_count && !rxr_count)
1982 /* tx only vector */
1983 q_vector->itr = wx->tx_itr_setting ?
1984 default_itr : wx->tx_itr_setting;
1985 else
1986 /* rx or rx/tx vector */
1987 q_vector->itr = wx->rx_itr_setting ?
1988 default_itr : wx->rx_itr_setting;
1989
1990 while (txr_count) {
1991 /* assign generic ring traits */
1992 ring->dev = &wx->pdev->dev;
1993 ring->netdev = wx->netdev;
1994
1995 /* configure backlink on ring */
1996 ring->q_vector = q_vector;
1997
1998 /* update q_vector Tx values */
1999 wx_add_ring(ring, &q_vector->tx);
2000
2001 /* apply Tx specific ring traits */
2002 ring->count = wx->tx_ring_count;
2003
2004 ring->queue_index = txr_idx;
2005
2006 /* assign ring to wx */
2007 wx->tx_ring[txr_idx] = ring;
2008
2009 /* update count and index */
2010 txr_count--;
2011 txr_idx += v_count;
2012
2013 /* push pointer to next ring */
2014 ring++;
2015 }
2016
2017 while (rxr_count) {
2018 /* assign generic ring traits */
2019 ring->dev = &wx->pdev->dev;
2020 ring->netdev = wx->netdev;
2021
2022 /* configure backlink on ring */
2023 ring->q_vector = q_vector;
2024
2025 /* update q_vector Rx values */
2026 wx_add_ring(ring, &q_vector->rx);
2027
2028 /* apply Rx specific ring traits */
2029 ring->count = wx->rx_ring_count;
2030 ring->queue_index = rxr_idx;
2031
2032 /* assign ring to wx */
2033 wx->rx_ring[rxr_idx] = ring;
2034
2035 /* update count and index */
2036 rxr_count--;
2037 rxr_idx += v_count;
2038
2039 /* push pointer to next ring */
2040 ring++;
2041 }
2042
2043 return 0;
2044 }
2045
2046 /**
2047 * wx_free_q_vector - Free memory allocated for specific interrupt vector
2048 * @wx: board private structure to initialize
2049 * @v_idx: Index of vector to be freed
2050 *
2051 * This function frees the memory allocated to the q_vector. In addition if
2052 * NAPI is enabled it will delete any references to the NAPI struct prior
2053 * to freeing the q_vector.
2054 **/
wx_free_q_vector(struct wx * wx,int v_idx)2055 static void wx_free_q_vector(struct wx *wx, int v_idx)
2056 {
2057 struct wx_q_vector *q_vector = wx->q_vector[v_idx];
2058 struct wx_ring *ring;
2059
2060 wx_for_each_ring(ring, q_vector->tx)
2061 wx->tx_ring[ring->queue_index] = NULL;
2062
2063 wx_for_each_ring(ring, q_vector->rx)
2064 wx->rx_ring[ring->queue_index] = NULL;
2065
2066 wx->q_vector[v_idx] = NULL;
2067 netif_napi_del(&q_vector->napi);
2068 kfree_rcu(q_vector, rcu);
2069 }
2070
2071 /**
2072 * wx_alloc_q_vectors - Allocate memory for interrupt vectors
2073 * @wx: board private structure to initialize
2074 *
2075 * We allocate one q_vector per queue interrupt. If allocation fails we
2076 * return -ENOMEM.
2077 **/
wx_alloc_q_vectors(struct wx * wx)2078 static int wx_alloc_q_vectors(struct wx *wx)
2079 {
2080 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0;
2081 unsigned int rxr_remaining = wx->num_rx_queues;
2082 unsigned int txr_remaining = wx->num_tx_queues;
2083 unsigned int q_vectors = wx->num_q_vectors;
2084 int rqpv, tqpv;
2085 int err;
2086
2087 for (; v_idx < q_vectors; v_idx++) {
2088 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
2089 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
2090 err = wx_alloc_q_vector(wx, q_vectors, v_idx,
2091 tqpv, txr_idx,
2092 rqpv, rxr_idx);
2093
2094 if (err)
2095 goto err_out;
2096
2097 /* update counts and index */
2098 rxr_remaining -= rqpv;
2099 txr_remaining -= tqpv;
2100 rxr_idx++;
2101 txr_idx++;
2102 }
2103
2104 return 0;
2105
2106 err_out:
2107 wx->num_tx_queues = 0;
2108 wx->num_rx_queues = 0;
2109 wx->num_q_vectors = 0;
2110
2111 while (v_idx--)
2112 wx_free_q_vector(wx, v_idx);
2113
2114 return -ENOMEM;
2115 }
2116
2117 /**
2118 * wx_free_q_vectors - Free memory allocated for interrupt vectors
2119 * @wx: board private structure to initialize
2120 *
2121 * This function frees the memory allocated to the q_vectors. In addition if
2122 * NAPI is enabled it will delete any references to the NAPI struct prior
2123 * to freeing the q_vector.
2124 **/
wx_free_q_vectors(struct wx * wx)2125 static void wx_free_q_vectors(struct wx *wx)
2126 {
2127 int v_idx = wx->num_q_vectors;
2128
2129 wx->num_tx_queues = 0;
2130 wx->num_rx_queues = 0;
2131 wx->num_q_vectors = 0;
2132
2133 while (v_idx--)
2134 wx_free_q_vector(wx, v_idx);
2135 }
2136
wx_reset_interrupt_capability(struct wx * wx)2137 void wx_reset_interrupt_capability(struct wx *wx)
2138 {
2139 struct pci_dev *pdev = wx->pdev;
2140
2141 if (!pdev->msi_enabled && !pdev->msix_enabled)
2142 return;
2143
2144 if (pdev->msix_enabled) {
2145 kfree(wx->msix_q_entries);
2146 wx->msix_q_entries = NULL;
2147 kfree(wx->msix_entry);
2148 wx->msix_entry = NULL;
2149 }
2150 pci_free_irq_vectors(wx->pdev);
2151 }
2152 EXPORT_SYMBOL(wx_reset_interrupt_capability);
2153
2154 /**
2155 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings
2156 * @wx: board private structure to clear interrupt scheme on
2157 *
2158 * We go through and clear interrupt specific resources and reset the structure
2159 * to pre-load conditions
2160 **/
wx_clear_interrupt_scheme(struct wx * wx)2161 void wx_clear_interrupt_scheme(struct wx *wx)
2162 {
2163 wx_free_q_vectors(wx);
2164 wx_reset_interrupt_capability(wx);
2165 }
2166 EXPORT_SYMBOL(wx_clear_interrupt_scheme);
2167
wx_init_interrupt_scheme(struct wx * wx)2168 int wx_init_interrupt_scheme(struct wx *wx)
2169 {
2170 int ret;
2171
2172 /* Number of supported queues */
2173 wx_set_num_queues(wx);
2174
2175 /* Set interrupt mode */
2176 ret = wx_set_interrupt_capability(wx);
2177 if (ret) {
2178 wx_err(wx, "Allocate irq vectors for failed.\n");
2179 return ret;
2180 }
2181
2182 /* Allocate memory for queues */
2183 ret = wx_alloc_q_vectors(wx);
2184 if (ret) {
2185 wx_err(wx, "Unable to allocate memory for queue vectors.\n");
2186 wx_reset_interrupt_capability(wx);
2187 return ret;
2188 }
2189
2190 wx_cache_ring_rss(wx);
2191
2192 return 0;
2193 }
2194 EXPORT_SYMBOL(wx_init_interrupt_scheme);
2195
wx_msix_clean_rings(int __always_unused irq,void * data)2196 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data)
2197 {
2198 struct wx_q_vector *q_vector = data;
2199
2200 /* EIAM disabled interrupts (on this vector) for us */
2201 if (q_vector->rx.ring || q_vector->tx.ring)
2202 napi_schedule_irqoff(&q_vector->napi);
2203
2204 return IRQ_HANDLED;
2205 }
2206 EXPORT_SYMBOL(wx_msix_clean_rings);
2207
wx_free_irq(struct wx * wx)2208 void wx_free_irq(struct wx *wx)
2209 {
2210 struct pci_dev *pdev = wx->pdev;
2211 int vector;
2212
2213 if (!(pdev->msix_enabled)) {
2214 if (!wx->misc_irq_domain)
2215 free_irq(pdev->irq, wx);
2216 return;
2217 }
2218
2219 for (vector = 0; vector < wx->num_q_vectors; vector++) {
2220 struct wx_q_vector *q_vector = wx->q_vector[vector];
2221 struct msix_entry *entry = &wx->msix_q_entries[vector];
2222
2223 /* free only the irqs that were actually requested */
2224 if (!q_vector->rx.ring && !q_vector->tx.ring)
2225 continue;
2226
2227 free_irq(entry->vector, q_vector);
2228 }
2229
2230 if (!wx->misc_irq_domain)
2231 free_irq(wx->msix_entry->vector, wx);
2232 }
2233 EXPORT_SYMBOL(wx_free_irq);
2234
2235 /**
2236 * wx_setup_isb_resources - allocate interrupt status resources
2237 * @wx: board private structure
2238 *
2239 * Return 0 on success, negative on failure
2240 **/
wx_setup_isb_resources(struct wx * wx)2241 int wx_setup_isb_resources(struct wx *wx)
2242 {
2243 struct pci_dev *pdev = wx->pdev;
2244
2245 if (wx->isb_mem)
2246 return 0;
2247
2248 wx->isb_mem = dma_alloc_coherent(&pdev->dev,
2249 sizeof(u32) * 4,
2250 &wx->isb_dma,
2251 GFP_KERNEL);
2252 if (!wx->isb_mem) {
2253 wx_err(wx, "Alloc isb_mem failed\n");
2254 return -ENOMEM;
2255 }
2256
2257 return 0;
2258 }
2259 EXPORT_SYMBOL(wx_setup_isb_resources);
2260
2261 /**
2262 * wx_free_isb_resources - allocate all queues Rx resources
2263 * @wx: board private structure
2264 *
2265 * Return 0 on success, negative on failure
2266 **/
wx_free_isb_resources(struct wx * wx)2267 void wx_free_isb_resources(struct wx *wx)
2268 {
2269 struct pci_dev *pdev = wx->pdev;
2270
2271 dma_free_coherent(&pdev->dev, sizeof(u32) * 4,
2272 wx->isb_mem, wx->isb_dma);
2273 wx->isb_mem = NULL;
2274 }
2275 EXPORT_SYMBOL(wx_free_isb_resources);
2276
wx_misc_isb(struct wx * wx,enum wx_isb_idx idx)2277 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx)
2278 {
2279 u32 cur_tag = 0;
2280
2281 cur_tag = wx->isb_mem[WX_ISB_HEADER];
2282 wx->isb_tag[idx] = cur_tag;
2283
2284 return (__force u32)cpu_to_le32(wx->isb_mem[idx]);
2285 }
2286 EXPORT_SYMBOL(wx_misc_isb);
2287
2288 /**
2289 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
2290 * @wx: pointer to wx struct
2291 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
2292 * @queue: queue to map the corresponding interrupt to
2293 * @msix_vector: the vector to map to the corresponding queue
2294 *
2295 **/
wx_set_ivar(struct wx * wx,s8 direction,u16 queue,u16 msix_vector)2296 static void wx_set_ivar(struct wx *wx, s8 direction,
2297 u16 queue, u16 msix_vector)
2298 {
2299 u32 ivar, index;
2300
2301 if (direction == -1) {
2302 /* other causes */
2303 if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags))
2304 msix_vector = 0;
2305 msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2306 index = 0;
2307 ivar = rd32(wx, WX_PX_MISC_IVAR);
2308 ivar &= ~(0xFF << index);
2309 ivar |= (msix_vector << index);
2310 wr32(wx, WX_PX_MISC_IVAR, ivar);
2311 } else {
2312 /* tx or rx causes */
2313 msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2314 index = ((16 * (queue & 1)) + (8 * direction));
2315 ivar = rd32(wx, WX_PX_IVAR(queue >> 1));
2316 ivar &= ~(0xFF << index);
2317 ivar |= (msix_vector << index);
2318 wr32(wx, WX_PX_IVAR(queue >> 1), ivar);
2319 }
2320 }
2321
2322 /**
2323 * wx_write_eitr - write EITR register in hardware specific way
2324 * @q_vector: structure containing interrupt and ring information
2325 *
2326 * This function is made to be called by ethtool and by the driver
2327 * when it needs to update EITR registers at runtime. Hardware
2328 * specific quirks/differences are taken care of here.
2329 */
wx_write_eitr(struct wx_q_vector * q_vector)2330 void wx_write_eitr(struct wx_q_vector *q_vector)
2331 {
2332 struct wx *wx = q_vector->wx;
2333 int v_idx = q_vector->v_idx;
2334 u32 itr_reg;
2335
2336 switch (wx->mac.type) {
2337 case wx_mac_sp:
2338 itr_reg = q_vector->itr & WX_SP_MAX_EITR;
2339 break;
2340 case wx_mac_aml:
2341 case wx_mac_aml40:
2342 itr_reg = (q_vector->itr >> 3) & WX_AML_MAX_EITR;
2343 break;
2344 default:
2345 itr_reg = q_vector->itr & WX_EM_MAX_EITR;
2346 break;
2347 }
2348
2349 itr_reg |= WX_PX_ITR_CNT_WDIS;
2350
2351 wr32(wx, WX_PX_ITR(v_idx), itr_reg);
2352 }
2353
2354 /**
2355 * wx_configure_vectors - Configure vectors for hardware
2356 * @wx: board private structure
2357 *
2358 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx
2359 * interrupts.
2360 **/
wx_configure_vectors(struct wx * wx)2361 void wx_configure_vectors(struct wx *wx)
2362 {
2363 struct pci_dev *pdev = wx->pdev;
2364 u32 eitrsel = 0;
2365 u16 v_idx, i;
2366
2367 if (pdev->msix_enabled) {
2368 /* Populate MSIX to EITR Select */
2369 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) {
2370 if (wx->num_vfs >= 32)
2371 eitrsel = BIT(wx->num_vfs % 32) - 1;
2372 } else {
2373 for (i = 0; i < wx->num_vfs; i++)
2374 eitrsel |= BIT(i);
2375 }
2376 wr32(wx, WX_PX_ITRSEL, eitrsel);
2377 /* use EIAM to auto-mask when MSI-X interrupt is asserted
2378 * this saves a register write for every interrupt
2379 */
2380 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL);
2381 } else {
2382 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2383 * specifically only auto mask tx and rx interrupts.
2384 */
2385 wr32(wx, WX_PX_GPIE, 0);
2386 }
2387
2388 /* Populate the IVAR table and set the ITR values to the
2389 * corresponding register.
2390 */
2391 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) {
2392 struct wx_q_vector *q_vector = wx->q_vector[v_idx];
2393 struct wx_ring *ring;
2394
2395 wx_for_each_ring(ring, q_vector->rx)
2396 wx_set_ivar(wx, 0, ring->reg_idx, v_idx);
2397
2398 wx_for_each_ring(ring, q_vector->tx)
2399 wx_set_ivar(wx, 1, ring->reg_idx, v_idx);
2400
2401 wx_write_eitr(q_vector);
2402 }
2403
2404 wx_set_ivar(wx, -1, 0, v_idx);
2405 if (pdev->msix_enabled)
2406 wr32(wx, WX_PX_ITR(v_idx), 1950);
2407 }
2408 EXPORT_SYMBOL(wx_configure_vectors);
2409
2410 /**
2411 * wx_clean_rx_ring - Free Rx Buffers per Queue
2412 * @rx_ring: ring to free buffers from
2413 **/
wx_clean_rx_ring(struct wx_ring * rx_ring)2414 static void wx_clean_rx_ring(struct wx_ring *rx_ring)
2415 {
2416 struct wx_rx_buffer *rx_buffer;
2417 u16 i = rx_ring->next_to_clean;
2418
2419 rx_buffer = &rx_ring->rx_buffer_info[i];
2420
2421 /* Free all the Rx ring sk_buffs */
2422 while (i != rx_ring->next_to_alloc) {
2423 if (rx_buffer->skb) {
2424 struct sk_buff *skb = rx_buffer->skb;
2425
2426 if (WX_CB(skb)->page_released)
2427 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2428
2429 dev_kfree_skb(skb);
2430 }
2431
2432 /* Invalidate cache lines that may have been written to by
2433 * device so that we avoid corrupting memory.
2434 */
2435 dma_sync_single_range_for_cpu(rx_ring->dev,
2436 rx_buffer->dma,
2437 rx_buffer->page_offset,
2438 WX_RX_BUFSZ,
2439 DMA_FROM_DEVICE);
2440
2441 /* free resources associated with mapping */
2442 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2443
2444 i++;
2445 rx_buffer++;
2446 if (i == rx_ring->count) {
2447 i = 0;
2448 rx_buffer = rx_ring->rx_buffer_info;
2449 }
2450 }
2451
2452 rx_ring->next_to_alloc = 0;
2453 rx_ring->next_to_clean = 0;
2454 rx_ring->next_to_use = 0;
2455 }
2456
2457 /**
2458 * wx_clean_all_rx_rings - Free Rx Buffers for all queues
2459 * @wx: board private structure
2460 **/
wx_clean_all_rx_rings(struct wx * wx)2461 void wx_clean_all_rx_rings(struct wx *wx)
2462 {
2463 int i;
2464
2465 for (i = 0; i < wx->num_rx_queues; i++)
2466 wx_clean_rx_ring(wx->rx_ring[i]);
2467 }
2468 EXPORT_SYMBOL(wx_clean_all_rx_rings);
2469
2470 /**
2471 * wx_free_rx_resources - Free Rx Resources
2472 * @rx_ring: ring to clean the resources from
2473 *
2474 * Free all receive software resources
2475 **/
wx_free_rx_resources(struct wx_ring * rx_ring)2476 static void wx_free_rx_resources(struct wx_ring *rx_ring)
2477 {
2478 wx_clean_rx_ring(rx_ring);
2479 kvfree(rx_ring->rx_buffer_info);
2480 rx_ring->rx_buffer_info = NULL;
2481
2482 /* if not set, then don't free */
2483 if (!rx_ring->desc)
2484 return;
2485
2486 dma_free_coherent(rx_ring->dev, rx_ring->size,
2487 rx_ring->desc, rx_ring->dma);
2488
2489 rx_ring->desc = NULL;
2490
2491 if (rx_ring->page_pool) {
2492 page_pool_destroy(rx_ring->page_pool);
2493 rx_ring->page_pool = NULL;
2494 }
2495 }
2496
2497 /**
2498 * wx_free_all_rx_resources - Free Rx Resources for All Queues
2499 * @wx: pointer to hardware structure
2500 *
2501 * Free all receive software resources
2502 **/
wx_free_all_rx_resources(struct wx * wx)2503 static void wx_free_all_rx_resources(struct wx *wx)
2504 {
2505 int i;
2506
2507 for (i = 0; i < wx->num_rx_queues; i++)
2508 wx_free_rx_resources(wx->rx_ring[i]);
2509 }
2510
2511 /**
2512 * wx_clean_tx_ring - Free Tx Buffers
2513 * @tx_ring: ring to be cleaned
2514 **/
wx_clean_tx_ring(struct wx_ring * tx_ring)2515 static void wx_clean_tx_ring(struct wx_ring *tx_ring)
2516 {
2517 struct wx_tx_buffer *tx_buffer;
2518 u16 i = tx_ring->next_to_clean;
2519
2520 tx_buffer = &tx_ring->tx_buffer_info[i];
2521
2522 while (i != tx_ring->next_to_use) {
2523 union wx_tx_desc *eop_desc, *tx_desc;
2524
2525 /* Free all the Tx ring sk_buffs */
2526 dev_kfree_skb_any(tx_buffer->skb);
2527
2528 /* unmap skb header data */
2529 dma_unmap_single(tx_ring->dev,
2530 dma_unmap_addr(tx_buffer, dma),
2531 dma_unmap_len(tx_buffer, len),
2532 DMA_TO_DEVICE);
2533
2534 /* check for eop_desc to determine the end of the packet */
2535 eop_desc = tx_buffer->next_to_watch;
2536 tx_desc = WX_TX_DESC(tx_ring, i);
2537
2538 /* unmap remaining buffers */
2539 while (tx_desc != eop_desc) {
2540 tx_buffer++;
2541 tx_desc++;
2542 i++;
2543 if (unlikely(i == tx_ring->count)) {
2544 i = 0;
2545 tx_buffer = tx_ring->tx_buffer_info;
2546 tx_desc = WX_TX_DESC(tx_ring, 0);
2547 }
2548
2549 /* unmap any remaining paged data */
2550 if (dma_unmap_len(tx_buffer, len))
2551 dma_unmap_page(tx_ring->dev,
2552 dma_unmap_addr(tx_buffer, dma),
2553 dma_unmap_len(tx_buffer, len),
2554 DMA_TO_DEVICE);
2555 }
2556
2557 /* move us one more past the eop_desc for start of next pkt */
2558 tx_buffer++;
2559 i++;
2560 if (unlikely(i == tx_ring->count)) {
2561 i = 0;
2562 tx_buffer = tx_ring->tx_buffer_info;
2563 }
2564 }
2565
2566 netdev_tx_reset_queue(wx_txring_txq(tx_ring));
2567
2568 /* reset next_to_use and next_to_clean */
2569 tx_ring->next_to_use = 0;
2570 tx_ring->next_to_clean = 0;
2571 }
2572
2573 /**
2574 * wx_clean_all_tx_rings - Free Tx Buffers for all queues
2575 * @wx: board private structure
2576 **/
wx_clean_all_tx_rings(struct wx * wx)2577 void wx_clean_all_tx_rings(struct wx *wx)
2578 {
2579 int i;
2580
2581 for (i = 0; i < wx->num_tx_queues; i++)
2582 wx_clean_tx_ring(wx->tx_ring[i]);
2583 }
2584 EXPORT_SYMBOL(wx_clean_all_tx_rings);
2585
2586 /**
2587 * wx_free_tx_resources - Free Tx Resources per Queue
2588 * @tx_ring: Tx descriptor ring for a specific queue
2589 *
2590 * Free all transmit software resources
2591 **/
wx_free_tx_resources(struct wx_ring * tx_ring)2592 static void wx_free_tx_resources(struct wx_ring *tx_ring)
2593 {
2594 wx_clean_tx_ring(tx_ring);
2595 kvfree(tx_ring->tx_buffer_info);
2596 tx_ring->tx_buffer_info = NULL;
2597
2598 /* if not set, then don't free */
2599 if (!tx_ring->desc)
2600 return;
2601
2602 dma_free_coherent(tx_ring->dev, tx_ring->size,
2603 tx_ring->desc, tx_ring->dma);
2604 tx_ring->desc = NULL;
2605 }
2606
2607 /**
2608 * wx_free_all_tx_resources - Free Tx Resources for All Queues
2609 * @wx: pointer to hardware structure
2610 *
2611 * Free all transmit software resources
2612 **/
wx_free_all_tx_resources(struct wx * wx)2613 static void wx_free_all_tx_resources(struct wx *wx)
2614 {
2615 int i;
2616
2617 for (i = 0; i < wx->num_tx_queues; i++)
2618 wx_free_tx_resources(wx->tx_ring[i]);
2619 }
2620
wx_free_resources(struct wx * wx)2621 void wx_free_resources(struct wx *wx)
2622 {
2623 wx_free_all_rx_resources(wx);
2624 wx_free_all_tx_resources(wx);
2625 }
2626 EXPORT_SYMBOL(wx_free_resources);
2627
wx_alloc_page_pool(struct wx_ring * rx_ring)2628 static int wx_alloc_page_pool(struct wx_ring *rx_ring)
2629 {
2630 int ret = 0;
2631
2632 struct page_pool_params pp_params = {
2633 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
2634 .order = 0,
2635 .pool_size = rx_ring->count,
2636 .nid = dev_to_node(rx_ring->dev),
2637 .dev = rx_ring->dev,
2638 .dma_dir = DMA_FROM_DEVICE,
2639 .offset = 0,
2640 .max_len = PAGE_SIZE,
2641 };
2642
2643 rx_ring->page_pool = page_pool_create(&pp_params);
2644 if (IS_ERR(rx_ring->page_pool)) {
2645 ret = PTR_ERR(rx_ring->page_pool);
2646 rx_ring->page_pool = NULL;
2647 }
2648
2649 return ret;
2650 }
2651
2652 /**
2653 * wx_setup_rx_resources - allocate Rx resources (Descriptors)
2654 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2655 *
2656 * Returns 0 on success, negative on failure
2657 **/
wx_setup_rx_resources(struct wx_ring * rx_ring)2658 static int wx_setup_rx_resources(struct wx_ring *rx_ring)
2659 {
2660 struct device *dev = rx_ring->dev;
2661 int orig_node = dev_to_node(dev);
2662 int numa_node = NUMA_NO_NODE;
2663 int size, ret;
2664
2665 size = sizeof(struct wx_rx_buffer) * rx_ring->count;
2666
2667 if (rx_ring->q_vector)
2668 numa_node = rx_ring->q_vector->numa_node;
2669
2670 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2671 if (!rx_ring->rx_buffer_info)
2672 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL);
2673 if (!rx_ring->rx_buffer_info)
2674 goto err;
2675
2676 /* Round up to nearest 4K */
2677 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc);
2678 rx_ring->size = ALIGN(rx_ring->size, 4096);
2679
2680 set_dev_node(dev, numa_node);
2681 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2682 &rx_ring->dma, GFP_KERNEL);
2683 if (!rx_ring->desc) {
2684 set_dev_node(dev, orig_node);
2685 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2686 &rx_ring->dma, GFP_KERNEL);
2687 }
2688
2689 if (!rx_ring->desc)
2690 goto err;
2691
2692 rx_ring->next_to_clean = 0;
2693 rx_ring->next_to_use = 0;
2694
2695 ret = wx_alloc_page_pool(rx_ring);
2696 if (ret < 0) {
2697 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret);
2698 goto err_desc;
2699 }
2700
2701 return 0;
2702
2703 err_desc:
2704 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2705 err:
2706 kvfree(rx_ring->rx_buffer_info);
2707 rx_ring->rx_buffer_info = NULL;
2708 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2709 return -ENOMEM;
2710 }
2711
2712 /**
2713 * wx_setup_all_rx_resources - allocate all queues Rx resources
2714 * @wx: pointer to hardware structure
2715 *
2716 * If this function returns with an error, then it's possible one or
2717 * more of the rings is populated (while the rest are not). It is the
2718 * callers duty to clean those orphaned rings.
2719 *
2720 * Return 0 on success, negative on failure
2721 **/
wx_setup_all_rx_resources(struct wx * wx)2722 static int wx_setup_all_rx_resources(struct wx *wx)
2723 {
2724 int i, err = 0;
2725
2726 for (i = 0; i < wx->num_rx_queues; i++) {
2727 err = wx_setup_rx_resources(wx->rx_ring[i]);
2728 if (!err)
2729 continue;
2730
2731 wx_err(wx, "Allocation for Rx Queue %u failed\n", i);
2732 goto err_setup_rx;
2733 }
2734
2735 return 0;
2736 err_setup_rx:
2737 /* rewind the index freeing the rings as we go */
2738 while (i--)
2739 wx_free_rx_resources(wx->rx_ring[i]);
2740 return err;
2741 }
2742
2743 /**
2744 * wx_setup_tx_resources - allocate Tx resources (Descriptors)
2745 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2746 *
2747 * Return 0 on success, negative on failure
2748 **/
wx_setup_tx_resources(struct wx_ring * tx_ring)2749 static int wx_setup_tx_resources(struct wx_ring *tx_ring)
2750 {
2751 struct device *dev = tx_ring->dev;
2752 int orig_node = dev_to_node(dev);
2753 int numa_node = NUMA_NO_NODE;
2754 int size;
2755
2756 size = sizeof(struct wx_tx_buffer) * tx_ring->count;
2757
2758 if (tx_ring->q_vector)
2759 numa_node = tx_ring->q_vector->numa_node;
2760
2761 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2762 if (!tx_ring->tx_buffer_info)
2763 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL);
2764 if (!tx_ring->tx_buffer_info)
2765 goto err;
2766
2767 /* round up to nearest 4K */
2768 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc);
2769 tx_ring->size = ALIGN(tx_ring->size, 4096);
2770
2771 set_dev_node(dev, numa_node);
2772 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2773 &tx_ring->dma, GFP_KERNEL);
2774 if (!tx_ring->desc) {
2775 set_dev_node(dev, orig_node);
2776 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2777 &tx_ring->dma, GFP_KERNEL);
2778 }
2779
2780 if (!tx_ring->desc)
2781 goto err;
2782
2783 tx_ring->next_to_use = 0;
2784 tx_ring->next_to_clean = 0;
2785
2786 return 0;
2787
2788 err:
2789 kvfree(tx_ring->tx_buffer_info);
2790 tx_ring->tx_buffer_info = NULL;
2791 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2792 return -ENOMEM;
2793 }
2794
2795 /**
2796 * wx_setup_all_tx_resources - allocate all queues Tx resources
2797 * @wx: pointer to private structure
2798 *
2799 * If this function returns with an error, then it's possible one or
2800 * more of the rings is populated (while the rest are not). It is the
2801 * callers duty to clean those orphaned rings.
2802 *
2803 * Return 0 on success, negative on failure
2804 **/
wx_setup_all_tx_resources(struct wx * wx)2805 static int wx_setup_all_tx_resources(struct wx *wx)
2806 {
2807 int i, err = 0;
2808
2809 for (i = 0; i < wx->num_tx_queues; i++) {
2810 err = wx_setup_tx_resources(wx->tx_ring[i]);
2811 if (!err)
2812 continue;
2813
2814 wx_err(wx, "Allocation for Tx Queue %u failed\n", i);
2815 goto err_setup_tx;
2816 }
2817
2818 return 0;
2819 err_setup_tx:
2820 /* rewind the index freeing the rings as we go */
2821 while (i--)
2822 wx_free_tx_resources(wx->tx_ring[i]);
2823 return err;
2824 }
2825
wx_setup_resources(struct wx * wx)2826 int wx_setup_resources(struct wx *wx)
2827 {
2828 int err;
2829
2830 /* allocate transmit descriptors */
2831 err = wx_setup_all_tx_resources(wx);
2832 if (err)
2833 return err;
2834
2835 /* allocate receive descriptors */
2836 err = wx_setup_all_rx_resources(wx);
2837 if (err)
2838 goto err_free_tx;
2839
2840 err = wx_setup_isb_resources(wx);
2841 if (err)
2842 goto err_free_rx;
2843
2844 return 0;
2845
2846 err_free_rx:
2847 wx_free_all_rx_resources(wx);
2848 err_free_tx:
2849 wx_free_all_tx_resources(wx);
2850
2851 return err;
2852 }
2853 EXPORT_SYMBOL(wx_setup_resources);
2854
2855 /**
2856 * wx_get_stats64 - Get System Network Statistics
2857 * @netdev: network interface device structure
2858 * @stats: storage space for 64bit statistics
2859 */
wx_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2860 void wx_get_stats64(struct net_device *netdev,
2861 struct rtnl_link_stats64 *stats)
2862 {
2863 struct wx *wx = netdev_priv(netdev);
2864 struct wx_hw_stats *hwstats;
2865 int i;
2866
2867 wx_update_stats(wx);
2868
2869 rcu_read_lock();
2870 for (i = 0; i < wx->num_rx_queues; i++) {
2871 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]);
2872 u64 bytes, packets;
2873 unsigned int start;
2874
2875 if (ring) {
2876 do {
2877 start = u64_stats_fetch_begin(&ring->syncp);
2878 packets = ring->stats.packets;
2879 bytes = ring->stats.bytes;
2880 } while (u64_stats_fetch_retry(&ring->syncp, start));
2881 stats->rx_packets += packets;
2882 stats->rx_bytes += bytes;
2883 }
2884 }
2885
2886 for (i = 0; i < wx->num_tx_queues; i++) {
2887 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]);
2888 u64 bytes, packets;
2889 unsigned int start;
2890
2891 if (ring) {
2892 do {
2893 start = u64_stats_fetch_begin(&ring->syncp);
2894 packets = ring->stats.packets;
2895 bytes = ring->stats.bytes;
2896 } while (u64_stats_fetch_retry(&ring->syncp,
2897 start));
2898 stats->tx_packets += packets;
2899 stats->tx_bytes += bytes;
2900 }
2901 }
2902
2903 rcu_read_unlock();
2904
2905 hwstats = &wx->stats;
2906 stats->rx_errors = hwstats->crcerrs + hwstats->rlec;
2907 stats->multicast = hwstats->qmprc;
2908 stats->rx_length_errors = hwstats->rlec;
2909 stats->rx_crc_errors = hwstats->crcerrs;
2910 }
2911 EXPORT_SYMBOL(wx_get_stats64);
2912
wx_set_features(struct net_device * netdev,netdev_features_t features)2913 int wx_set_features(struct net_device *netdev, netdev_features_t features)
2914 {
2915 netdev_features_t changed = netdev->features ^ features;
2916 struct wx *wx = netdev_priv(netdev);
2917 bool need_reset = false;
2918
2919 if (features & NETIF_F_RXHASH) {
2920 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN,
2921 WX_RDB_RA_CTL_RSS_EN);
2922 wx->rss_enabled = true;
2923 } else {
2924 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0);
2925 wx->rss_enabled = false;
2926 }
2927
2928 netdev->features = features;
2929
2930 if (changed & NETIF_F_HW_VLAN_CTAG_RX && wx->do_reset)
2931 wx->do_reset(netdev);
2932 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER))
2933 wx_set_rx_mode(netdev);
2934
2935 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)))
2936 return 0;
2937
2938 /* Check if Flow Director n-tuple support was enabled or disabled. If
2939 * the state changed, we need to reset.
2940 */
2941 switch (features & NETIF_F_NTUPLE) {
2942 case NETIF_F_NTUPLE:
2943 /* turn off ATR, enable perfect filters and reset */
2944 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags)))
2945 need_reset = true;
2946
2947 clear_bit(WX_FLAG_FDIR_HASH, wx->flags);
2948 break;
2949 default:
2950 /* turn off perfect filters, enable ATR and reset */
2951 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags))
2952 need_reset = true;
2953
2954 /* We cannot enable ATR if RSS is disabled */
2955 if (wx->ring_feature[RING_F_RSS].limit <= 1)
2956 break;
2957
2958 set_bit(WX_FLAG_FDIR_HASH, wx->flags);
2959 break;
2960 }
2961
2962 if (need_reset && wx->do_reset)
2963 wx->do_reset(netdev);
2964
2965 return 0;
2966 }
2967 EXPORT_SYMBOL(wx_set_features);
2968
2969 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \
2970 NETIF_F_HW_VLAN_STAG_RX)
2971
2972 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \
2973 NETIF_F_HW_VLAN_STAG_TX)
2974
2975 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
2976 NETIF_F_HW_VLAN_STAG_FILTER)
2977
wx_fix_features(struct net_device * netdev,netdev_features_t features)2978 netdev_features_t wx_fix_features(struct net_device *netdev,
2979 netdev_features_t features)
2980 {
2981 netdev_features_t changed = netdev->features ^ features;
2982 struct wx *wx = netdev_priv(netdev);
2983
2984 if (changed & NETIF_VLAN_STRIPPING_FEATURES) {
2985 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES &&
2986 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) {
2987 features &= ~NETIF_VLAN_STRIPPING_FEATURES;
2988 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES;
2989 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off.");
2990 }
2991 }
2992
2993 if (changed & NETIF_VLAN_INSERTION_FEATURES) {
2994 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES &&
2995 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) {
2996 features &= ~NETIF_VLAN_INSERTION_FEATURES;
2997 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES;
2998 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off.");
2999 }
3000 }
3001
3002 if (changed & NETIF_VLAN_FILTERING_FEATURES) {
3003 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES &&
3004 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) {
3005 features &= ~NETIF_VLAN_FILTERING_FEATURES;
3006 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES;
3007 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off.");
3008 }
3009 }
3010
3011 return features;
3012 }
3013 EXPORT_SYMBOL(wx_fix_features);
3014
3015 #define WX_MAX_TUNNEL_HDR_LEN 80
wx_features_check(struct sk_buff * skb,struct net_device * netdev,netdev_features_t features)3016 netdev_features_t wx_features_check(struct sk_buff *skb,
3017 struct net_device *netdev,
3018 netdev_features_t features)
3019 {
3020 struct wx *wx = netdev_priv(netdev);
3021
3022 if (!skb->encapsulation)
3023 return features;
3024
3025 if (wx->mac.type == wx_mac_em)
3026 return features & ~NETIF_F_CSUM_MASK;
3027
3028 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
3029 WX_MAX_TUNNEL_HDR_LEN))
3030 return features & ~NETIF_F_CSUM_MASK;
3031
3032 if (skb->inner_protocol_type == ENCAP_TYPE_ETHER &&
3033 skb->inner_protocol != htons(ETH_P_IP) &&
3034 skb->inner_protocol != htons(ETH_P_IPV6) &&
3035 skb->inner_protocol != htons(ETH_P_TEB))
3036 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3037
3038 return features;
3039 }
3040 EXPORT_SYMBOL(wx_features_check);
3041
wx_set_ring(struct wx * wx,u32 new_tx_count,u32 new_rx_count,struct wx_ring * temp_ring)3042 void wx_set_ring(struct wx *wx, u32 new_tx_count,
3043 u32 new_rx_count, struct wx_ring *temp_ring)
3044 {
3045 int i, err = 0;
3046
3047 /* Setup new Tx resources and free the old Tx resources in that order.
3048 * We can then assign the new resources to the rings via a memcpy.
3049 * The advantage to this approach is that we are guaranteed to still
3050 * have resources even in the case of an allocation failure.
3051 */
3052 if (new_tx_count != wx->tx_ring_count) {
3053 for (i = 0; i < wx->num_tx_queues; i++) {
3054 memcpy(&temp_ring[i], wx->tx_ring[i],
3055 sizeof(struct wx_ring));
3056
3057 temp_ring[i].count = new_tx_count;
3058 err = wx_setup_tx_resources(&temp_ring[i]);
3059 if (err) {
3060 wx_err(wx, "setup new tx resources failed, keep using the old config\n");
3061 while (i) {
3062 i--;
3063 wx_free_tx_resources(&temp_ring[i]);
3064 }
3065 return;
3066 }
3067 }
3068
3069 for (i = 0; i < wx->num_tx_queues; i++) {
3070 wx_free_tx_resources(wx->tx_ring[i]);
3071
3072 memcpy(wx->tx_ring[i], &temp_ring[i],
3073 sizeof(struct wx_ring));
3074 }
3075
3076 wx->tx_ring_count = new_tx_count;
3077 }
3078
3079 /* Repeat the process for the Rx rings if needed */
3080 if (new_rx_count != wx->rx_ring_count) {
3081 for (i = 0; i < wx->num_rx_queues; i++) {
3082 memcpy(&temp_ring[i], wx->rx_ring[i],
3083 sizeof(struct wx_ring));
3084
3085 temp_ring[i].count = new_rx_count;
3086 err = wx_setup_rx_resources(&temp_ring[i]);
3087 if (err) {
3088 wx_err(wx, "setup new rx resources failed, keep using the old config\n");
3089 while (i) {
3090 i--;
3091 wx_free_rx_resources(&temp_ring[i]);
3092 }
3093 return;
3094 }
3095 }
3096
3097 for (i = 0; i < wx->num_rx_queues; i++) {
3098 wx_free_rx_resources(wx->rx_ring[i]);
3099 memcpy(wx->rx_ring[i], &temp_ring[i],
3100 sizeof(struct wx_ring));
3101 }
3102
3103 wx->rx_ring_count = new_rx_count;
3104 }
3105 }
3106 EXPORT_SYMBOL(wx_set_ring);
3107
wx_service_event_schedule(struct wx * wx)3108 void wx_service_event_schedule(struct wx *wx)
3109 {
3110 if (!test_and_set_bit(WX_STATE_SERVICE_SCHED, wx->state))
3111 queue_work(system_power_efficient_wq, &wx->service_task);
3112 }
3113 EXPORT_SYMBOL(wx_service_event_schedule);
3114
wx_service_event_complete(struct wx * wx)3115 void wx_service_event_complete(struct wx *wx)
3116 {
3117 if (WARN_ON(!test_bit(WX_STATE_SERVICE_SCHED, wx->state)))
3118 return;
3119
3120 /* flush memory to make sure state is correct before next watchdog */
3121 smp_mb__before_atomic();
3122 clear_bit(WX_STATE_SERVICE_SCHED, wx->state);
3123 }
3124 EXPORT_SYMBOL(wx_service_event_complete);
3125
wx_service_timer(struct timer_list * t)3126 void wx_service_timer(struct timer_list *t)
3127 {
3128 struct wx *wx = timer_container_of(wx, t, service_timer);
3129 unsigned long next_event_offset = HZ * 2;
3130
3131 /* Reset the timer */
3132 mod_timer(&wx->service_timer, next_event_offset + jiffies);
3133
3134 wx_service_event_schedule(wx);
3135 }
3136 EXPORT_SYMBOL(wx_service_timer);
3137
3138 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers.");
3139 MODULE_LICENSE("GPL");
3140