1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ROHM ADC driver for BD79112 signal monitoring hub.
4 * Copyright (C) 2025, ROHM Semiconductor.
5 *
6 * SPI communication derived from ad7923.c and ti-ads7950.c
7 */
8
9 #include <linux/array_size.h>
10 #include <linux/bitfield.h>
11 #include <linux/bitops.h>
12 #include <linux/bits.h>
13 #include <linux/dev_printk.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/gpio/driver.h>
17 #include <linux/module.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
22 #include <asm/byteorder.h>
23
24 #include <linux/iio/adc-helpers.h>
25 #include <linux/iio/iio.h>
26
27 #define BD79112_MAX_NUM_CHANNELS 32
28
29 struct bd79112_data {
30 struct spi_device *spi;
31 struct regmap *map;
32 struct device *dev;
33 struct gpio_chip gc;
34 unsigned long gpio_valid_mask;
35 unsigned int vref_mv;
36 struct spi_transfer read_xfer[2];
37 struct spi_transfer write_xfer;
38 struct spi_message read_msg;
39 struct spi_message write_msg;
40 /* 16-bit TX, valid data in high byte */
41 u8 read_tx[2] __aligned(IIO_DMA_MINALIGN);
42 /* 8-bit address followed by 8-bit data */
43 u8 reg_write_tx[2];
44 /* 12-bit of ADC data or 8 bit of reg data */
45 __be16 read_rx;
46 };
47
48 /*
49 * The ADC data is read issuing SPI-command matching the channel number.
50 * We treat this as a register address.
51 */
52 #define BD79112_REG_AGIO0A 0x00
53 #define BD79112_REG_AGIO15B 0x1f
54
55 /*
56 * ADC STATUS_FLAG appended to ADC data will be set, if the ADC result is being
57 * read for a channel, which input pin is muxed to be a GPIO.
58 */
59 #define BD79112_ADC_STATUS_FLAG BIT(14)
60
61 /*
62 * The BD79112 requires "R/W bit" to be set for SPI register (not ADC data)
63 * reads and an "IOSET bit" to be set for read/write operations (which aren't
64 * reading the ADC data).
65 */
66 #define BD79112_BIT_RW BIT(4)
67 #define BD79112_BIT_IO BIT(5)
68
69 #define BD79112_REG_GPI_VALUE_B8_15 (BD79112_BIT_IO | 0x0)
70 #define BD79112_REG_GPI_VALUE_B0_B7 (BD79112_BIT_IO | 0x1)
71 #define BD79112_REG_GPI_VALUE_A8_15 (BD79112_BIT_IO | 0x2)
72 #define BD79112_REG_GPI_VALUE_A0_A7 (BD79112_BIT_IO | 0x3)
73
74 #define BD79112_REG_GPI_EN_B7_B15 (BD79112_BIT_IO | 0x4)
75 #define BD79112_REG_GPI_EN_B0_B7 (BD79112_BIT_IO | 0x5)
76 #define BD79112_REG_GPI_EN_A8_A15 (BD79112_BIT_IO | 0x6)
77 #define BD79112_REG_GPI_EN_A0_A7 (BD79112_BIT_IO | 0x7)
78
79 #define BD79112_REG_GPO_EN_B7_B15 (BD79112_BIT_IO | 0x8)
80 #define BD79112_REG_GPO_EN_B0_B7 (BD79112_BIT_IO | 0x9)
81 #define BD79112_REG_GPO_EN_A8_A15 (BD79112_BIT_IO | 0xa)
82 #define BD79112_REG_GPO_EN_A0_A7 (BD79112_BIT_IO | 0xb)
83
84 #define BD79112_NUM_GPIO_EN_REGS 8
85 #define BD79112_FIRST_GPIO_EN_REG BD79112_REG_GPI_EN_B7_B15
86
87 #define BD79112_REG_GPO_VALUE_B8_15 (BD79112_BIT_IO | 0xc)
88 #define BD79112_REG_GPO_VALUE_B0_B7 (BD79112_BIT_IO | 0xd)
89 #define BD79112_REG_GPO_VALUE_A8_15 (BD79112_BIT_IO | 0xe)
90 #define BD79112_REG_GPO_VALUE_A0_A7 (BD79112_BIT_IO | 0xf)
91
92 #define BD79112_REG_MAX BD79112_REG_GPO_VALUE_A0_A7
93
94 /*
95 * Read transaction consists of two 16-bit sequences separated by CSB.
96 * For register read, 'IOSET' bit must be set. For ADC read, IOSET is cleared
97 * and ADDR equals the channel number (0 ... 31).
98 *
99 * First 16-bit sequence, MOSI as below, MISO data ignored:
100 * - SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 9 .. 16 |
101 * - MOSI:| 0 | 0 | IOSET | RW (1) | ADDR | 8'b0 |
102 *
103 * CSB released and re-acquired between these sequences
104 *
105 * Second 16-bit sequence, MISO as below, MOSI data ignored:
106 * For Register read data is 8 bits:
107 * - SCK: | 1 .. 8 | 9 .. 16 |
108 * - MISO:| 8'b0 | 8-bit data |
109 *
110 * For ADC read data is 12 bits:
111 * - SCK: | 1 | 2 | 3 4 | 4 .. 16 |
112 * - MISO:| 0 | STATUS_FLAG | 2'b0 | 12-bit data |
113 * The 'STATUS_FLAG' is set if the read input pin was configured as a GPIO.
114 */
bd79112_reg_read(void * context,unsigned int reg,unsigned int * val)115 static int bd79112_reg_read(void *context, unsigned int reg, unsigned int *val)
116 {
117 struct bd79112_data *data = context;
118 int ret;
119
120 if (reg & BD79112_BIT_IO)
121 reg |= BD79112_BIT_RW;
122
123 data->read_tx[0] = reg;
124
125 ret = spi_sync(data->spi, &data->read_msg);
126 if (!ret)
127 *val = be16_to_cpu(data->read_rx);
128
129 return ret;
130 }
131
132 /*
133 * Write, single 16-bit sequence (broken down below):
134 *
135 * First 8-bit, MOSI as below, MISO data ignored:
136 * - SCK: | 1 | 2 | 3 | 4 | 5 .. 8 |
137 * - MOSI:| 0 | 0 |IOSET| RW(0) | ADDR |
138 *
139 * Last 8 SCK cycles (b8 ... b15), MISO contains register data, MOSI ignored.
140 * - SCK: | 9 .. 16 |
141 * - MISO:| data |
142 */
bd79112_reg_write(void * context,unsigned int reg,unsigned int val)143 static int bd79112_reg_write(void *context, unsigned int reg, unsigned int val)
144 {
145 struct bd79112_data *data = context;
146
147 data->reg_write_tx[0] = reg;
148 data->reg_write_tx[1] = val;
149
150 return spi_sync(data->spi, &data->write_msg);
151 }
152
_get_gpio_reg(unsigned int offset,unsigned int base)153 static int _get_gpio_reg(unsigned int offset, unsigned int base)
154 {
155 int regoffset = offset / 8;
156
157 if (offset > 31)
158 return -EINVAL;
159
160 return base - regoffset;
161 }
162
163 #define GET_GPIO_BIT(offset) BIT((offset) % 8)
164 #define GET_GPO_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_EN_A0_A7)
165 #define GET_GPI_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_EN_A0_A7)
166 #define GET_GPO_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_VALUE_A0_A7)
167 #define GET_GPI_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_VALUE_A0_A7)
168
169 static const struct regmap_range bd71815_volatile_ro_ranges[] = {
170 /* Read ADC data */
171 regmap_reg_range(BD79112_REG_AGIO0A, BD79112_REG_AGIO15B),
172 /* GPI state */
173 regmap_reg_range(BD79112_REG_GPI_VALUE_B8_15, BD79112_REG_GPI_VALUE_A0_A7),
174 };
175
176 static const struct regmap_access_table bd79112_volatile_regs = {
177 .yes_ranges = &bd71815_volatile_ro_ranges[0],
178 .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ro_ranges),
179 };
180
181 static const struct regmap_access_table bd79112_ro_regs = {
182 .no_ranges = &bd71815_volatile_ro_ranges[0],
183 .n_no_ranges = ARRAY_SIZE(bd71815_volatile_ro_ranges),
184 };
185
186 static const struct regmap_config bd79112_regmap = {
187 .reg_read = bd79112_reg_read,
188 .reg_write = bd79112_reg_write,
189 .volatile_table = &bd79112_volatile_regs,
190 .wr_table = &bd79112_ro_regs,
191 .cache_type = REGCACHE_MAPLE,
192 .max_register = BD79112_REG_MAX,
193 };
194
bd79112_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)195 static int bd79112_read_raw(struct iio_dev *indio_dev,
196 struct iio_chan_spec const *chan, int *val,
197 int *val2, long m)
198 {
199 struct bd79112_data *data = iio_priv(indio_dev);
200 int ret;
201
202 switch (m) {
203 case IIO_CHAN_INFO_RAW:
204 ret = regmap_read(data->map, chan->channel, val);
205 if (ret < 0)
206 return ret;
207
208 return IIO_VAL_INT;
209
210 case IIO_CHAN_INFO_SCALE:
211 *val = data->vref_mv;
212 *val2 = 12;
213
214 return IIO_VAL_FRACTIONAL_LOG2;
215 default:
216 return -EINVAL;
217 }
218 }
219
220 static const struct iio_info bd79112_info = {
221 .read_raw = bd79112_read_raw,
222 };
223
224 static const struct iio_chan_spec bd79112_chan_template = {
225 .type = IIO_VOLTAGE,
226 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
227 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
228 .indexed = 1,
229 };
230
bd79112_gpio_init_valid_mask(struct gpio_chip * gc,unsigned long * valid_mask,unsigned int ngpios)231 static int bd79112_gpio_init_valid_mask(struct gpio_chip *gc,
232 unsigned long *valid_mask,
233 unsigned int ngpios)
234 {
235 struct bd79112_data *data = gpiochip_get_data(gc);
236
237 *valid_mask = data->gpio_valid_mask;
238
239 return 0;
240 }
241
bd79112_gpio_dir_get(struct gpio_chip * gc,unsigned int offset)242 static int bd79112_gpio_dir_get(struct gpio_chip *gc, unsigned int offset)
243 {
244 struct bd79112_data *data = gpiochip_get_data(gc);
245 unsigned int reg, bit, val;
246 int ret;
247
248 bit = GET_GPIO_BIT(offset);
249 reg = GET_GPO_EN_REG(offset);
250
251 ret = regmap_read(data->map, reg, &val);
252 if (ret)
253 return ret;
254
255 if (bit & val)
256 return GPIO_LINE_DIRECTION_OUT;
257
258 reg = GET_GPI_EN_REG(offset);
259 ret = regmap_read(data->map, reg, &val);
260 if (ret)
261 return ret;
262
263 if (bit & val)
264 return GPIO_LINE_DIRECTION_IN;
265
266 /*
267 * Ouch. Seems the pin is ADC input - shouldn't happen as changing mux
268 * at runtime is not supported and non GPIO pins should be invalidated
269 * by the valid_mask at probe. Maybe someone wrote a register bypassing
270 * the driver?
271 */
272 dev_err(data->dev, "Pin not a GPIO\n");
273
274 return -EINVAL;
275 }
276
bd79112_gpio_get(struct gpio_chip * gc,unsigned int offset)277 static int bd79112_gpio_get(struct gpio_chip *gc, unsigned int offset)
278 {
279 struct bd79112_data *data = gpiochip_get_data(gc);
280 unsigned int reg, bit, val;
281 int ret;
282
283 bit = GET_GPIO_BIT(offset);
284 reg = GET_GPI_VAL_REG(offset);
285
286 ret = regmap_read(data->map, reg, &val);
287 if (ret)
288 return ret;
289
290 return !!(val & bit);
291 }
292
bd79112_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)293 static int bd79112_gpio_set(struct gpio_chip *gc, unsigned int offset,
294 int value)
295 {
296 struct bd79112_data *data = gpiochip_get_data(gc);
297 unsigned int reg, bit;
298
299 bit = GET_GPIO_BIT(offset);
300 reg = GET_GPO_VAL_REG(offset);
301
302 return regmap_assign_bits(data->map, reg, bit, value);
303 }
304
bd79112_gpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)305 static int bd79112_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
306 unsigned long *bits)
307 {
308 struct bd79112_data *data = gpiochip_get_data(gc);
309 unsigned long i, bank_mask;
310
311 for_each_set_clump8(i, bank_mask, mask, gc->ngpio) {
312 unsigned long bank_bits;
313 unsigned int reg;
314 int ret;
315
316 bank_bits = bitmap_get_value8(bits, i);
317 reg = BD79112_REG_GPO_VALUE_A0_A7 - i / 8;
318 ret = regmap_update_bits(data->map, reg, bank_mask, bank_bits);
319 if (ret)
320 return ret;
321 }
322
323 return 0;
324 }
325
bd79112_gpio_dir_set(struct bd79112_data * data,unsigned int offset,int dir)326 static int bd79112_gpio_dir_set(struct bd79112_data *data, unsigned int offset,
327 int dir)
328 {
329 unsigned int gpi_reg, gpo_reg, bit;
330 int ret;
331
332 bit = GET_GPIO_BIT(offset);
333 gpi_reg = GET_GPI_EN_REG(offset);
334 gpo_reg = GET_GPO_EN_REG(offset);
335
336 if (dir == GPIO_LINE_DIRECTION_OUT) {
337 ret = regmap_clear_bits(data->map, gpi_reg, bit);
338 if (ret)
339 return ret;
340
341 return regmap_set_bits(data->map, gpo_reg, bit);
342 }
343
344 ret = regmap_set_bits(data->map, gpi_reg, bit);
345 if (ret)
346 return ret;
347
348 return regmap_clear_bits(data->map, gpo_reg, bit);
349 }
350
bd79112_gpio_input(struct gpio_chip * gc,unsigned int offset)351 static int bd79112_gpio_input(struct gpio_chip *gc, unsigned int offset)
352 {
353 struct bd79112_data *data = gpiochip_get_data(gc);
354
355 return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_IN);
356 }
357
bd79112_gpio_output(struct gpio_chip * gc,unsigned int offset,int value)358 static int bd79112_gpio_output(struct gpio_chip *gc, unsigned int offset,
359 int value)
360 {
361 struct bd79112_data *data = gpiochip_get_data(gc);
362 int ret;
363
364 ret = bd79112_gpio_set(gc, offset, value);
365 if (ret)
366 return ret;
367
368 return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_OUT);
369 }
370
371 static const struct gpio_chip bd79112_gpio_chip = {
372 .label = "bd79112-gpio",
373 .get_direction = bd79112_gpio_dir_get,
374 .direction_input = bd79112_gpio_input,
375 .direction_output = bd79112_gpio_output,
376 .get = bd79112_gpio_get,
377 .set = bd79112_gpio_set,
378 .set_multiple = bd79112_gpio_set_multiple,
379 .init_valid_mask = bd79112_gpio_init_valid_mask,
380 .can_sleep = true,
381 .ngpio = 32,
382 .base = -1,
383 };
384
bd79112_get_gpio_pins(const struct iio_chan_spec * cs,int num_channels)385 static unsigned int bd79112_get_gpio_pins(const struct iio_chan_spec *cs, int num_channels)
386 {
387 unsigned int i, gpio_channels;
388
389 /*
390 * Let's initialize the mux config to say that all 32 channels are
391 * GPIOs. Then we can just loop through the iio_chan_spec and clear the
392 * bits for found ADC channels.
393 */
394 gpio_channels = GENMASK(31, 0);
395 for (i = 0; i < num_channels; i++)
396 gpio_channels &= ~BIT(cs[i].channel);
397
398 return gpio_channels;
399 }
400
401 /* ADC channels as named in the data-sheet */
402 static const char * const bd79112_chan_names[] = {
403 "AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", /* 0 - 3 */
404 "AGIO4A", "AGIO5A", "AGIO6A", "AGIO7A", /* 4 - 7 */
405 "AGIO8A", "AGIO9A", "AGIO10A", "AGIO11A", /* 8 - 11 */
406 "AGIO12A", "AGIO13A", "AGIO14A", "AGIO15A", /* 12 - 15 */
407 "AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B", /* 16 - 19 */
408 "AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B", /* 20 - 23 */
409 "AGIO8B", "AGIO9B", "AGIO10B", "AGIO11B", /* 24 - 27 */
410 "AGIO12B", "AGIO13B", "AGIO14B", "AGIO15B", /* 28 - 31 */
411 };
412
bd79112_probe(struct spi_device * spi)413 static int bd79112_probe(struct spi_device *spi)
414 {
415 struct bd79112_data *data;
416 struct iio_dev *iio_dev;
417 struct iio_chan_spec *cs;
418 struct device *dev = &spi->dev;
419 unsigned long gpio_pins, pin;
420 unsigned int i;
421 int ret;
422
423 iio_dev = devm_iio_device_alloc(dev, sizeof(*data));
424 if (!iio_dev)
425 return -ENOMEM;
426
427 data = iio_priv(iio_dev);
428 data->spi = spi;
429 data->dev = dev;
430 data->map = devm_regmap_init(dev, NULL, data, &bd79112_regmap);
431 if (IS_ERR(data->map))
432 return dev_err_probe(dev, PTR_ERR(data->map),
433 "Failed to initialize Regmap\n");
434
435 ret = devm_regulator_get_enable_read_voltage(dev, "vdd");
436 if (ret < 0)
437 return dev_err_probe(dev, ret, "Failed to get the Vdd\n");
438
439 data->vref_mv = ret / 1000;
440
441 ret = devm_regulator_get_enable(dev, "iovdd");
442 if (ret < 0)
443 return dev_err_probe(dev, ret, "Failed to enable I/O voltage\n");
444
445 data->read_xfer[0].tx_buf = &data->read_tx[0];
446 data->read_xfer[0].len = sizeof(data->read_tx);
447 data->read_xfer[0].cs_change = 1;
448 data->read_xfer[1].rx_buf = &data->read_rx;
449 data->read_xfer[1].len = sizeof(data->read_rx);
450 spi_message_init_with_transfers(&data->read_msg, data->read_xfer, 2);
451 ret = devm_spi_optimize_message(dev, spi, &data->read_msg);
452 if (ret < 0)
453 return dev_err_probe(dev, ret,
454 "Failed to optimize SPI read message\n");
455
456 data->write_xfer.tx_buf = &data->reg_write_tx[0];
457 data->write_xfer.len = sizeof(data->reg_write_tx);
458 spi_message_init_with_transfers(&data->write_msg, &data->write_xfer, 1);
459 ret = devm_spi_optimize_message(dev, spi, &data->write_msg);
460 if (ret < 0)
461 return dev_err_probe(dev, ret,
462 "Failed to optimize SPI write message\n");
463
464 ret = devm_iio_adc_device_alloc_chaninfo_se(dev, &bd79112_chan_template,
465 BD79112_MAX_NUM_CHANNELS - 1,
466 &cs);
467
468 /* Register all pins as GPIOs if there are no ADC channels */
469 if (ret == -ENOENT)
470 goto register_gpios;
471
472 if (ret < 0)
473 return ret;
474
475 iio_dev->num_channels = ret;
476 iio_dev->channels = cs;
477
478 for (i = 0; i < iio_dev->num_channels; i++)
479 cs[i].datasheet_name = bd79112_chan_names[cs[i].channel];
480
481 iio_dev->info = &bd79112_info;
482 iio_dev->name = "bd79112";
483 iio_dev->modes = INDIO_DIRECT_MODE;
484
485 /*
486 * Ensure all channels are ADCs. This allows us to register the IIO
487 * device early (before checking which pins are to be used for GPIO)
488 * without having to worry about some pins being initially used for
489 * GPIO.
490 */
491 for (i = 0; i < BD79112_NUM_GPIO_EN_REGS; i++) {
492 ret = regmap_write(data->map, BD79112_FIRST_GPIO_EN_REG + i, 0);
493 if (ret)
494 return dev_err_probe(dev, ret,
495 "Failed to initialize channels\n");
496 }
497
498 ret = devm_iio_device_register(data->dev, iio_dev);
499 if (ret)
500 return dev_err_probe(data->dev, ret, "Failed to register ADC\n");
501
502 register_gpios:
503 gpio_pins = bd79112_get_gpio_pins(iio_dev->channels,
504 iio_dev->num_channels);
505
506 /* If all channels are reserved for ADC, then we're done. */
507 if (!gpio_pins)
508 return 0;
509
510 /* Default all the GPIO pins to GPI */
511 for_each_set_bit(pin, &gpio_pins, BD79112_MAX_NUM_CHANNELS) {
512 ret = bd79112_gpio_dir_set(data, pin, GPIO_LINE_DIRECTION_IN);
513 if (ret)
514 return dev_err_probe(dev, ret,
515 "Failed to mark pin as GPI\n");
516 }
517
518 data->gpio_valid_mask = gpio_pins;
519 data->gc = bd79112_gpio_chip;
520 data->gc.parent = dev;
521
522 return devm_gpiochip_add_data(dev, &data->gc, data);
523 }
524
525 static const struct of_device_id bd79112_of_match[] = {
526 { .compatible = "rohm,bd79112" },
527 { }
528 };
529 MODULE_DEVICE_TABLE(of, bd79112_of_match);
530
531 static const struct spi_device_id bd79112_id[] = {
532 { "bd79112" },
533 { }
534 };
535 MODULE_DEVICE_TABLE(spi, bd79112_id);
536
537 static struct spi_driver bd79112_driver = {
538 .driver = {
539 .name = "bd79112",
540 .of_match_table = bd79112_of_match,
541 },
542 .probe = bd79112_probe,
543 .id_table = bd79112_id,
544 };
545 module_spi_driver(bd79112_driver);
546
547 MODULE_AUTHOR("Matti Vaittinen <mazziesaccount@gmail.com>");
548 MODULE_DESCRIPTION("Driver for ROHM BD79112 ADC/GPIO");
549 MODULE_LICENSE("GPL");
550 MODULE_IMPORT_NS("IIO_DRIVER");
551