xref: /linux/drivers/gpu/nova-core/fb/hal/tu102.rs (revision 6dfafbd0299a60bfb5d5e277fdf100037c7ded07)
1 // SPDX-License-Identifier: GPL-2.0
2 
3 use kernel::prelude::*;
4 
5 use crate::{
6     driver::Bar0,
7     fb::hal::FbHal,
8     regs, //
9 };
10 
11 /// Shift applied to the sysmem address before it is written into `NV_PFB_NISO_FLUSH_SYSMEM_ADDR`,
12 /// to be used by HALs.
13 pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8;
14 
15 pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 {
16     u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
17 }
18 
19 pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {
20     // Check that the address doesn't overflow the receiving 32-bit register.
21     u32::try_from(addr >> FLUSH_SYSMEM_ADDR_SHIFT)
22         .map_err(|_| EINVAL)
23         .map(|addr| {
24             regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default()
25                 .set_adr_39_08(addr)
26                 .write(bar)
27         })
28 }
29 
30 pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool {
31     !regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
32 }
33 
34 pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
35     regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE::read(bar).usable_fb_size()
36 }
37 
38 struct Tu102;
39 
40 impl FbHal for Tu102 {
41     fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {
42         read_sysmem_flush_page_gm107(bar)
43     }
44 
45     fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {
46         write_sysmem_flush_page_gm107(bar, addr)
47     }
48 
49     fn supports_display(&self, bar: &Bar0) -> bool {
50         display_enabled_gm107(bar)
51     }
52 
53     fn vidmem_size(&self, bar: &Bar0) -> u64 {
54         vidmem_size_gp102(bar)
55     }
56 }
57 
58 const TU102: Tu102 = Tu102;
59 pub(super) const TU102_HAL: &dyn FbHal = &TU102;
60