1 /*
2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
35
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <linux/atomic.h>
39 #include <linux/wait.h>
40 #include <linux/xarray.h>
41 #include <net/devlink.h>
42 #include <linux/mlx5/device.h>
43 #include <linux/mlx5/eswitch.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/fs.h>
46 #include "lib/mpfs.h"
47 #include "lib/fs_chains.h"
48 #include "sf/sf.h"
49 #include "en/tc_ct.h"
50 #include "en/tc/sample.h"
51
52 enum mlx5_mapped_obj_type {
53 MLX5_MAPPED_OBJ_CHAIN,
54 MLX5_MAPPED_OBJ_SAMPLE,
55 MLX5_MAPPED_OBJ_INT_PORT_METADATA,
56 MLX5_MAPPED_OBJ_ACT_MISS,
57 };
58
59 struct mlx5_mapped_obj {
60 enum mlx5_mapped_obj_type type;
61 union {
62 u32 chain;
63 u64 act_miss_cookie;
64 struct {
65 u32 group_id;
66 u32 rate;
67 u32 trunc_size;
68 u32 tunnel_id;
69 } sample;
70 u32 int_port_metadata;
71 };
72 };
73
74 struct mlx5_esw_pf_info {
75 bool pf_not_exist;
76 bool pf_disabled;
77 u16 num_of_vfs;
78 u16 total_vfs;
79 u16 host_number;
80 u16 pf_num;
81 };
82
83 #ifdef CONFIG_MLX5_ESWITCH
84
85 #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15
86
87 #define MLX5_MAX_UC_PER_VPORT(dev) \
88 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
89
90 #define MLX5_MAX_MC_PER_VPORT(dev) \
91 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
92
93 #define mlx5_esw_has_fwd_fdb(dev) \
94 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
95
96 #define esw_chains(esw) \
97 ((esw)->fdb_table.offloads.esw_chains_priv)
98
99 enum {
100 MAPPING_TYPE_CHAIN,
101 MAPPING_TYPE_TUNNEL,
102 MAPPING_TYPE_TUNNEL_ENC_OPTS,
103 MAPPING_TYPE_LABELS,
104 MAPPING_TYPE_ZONE,
105 MAPPING_TYPE_INT_PORT,
106 };
107
108 struct vport_ingress {
109 struct mlx5_flow_table *acl;
110 struct mlx5_flow_handle *allow_rule;
111 struct {
112 struct mlx5_flow_group *allow_spoofchk_only_grp;
113 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
114 struct mlx5_flow_group *allow_untagged_only_grp;
115 struct mlx5_flow_group *drop_grp;
116 struct mlx5_flow_handle *drop_rule;
117 struct mlx5_fc *drop_counter;
118 } legacy;
119 struct {
120 /* Optional group to add an FTE to do internal priority
121 * tagging on ingress packets.
122 */
123 struct mlx5_flow_group *metadata_prio_tag_grp;
124 /* Group to add default match-all FTE entry to tag ingress
125 * packet with metadata.
126 */
127 struct mlx5_flow_group *metadata_allmatch_grp;
128 /* Optional group to add a drop all rule */
129 struct mlx5_flow_group *drop_grp;
130 struct mlx5_modify_hdr *modify_metadata;
131 struct mlx5_flow_handle *modify_metadata_rule;
132 struct mlx5_flow_handle *drop_rule;
133 } offloads;
134 };
135
136 enum vport_egress_acl_type {
137 VPORT_EGRESS_ACL_TYPE_DEFAULT,
138 VPORT_EGRESS_ACL_TYPE_SHARED_FDB,
139 };
140
141 struct vport_egress {
142 struct mlx5_flow_table *acl;
143 enum vport_egress_acl_type type;
144 struct mlx5_flow_handle *allowed_vlan;
145 struct mlx5_flow_group *vlan_grp;
146 union {
147 struct {
148 struct mlx5_flow_group *drop_grp;
149 struct mlx5_flow_handle *drop_rule;
150 struct mlx5_fc *drop_counter;
151 } legacy;
152 struct {
153 struct mlx5_flow_group *fwd_grp;
154 struct mlx5_flow_handle *fwd_rule;
155 struct xarray bounce_rules;
156 struct mlx5_flow_group *bounce_grp;
157 } offloads;
158 };
159 };
160
161 struct mlx5_vport_drop_stats {
162 u64 rx_dropped;
163 u64 tx_dropped;
164 };
165
166 struct mlx5_vport_info {
167 u8 mac[ETH_ALEN];
168 u16 vlan;
169 u64 node_guid;
170 int link_state;
171 u8 qos;
172 u8 spoofchk: 1;
173 u8 trusted: 1;
174 u8 roce_enabled: 1;
175 u8 mig_enabled: 1;
176 u8 ipsec_crypto_enabled: 1;
177 u8 ipsec_packet_enabled: 1;
178 };
179
180 /* Vport context events */
181 enum mlx5_eswitch_vport_event {
182 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0),
183 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1),
184 MLX5_VPORT_PROMISC_CHANGE = BIT(3),
185 };
186
187 struct mlx5_vport;
188
189 struct mlx5_devlink_port {
190 struct devlink_port dl_port;
191 struct mlx5_vport *vport;
192 };
193
mlx5_devlink_port_init(struct mlx5_devlink_port * dl_port,struct mlx5_vport * vport)194 static inline void mlx5_devlink_port_init(struct mlx5_devlink_port *dl_port,
195 struct mlx5_vport *vport)
196 {
197 dl_port->vport = vport;
198 }
199
mlx5_devlink_port_get(struct devlink_port * dl_port)200 static inline struct mlx5_devlink_port *mlx5_devlink_port_get(struct devlink_port *dl_port)
201 {
202 return container_of(dl_port, struct mlx5_devlink_port, dl_port);
203 }
204
mlx5_devlink_port_vport_get(struct devlink_port * dl_port)205 static inline struct mlx5_vport *mlx5_devlink_port_vport_get(struct devlink_port *dl_port)
206 {
207 return mlx5_devlink_port_get(dl_port)->vport;
208 }
209
210 #define MLX5_VHCA_ID_INVALID (-1)
211
212 #define MLX5_VPORT_INVAL_VHCA_ID(vport) \
213 ((vport)->vhca_id == MLX5_VHCA_ID_INVALID)
214
215 struct mlx5_vport {
216 struct mlx5_core_dev *dev;
217 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
218 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
219 struct mlx5_flow_handle *promisc_rule;
220 struct mlx5_flow_handle *allmulti_rule;
221 struct work_struct vport_change_handler;
222
223 struct vport_ingress ingress;
224 struct vport_egress egress;
225 u32 default_metadata;
226 u32 metadata;
227 int vhca_id;
228
229 bool adjacent; /* delegated vhca from adjacent function */
230 struct {
231 u16 parent_pci_devfn; /* Adjacent parent PCI device function */
232 u16 function_id; /* Function ID of the delegated VPort */
233 } adj_info;
234
235 struct mlx5_vport_info info;
236
237 /* Protected by either the shared devlink (dev->shd) lock or by
238 * esw->state_lock. See esw_assert_qos_lock_held() for more details.
239 * The Vport QoS can either be disabled (sched_node is NULL) or in one
240 * of three states:
241 * 1. Regular QoS (sched_node is a vport node).
242 * 2. TC QoS enabled on the vport (sched_node is a TC arbiter).
243 * 3. TC QoS enabled on the vport's parent node
244 * (sched_node is a rate limit node).
245 * When TC is enabled in either mode, the vport owns vport TC scheduling
246 * nodes.
247 */
248 struct {
249 /* Vport scheduling node. */
250 struct mlx5_esw_sched_node *sched_node;
251 /* Array of vport traffic class scheduling nodes. */
252 struct mlx5_esw_sched_node **sched_nodes;
253 } qos;
254
255 u16 vport;
256 bool enabled;
257 bool max_eqs_set;
258 bool pf_activated;
259 enum mlx5_eswitch_vport_event enabled_events;
260 int index;
261 struct mlx5_devlink_port *dl_port;
262 u32 agg_max_tx_speed;
263 };
264
265 struct mlx5_esw_indir_table;
266
267 struct mlx5_eswitch_fdb {
268 union {
269 struct legacy_fdb {
270 struct mlx5_flow_table *fdb;
271 struct mlx5_flow_group *addr_grp;
272 struct mlx5_flow_group *allmulti_grp;
273 struct mlx5_flow_group *promisc_grp;
274 struct mlx5_flow_table *vepa_fdb;
275 struct mlx5_flow_handle *vepa_uplink_rule;
276 struct mlx5_flow_handle *vepa_star_rule;
277 } legacy;
278
279 struct offloads_fdb {
280 struct mlx5_flow_namespace *ns;
281 struct mlx5_flow_table *drop_root;
282 struct mlx5_flow_handle *drop_root_rule;
283 struct mlx5_fc *drop_root_fc;
284 struct mlx5_flow_table *tc_miss_table;
285 struct mlx5_flow_table *slow_fdb;
286 struct mlx5_flow_group *send_to_vport_grp;
287 struct mlx5_flow_group *send_to_vport_meta_grp;
288 struct mlx5_flow_group *peer_miss_grp;
289 struct xarray peer_miss_rules;
290 struct mlx5_flow_group *miss_grp;
291 struct mlx5_flow_handle **send_to_vport_meta_rules;
292 struct mlx5_flow_handle *miss_rule_uni;
293 struct mlx5_flow_handle *miss_rule_multi;
294
295 struct mlx5_fs_chains *esw_chains_priv;
296 struct {
297 DECLARE_HASHTABLE(table, 8);
298 /* Protects vports.table */
299 struct mutex lock;
300 } vports;
301
302 struct mlx5_esw_indir_table *indir;
303
304 } offloads;
305 };
306 u32 flags;
307 };
308
309 struct mlx5_esw_offload {
310 struct mlx5_flow_table *ft_offloads_restore;
311 struct mlx5_flow_group *restore_group;
312 struct mlx5_modify_hdr *restore_copy_hdr_id;
313 struct mapping_ctx *reg_c0_obj_pool;
314
315 struct mlx5_flow_table *ft_offloads;
316 struct mlx5_flow_group *vport_rx_group;
317 struct mlx5_flow_group *vport_rx_drop_group;
318 struct mlx5_flow_handle *vport_rx_drop_rule;
319 struct mlx5_flow_table *ft_ipsec_tx_pol;
320 struct xarray vport_reps;
321 struct list_head peer_flows[MLX5_MAX_PORTS];
322 struct mutex peer_mutex;
323 struct mutex encap_tbl_lock; /* protects encap_tbl */
324 DECLARE_HASHTABLE(encap_tbl, 8);
325 struct mutex decap_tbl_lock; /* protects decap_tbl */
326 DECLARE_HASHTABLE(decap_tbl, 8);
327 struct mod_hdr_tbl mod_hdr;
328 DECLARE_HASHTABLE(termtbl_tbl, 8);
329 struct mutex termtbl_mutex; /* protects termtbl hash */
330 struct xarray vhca_map;
331 struct mutex reps_lock; /* protects representor load/unload/register */
332 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES];
333 u8 inline_mode;
334 atomic64_t num_flows;
335 u64 num_block_encap;
336 u64 num_block_mode;
337 enum devlink_eswitch_encap_mode encap;
338 struct ida vport_metadata_ida;
339 };
340
341 /* E-Switch MC FDB table hash node */
342 struct esw_mc_addr { /* SRIOV only */
343 struct l2addr_node node;
344 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
345 u32 refcnt;
346 };
347
348 struct mlx5_host_work {
349 struct work_struct work;
350 struct mlx5_eswitch *esw;
351 int work_gen;
352 void (*func)(struct mlx5_eswitch *esw);
353 };
354
355 struct mlx5_esw_spf {
356 u16 vport_num;
357 u16 vhca_id;
358 u16 host_number;
359 u16 pf_num;
360 };
361
362 struct mlx5_esw_functions {
363 struct mlx5_nb nb;
364 bool host_funcs_disabled;
365 u16 num_vfs;
366 u16 num_ec_vfs;
367 u16 hpf_host_number;
368 u16 hpf_pf_num;
369 bool has_spf_sfs;
370 struct mlx5_esw_spf *spfs;
371 int num_spfs;
372 };
373
374 enum {
375 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0),
376 MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1),
377 MLX5_ESWITCH_VPORT_ACL_NS_CREATED = BIT(2),
378 };
379
380 struct mlx5_esw_bridge_offloads;
381
382 enum {
383 MLX5_ESW_FDB_CREATED = BIT(0),
384 };
385
386 struct dentry;
387
388 struct mlx5_eswitch {
389 struct mlx5_core_dev *dev;
390 struct mlx5_nb nb;
391 struct mlx5_eswitch_fdb fdb_table;
392 /* legacy data structures */
393 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
394 struct esw_mc_addr mc_promisc;
395 /* end of legacy */
396 struct dentry *debugfs_root;
397 struct workqueue_struct *work_queue;
398 struct xarray vports;
399 struct xarray vhca_type_map;
400 u32 flags;
401 int total_vports;
402 int enabled_vports;
403 /* Synchronize between vport change events
404 * and async SRIOV admin state changes
405 */
406 struct mutex state_lock;
407
408 /* Protects eswitch mode change that occurs via one or more
409 * user commands, i.e. sriov state change, devlink commands.
410 */
411 struct rw_semaphore mode_lock;
412 atomic64_t user_count;
413 wait_queue_head_t work_queue_wait;
414
415 /* QoS changes are serialized by either the shared devlink (dev->shd)
416 * lock or by esw->state_lock. See esw_assert_qos_lock_held() for more
417 * details.
418 */
419 struct {
420 /* Initially 0, meaning no QoS users and QoS is disabled. */
421 refcount_t refcnt;
422 /* The root node of the hierarchy. */
423 struct mlx5_esw_sched_node *root;
424 } qos;
425
426 struct mlx5_esw_bridge_offloads *br_offloads;
427 struct mlx5_esw_offload offloads;
428 u32 last_vport_idx;
429 int mode;
430 bool offloads_inactive;
431 u16 manager_vport;
432 u16 first_host_vport;
433 u8 num_peers;
434 struct mlx5_esw_functions esw_funcs;
435 struct {
436 u32 large_group_num;
437 } params;
438 struct xarray paired;
439 struct mlx5_devcom_comp_dev *devcom;
440 u16 enabled_ipsec_vf_count;
441 bool eswitch_operation_in_progress;
442 atomic_t generation;
443 };
444
445 void esw_offloads_disable(struct mlx5_eswitch *esw);
446 int esw_offloads_enable(struct mlx5_eswitch *esw);
447 int mlx5_esw_offloads_init_deferred_metadata(struct mlx5_eswitch *esw);
448 void esw_offloads_cleanup(struct mlx5_eswitch *esw);
449 int esw_offloads_init(struct mlx5_eswitch *esw);
450
451 struct mlx5_flow_handle *
452 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num);
453 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule);
454
455 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw);
456 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw);
457 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata);
458
459 int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 rate_mbps);
460
461 /* E-Switch API */
462 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
463 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
464 int mlx5_esw_vport_alloc(struct mlx5_eswitch *esw, int index, u16 vport_num);
465 void mlx5_esw_vport_free(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
466
467 #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1)
468 int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int num_vfs);
469 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs);
470 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf);
471 void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw);
472 void mlx5_eswitch_disable(struct mlx5_eswitch *esw);
473 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw,
474 const struct mlx5_devcom_match_attr *attr);
475 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw);
476 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw);
477 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
478 u16 vport, const u8 *mac);
479 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
480 u16 vport, int link_state);
481 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
482 u16 vport, u16 vlan, u8 qos);
483 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
484 u16 vport, bool spoofchk);
485 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
486 u16 vport_num, bool setting);
487 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
488 u32 max_rate, u32 min_rate);
489 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
490 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
491 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
492 u16 vport, struct ifla_vf_info *ivi);
493 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
494 u16 vport,
495 struct ifla_vf_stats *vf_stats);
496 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
497
498 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport,
499 bool other_vport, void *in);
500
501 struct mlx5_flow_spec;
502 struct mlx5_esw_flow_attr;
503 struct mlx5_termtbl_handle;
504
505 bool
506 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw,
507 struct mlx5_flow_attr *attr,
508 struct mlx5_flow_act *flow_act,
509 struct mlx5_flow_spec *spec);
510
511 struct mlx5_flow_handle *
512 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw,
513 struct mlx5_flow_table *ft,
514 struct mlx5_flow_spec *spec,
515 struct mlx5_esw_flow_attr *attr,
516 struct mlx5_flow_act *flow_act,
517 struct mlx5_flow_destination *dest,
518 int num_dest);
519
520 void
521 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw,
522 struct mlx5_termtbl_handle *tt);
523
524 void
525 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec);
526
527 struct mlx5_flow_handle *
528 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
529 struct mlx5_flow_spec *spec,
530 struct mlx5_flow_attr *attr);
531 struct mlx5_flow_handle *
532 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
533 struct mlx5_flow_spec *spec,
534 struct mlx5_flow_attr *attr);
535 void
536 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
537 struct mlx5_flow_handle *rule,
538 struct mlx5_flow_attr *attr);
539 void
540 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
541 struct mlx5_flow_handle *rule,
542 struct mlx5_flow_attr *attr);
543
544 struct mlx5_flow_handle *
545 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
546 struct mlx5_flow_destination *dest);
547
548 enum {
549 SET_VLAN_STRIP = BIT(0),
550 SET_VLAN_INSERT = BIT(1)
551 };
552
553 enum mlx5_flow_match_level {
554 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
555 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
556 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
557 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
558 };
559
560 /* current maximum for flow based vport multicasting */
561 #define MLX5_MAX_FLOW_FWD_VPORTS 32
562
563 enum {
564 MLX5_ESW_DEST_ENCAP = BIT(0),
565 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
566 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE = BIT(2),
567 };
568
569 struct mlx5_esw_flow_attr {
570 struct mlx5_eswitch_rep *in_rep;
571 struct mlx5_core_dev *in_mdev;
572 struct mlx5_core_dev *counter_dev;
573 struct mlx5e_tc_int_port *dest_int_port;
574 struct mlx5e_tc_int_port *int_port;
575
576 int split_count;
577 int out_count;
578
579 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
580 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
581 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
582 u8 total_vlan;
583 struct {
584 u32 flags;
585 bool vport_valid;
586 u16 vport;
587 struct mlx5_pkt_reformat *pkt_reformat;
588 struct mlx5_core_dev *mdev;
589 struct mlx5_termtbl_handle *termtbl;
590 int src_port_rewrite_act_id;
591 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
592 struct mlx5_rx_tun_attr *rx_tun_attr;
593 struct ethhdr eth;
594 struct mlx5_pkt_reformat *decap_pkt_reformat;
595 };
596
597 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
598 struct netlink_ext_ack *extack);
599 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
600 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
601 struct netlink_ext_ack *extack);
602 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
603 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
604 enum devlink_eswitch_encap_mode encap,
605 struct netlink_ext_ack *extack);
606 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
607 enum devlink_eswitch_encap_mode *encap);
608 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
609 u8 *hw_addr, int *hw_addr_len,
610 struct netlink_ext_ack *extack);
611 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
612 const u8 *hw_addr, int hw_addr_len,
613 struct netlink_ext_ack *extack);
614 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
615 struct netlink_ext_ack *extack);
616 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
617 struct netlink_ext_ack *extack);
618 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
619 struct netlink_ext_ack *extack);
620 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
621 struct netlink_ext_ack *extack);
622 int mlx5_devlink_pf_port_fn_state_get(struct devlink_port *port,
623 enum devlink_port_fn_state *state,
624 enum devlink_port_fn_opstate *opstate,
625 struct netlink_ext_ack *extack);
626 int mlx5_devlink_pf_port_fn_state_set(struct devlink_port *port,
627 enum devlink_port_fn_state state,
628 struct netlink_ext_ack *extack);
629 #ifdef CONFIG_XFRM_OFFLOAD
630 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled,
631 struct netlink_ext_ack *extack);
632 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable,
633 struct netlink_ext_ack *extack);
634 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled,
635 struct netlink_ext_ack *extack);
636 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port, bool enable,
637 struct netlink_ext_ack *extack);
638 #endif /* CONFIG_XFRM_OFFLOAD */
639 int mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port,
640 u32 *max_io_eqs,
641 struct netlink_ext_ack *extack);
642 int mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port,
643 u32 max_io_eqs,
644 struct netlink_ext_ack *extack);
645 int mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port,
646 struct netlink_ext_ack *extack);
647
648 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
649
650 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
651 u16 vport, u16 vlan, u8 qos, u8 set_flags);
652
esw_vst_mode_is_steering(struct mlx5_eswitch * esw)653 static inline bool esw_vst_mode_is_steering(struct mlx5_eswitch *esw)
654 {
655 return (MLX5_CAP_ESW_EGRESS_ACL(esw->dev, pop_vlan) &&
656 MLX5_CAP_ESW_INGRESS_ACL(esw->dev, push_vlan));
657 }
658
mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev * dev,u8 vlan_depth)659 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
660 u8 vlan_depth)
661 {
662 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
663 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
664
665 if (vlan_depth == 1)
666 return ret;
667
668 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
669 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
670 }
671
672 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
673 struct mlx5_core_dev *dev1);
674
675 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev);
676 struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev,
677 const u32 *out);
678 bool mlx5_esw_get_spf_disabled(struct mlx5_core_dev *dev, const u32 *out,
679 u16 vhca_id);
680 int mlx5_esw_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num);
681 int mlx5_esw_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num);
682 int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev);
683 int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev);
684
685 void mlx5_esw_adjacent_vhcas_setup(struct mlx5_eswitch *esw);
686 void mlx5_esw_adjacent_vhcas_cleanup(struct mlx5_eswitch *esw);
687 int mlx5_esw_adj_vport_modify(struct mlx5_core_dev *dev, u16 vport,
688 bool connect);
689 int mlx5_esw_create_esw_vport(struct mlx5_core_dev *dev, u16 vhca_id,
690 u16 *vport_num);
691 void mlx5_esw_destroy_esw_vport(struct mlx5_core_dev *dev, u16 vport);
692
693 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
694
695 #define esw_info(__dev, format, ...) \
696 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
697
698 #define esw_warn(__dev, format, ...) \
699 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
700
701 #define esw_debug(dev, format, ...) \
702 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
703
mlx5_esw_allowed(const struct mlx5_eswitch * esw)704 static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw)
705 {
706 return esw && MLX5_ESWITCH_MANAGER(esw->dev);
707 }
708
709 static inline bool
mlx5_esw_is_manager_vport(const struct mlx5_eswitch * esw,u16 vport_num)710 mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num)
711 {
712 return esw->manager_vport == vport_num;
713 }
714
mlx5_esw_is_owner(struct mlx5_eswitch * esw,u16 vport_num,u16 esw_owner_vhca_id)715 static inline bool mlx5_esw_is_owner(struct mlx5_eswitch *esw, u16 vport_num,
716 u16 esw_owner_vhca_id)
717 {
718 return esw_owner_vhca_id == MLX5_CAP_GEN(esw->dev, vhca_id) ||
719 (vport_num == MLX5_VPORT_UPLINK && mlx5_lag_is_master(esw->dev));
720 }
721
mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev * dev)722 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev)
723 {
724 return mlx5_core_is_ecpf_esw_manager(dev) ?
725 MLX5_VPORT_HOST_PF : MLX5_VPORT_FIRST_HOST_VF;
726 }
727
mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev * dev)728 static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev)
729 {
730 return mlx5_core_is_ecpf_esw_manager(dev);
731 }
732
733 static inline unsigned int
mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev * dev,u16 vport_num)734 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev,
735 u16 vport_num)
736 {
737 return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num;
738 }
739
740 static inline u16
mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index)741 mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index)
742 {
743 return dl_port_index & 0xffff;
744 }
745
mlx5_esw_is_fdb_created(struct mlx5_eswitch * esw)746 static inline bool mlx5_esw_is_fdb_created(struct mlx5_eswitch *esw)
747 {
748 return esw->fdb_table.flags & MLX5_ESW_FDB_CREATED;
749 }
750
751 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */
752 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
753
754 /* Each mark identifies eswitch vport type.
755 * MLX5_ESW_VPT_HOST_FN is used to identify both PF and VF ports using
756 * a single mark.
757 * MLX5_ESW_VPT_VF identifies a SRIOV VF vport.
758 * MLX5_ESW_VPT_SF identifies SF vport.
759 */
760 #define MLX5_ESW_VPT_HOST_FN XA_MARK_0
761 #define MLX5_ESW_VPT_VF XA_MARK_1
762 #define MLX5_ESW_VPT_SF XA_MARK_2
763
764 /* The vport iterator is valid only after vport are initialized in mlx5_eswitch_init.
765 * Borrowed the idea from xa_for_each_marked() but with support for desired last element.
766 */
767
768 #define mlx5_esw_for_each_vport(esw, index, vport) \
769 xa_for_each(&((esw)->vports), index, vport)
770
771 #define mlx5_esw_for_each_entry_marked(xa, index, entry, last, filter) \
772 for (index = 0, entry = xa_find(xa, &index, last, filter); \
773 entry; entry = xa_find_after(xa, &index, last, filter))
774
775 #define mlx5_esw_for_each_vport_marked(esw, index, vport, last, filter) \
776 mlx5_esw_for_each_entry_marked(&((esw)->vports), index, vport, last, filter)
777
778 #define mlx5_esw_for_each_vf_vport(esw, index, vport, last) \
779 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_VF)
780
781 #define mlx5_esw_for_each_host_func_vport(esw, index, vport, last) \
782 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_HOST_FN)
783
784 /* This macro should only be used if EC SRIOV is enabled.
785 *
786 * Because there were no more marks available on the xarray this uses a
787 * for_each_range approach. The range is only valid when EC SRIOV is enabled
788 */
789 #define mlx5_esw_for_each_ec_vf_vport(esw, index, vport, last) \
790 xa_for_each_range(&((esw)->vports), \
791 index, \
792 vport, \
793 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base), \
794 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base) +\
795 (last) - 1)
796
797 /* SPF vport numbers are not contiguous, iterate via the spfs array
798 * and look up each vport in the xarray.
799 */
800 #define mlx5_esw_for_each_spf_vport(esw, index, vport) \
801 for ((index) = 0; \
802 (index) < (esw)->esw_funcs.num_spfs && \
803 ((vport) = xa_load(&(esw)->vports, \
804 (esw)->esw_funcs.spfs[(index)].vport_num)); \
805 (index)++)
806
807 #define mlx5_esw_for_each_rep(esw, i, rep) \
808 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
809
810 struct mlx5_eswitch *__must_check
811 mlx5_devlink_eswitch_get(struct devlink *devlink);
812
813 struct mlx5_eswitch *mlx5_devlink_eswitch_nocheck_get(struct devlink *devlink);
814
815 struct mlx5_vport *__must_check
816 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
817
818 bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *esw, u16 vport_num);
819 int mlx5_esw_spf_vport_to_idx(struct mlx5_eswitch *esw, u16 vport_num);
820 bool mlx5_esw_is_spf_vport(struct mlx5_eswitch *esw, u16 vport_num);
821 bool mlx5_eswitch_is_pf_vf_vport(struct mlx5_eswitch *esw, u16 vport_num);
822 bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num);
823
824 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data);
825
826 int
827 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
828 enum mlx5_eswitch_vport_event enabled_events);
829 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw);
830
831 int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
832 enum mlx5_eswitch_vport_event enabled_events);
833 void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
834
835 int
836 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
837 struct mlx5_vport *vport);
838 void
839 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
840 struct mlx5_vport *vport);
841
842 struct esw_vport_tbl_namespace {
843 int max_fte;
844 int max_num_groups;
845 u32 flags;
846 };
847
848 struct mlx5_vport_tbl_attr {
849 u32 chain;
850 u16 prio;
851 u16 vport;
852 struct esw_vport_tbl_namespace *vport_ns;
853 };
854
855 struct mlx5_flow_table *
856 mlx5_esw_vporttbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr);
857 void
858 mlx5_esw_vporttbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr);
859
860 struct mlx5_flow_handle *
861 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag);
862
863 void mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
864 u32 *flow_group_in,
865 int match_params);
866
867 void mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
868 u16 vport,
869 struct mlx5_flow_spec *spec);
870
871 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
872 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
873
874 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
875 struct mlx5_devlink_port *dl_port,
876 u32 controller, u32 sfnum);
877 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
878
879 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
880 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
881
882 int mlx5_eswitch_load_sf_vport(struct mlx5_eswitch *esw, u16 vport_num,
883 enum mlx5_eswitch_vport_event enabled_events,
884 struct mlx5_devlink_port *dl_port, u32 controller, u32 sfnum);
885 void mlx5_eswitch_unload_sf_vport(struct mlx5_eswitch *esw, u16 vport_num);
886
887 int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs,
888 enum mlx5_eswitch_vport_event enabled_events);
889 void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs);
890
891 int mlx5_esw_offloads_pf_vf_devlink_port_init(struct mlx5_eswitch *esw,
892 struct mlx5_vport *vport);
893 void mlx5_esw_offloads_pf_vf_devlink_port_cleanup(struct mlx5_eswitch *esw,
894 struct mlx5_vport *vport);
895
896 int mlx5_esw_offloads_sf_devlink_port_init(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
897 struct mlx5_devlink_port *dl_port,
898 u32 controller, u32 sfnum);
899 void mlx5_esw_offloads_sf_devlink_port_cleanup(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
900
901 int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
902 void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_vport *vport);
903 struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num);
904
905 int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, u16 *sf_base_id);
906 int mlx5_esw_sf_max_spf_functions(struct mlx5_core_dev *dev, int spf_idx,
907 u16 *max_sfs, u16 *sf_base_id);
908
909 int mlx5_esw_get_num_spfs(struct mlx5_core_dev *dev);
910 int mlx5_esw_spf_get_host_number(struct mlx5_core_dev *dev, int spf_idx,
911 u16 *host_number);
912 u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev);
913 u16 mlx5_esw_get_hpf_pf_num(struct mlx5_core_dev *dev);
914 u16 mlx5_esw_sf_controller_to_pfnum(struct mlx5_core_dev *dev, u32 controller);
915 bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev);
916
917 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw,
918 struct mlx5_vport *vport);
919 void mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch *esw,
920 struct mlx5_vport *vport);
921 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num);
922 bool mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id);
923 u16 mlx5_esw_vhca_id_to_func_type(struct mlx5_core_dev *dev, u16 vhca_id);
924
925 void mlx5_esw_offloads_rep_remove(struct mlx5_eswitch *esw,
926 const struct mlx5_vport *vport);
927 int mlx5_esw_offloads_rep_add(struct mlx5_eswitch *esw,
928 const struct mlx5_vport *vport);
929
930 /**
931 * struct mlx5_esw_event_info - Indicates eswitch mode changed/changing.
932 *
933 * @new_mode: New mode of eswitch.
934 */
935 struct mlx5_esw_event_info {
936 u16 new_mode;
937 };
938
939 int mlx5_esw_event_notifier_register(struct mlx5_core_dev *dev,
940 struct notifier_block *n);
941 void mlx5_esw_event_notifier_unregister(struct mlx5_core_dev *dev,
942 struct notifier_block *n);
943
944 bool mlx5_esw_hold(struct mlx5_core_dev *dev);
945 void mlx5_esw_release(struct mlx5_core_dev *dev);
946 void mlx5_esw_get(struct mlx5_core_dev *dev);
947 void mlx5_esw_put(struct mlx5_core_dev *dev);
948 int mlx5_esw_try_lock(struct mlx5_eswitch *esw);
949 int mlx5_esw_lock(struct mlx5_eswitch *esw);
950 void mlx5_esw_unlock(struct mlx5_eswitch *esw);
951
952 void esw_vport_change_handle_locked(struct mlx5_vport *vport);
953
954 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller);
955
956 int mlx5_eswitch_offloads_vport_lag_add_one(struct mlx5_eswitch *master_esw,
957 struct mlx5_eswitch *slave_esw);
958 void mlx5_eswitch_offloads_vport_lag_del_one(struct mlx5_eswitch *master_esw,
959 struct mlx5_eswitch *slave_esw);
960 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
961 struct mlx5_eswitch *slave_esw, int max_slaves);
962 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
963 struct mlx5_eswitch *slave_esw);
964 int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw);
965 void mlx5_eswitch_unload_reps(struct mlx5_eswitch *esw);
966 bool mlx5_eswitch_is_peer(struct mlx5_eswitch *esw,
967 struct mlx5_eswitch *peer_esw);
968
969 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb);
970 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev);
971
972 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev);
973 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev);
974
mlx5_eswitch_num_vfs(struct mlx5_eswitch * esw)975 static inline int mlx5_eswitch_num_vfs(struct mlx5_eswitch *esw)
976 {
977 if (mlx5_esw_allowed(esw))
978 return esw->esw_funcs.num_vfs;
979
980 return 0;
981 }
982
983 static inline struct mlx5_flow_table *
mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch * esw)984 mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch *esw)
985 {
986 return esw->fdb_table.offloads.slow_fdb;
987 }
988
989 int mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule,
990 struct mlx5_esw_flow_attr *esw_attr, int attr_idx);
991 bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev);
992 void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev);
993 bool mlx5_esw_ipsec_vf_offload_supported(struct mlx5_core_dev *dev);
994 int mlx5_esw_ipsec_vf_offload_get(struct mlx5_core_dev *dev,
995 struct mlx5_vport *vport);
996 int mlx5_esw_ipsec_vf_crypto_offload_supported(struct mlx5_core_dev *dev,
997 u16 vport_num);
998 int mlx5_esw_ipsec_vf_crypto_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
999 bool enable);
1000 int mlx5_esw_ipsec_vf_packet_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
1001 bool enable);
1002 int mlx5_esw_ipsec_vf_packet_offload_supported(struct mlx5_core_dev *dev,
1003 u16 vport_num);
1004 bool mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev);
1005 void mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev *dev);
1006 struct mlx5_flow_group *
1007 mlx5_esw_lag_demux_fg_create(struct mlx5_eswitch *esw,
1008 struct mlx5_flow_table *ft);
1009 struct mlx5_flow_handle *
1010 mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num,
1011 struct mlx5_flow_table *lag_ft);
1012 void mlx5_esw_reps_block(struct mlx5_eswitch *esw);
1013 void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw);
1014 #else /* CONFIG_MLX5_ESWITCH */
1015 /* eswitch API stubs */
mlx5_eswitch_init(struct mlx5_core_dev * dev)1016 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
mlx5_eswitch_cleanup(struct mlx5_eswitch * esw)1017 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
mlx5_eswitch_enable(struct mlx5_eswitch * esw,int num_vfs)1018 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; }
mlx5_eswitch_disable_sriov(struct mlx5_eswitch * esw,bool clear_vf)1019 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf) {}
mlx5_eswitch_disable(struct mlx5_eswitch * esw)1020 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {}
1021 static inline void
mlx5_esw_offloads_devcom_init(struct mlx5_eswitch * esw,const struct mlx5_devcom_match_attr * attr)1022 mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw,
1023 const struct mlx5_devcom_match_attr *attr) {}
mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch * esw)1024 static inline void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw) {}
mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch * esw)1025 static inline bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw) { return false; }
mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev * dev)1026 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
1027 static inline
mlx5_eswitch_set_vport_state(struct mlx5_eswitch * esw,u16 vport,int link_state)1028 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; }
mlx5_esw_query_functions(struct mlx5_core_dev * dev)1029 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev)
1030 {
1031 return ERR_PTR(-EOPNOTSUPP);
1032 }
1033
1034 static inline struct mlx5_esw_pf_info
mlx5_esw_get_host_pf_info(struct mlx5_core_dev * dev,const u32 * out)1035 mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, const u32 *out)
1036 {
1037 return (struct mlx5_esw_pf_info) {};
1038 }
1039
1040 static inline struct mlx5_flow_handle *
esw_add_restore_rule(struct mlx5_eswitch * esw,u32 tag)1041 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1042 {
1043 return ERR_PTR(-EOPNOTSUPP);
1044 }
1045
1046 static inline unsigned int
mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev * dev,u16 vport_num)1047 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev,
1048 u16 vport_num)
1049 {
1050 return vport_num;
1051 }
1052
1053 static inline int
mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw,int max_slaves)1054 mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
1055 struct mlx5_eswitch *slave_esw, int max_slaves)
1056 {
1057 return 0;
1058 }
1059
1060 static inline void
mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw)1061 mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
1062 struct mlx5_eswitch *slave_esw) {}
1063
1064 static inline int
mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch * esw)1065 mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw)
1066 {
1067 return 0;
1068 }
1069
1070 static inline void
mlx5_eswitch_unload_reps(struct mlx5_eswitch * esw)1071 mlx5_eswitch_unload_reps(struct mlx5_eswitch *esw) {}
1072
1073 static inline bool
mlx5_eswitch_block_encap(struct mlx5_core_dev * dev,bool from_fdb)1074 mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb)
1075 {
1076 return true;
1077 }
1078
mlx5_eswitch_unblock_encap(struct mlx5_core_dev * dev)1079 static inline void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
1080 {
1081 }
1082
mlx5_eswitch_block_mode(struct mlx5_core_dev * dev)1083 static inline int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev) { return 0; }
mlx5_eswitch_unblock_mode(struct mlx5_core_dev * dev)1084 static inline void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev) {}
mlx5_eswitch_block_ipsec(struct mlx5_core_dev * dev)1085 static inline bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev)
1086 {
1087 return false;
1088 }
1089
mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev * dev)1090 static inline void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev) {}
1091
1092 static inline bool
mlx5_esw_host_functions_enabled(const struct mlx5_core_dev * dev)1093 mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev)
1094 {
1095 return true;
1096 }
1097
mlx5_esw_reps_block(struct mlx5_eswitch * esw)1098 static inline void mlx5_esw_reps_block(struct mlx5_eswitch *esw) {}
mlx5_esw_reps_unblock(struct mlx5_eswitch * esw)1099 static inline void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw) {}
1100
1101 static inline bool
mlx5_esw_vport_vhca_id(struct mlx5_eswitch * esw,u16 vportn,u16 * vhca_id)1102 mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id)
1103 {
1104 return false;
1105 }
1106
1107 static inline u16
mlx5_esw_vhca_id_to_func_type(struct mlx5_core_dev * dev,u16 vhca_id)1108 mlx5_esw_vhca_id_to_func_type(struct mlx5_core_dev *dev, u16 vhca_id)
1109 {
1110 return MLX5_FUNC_TYPE_NONE;
1111 }
1112
1113 static inline void
mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev * dev)1114 mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev *dev) {}
1115 static inline struct mlx5_flow_handle *
mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch * esw,u16 vport_num,struct mlx5_flow_table * lag_ft)1116 mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num,
1117 struct mlx5_flow_table *lag_ft)
1118 {
1119 return ERR_PTR(-EOPNOTSUPP);
1120 }
1121
1122 #endif /* CONFIG_MLX5_ESWITCH */
1123
1124 #endif /* __MLX5_ESWITCH_H__ */
1125