xref: /linux/sound/pci/rme9652/hdspm.c (revision 05a54fa773284d1a7923cdfdd8f0c8dabb98bd26)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4  *
5  *      Copyright (c) 2003 Winfried Ritsch (IEM)
6  *      code based on hdsp.c   Paul Davis
7  *                             Marcus Andersson
8  *                             Thomas Charbonnel
9  *      Modified 2006-06-01 for AES32 support by Remy Bruno
10  *                                               <remy.bruno@trinnov.com>
11  *
12  *      Modified 2009-04-13 for proper metering by Florian Faber
13  *                                               <faber@faberman.de>
14  *
15  *      Modified 2009-04-14 for native float support by Florian Faber
16  *                                               <faber@faberman.de>
17  *
18  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
19  *                                               <faber@faberman.de>
20  *
21  *      Modified 2009-04-30 added hw serial number support by Florian Faber
22  *
23  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
24  *
25  *	Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
26  *
27  *      Modified 2019-05-23 fix AIO single speed ADAT capture and playback
28  *      by Philippe.Bekaert@uhasselt.be
29  */
30 
31 /* *************    Register Documentation   *******************************************************
32  *
33  * Work in progress! Documentation is based on the code in this file.
34  *
35  * --------- HDSPM_controlRegister ---------
36  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
37  * :||||.||||:||||.||||:||||.||||:||||.||||:
38  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
39  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
40  * :||||.||||:||||.||||:||||.||||:||||.||||:
41  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
42  * :    .    :    .    :    .    :  x .    :  HDSPM_AudioInterruptEnable \_ setting both bits
43  * :    .    :    .    :    .    :    .   x:  HDSPM_Start                /  enables audio IO
44  * :    .    :    .    :    .    :   x.    :  HDSPM_ClockModeMaster - 1: Master, 0: Slave
45  * :    .    :    .    :    .    :    .210 :  HDSPM_LatencyMask - 3 Bit value for latency
46  * :    .    :    .    :    .    :    .    :      0:64, 1:128, 2:256, 3:512,
47  * :    .    :    .    :    .    :    .    :      4:1024, 5:2048, 6:4096, 7:8192
48  * :x   .    :    .    :    .   x:xx  .    :  HDSPM_FrequencyMask
49  * :    .    :    .    :    .    :10  .    :  HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
50  * :    .    :    .    :    .   x:    .    :  <MADI> HDSPM_DoubleSpeed
51  * :x   .    :    .    :    .    :    .    :  <MADI> HDSPM_QuadSpeed
52  * :    .  3 :    .  10:  2 .    :    .    :  HDSPM_SyncRefMask :
53  * :    .    :    .   x:    .    :    .    :  HDSPM_SyncRef0
54  * :    .    :    .  x :    .    :    .    :  HDSPM_SyncRef1
55  * :    .    :    .    :  x .    :    .    :  <AES32> HDSPM_SyncRef2
56  * :    .  x :    .    :    .    :    .    :  <AES32> HDSPM_SyncRef3
57  * :    .    :    .  10:    .    :    .    :  <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
58  * :    .  3 :    .  10:  2 .    :    .    :  <AES32>  0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
59  * :    .  x :    .    :    .    :    .    :  <MADIe> HDSPe_FLOAT_FORMAT
60  * :    .    :    .    : x  .    :    .    :  <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
61  * :    .    :    .    :x   .    :    .    :  <MADI> HDSPM_InputSelect1
62  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
63  * :    .    :    .    :    . x  :    .    :  <MADI> HDSPM_TX_64ch
64  * :    .    :    .    :    . x  :    .    :  <AES32> HDSPM_Emphasis
65  * :    .    :    .    :    .x   :    .    :  <MADI> HDSPM_AutoInp
66  * :    .    :    . x  :    .    :    .    :  <MADI> HDSPM_SMUX
67  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
68  * :    .    :   x.    :    .    :    .    :  <MADI> HDSPM_taxi_reset
69  * :    .   x:    .    :    .    :    .    :  <MADI> HDSPM_LineOut
70  * :    .   x:    .    :    .    :    .    :  <AES32> ??????????????????
71  * :    .    :   x.    :    .    :    .    :  <AES32> HDSPM_WCK48
72  * :    .    :    .    :    .x   :    .    :  <AES32> HDSPM_Dolby
73  * :    .    : x  .    :    .    :    .    :  HDSPM_Midi0InterruptEnable
74  * :    .    :x   .    :    .    :    .    :  HDSPM_Midi1InterruptEnable
75  * :    .    :  x .    :    .    :    .    :  HDSPM_Midi2InterruptEnable
76  * :    . x  :    .    :    .    :    .    :  <MADI> HDSPM_Midi3InterruptEnable
77  * :    . x  :    .    :    .    :    .    :  <AES32> HDSPM_DS_DoubleWire
78  * :    .x   :    .    :    .    :    .    :  <AES32> HDSPM_QS_DoubleWire
79  * :   x.    :    .    :    .    :    .    :  <AES32> HDSPM_QS_QuadWire
80  * :    .    :    .    :    .  x :    .    :  <AES32> HDSPM_Professional
81  * : x  .    :    .    :    .    :    .    :  HDSPM_wclk_sel
82  * :    .    :    .    :    .    :    .    :
83  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
84  * :||||.||||:||||.||||:||||.||||:||||.||||:
85  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
86  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
87  * :||||.||||:||||.||||:||||.||||:||||.||||:
88  * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
89  *
90  *
91  *
92  * AIO / RayDAT only
93  *
94  * ------------ HDSPM_WR_SETTINGS ----------
95  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
96  * :1098.7654:3210.9876:5432.1098:7654.3210:
97  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
98  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
99  * :||||.||||:||||.||||:||||.||||:||||.||||:
100  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
101  * :    .    :    .    :    .    :    .   x: HDSPM_c0Master 1: Master, 0: Slave
102  * :    .    :    .    :    .    :    .  x : HDSPM_c0_SyncRef0
103  * :    .    :    .    :    .    :    . x  : HDSPM_c0_SyncRef1
104  * :    .    :    .    :    .    :    .x   : HDSPM_c0_SyncRef2
105  * :    .    :    .    :    .    :   x.    : HDSPM_c0_SyncRef3
106  * :    .    :    .    :    .    :   3.210 : HDSPM_c0_SyncRefMask:
107  * :    .    :    .    :    .    :    .    :  RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
108  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
109  * :    .    :    .    :    .    :    .    :  AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
110  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
111  * :    .    :    .    :    .    :    .    :
112  * :    .    :    .    :    .    :    .    :
113  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
114  * :1098.7654:3210.9876:5432.1098:7654.3210:
115  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
116  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
117  * :||||.||||:||||.||||:||||.||||:||||.||||:
118  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
119  *
120  */
121 #include <linux/init.h>
122 #include <linux/delay.h>
123 #include <linux/interrupt.h>
124 #include <linux/module.h>
125 #include <linux/slab.h>
126 #include <linux/pci.h>
127 #include <linux/math64.h>
128 #include <linux/io.h>
129 #include <linux/nospec.h>
130 
131 #include <sound/core.h>
132 #include <sound/control.h>
133 #include <sound/pcm.h>
134 #include <sound/pcm_params.h>
135 #include <sound/info.h>
136 #include <sound/asoundef.h>
137 #include <sound/rawmidi.h>
138 #include <sound/hwdep.h>
139 #include <sound/initval.h>
140 
141 #include <sound/hdspm.h>
142 
143 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	  /* Index 0-MAX */
144 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	  /* ID for this card */
145 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
146 
147 module_param_array(index, int, NULL, 0444);
148 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
149 
150 module_param_array(id, charp, NULL, 0444);
151 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
152 
153 module_param_array(enable, bool, NULL, 0444);
154 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
155 
156 
157 MODULE_AUTHOR
158 (
159 	"Winfried Ritsch <ritsch_AT_iem.at>, "
160 	"Paul Davis <paul@linuxaudiosystems.com>, "
161 	"Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
162 	"Remy Bruno <remy.bruno@trinnov.com>, "
163 	"Florian Faber <faberman@linuxproaudio.org>, "
164 	"Adrian Knoth <adi@drcomp.erfurt.thur.de>"
165 );
166 MODULE_DESCRIPTION("RME HDSPM");
167 MODULE_LICENSE("GPL");
168 
169 /* --- Write registers. ---
170   These are defined as byte-offsets from the iobase value.  */
171 
172 #define HDSPM_WR_SETTINGS             0
173 #define HDSPM_outputBufferAddress    32
174 #define HDSPM_inputBufferAddress     36
175 #define HDSPM_controlRegister	     64
176 #define HDSPM_interruptConfirmation  96
177 #define HDSPM_control2Reg	     256  /* not in specs ???????? */
178 #define HDSPM_freqReg                256  /* for setting arbitrary clock values (DDS feature) */
179 #define HDSPM_midiDataOut0	     352  /* just believe in old code */
180 #define HDSPM_midiDataOut1	     356
181 #define HDSPM_eeprom_wr		     384  /* for AES32 */
182 
183 /* DMA enable for 64 channels, only Bit 0 is relevant */
184 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
185 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
186 
187 /* 16 page addresses for each of the 64 channels DMA buffer in and out
188    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
189 #define HDSPM_pageAddressBufferOut       8192
190 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
191 
192 #define HDSPM_MADI_mixerBase    32768	/* 32768-65535 for 2x64x64 Fader */
193 
194 #define HDSPM_MATRIX_MIXER_SIZE  8192	/* = 2*64*64 * 4 Byte => 32kB */
195 
196 /* --- Read registers. ---
197    These are defined as byte-offsets from the iobase value */
198 #define HDSPM_statusRegister    0
199 /*#define HDSPM_statusRegister2  96 */
200 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
201  * offset 192, for AES32 *and* MADI
202  * => need to check that offset 192 is working on MADI */
203 #define HDSPM_statusRegister2  192
204 #define HDSPM_timecodeRegister 128
205 
206 /* AIO, RayDAT */
207 #define HDSPM_RD_STATUS_0 0
208 #define HDSPM_RD_STATUS_1 64
209 #define HDSPM_RD_STATUS_2 128
210 #define HDSPM_RD_STATUS_3 192
211 
212 #define HDSPM_RD_TCO           256
213 #define HDSPM_RD_PLL_FREQ      512
214 #define HDSPM_WR_TCO           128
215 
216 #define HDSPM_TCO1_TCO_lock			0x00000001
217 #define HDSPM_TCO1_WCK_Input_Range_LSB		0x00000002
218 #define HDSPM_TCO1_WCK_Input_Range_MSB		0x00000004
219 #define HDSPM_TCO1_LTC_Input_valid		0x00000008
220 #define HDSPM_TCO1_WCK_Input_valid		0x00000010
221 #define HDSPM_TCO1_Video_Input_Format_NTSC	0x00000020
222 #define HDSPM_TCO1_Video_Input_Format_PAL	0x00000040
223 
224 #define HDSPM_TCO1_set_TC			0x00000100
225 #define HDSPM_TCO1_set_drop_frame_flag		0x00000200
226 #define HDSPM_TCO1_LTC_Format_LSB		0x00000400
227 #define HDSPM_TCO1_LTC_Format_MSB		0x00000800
228 
229 #define HDSPM_TCO2_TC_run			0x00010000
230 #define HDSPM_TCO2_WCK_IO_ratio_LSB		0x00020000
231 #define HDSPM_TCO2_WCK_IO_ratio_MSB		0x00040000
232 #define HDSPM_TCO2_set_num_drop_frames_LSB	0x00080000
233 #define HDSPM_TCO2_set_num_drop_frames_MSB	0x00100000
234 #define HDSPM_TCO2_set_jam_sync			0x00200000
235 #define HDSPM_TCO2_set_flywheel			0x00400000
236 
237 #define HDSPM_TCO2_set_01_4			0x01000000
238 #define HDSPM_TCO2_set_pull_down		0x02000000
239 #define HDSPM_TCO2_set_pull_up			0x04000000
240 #define HDSPM_TCO2_set_freq			0x08000000
241 #define HDSPM_TCO2_set_term_75R			0x10000000
242 #define HDSPM_TCO2_set_input_LSB		0x20000000
243 #define HDSPM_TCO2_set_input_MSB		0x40000000
244 #define HDSPM_TCO2_set_freq_from_app		0x80000000
245 
246 
247 #define HDSPM_midiDataOut0    352
248 #define HDSPM_midiDataOut1    356
249 #define HDSPM_midiDataOut2    368
250 
251 #define HDSPM_midiDataIn0     360
252 #define HDSPM_midiDataIn1     364
253 #define HDSPM_midiDataIn2     372
254 #define HDSPM_midiDataIn3     376
255 
256 /* status is data bytes in MIDI-FIFO (0-128) */
257 #define HDSPM_midiStatusOut0  384
258 #define HDSPM_midiStatusOut1  388
259 #define HDSPM_midiStatusOut2  400
260 
261 #define HDSPM_midiStatusIn0   392
262 #define HDSPM_midiStatusIn1   396
263 #define HDSPM_midiStatusIn2   404
264 #define HDSPM_midiStatusIn3   408
265 
266 
267 /* the meters are regular i/o-mapped registers, but offset
268    considerably from the rest. the peak registers are reset
269    when read; the least-significant 4 bits are full-scale counters;
270    the actual peak value is in the most-significant 24 bits.
271 */
272 
273 #define HDSPM_MADI_INPUT_PEAK		4096
274 #define HDSPM_MADI_PLAYBACK_PEAK	4352
275 #define HDSPM_MADI_OUTPUT_PEAK		4608
276 
277 #define HDSPM_MADI_INPUT_RMS_L		6144
278 #define HDSPM_MADI_PLAYBACK_RMS_L	6400
279 #define HDSPM_MADI_OUTPUT_RMS_L		6656
280 
281 #define HDSPM_MADI_INPUT_RMS_H		7168
282 #define HDSPM_MADI_PLAYBACK_RMS_H	7424
283 #define HDSPM_MADI_OUTPUT_RMS_H		7680
284 
285 /* --- Control Register bits --------- */
286 #define HDSPM_Start                (1<<0) /* start engine */
287 
288 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
289 #define HDSPM_Latency1             (1<<2) /* where n is defined */
290 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
291 
292 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
293 #define HDSPM_c0Master		0x1    /* Master clock bit in settings
294 					  register [RayDAT, AIO] */
295 
296 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
297 
298 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
299 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
300 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
301 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
302 
303 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
304 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
305 				     56channelMODE=0 */ /* MADI ONLY*/
306 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
307 
308 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
309                                      0=off, 1=on  */ /* MADI ONLY */
310 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
311 
312 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
313 				    * -- MADI ONLY
314 				    */
315 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
316 
317 #define HDSPM_SyncRef2     (1<<13)
318 #define HDSPM_SyncRef3     (1<<25)
319 
320 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
321 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
322                                       AES additional bits in
323 				      lower 5 Audiodatabits ??? */
324 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
325 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
326 
327 #define HDSPM_Midi0InterruptEnable 0x0400000
328 #define HDSPM_Midi1InterruptEnable 0x0800000
329 #define HDSPM_Midi2InterruptEnable 0x0200000
330 #define HDSPM_Midi3InterruptEnable 0x4000000
331 
332 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
333 #define HDSPe_FLOAT_FORMAT         0x2000000
334 
335 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
336 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
337 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
338 
339 #define HDSPM_wclk_sel (1<<30)
340 
341 /* additional control register bits for AIO*/
342 #define HDSPM_c0_Wck48				0x20 /* also RayDAT */
343 #define HDSPM_c0_Input0				0x1000
344 #define HDSPM_c0_Input1				0x2000
345 #define HDSPM_c0_Spdif_Opt			0x4000
346 #define HDSPM_c0_Pro				0x8000
347 #define HDSPM_c0_clr_tms			0x10000
348 #define HDSPM_c0_AEB1				0x20000
349 #define HDSPM_c0_AEB2				0x40000
350 #define HDSPM_c0_LineOut			0x80000
351 #define HDSPM_c0_AD_GAIN0			0x100000
352 #define HDSPM_c0_AD_GAIN1			0x200000
353 #define HDSPM_c0_DA_GAIN0			0x400000
354 #define HDSPM_c0_DA_GAIN1			0x800000
355 #define HDSPM_c0_PH_GAIN0			0x1000000
356 #define HDSPM_c0_PH_GAIN1			0x2000000
357 #define HDSPM_c0_Sym6db				0x4000000
358 
359 
360 /* --- bit helper defines */
361 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
362 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
363 			      HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
364 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
365 #define HDSPM_InputOptical   0
366 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
367 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
368 			      HDSPM_SyncRef2|HDSPM_SyncRef3)
369 
370 #define HDSPM_c0_SyncRef0      0x2
371 #define HDSPM_c0_SyncRef1      0x4
372 #define HDSPM_c0_SyncRef2      0x8
373 #define HDSPM_c0_SyncRef3      0x10
374 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
375 				HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
376 
377 #define HDSPM_SYNC_FROM_WORD    0	/* Preferred sync reference */
378 #define HDSPM_SYNC_FROM_MADI    1	/* choices - used by "pref_sync_ref" */
379 #define HDSPM_SYNC_FROM_TCO     2
380 #define HDSPM_SYNC_FROM_SYNC_IN 3
381 
382 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
383 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
384 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
385 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
386 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
387 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
388 				HDSPM_Frequency0)
389 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
390 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
391 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
392 				 HDSPM_Frequency0)
393 
394 
395 /* Synccheck Status */
396 #define HDSPM_SYNC_CHECK_NO_LOCK 0
397 #define HDSPM_SYNC_CHECK_LOCK    1
398 #define HDSPM_SYNC_CHECK_SYNC	 2
399 
400 /* AutoSync References - used by "autosync_ref" control switch */
401 #define HDSPM_AUTOSYNC_FROM_WORD      0
402 #define HDSPM_AUTOSYNC_FROM_MADI      1
403 #define HDSPM_AUTOSYNC_FROM_TCO       2
404 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
405 #define HDSPM_AUTOSYNC_FROM_NONE      4
406 
407 /* Possible sources of MADI input */
408 #define HDSPM_OPTICAL 0		/* optical   */
409 #define HDSPM_COAXIAL 1		/* BNC */
410 
411 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
412 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
413 
414 #define hdspm_encode_in(x) (((x)&0x3)<<14)
415 #define hdspm_decode_in(x) (((x)>>14)&0x3)
416 
417 /* --- control2 register bits --- */
418 #define HDSPM_TMS             (1<<0)
419 #define HDSPM_TCK             (1<<1)
420 #define HDSPM_TDI             (1<<2)
421 #define HDSPM_JTAG            (1<<3)
422 #define HDSPM_PWDN            (1<<4)
423 #define HDSPM_PROGRAM	      (1<<5)
424 #define HDSPM_CONFIG_MODE_0   (1<<6)
425 #define HDSPM_CONFIG_MODE_1   (1<<7)
426 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
427 #define HDSPM_BIGENDIAN_MODE  (1<<9)
428 #define HDSPM_RD_MULTIPLE     (1<<10)
429 
430 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
431      that do not conflict with specific bits for AES32 seem to be valid also
432      for the AES32
433  */
434 #define HDSPM_audioIRQPending    (1<<0)	/* IRQ is high and pending */
435 #define HDSPM_RX_64ch            (1<<1)	/* Input 64chan. MODE=1, 56chn MODE=0 */
436 #define HDSPM_AB_int             (1<<2)	/* InputChannel Opt=0, Coax=1
437 					 * (like inp0)
438 					 */
439 
440 #define HDSPM_madiLock           (1<<3)	/* MADI Locked =1, no=0 */
441 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
442 
443 #define HDSPM_tcoLockMadi    0x00000020 /* Optional TCO locked status for HDSPe MADI*/
444 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
445 
446 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
447 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
448 
449 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
450 			/* since 64byte accurate, last 6 bits are not used */
451 
452 
453 
454 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
455 
456 #define HDSPM_madiFreq0         (1<<22)	/* system freq 0=error */
457 #define HDSPM_madiFreq1         (1<<23)	/* 1=32, 2=44.1 3=48 */
458 #define HDSPM_madiFreq2         (1<<24)	/* 4=64, 5=88.2 6=96 */
459 #define HDSPM_madiFreq3         (1<<25)	/* 7=128, 8=176.4 9=192 */
460 
461 #define HDSPM_BufferID          (1<<26)	/* (Double)Buffer ID toggles with
462 					 * Interrupt
463 					 */
464 #define HDSPM_tco_detect         0x08000000
465 #define HDSPM_tcoLockAes         0x20000000 /* Optional TCO locked status for HDSPe AES */
466 
467 #define HDSPM_s2_tco_detect      0x00000040
468 #define HDSPM_s2_AEBO_D          0x00000080
469 #define HDSPM_s2_AEBI_D          0x00000100
470 
471 
472 #define HDSPM_midi0IRQPending    0x40000000
473 #define HDSPM_midi1IRQPending    0x80000000
474 #define HDSPM_midi2IRQPending    0x20000000
475 #define HDSPM_midi2IRQPendingAES 0x00000020
476 #define HDSPM_midi3IRQPending    0x00200000
477 
478 /* --- status bit helpers */
479 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
480 			     HDSPM_madiFreq2|HDSPM_madiFreq3)
481 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
482 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
483 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
484 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
485 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
486 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
487 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
488 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
489 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
490 
491 /* Status2 Register bits */ /* MADI ONLY */
492 
493 #define HDSPM_version0 (1<<0)	/* not really defined but I guess */
494 #define HDSPM_version1 (1<<1)	/* in former cards it was ??? */
495 #define HDSPM_version2 (1<<2)
496 
497 #define HDSPM_wcLock (1<<3)	/* Wordclock is detected and locked */
498 #define HDSPM_wcSync (1<<4)	/* Wordclock is in sync with systemclock */
499 
500 #define HDSPM_wc_freq0 (1<<5)	/* input freq detected via autosync  */
501 #define HDSPM_wc_freq1 (1<<6)	/* 001=32, 010==44.1, 011=48, */
502 #define HDSPM_wc_freq2 (1<<7)	/* 100=64, 101=88.2, 110=96, 111=128 */
503 #define HDSPM_wc_freq3 0x800	/* 1000=176.4, 1001=192 */
504 
505 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
506 #define HDSPM_SyncRef1 0x20000
507 
508 #define HDSPM_SelSyncRef0 (1<<8)	/* AutoSync Source */
509 #define HDSPM_SelSyncRef1 (1<<9)	/* 000=word, 001=MADI, */
510 #define HDSPM_SelSyncRef2 (1<<10)	/* 111=no valid signal */
511 
512 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
513 
514 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
515 			    HDSPM_wc_freq3)
516 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
517 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
518 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
519 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
520 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
521 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
522 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
523 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
524 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
525 
526 #define HDSPM_status1_F_0 0x0400000
527 #define HDSPM_status1_F_1 0x0800000
528 #define HDSPM_status1_F_2 0x1000000
529 #define HDSPM_status1_F_3 0x2000000
530 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
531 
532 
533 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
534 				    HDSPM_SelSyncRef2)
535 #define HDSPM_SelSyncRef_WORD      0
536 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
537 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
538 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
539 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
540 				    HDSPM_SelSyncRef2)
541 
542 /*
543    For AES32, bits for status, status2 and timecode are different
544 */
545 /* status */
546 #define HDSPM_AES32_wcLock	0x0200000
547 #define HDSPM_AES32_wcSync	0x0100000
548 #define HDSPM_AES32_wcFreq_bit  22
549 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
550   HDSPM_bit2freq */
551 #define HDSPM_AES32_syncref_bit  16
552 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
553 
554 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
555 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
556 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
557 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
558 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
559 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
560 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
561 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
562 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
563 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
564 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
565 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
566 
567 /*  status2 */
568 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
569 #define HDSPM_LockAES   0x80
570 #define HDSPM_LockAES1  0x80
571 #define HDSPM_LockAES2  0x40
572 #define HDSPM_LockAES3  0x20
573 #define HDSPM_LockAES4  0x10
574 #define HDSPM_LockAES5  0x8
575 #define HDSPM_LockAES6  0x4
576 #define HDSPM_LockAES7  0x2
577 #define HDSPM_LockAES8  0x1
578 /*
579    Timecode
580    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
581    AES i+1
582  bits 3210
583       0001  32kHz
584       0010  44.1kHz
585       0011  48kHz
586       0100  64kHz
587       0101  88.2kHz
588       0110  96kHz
589       0111  128kHz
590       1000  176.4kHz
591       1001  192kHz
592   NB: Timecode register doesn't seem to work on AES32 card revision 230
593 */
594 
595 /* Mixer Values */
596 #define UNITY_GAIN          32768	/* = 65536/2 */
597 #define MINUS_INFINITY_GAIN 0
598 
599 /* Number of channels for different Speed Modes */
600 #define MADI_SS_CHANNELS       64
601 #define MADI_DS_CHANNELS       32
602 #define MADI_QS_CHANNELS       16
603 
604 #define RAYDAT_SS_CHANNELS     36
605 #define RAYDAT_DS_CHANNELS     20
606 #define RAYDAT_QS_CHANNELS     12
607 
608 #define AIO_IN_SS_CHANNELS        14
609 #define AIO_IN_DS_CHANNELS        10
610 #define AIO_IN_QS_CHANNELS        8
611 #define AIO_OUT_SS_CHANNELS        16
612 #define AIO_OUT_DS_CHANNELS        12
613 #define AIO_OUT_QS_CHANNELS        10
614 
615 #define AES32_CHANNELS		16
616 
617 /* the size of a substream (1 mono data stream) */
618 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
619 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
620 
621 /* the size of the area we need to allocate for DMA transfers. the
622    size is the same regardless of the number of channels, and
623    also the latency to use.
624    for one direction !!!
625 */
626 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
627 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
628 
629 #define HDSPM_RAYDAT_REV	211
630 #define HDSPM_AIO_REV		212
631 #define HDSPM_MADIFACE_REV	213
632 
633 /* speed factor modes */
634 #define HDSPM_SPEED_SINGLE 0
635 #define HDSPM_SPEED_DOUBLE 1
636 #define HDSPM_SPEED_QUAD   2
637 
638 /* names for speed modes */
639 static const char * const hdspm_speed_names[] = { "single", "double", "quad" };
640 
641 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
642 					  "AES1", "AES2", "AES3", "AES4",
643 					  "AES5", "AES6", "AES7", "AES8",
644 					  "TCO", "Sync In"
645 };
646 static const char *const texts_autosync_aes[] = { "Word Clock",
647 				      "AES1", "AES2", "AES3", "AES4",
648 				      "AES5", "AES6", "AES7", "AES8",
649 				      "Sync In"
650 };
651 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
652 					   "MADI", "TCO", "Sync In" };
653 static const char *const texts_autosync_madi[] = { "Word Clock",
654 				       "MADI", "Sync In" };
655 
656 static const char *const texts_autosync_raydat_tco[] = {
657 	"Word Clock",
658 	"ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
659 	"AES", "SPDIF", "TCO", "Sync In"
660 };
661 static const char *const texts_autosync_raydat[] = {
662 	"Word Clock",
663 	"ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
664 	"AES", "SPDIF", "Sync In"
665 };
666 static const char *const texts_autosync_aio_tco[] = {
667 	"Word Clock",
668 	"ADAT", "AES", "SPDIF", "TCO", "Sync In"
669 };
670 static const char *const texts_autosync_aio[] = { "Word Clock",
671 				      "ADAT", "AES", "SPDIF", "Sync In" };
672 
673 static const char *const texts_freq[] = {
674 	"No Lock",
675 	"32 kHz",
676 	"44.1 kHz",
677 	"48 kHz",
678 	"64 kHz",
679 	"88.2 kHz",
680 	"96 kHz",
681 	"128 kHz",
682 	"176.4 kHz",
683 	"192 kHz"
684 };
685 
686 static const char * const texts_ports_madi[] = {
687 	"MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
688 	"MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
689 	"MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
690 	"MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
691 	"MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
692 	"MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
693 	"MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
694 	"MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
695 	"MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
696 	"MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
697 	"MADI.61", "MADI.62", "MADI.63", "MADI.64",
698 };
699 
700 
701 static const char * const texts_ports_raydat_ss[] = {
702 	"ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
703 	"ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
704 	"ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
705 	"ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
706 	"ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
707 	"ADAT4.7", "ADAT4.8",
708 	"AES.L", "AES.R",
709 	"SPDIF.L", "SPDIF.R"
710 };
711 
712 static const char * const texts_ports_raydat_ds[] = {
713 	"ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
714 	"ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
715 	"ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
716 	"ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
717 	"AES.L", "AES.R",
718 	"SPDIF.L", "SPDIF.R"
719 };
720 
721 static const char * const texts_ports_raydat_qs[] = {
722 	"ADAT1.1", "ADAT1.2",
723 	"ADAT2.1", "ADAT2.2",
724 	"ADAT3.1", "ADAT3.2",
725 	"ADAT4.1", "ADAT4.2",
726 	"AES.L", "AES.R",
727 	"SPDIF.L", "SPDIF.R"
728 };
729 
730 
731 static const char * const texts_ports_aio_in_ss[] = {
732 	"Analogue.L", "Analogue.R",
733 	"AES.L", "AES.R",
734 	"SPDIF.L", "SPDIF.R",
735 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
736 	"ADAT.7", "ADAT.8",
737 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
738 };
739 
740 static const char * const texts_ports_aio_out_ss[] = {
741 	"Analogue.L", "Analogue.R",
742 	"AES.L", "AES.R",
743 	"SPDIF.L", "SPDIF.R",
744 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
745 	"ADAT.7", "ADAT.8",
746 	"Phone.L", "Phone.R",
747 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
748 };
749 
750 static const char * const texts_ports_aio_in_ds[] = {
751 	"Analogue.L", "Analogue.R",
752 	"AES.L", "AES.R",
753 	"SPDIF.L", "SPDIF.R",
754 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
755 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
756 };
757 
758 static const char * const texts_ports_aio_out_ds[] = {
759 	"Analogue.L", "Analogue.R",
760 	"AES.L", "AES.R",
761 	"SPDIF.L", "SPDIF.R",
762 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
763 	"Phone.L", "Phone.R",
764 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
765 };
766 
767 static const char * const texts_ports_aio_in_qs[] = {
768 	"Analogue.L", "Analogue.R",
769 	"AES.L", "AES.R",
770 	"SPDIF.L", "SPDIF.R",
771 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
772 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
773 };
774 
775 static const char * const texts_ports_aio_out_qs[] = {
776 	"Analogue.L", "Analogue.R",
777 	"AES.L", "AES.R",
778 	"SPDIF.L", "SPDIF.R",
779 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
780 	"Phone.L", "Phone.R",
781 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
782 };
783 
784 static const char * const texts_ports_aes32[] = {
785 	"AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
786 	"AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
787 	"AES.15", "AES.16"
788 };
789 
790 /* These tables map the ALSA channels 1..N to the channels that we
791    need to use in order to find the relevant channel buffer. RME
792    refers to this kind of mapping as between "the ADAT channel and
793    the DMA channel." We index it using the logical audio channel,
794    and the value is the DMA channel (i.e. channel buffer number)
795    where the data for that channel can be read/written from/to.
796 */
797 
798 static const char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
799 	0, 1, 2, 3, 4, 5, 6, 7,
800 	8, 9, 10, 11, 12, 13, 14, 15,
801 	16, 17, 18, 19, 20, 21, 22, 23,
802 	24, 25, 26, 27, 28, 29, 30, 31,
803 	32, 33, 34, 35, 36, 37, 38, 39,
804 	40, 41, 42, 43, 44, 45, 46, 47,
805 	48, 49, 50, 51, 52, 53, 54, 55,
806 	56, 57, 58, 59, 60, 61, 62, 63
807 };
808 
809 static const char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
810 	4, 5, 6, 7, 8, 9, 10, 11,	/* ADAT 1 */
811 	12, 13, 14, 15, 16, 17, 18, 19,	/* ADAT 2 */
812 	20, 21, 22, 23, 24, 25, 26, 27,	/* ADAT 3 */
813 	28, 29, 30, 31, 32, 33, 34, 35,	/* ADAT 4 */
814 	0, 1,			/* AES */
815 	2, 3,			/* SPDIF */
816 	-1, -1, -1, -1,
817 	-1, -1, -1, -1, -1, -1, -1, -1,
818 	-1, -1, -1, -1, -1, -1, -1, -1,
819 	-1, -1, -1, -1, -1, -1, -1, -1,
820 };
821 
822 static const char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
823 	4, 5, 6, 7,		/* ADAT 1 */
824 	8, 9, 10, 11,		/* ADAT 2 */
825 	12, 13, 14, 15,		/* ADAT 3 */
826 	16, 17, 18, 19,		/* ADAT 4 */
827 	0, 1,			/* AES */
828 	2, 3,			/* SPDIF */
829 	-1, -1, -1, -1,
830 	-1, -1, -1, -1, -1, -1, -1, -1,
831 	-1, -1, -1, -1, -1, -1, -1, -1,
832 	-1, -1, -1, -1, -1, -1, -1, -1,
833 	-1, -1, -1, -1, -1, -1, -1, -1,
834 	-1, -1, -1, -1, -1, -1, -1, -1,
835 };
836 
837 static const char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
838 	4, 5,			/* ADAT 1 */
839 	6, 7,			/* ADAT 2 */
840 	8, 9,			/* ADAT 3 */
841 	10, 11,			/* ADAT 4 */
842 	0, 1,			/* AES */
843 	2, 3,			/* SPDIF */
844 	-1, -1, -1, -1,
845 	-1, -1, -1, -1, -1, -1, -1, -1,
846 	-1, -1, -1, -1, -1, -1, -1, -1,
847 	-1, -1, -1, -1, -1, -1, -1, -1,
848 	-1, -1, -1, -1, -1, -1, -1, -1,
849 	-1, -1, -1, -1, -1, -1, -1, -1,
850 	-1, -1, -1, -1, -1, -1, -1, -1,
851 };
852 
853 static const char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
854 	0, 1,			/* line in */
855 	8, 9,			/* aes in, */
856 	10, 11,			/* spdif in */
857 	12, 13, 14, 15, 16, 17, 18, 19,	/* ADAT in */
858 	2, 3, 4, 5,		/* AEB */
859 	-1, -1, -1, -1, -1, -1,
860 	-1, -1, -1, -1, -1, -1, -1, -1,
861 	-1, -1, -1, -1, -1, -1, -1, -1,
862 	-1, -1, -1, -1, -1, -1, -1, -1,
863 	-1, -1, -1, -1, -1, -1, -1, -1,
864 	-1, -1, -1, -1, -1, -1, -1, -1,
865 };
866 
867 static const char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
868 	0, 1,			/* line out */
869 	8, 9,			/* aes out */
870 	10, 11,			/* spdif out */
871 	12, 13, 14, 15, 16, 17, 18, 19,	/* ADAT out */
872 	6, 7,			/* phone out */
873 	2, 3, 4, 5,		/* AEB */
874 	-1, -1, -1, -1,
875 	-1, -1, -1, -1, -1, -1, -1, -1,
876 	-1, -1, -1, -1, -1, -1, -1, -1,
877 	-1, -1, -1, -1, -1, -1, -1, -1,
878 	-1, -1, -1, -1, -1, -1, -1, -1,
879 	-1, -1, -1, -1, -1, -1, -1, -1,
880 };
881 
882 static const char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
883 	0, 1,			/* line in */
884 	8, 9,			/* aes in */
885 	10, 11,			/* spdif in */
886 	12, 14, 16, 18,		/* adat in */
887 	2, 3, 4, 5,		/* AEB */
888 	-1, -1,
889 	-1, -1, -1, -1, -1, -1, -1, -1,
890 	-1, -1, -1, -1, -1, -1, -1, -1,
891 	-1, -1, -1, -1, -1, -1, -1, -1,
892 	-1, -1, -1, -1, -1, -1, -1, -1,
893 	-1, -1, -1, -1, -1, -1, -1, -1,
894 	-1, -1, -1, -1, -1, -1, -1, -1
895 };
896 
897 static const char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
898 	0, 1,			/* line out */
899 	8, 9,			/* aes out */
900 	10, 11,			/* spdif out */
901 	12, 14, 16, 18,		/* adat out */
902 	6, 7,			/* phone out */
903 	2, 3, 4, 5,		/* AEB */
904 	-1, -1, -1, -1, -1, -1, -1, -1,
905 	-1, -1, -1, -1, -1, -1, -1, -1,
906 	-1, -1, -1, -1, -1, -1, -1, -1,
907 	-1, -1, -1, -1, -1, -1, -1, -1,
908 	-1, -1, -1, -1, -1, -1, -1, -1,
909 	-1, -1, -1, -1, -1, -1, -1, -1
910 };
911 
912 static const char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
913 	0, 1,			/* line in */
914 	8, 9,			/* aes in */
915 	10, 11,			/* spdif in */
916 	12, 16,			/* adat in */
917 	2, 3, 4, 5,		/* AEB */
918 	-1, -1, -1, -1,
919 	-1, -1, -1, -1, -1, -1, -1, -1,
920 	-1, -1, -1, -1, -1, -1, -1, -1,
921 	-1, -1, -1, -1, -1, -1, -1, -1,
922 	-1, -1, -1, -1, -1, -1, -1, -1,
923 	-1, -1, -1, -1, -1, -1, -1, -1,
924 	-1, -1, -1, -1, -1, -1, -1, -1
925 };
926 
927 static const char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
928 	0, 1,			/* line out */
929 	8, 9,			/* aes out */
930 	10, 11,			/* spdif out */
931 	12, 16,			/* adat out */
932 	6, 7,			/* phone out */
933 	2, 3, 4, 5,		/* AEB */
934 	-1, -1,
935 	-1, -1, -1, -1, -1, -1, -1, -1,
936 	-1, -1, -1, -1, -1, -1, -1, -1,
937 	-1, -1, -1, -1, -1, -1, -1, -1,
938 	-1, -1, -1, -1, -1, -1, -1, -1,
939 	-1, -1, -1, -1, -1, -1, -1, -1,
940 	-1, -1, -1, -1, -1, -1, -1, -1
941 };
942 
943 static const char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
944 	0, 1, 2, 3, 4, 5, 6, 7,
945 	8, 9, 10, 11, 12, 13, 14, 15,
946 	-1, -1, -1, -1, -1, -1, -1, -1,
947 	-1, -1, -1, -1, -1, -1, -1, -1,
948 	-1, -1, -1, -1, -1, -1, -1, -1,
949 	-1, -1, -1, -1, -1, -1, -1, -1,
950 	-1, -1, -1, -1, -1, -1, -1, -1,
951 	-1, -1, -1, -1, -1, -1, -1, -1
952 };
953 
954 struct hdspm_midi {
955 	struct hdspm *hdspm;
956 	int id;
957 	struct snd_rawmidi *rmidi;
958 	struct snd_rawmidi_substream *input;
959 	struct snd_rawmidi_substream *output;
960 	char istimer;		/* timer in use */
961 	struct timer_list timer;
962 	spinlock_t lock;
963 	int pending;
964 	int dataIn;
965 	int statusIn;
966 	int dataOut;
967 	int statusOut;
968 	int ie;
969 	int irq;
970 };
971 
972 struct hdspm_tco {
973 	int input; /* 0: LTC, 1:Video, 2: WC*/
974 	int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
975 	int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
976 	int samplerate; /* 0=44.1, 1=48, 2= freq from app */
977 	int pull; /*   0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
978 	int term; /* 0 = off, 1 = on */
979 };
980 
981 struct hdspm {
982         spinlock_t lock;
983 	/* only one playback and/or capture stream */
984         struct snd_pcm_substream *capture_substream;
985         struct snd_pcm_substream *playback_substream;
986 
987 	char *card_name;	     /* for procinfo */
988 	unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
989 
990 	uint8_t io_type;
991 
992 	int monitor_outs;	/* set up monitoring outs init flag */
993 
994 	u32 control_register;	/* cached value */
995 	u32 control2_register;	/* cached value */
996 	u32 settings_register;  /* cached value for AIO / RayDat (sync reference, master/slave) */
997 
998 	struct hdspm_midi midi[4];
999 	struct work_struct midi_work;
1000 
1001 	size_t period_bytes;
1002 	unsigned char ss_in_channels;
1003 	unsigned char ds_in_channels;
1004 	unsigned char qs_in_channels;
1005 	unsigned char ss_out_channels;
1006 	unsigned char ds_out_channels;
1007 	unsigned char qs_out_channels;
1008 
1009 	unsigned char max_channels_in;
1010 	unsigned char max_channels_out;
1011 
1012 	const signed char *channel_map_in;
1013 	const signed char *channel_map_out;
1014 
1015 	const signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1016 	const signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
1017 
1018 	const char * const *port_names_in;
1019 	const char * const *port_names_out;
1020 
1021 	const char * const *port_names_in_ss;
1022 	const char * const *port_names_in_ds;
1023 	const char * const *port_names_in_qs;
1024 	const char * const *port_names_out_ss;
1025 	const char * const *port_names_out_ds;
1026 	const char * const *port_names_out_qs;
1027 
1028 	unsigned char *playback_buffer;	/* suitably aligned address */
1029 	unsigned char *capture_buffer;	/* suitably aligned address */
1030 
1031 	pid_t capture_pid;	/* process id which uses capture */
1032 	pid_t playback_pid;	/* process id which uses capture */
1033 	int running;		/* running status */
1034 
1035 	int last_external_sample_rate;	/* samplerate mystic ... */
1036 	int last_internal_sample_rate;
1037 	int system_sample_rate;
1038 
1039 	int dev;		/* Hardware vars... */
1040 	int irq;
1041 	unsigned long port;
1042 	void __iomem *iobase;
1043 
1044 	int irq_count;		/* for debug */
1045 	int midiPorts;
1046 
1047 	struct snd_card *card;	/* one card */
1048 	struct snd_pcm *pcm;		/* has one pcm */
1049 	struct snd_hwdep *hwdep;	/* and a hwdep for additional ioctl */
1050 	struct pci_dev *pci;	/* and an pci info */
1051 
1052 	/* Mixer vars */
1053 	/* fast alsa mixer */
1054 	struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1055 	/* but input to much, so not used */
1056 	struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
1057 	/* full mixer accessible over mixer ioctl or hwdep-device */
1058 	struct hdspm_mixer *mixer;
1059 
1060 	struct hdspm_tco *tco;  /* NULL if no TCO detected */
1061 
1062 	const char *const *texts_autosync;
1063 	int texts_autosync_items;
1064 
1065 	cycles_t last_interrupt;
1066 
1067 	unsigned int serial;
1068 
1069 	struct hdspm_peak_rms peak_rms;
1070 };
1071 
1072 
1073 static const struct pci_device_id snd_hdspm_ids[] = {
1074 	{
1075 	 .vendor = PCI_VENDOR_ID_XILINX,
1076 	 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1077 	 .subvendor = PCI_ANY_ID,
1078 	 .subdevice = PCI_ANY_ID,
1079 	 .class = 0,
1080 	 .class_mask = 0,
1081 	 .driver_data = 0},
1082 	{0,}
1083 };
1084 
1085 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1086 
1087 /* prototypes */
1088 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1089 					 struct hdspm *hdspm);
1090 static int snd_hdspm_create_pcm(struct snd_card *card,
1091 				struct hdspm *hdspm);
1092 
1093 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1094 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1095 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1096 static int hdspm_autosync_ref(struct hdspm *hdspm);
1097 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1098 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1099 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1100 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm,
1101 				       struct snd_pcm_substream *substream,
1102 				       unsigned int reg, int channels);
1103 
1104 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1105 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1106 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1107 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1108 
1109 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1110 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1111 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1112 
1113 
1114 
1115 static inline int HDSPM_bit2freq(int n)
1116 {
1117 	static const int bit2freq_tab[] = {
1118 		0, 32000, 44100, 48000, 64000, 88200,
1119 		96000, 128000, 176400, 192000 };
1120 	if (n < 1 || n > 9)
1121 		return 0;
1122 	return bit2freq_tab[n];
1123 }
1124 
1125 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1126 {
1127 	return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1128 }
1129 
1130 
1131 /* Write/read to/from HDSPM with Adresses in Bytes
1132    not words but only 32Bit writes are allowed */
1133 
1134 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1135 			       unsigned int val)
1136 {
1137 	writel(val, hdspm->iobase + reg);
1138 }
1139 
1140 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1141 {
1142 	return readl(hdspm->iobase + reg);
1143 }
1144 
1145 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1146    mixer is write only on hardware so we have to cache him for read
1147    each fader is a u32, but uses only the first 16 bit */
1148 
1149 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1150 				     unsigned int in)
1151 {
1152 	if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1153 		return 0;
1154 
1155 	return hdspm->mixer->ch[chan].in[in];
1156 }
1157 
1158 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1159 				     unsigned int pb)
1160 {
1161 	if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1162 		return 0;
1163 	return hdspm->mixer->ch[chan].pb[pb];
1164 }
1165 
1166 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1167 				      unsigned int in, unsigned short data)
1168 {
1169 	if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1170 		return -1;
1171 
1172 	hdspm_write(hdspm,
1173 		    HDSPM_MADI_mixerBase +
1174 		    ((in + 128 * chan) * sizeof(u32)),
1175 		    (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1176 	return 0;
1177 }
1178 
1179 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1180 				      unsigned int pb, unsigned short data)
1181 {
1182 	if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1183 		return -1;
1184 
1185 	hdspm_write(hdspm,
1186 		    HDSPM_MADI_mixerBase +
1187 		    ((64 + pb + 128 * chan) * sizeof(u32)),
1188 		    (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1189 	return 0;
1190 }
1191 
1192 
1193 /* enable DMA for specific channels, now available for DSP-MADI */
1194 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1195 {
1196 	hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1197 }
1198 
1199 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1200 {
1201 	hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1202 }
1203 
1204 /* check if same process is writing and reading */
1205 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1206 {
1207 	guard(spinlock_irqsave)(&hdspm->lock);
1208 	if ((hdspm->playback_pid != hdspm->capture_pid) &&
1209 	    (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0))
1210 		return 0;
1211 	return 1;
1212 }
1213 
1214 /* round arbitrary sample rates to commonly known rates */
1215 static int hdspm_round_frequency(int rate)
1216 {
1217 	if (rate < 38050)
1218 		return 32000;
1219 	if (rate < 46008)
1220 		return 44100;
1221 	else
1222 		return 48000;
1223 }
1224 
1225 /* QS and DS rates normally can not be detected
1226  * automatically by the card. Only exception is MADI
1227  * in 96k frame mode.
1228  *
1229  * So if we read SS values (32 .. 48k), check for
1230  * user-provided DS/QS bits in the control register
1231  * and multiply the base frequency accordingly.
1232  */
1233 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1234 {
1235 	if (rate <= 48000) {
1236 		if (hdspm->control_register & HDSPM_QuadSpeed)
1237 			return rate * 4;
1238 		else if (hdspm->control_register &
1239 				HDSPM_DoubleSpeed)
1240 			return rate * 2;
1241 	}
1242 	return rate;
1243 }
1244 
1245 /* check for external sample rate, returns the sample rate in Hz*/
1246 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1247 {
1248 	unsigned int status, status2;
1249 	int syncref, rate = 0, rate_bits;
1250 
1251 	switch (hdspm->io_type) {
1252 	case AES32:
1253 		status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1254 		status = hdspm_read(hdspm, HDSPM_statusRegister);
1255 
1256 		syncref = hdspm_autosync_ref(hdspm);
1257 		switch (syncref) {
1258 		case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1259 		/* Check WC sync and get sample rate */
1260 			if (hdspm_wc_sync_check(hdspm))
1261 				return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1262 			break;
1263 
1264 		case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1265 		case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1266 		case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1267 		case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1268 		case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1269 		case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1270 		case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1271 		case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1272 		/* Check AES sync and get sample rate */
1273 			if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1274 				return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1275 							syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1276 			break;
1277 
1278 
1279 		case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1280 		/* Check TCO sync and get sample rate */
1281 			if (hdspm_tco_sync_check(hdspm))
1282 				return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1283 			break;
1284 		default:
1285 			return 0;
1286 		} /* end switch(syncref) */
1287 		break;
1288 
1289 	case MADIface:
1290 		status = hdspm_read(hdspm, HDSPM_statusRegister);
1291 
1292 		if (!(status & HDSPM_madiLock)) {
1293 			rate = 0;  /* no lock */
1294 		} else {
1295 			switch (status & (HDSPM_status1_freqMask)) {
1296 			case HDSPM_status1_F_0*1:
1297 				rate = 32000; break;
1298 			case HDSPM_status1_F_0*2:
1299 				rate = 44100; break;
1300 			case HDSPM_status1_F_0*3:
1301 				rate = 48000; break;
1302 			case HDSPM_status1_F_0*4:
1303 				rate = 64000; break;
1304 			case HDSPM_status1_F_0*5:
1305 				rate = 88200; break;
1306 			case HDSPM_status1_F_0*6:
1307 				rate = 96000; break;
1308 			case HDSPM_status1_F_0*7:
1309 				rate = 128000; break;
1310 			case HDSPM_status1_F_0*8:
1311 				rate = 176400; break;
1312 			case HDSPM_status1_F_0*9:
1313 				rate = 192000; break;
1314 			default:
1315 				rate = 0; break;
1316 			}
1317 		}
1318 
1319 		break;
1320 
1321 	case MADI:
1322 	case AIO:
1323 	case RayDAT:
1324 		status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1325 		status = hdspm_read(hdspm, HDSPM_statusRegister);
1326 		rate = 0;
1327 
1328 		/* if wordclock has synced freq and wordclock is valid */
1329 		if ((status2 & HDSPM_wcLock) != 0 &&
1330 				(status2 & HDSPM_SelSyncRef0) == 0) {
1331 
1332 			rate_bits = status2 & HDSPM_wcFreqMask;
1333 
1334 
1335 			switch (rate_bits) {
1336 			case HDSPM_wcFreq32:
1337 				rate = 32000;
1338 				break;
1339 			case HDSPM_wcFreq44_1:
1340 				rate = 44100;
1341 				break;
1342 			case HDSPM_wcFreq48:
1343 				rate = 48000;
1344 				break;
1345 			case HDSPM_wcFreq64:
1346 				rate = 64000;
1347 				break;
1348 			case HDSPM_wcFreq88_2:
1349 				rate = 88200;
1350 				break;
1351 			case HDSPM_wcFreq96:
1352 				rate = 96000;
1353 				break;
1354 			case HDSPM_wcFreq128:
1355 				rate = 128000;
1356 				break;
1357 			case HDSPM_wcFreq176_4:
1358 				rate = 176400;
1359 				break;
1360 			case HDSPM_wcFreq192:
1361 				rate = 192000;
1362 				break;
1363 			default:
1364 				rate = 0;
1365 				break;
1366 			}
1367 		}
1368 
1369 		/* if rate detected and Syncref is Word than have it,
1370 		 * word has priority to MADI
1371 		 */
1372 		if (rate != 0 &&
1373 		(status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1374 			return hdspm_rate_multiplier(hdspm, rate);
1375 
1376 		/* maybe a madi input (which is taken if sel sync is madi) */
1377 		if (status & HDSPM_madiLock) {
1378 			rate_bits = status & HDSPM_madiFreqMask;
1379 
1380 			switch (rate_bits) {
1381 			case HDSPM_madiFreq32:
1382 				rate = 32000;
1383 				break;
1384 			case HDSPM_madiFreq44_1:
1385 				rate = 44100;
1386 				break;
1387 			case HDSPM_madiFreq48:
1388 				rate = 48000;
1389 				break;
1390 			case HDSPM_madiFreq64:
1391 				rate = 64000;
1392 				break;
1393 			case HDSPM_madiFreq88_2:
1394 				rate = 88200;
1395 				break;
1396 			case HDSPM_madiFreq96:
1397 				rate = 96000;
1398 				break;
1399 			case HDSPM_madiFreq128:
1400 				rate = 128000;
1401 				break;
1402 			case HDSPM_madiFreq176_4:
1403 				rate = 176400;
1404 				break;
1405 			case HDSPM_madiFreq192:
1406 				rate = 192000;
1407 				break;
1408 			default:
1409 				rate = 0;
1410 				break;
1411 			}
1412 
1413 		} /* endif HDSPM_madiLock */
1414 
1415 		/* check sample rate from TCO or SYNC_IN */
1416 		{
1417 			bool is_valid_input = 0;
1418 			bool has_sync = 0;
1419 
1420 			syncref = hdspm_autosync_ref(hdspm);
1421 			if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1422 				is_valid_input = 1;
1423 				has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1424 					hdspm_tco_sync_check(hdspm));
1425 			} else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1426 				is_valid_input = 1;
1427 				has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1428 					hdspm_sync_in_sync_check(hdspm));
1429 			}
1430 
1431 			if (is_valid_input && has_sync) {
1432 				rate = hdspm_round_frequency(
1433 					hdspm_get_pll_freq(hdspm));
1434 			}
1435 		}
1436 
1437 		rate = hdspm_rate_multiplier(hdspm, rate);
1438 
1439 		break;
1440 	}
1441 
1442 	return rate;
1443 }
1444 
1445 /* return latency in samples per period */
1446 static int hdspm_get_latency(struct hdspm *hdspm)
1447 {
1448 	int n;
1449 
1450 	n = hdspm_decode_latency(hdspm->control_register);
1451 
1452 	/* Special case for new RME cards with 32 samples period size.
1453 	 * The three latency bits in the control register
1454 	 * (HDSP_LatencyMask) encode latency values of 64 samples as
1455 	 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1456 	 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1457 	 * it corresponds to 32 samples.
1458 	 */
1459 	if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1460 		n = -1;
1461 
1462 	return 1 << (n + 6);
1463 }
1464 
1465 /* Latency function */
1466 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1467 {
1468 	hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1469 }
1470 
1471 
1472 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1473 {
1474 	int position;
1475 
1476 	position = hdspm_read(hdspm, HDSPM_statusRegister);
1477 
1478 	switch (hdspm->io_type) {
1479 	case RayDAT:
1480 	case AIO:
1481 		position &= HDSPM_BufferPositionMask;
1482 		position /= 4; /* Bytes per sample */
1483 		break;
1484 	default:
1485 		position = (position & HDSPM_BufferID) ?
1486 			(hdspm->period_bytes / 4) : 0;
1487 	}
1488 
1489 	return position;
1490 }
1491 
1492 
1493 static inline void hdspm_start_audio(struct hdspm * s)
1494 {
1495 	s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1496 	hdspm_write(s, HDSPM_controlRegister, s->control_register);
1497 }
1498 
1499 static inline void hdspm_stop_audio(struct hdspm * s)
1500 {
1501 	s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1502 	hdspm_write(s, HDSPM_controlRegister, s->control_register);
1503 }
1504 
1505 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1506 static void hdspm_silence_playback(struct hdspm *hdspm)
1507 {
1508 	int i;
1509 	int n = hdspm->period_bytes;
1510 	void *buf = hdspm->playback_buffer;
1511 
1512 	if (!buf)
1513 		return;
1514 
1515 	for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1516 		memset(buf, 0, n);
1517 		buf += HDSPM_CHANNEL_BUFFER_BYTES;
1518 	}
1519 }
1520 
1521 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1522 {
1523 	int n;
1524 
1525 	guard(spinlock_irq)(&s->lock);
1526 
1527 	if (32 == frames) {
1528 		/* Special case for new RME cards like RayDAT/AIO which
1529 		 * support period sizes of 32 samples. Since latency is
1530 		 * encoded in the three bits of HDSP_LatencyMask, we can only
1531 		 * have values from 0 .. 7. While 0 still means 64 samples and
1532 		 * 6 represents 4096 samples on all cards, 7 represents 8192
1533 		 * on older cards and 32 samples on new cards.
1534 		 *
1535 		 * In other words, period size in samples is calculated by
1536 		 * 2^(n+6) with n ranging from 0 .. 7.
1537 		 */
1538 		n = 7;
1539 	} else {
1540 		frames >>= 7;
1541 		n = 0;
1542 		while (frames) {
1543 			n++;
1544 			frames >>= 1;
1545 		}
1546 	}
1547 
1548 	s->control_register &= ~HDSPM_LatencyMask;
1549 	s->control_register |= hdspm_encode_latency(n);
1550 
1551 	hdspm_write(s, HDSPM_controlRegister, s->control_register);
1552 
1553 	hdspm_compute_period_size(s);
1554 
1555 	return 0;
1556 }
1557 
1558 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1559 {
1560 	u64 freq_const;
1561 
1562 	if (period == 0)
1563 		return 0;
1564 
1565 	switch (hdspm->io_type) {
1566 	case MADI:
1567 	case AES32:
1568 		freq_const = 110069313433624ULL;
1569 		break;
1570 	case RayDAT:
1571 	case AIO:
1572 		freq_const = 104857600000000ULL;
1573 		break;
1574 	case MADIface:
1575 		freq_const = 131072000000000ULL;
1576 		break;
1577 	default:
1578 		snd_BUG();
1579 		return 0;
1580 	}
1581 
1582 	return div_u64(freq_const, period);
1583 }
1584 
1585 
1586 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1587 {
1588 	u64 n;
1589 
1590 	if (snd_BUG_ON(rate <= 0))
1591 		return;
1592 
1593 	if (rate >= 112000)
1594 		rate /= 4;
1595 	else if (rate >= 56000)
1596 		rate /= 2;
1597 
1598 	switch (hdspm->io_type) {
1599 	case MADIface:
1600 		n = 131072000000000ULL;  /* 125 MHz */
1601 		break;
1602 	case MADI:
1603 	case AES32:
1604 		n = 110069313433624ULL;  /* 105 MHz */
1605 		break;
1606 	case RayDAT:
1607 	case AIO:
1608 		n = 104857600000000ULL;  /* 100 MHz */
1609 		break;
1610 	default:
1611 		snd_BUG();
1612 		return;
1613 	}
1614 
1615 	n = div_u64(n, rate);
1616 	/* n should be less than 2^32 for being written to FREQ register */
1617 	snd_BUG_ON(n >> 32);
1618 	hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1619 }
1620 
1621 /* dummy set rate lets see what happens */
1622 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1623 {
1624 	int current_rate;
1625 	int rate_bits;
1626 	int not_set = 0;
1627 	int current_speed, target_speed;
1628 
1629 	/* ASSUMPTION: hdspm->lock is either set, or there is no need for
1630 	   it (e.g. during module initialization).
1631 	 */
1632 
1633 	if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1634 
1635 		/* SLAVE --- */
1636 		if (called_internally) {
1637 
1638 			/* request from ctl or card initialization
1639 			   just make a warning an remember setting
1640 			   for future master mode switching */
1641 
1642 			dev_warn(hdspm->card->dev,
1643 				 "Warning: device is not running as a clock master.\n");
1644 			not_set = 1;
1645 		} else {
1646 
1647 			/* hw_param request while in AutoSync mode */
1648 			int external_freq =
1649 			    hdspm_external_sample_rate(hdspm);
1650 
1651 			if (hdspm_autosync_ref(hdspm) ==
1652 			    HDSPM_AUTOSYNC_FROM_NONE) {
1653 
1654 				dev_warn(hdspm->card->dev,
1655 					 "Detected no External Sync\n");
1656 				not_set = 1;
1657 
1658 			} else if (rate != external_freq) {
1659 
1660 				dev_warn(hdspm->card->dev,
1661 					 "Warning: No AutoSync source for requested rate\n");
1662 				not_set = 1;
1663 			}
1664 		}
1665 	}
1666 
1667 	current_rate = hdspm->system_sample_rate;
1668 
1669 	/* Changing between Singe, Double and Quad speed is not
1670 	   allowed if any substreams are open. This is because such a change
1671 	   causes a shift in the location of the DMA buffers and a reduction
1672 	   in the number of available buffers.
1673 
1674 	   Note that a similar but essentially insoluble problem exists for
1675 	   externally-driven rate changes. All we can do is to flag rate
1676 	   changes in the read/write routines.
1677 	 */
1678 
1679 	if (current_rate <= 48000)
1680 		current_speed = HDSPM_SPEED_SINGLE;
1681 	else if (current_rate <= 96000)
1682 		current_speed = HDSPM_SPEED_DOUBLE;
1683 	else
1684 		current_speed = HDSPM_SPEED_QUAD;
1685 
1686 	if (rate <= 48000)
1687 		target_speed = HDSPM_SPEED_SINGLE;
1688 	else if (rate <= 96000)
1689 		target_speed = HDSPM_SPEED_DOUBLE;
1690 	else
1691 		target_speed = HDSPM_SPEED_QUAD;
1692 
1693 	switch (rate) {
1694 	case 32000:
1695 		rate_bits = HDSPM_Frequency32KHz;
1696 		break;
1697 	case 44100:
1698 		rate_bits = HDSPM_Frequency44_1KHz;
1699 		break;
1700 	case 48000:
1701 		rate_bits = HDSPM_Frequency48KHz;
1702 		break;
1703 	case 64000:
1704 		rate_bits = HDSPM_Frequency64KHz;
1705 		break;
1706 	case 88200:
1707 		rate_bits = HDSPM_Frequency88_2KHz;
1708 		break;
1709 	case 96000:
1710 		rate_bits = HDSPM_Frequency96KHz;
1711 		break;
1712 	case 128000:
1713 		rate_bits = HDSPM_Frequency128KHz;
1714 		break;
1715 	case 176400:
1716 		rate_bits = HDSPM_Frequency176_4KHz;
1717 		break;
1718 	case 192000:
1719 		rate_bits = HDSPM_Frequency192KHz;
1720 		break;
1721 	default:
1722 		return -EINVAL;
1723 	}
1724 
1725 	if (current_speed != target_speed
1726 	    && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1727 		dev_err(hdspm->card->dev,
1728 			"cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n",
1729 			hdspm_speed_names[current_speed],
1730 			hdspm_speed_names[target_speed],
1731 			hdspm->capture_pid, hdspm->playback_pid);
1732 		return -EBUSY;
1733 	}
1734 
1735 	hdspm->control_register &= ~HDSPM_FrequencyMask;
1736 	hdspm->control_register |= rate_bits;
1737 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1738 
1739 	/* For AES32, need to set DDS value in FREQ register
1740 	   For MADI, also apparently */
1741 	hdspm_set_dds_value(hdspm, rate);
1742 
1743 	if (AES32 == hdspm->io_type && rate != current_rate)
1744 		hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1745 
1746 	hdspm->system_sample_rate = rate;
1747 
1748 	if (rate <= 48000) {
1749 		hdspm->channel_map_in = hdspm->channel_map_in_ss;
1750 		hdspm->channel_map_out = hdspm->channel_map_out_ss;
1751 		hdspm->max_channels_in = hdspm->ss_in_channels;
1752 		hdspm->max_channels_out = hdspm->ss_out_channels;
1753 		hdspm->port_names_in = hdspm->port_names_in_ss;
1754 		hdspm->port_names_out = hdspm->port_names_out_ss;
1755 	} else if (rate <= 96000) {
1756 		hdspm->channel_map_in = hdspm->channel_map_in_ds;
1757 		hdspm->channel_map_out = hdspm->channel_map_out_ds;
1758 		hdspm->max_channels_in = hdspm->ds_in_channels;
1759 		hdspm->max_channels_out = hdspm->ds_out_channels;
1760 		hdspm->port_names_in = hdspm->port_names_in_ds;
1761 		hdspm->port_names_out = hdspm->port_names_out_ds;
1762 	} else {
1763 		hdspm->channel_map_in = hdspm->channel_map_in_qs;
1764 		hdspm->channel_map_out = hdspm->channel_map_out_qs;
1765 		hdspm->max_channels_in = hdspm->qs_in_channels;
1766 		hdspm->max_channels_out = hdspm->qs_out_channels;
1767 		hdspm->port_names_in = hdspm->port_names_in_qs;
1768 		hdspm->port_names_out = hdspm->port_names_out_qs;
1769 	}
1770 
1771 	if (not_set != 0)
1772 		return -1;
1773 
1774 	return 0;
1775 }
1776 
1777 /* mainly for init to 0 on load */
1778 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1779 {
1780 	int i, j;
1781 	unsigned int gain;
1782 
1783 	if (sgain > UNITY_GAIN)
1784 		gain = UNITY_GAIN;
1785 	else if (sgain < 0)
1786 		gain = 0;
1787 	else
1788 		gain = sgain;
1789 
1790 	for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1791 		for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1792 			hdspm_write_in_gain(hdspm, i, j, gain);
1793 			hdspm_write_pb_gain(hdspm, i, j, gain);
1794 		}
1795 }
1796 
1797 /*----------------------------------------------------------------------------
1798    MIDI
1799   ----------------------------------------------------------------------------*/
1800 
1801 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1802 						      int id)
1803 {
1804 	/* the hardware already does the relevant bit-mask with 0xff */
1805 	return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1806 }
1807 
1808 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1809 					      int val)
1810 {
1811 	/* the hardware already does the relevant bit-mask with 0xff */
1812 	return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1813 }
1814 
1815 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1816 {
1817 	return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1818 }
1819 
1820 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1821 {
1822 	int fifo_bytes_used;
1823 
1824 	fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1825 
1826 	if (fifo_bytes_used < 128)
1827 		return  128 - fifo_bytes_used;
1828 	else
1829 		return 0;
1830 }
1831 
1832 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1833 {
1834 	int count = 256;
1835 
1836 	while (snd_hdspm_midi_input_available(hdspm, id) && --count)
1837 		snd_hdspm_midi_read_byte(hdspm, id);
1838 }
1839 
1840 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1841 {
1842 	int n_pending;
1843 	int to_write;
1844 	int i;
1845 	unsigned char buf[128];
1846 
1847 	/* Output is not interrupt driven */
1848 
1849 	guard(spinlock_irqsave)(&hmidi->lock);
1850 	if (hmidi->output &&
1851 	    !snd_rawmidi_transmit_empty (hmidi->output)) {
1852 		n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1853 							    hmidi->id);
1854 		if (n_pending > 0) {
1855 			if (n_pending > (int)sizeof (buf))
1856 				n_pending = sizeof (buf);
1857 
1858 			to_write = snd_rawmidi_transmit (hmidi->output, buf,
1859 							 n_pending);
1860 			if (to_write > 0) {
1861 				for (i = 0; i < to_write; ++i)
1862 					snd_hdspm_midi_write_byte (hmidi->hdspm,
1863 								   hmidi->id,
1864 								   buf[i]);
1865 			}
1866 		}
1867 	}
1868 	return 0;
1869 }
1870 
1871 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1872 {
1873 	unsigned char buf[128]; /* this buffer is designed to match the MIDI
1874 				 * input FIFO size
1875 				 */
1876 	int n_pending;
1877 	int i;
1878 
1879 	scoped_guard(spinlock_irqsave, &hmidi->lock) {
1880 		n_pending = snd_hdspm_midi_input_available(hmidi->hdspm, hmidi->id);
1881 		if (n_pending > 0) {
1882 			if (hmidi->input) {
1883 				if (n_pending > (int)sizeof(buf))
1884 					n_pending = sizeof(buf);
1885 				for (i = 0; i < n_pending; ++i)
1886 					buf[i] = snd_hdspm_midi_read_byte(hmidi->hdspm,
1887 									  hmidi->id);
1888 				if (n_pending)
1889 					snd_rawmidi_receive(hmidi->input, buf,
1890 							    n_pending);
1891 			} else {
1892 				/* flush the MIDI input FIFO */
1893 				while (n_pending--)
1894 					snd_hdspm_midi_read_byte(hmidi->hdspm,
1895 								 hmidi->id);
1896 			}
1897 		}
1898 		hmidi->pending = 0;
1899 	}
1900 
1901 	scoped_guard(spinlock_irqsave, &hmidi->hdspm->lock) {
1902 		hmidi->hdspm->control_register |= hmidi->ie;
1903 		hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1904 			    hmidi->hdspm->control_register);
1905 	}
1906 
1907 	return snd_hdspm_midi_output_write (hmidi);
1908 }
1909 
1910 static void
1911 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1912 {
1913 	struct hdspm *hdspm;
1914 	struct hdspm_midi *hmidi;
1915 
1916 	hmidi = substream->rmidi->private_data;
1917 	hdspm = hmidi->hdspm;
1918 
1919 	guard(spinlock_irqsave)(&hdspm->lock);
1920 	if (up) {
1921 		if (!(hdspm->control_register & hmidi->ie)) {
1922 			snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1923 			hdspm->control_register |= hmidi->ie;
1924 		}
1925 	} else {
1926 		hdspm->control_register &= ~hmidi->ie;
1927 	}
1928 
1929 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1930 }
1931 
1932 static void snd_hdspm_midi_output_timer(struct timer_list *t)
1933 {
1934 	struct hdspm_midi *hmidi = timer_container_of(hmidi, t, timer);
1935 
1936 	snd_hdspm_midi_output_write(hmidi);
1937 	guard(spinlock_irqsave)(&hmidi->lock);
1938 
1939 	/* this does not bump hmidi->istimer, because the
1940 	   kernel automatically removed the timer when it
1941 	   expired, and we are now adding it back, thus
1942 	   leaving istimer wherever it was set before.
1943 	*/
1944 
1945 	if (hmidi->istimer)
1946 		mod_timer(&hmidi->timer, 1 + jiffies);
1947 }
1948 
1949 static void
1950 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1951 {
1952 	struct hdspm_midi *hmidi;
1953 
1954 	hmidi = substream->rmidi->private_data;
1955 	scoped_guard(spinlock_irqsave, &hmidi->lock) {
1956 		if (up) {
1957 			if (!hmidi->istimer) {
1958 				timer_setup(&hmidi->timer,
1959 					    snd_hdspm_midi_output_timer, 0);
1960 				mod_timer(&hmidi->timer, 1 + jiffies);
1961 				hmidi->istimer++;
1962 			}
1963 		} else {
1964 			if (hmidi->istimer && --hmidi->istimer <= 0)
1965 				timer_delete(&hmidi->timer);
1966 		}
1967 	}
1968 	if (up)
1969 		snd_hdspm_midi_output_write(hmidi);
1970 }
1971 
1972 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1973 {
1974 	struct hdspm_midi *hmidi;
1975 
1976 	hmidi = substream->rmidi->private_data;
1977 	guard(spinlock_irq)(&hmidi->lock);
1978 	snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1979 	hmidi->input = substream;
1980 
1981 	return 0;
1982 }
1983 
1984 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1985 {
1986 	struct hdspm_midi *hmidi;
1987 
1988 	hmidi = substream->rmidi->private_data;
1989 	guard(spinlock_irq)(&hmidi->lock);
1990 	hmidi->output = substream;
1991 
1992 	return 0;
1993 }
1994 
1995 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1996 {
1997 	struct hdspm_midi *hmidi;
1998 
1999 	snd_hdspm_midi_input_trigger (substream, 0);
2000 
2001 	hmidi = substream->rmidi->private_data;
2002 	guard(spinlock_irq)(&hmidi->lock);
2003 	hmidi->input = NULL;
2004 
2005 	return 0;
2006 }
2007 
2008 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
2009 {
2010 	struct hdspm_midi *hmidi;
2011 
2012 	snd_hdspm_midi_output_trigger (substream, 0);
2013 
2014 	hmidi = substream->rmidi->private_data;
2015 	guard(spinlock_irq)(&hmidi->lock);
2016 	hmidi->output = NULL;
2017 
2018 	return 0;
2019 }
2020 
2021 static const struct snd_rawmidi_ops snd_hdspm_midi_output =
2022 {
2023 	.open =		snd_hdspm_midi_output_open,
2024 	.close =	snd_hdspm_midi_output_close,
2025 	.trigger =	snd_hdspm_midi_output_trigger,
2026 };
2027 
2028 static const struct snd_rawmidi_ops snd_hdspm_midi_input =
2029 {
2030 	.open =		snd_hdspm_midi_input_open,
2031 	.close =	snd_hdspm_midi_input_close,
2032 	.trigger =	snd_hdspm_midi_input_trigger,
2033 };
2034 
2035 static int snd_hdspm_create_midi(struct snd_card *card,
2036 				 struct hdspm *hdspm, int id)
2037 {
2038 	int err;
2039 	char buf[64];
2040 
2041 	hdspm->midi[id].id = id;
2042 	hdspm->midi[id].hdspm = hdspm;
2043 	spin_lock_init (&hdspm->midi[id].lock);
2044 
2045 	if (0 == id) {
2046 		if (MADIface == hdspm->io_type) {
2047 			/* MIDI-over-MADI on HDSPe MADIface */
2048 			hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2049 			hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2050 			hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2051 			hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2052 			hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2053 			hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2054 		} else {
2055 			hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2056 			hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2057 			hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2058 			hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2059 			hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2060 			hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2061 		}
2062 	} else if (1 == id) {
2063 		hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2064 		hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2065 		hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2066 		hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2067 		hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2068 		hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2069 	} else if ((2 == id) && (MADI == hdspm->io_type)) {
2070 		/* MIDI-over-MADI on HDSPe MADI */
2071 		hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2072 		hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2073 		hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2074 		hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2075 		hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2076 		hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2077 	} else if (2 == id) {
2078 		/* TCO MTC, read only */
2079 		hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2080 		hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2081 		hdspm->midi[2].dataOut = -1;
2082 		hdspm->midi[2].statusOut = -1;
2083 		hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2084 		hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2085 	} else if (3 == id) {
2086 		/* TCO MTC on HDSPe MADI */
2087 		hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2088 		hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2089 		hdspm->midi[3].dataOut = -1;
2090 		hdspm->midi[3].statusOut = -1;
2091 		hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2092 		hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2093 	}
2094 
2095 	if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2096 					(MADIface == hdspm->io_type)))) {
2097 		if ((id == 0) && (MADIface == hdspm->io_type)) {
2098 			snprintf(buf, sizeof(buf), "%s MIDIoverMADI",
2099 				 card->shortname);
2100 		} else if ((id == 2) && (MADI == hdspm->io_type)) {
2101 			snprintf(buf, sizeof(buf), "%s MIDIoverMADI",
2102 				 card->shortname);
2103 		} else {
2104 			snprintf(buf, sizeof(buf), "%s MIDI %d",
2105 				 card->shortname, id+1);
2106 		}
2107 		err = snd_rawmidi_new(card, buf, id, 1, 1,
2108 				&hdspm->midi[id].rmidi);
2109 		if (err < 0)
2110 			return err;
2111 
2112 		snprintf(hdspm->midi[id].rmidi->name,
2113 			 sizeof(hdspm->midi[id].rmidi->name),
2114 			 "%s MIDI %d", card->id, id+1);
2115 		hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2116 
2117 		snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2118 				SNDRV_RAWMIDI_STREAM_OUTPUT,
2119 				&snd_hdspm_midi_output);
2120 		snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2121 				SNDRV_RAWMIDI_STREAM_INPUT,
2122 				&snd_hdspm_midi_input);
2123 
2124 		hdspm->midi[id].rmidi->info_flags |=
2125 			SNDRV_RAWMIDI_INFO_OUTPUT |
2126 			SNDRV_RAWMIDI_INFO_INPUT |
2127 			SNDRV_RAWMIDI_INFO_DUPLEX;
2128 	} else {
2129 		/* TCO MTC, read only */
2130 		snprintf(buf, sizeof(buf), "%s MTC %d",
2131 			 card->shortname, id+1);
2132 		err = snd_rawmidi_new(card, buf, id, 1, 1,
2133 				&hdspm->midi[id].rmidi);
2134 		if (err < 0)
2135 			return err;
2136 
2137 		snprintf(hdspm->midi[id].rmidi->name,
2138 			 sizeof(hdspm->midi[id].rmidi->name),
2139 			 "%s MTC %d", card->id, id+1);
2140 		hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2141 
2142 		snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2143 				SNDRV_RAWMIDI_STREAM_INPUT,
2144 				&snd_hdspm_midi_input);
2145 
2146 		hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2147 	}
2148 
2149 	return 0;
2150 }
2151 
2152 
2153 static void hdspm_midi_work(struct work_struct *work)
2154 {
2155 	struct hdspm *hdspm = container_of(work, struct hdspm, midi_work);
2156 	int i = 0;
2157 
2158 	while (i < hdspm->midiPorts) {
2159 		if (hdspm->midi[i].pending)
2160 			snd_hdspm_midi_input_read(&hdspm->midi[i]);
2161 
2162 		i++;
2163 	}
2164 }
2165 
2166 
2167 /*-----------------------------------------------------------------------------
2168   Status Interface
2169   ----------------------------------------------------------------------------*/
2170 
2171 /* get the system sample rate which is set */
2172 
2173 
2174 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2175 {
2176 	unsigned int period, rate;
2177 
2178 	period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2179 	rate = hdspm_calc_dds_value(hdspm, period);
2180 
2181 	return rate;
2182 }
2183 
2184 /*
2185  * Calculate the real sample rate from the
2186  * current DDS value.
2187  */
2188 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2189 {
2190 	unsigned int rate;
2191 
2192 	rate = hdspm_get_pll_freq(hdspm);
2193 
2194 	if (rate > 207000) {
2195 		/* Unreasonable high sample rate as seen on PCI MADI cards. */
2196 		if (0 == hdspm_system_clock_mode(hdspm)) {
2197 			/* master mode, return internal sample rate */
2198 			rate = hdspm->system_sample_rate;
2199 		} else {
2200 			/* slave mode, return external sample rate */
2201 			rate = hdspm_external_sample_rate(hdspm);
2202 			if (!rate)
2203 				rate = hdspm->system_sample_rate;
2204 		}
2205 	}
2206 
2207 	return rate;
2208 }
2209 
2210 
2211 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2212 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2213 	.name = xname, \
2214 	.index = xindex, \
2215 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2216 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2217 	.info = snd_hdspm_info_system_sample_rate, \
2218 	.put = snd_hdspm_put_system_sample_rate, \
2219 	.get = snd_hdspm_get_system_sample_rate \
2220 }
2221 
2222 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2223 					     struct snd_ctl_elem_info *uinfo)
2224 {
2225 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2226 	uinfo->count = 1;
2227 	uinfo->value.integer.min = 27000;
2228 	uinfo->value.integer.max = 207000;
2229 	uinfo->value.integer.step = 1;
2230 	return 0;
2231 }
2232 
2233 
2234 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2235 					    struct snd_ctl_elem_value *
2236 					    ucontrol)
2237 {
2238 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2239 
2240 	ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2241 	return 0;
2242 }
2243 
2244 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2245 					    struct snd_ctl_elem_value *
2246 					    ucontrol)
2247 {
2248 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2249 	int rate = ucontrol->value.integer.value[0];
2250 
2251 	if (rate < 27000 || rate > 207000)
2252 		return -EINVAL;
2253 	hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
2254 	return 0;
2255 }
2256 
2257 
2258 /*
2259  * Returns the WordClock sample rate class for the given card.
2260  */
2261 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2262 {
2263 	int status;
2264 
2265 	switch (hdspm->io_type) {
2266 	case RayDAT:
2267 	case AIO:
2268 		status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2269 		return (status >> 16) & 0xF;
2270 	case AES32:
2271 		status = hdspm_read(hdspm, HDSPM_statusRegister);
2272 		return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2273 	default:
2274 		break;
2275 	}
2276 
2277 
2278 	return 0;
2279 }
2280 
2281 
2282 /*
2283  * Returns the TCO sample rate class for the given card.
2284  */
2285 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2286 {
2287 	int status;
2288 
2289 	if (hdspm->tco) {
2290 		switch (hdspm->io_type) {
2291 		case RayDAT:
2292 		case AIO:
2293 			status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2294 			return (status >> 20) & 0xF;
2295 		case AES32:
2296 			status = hdspm_read(hdspm, HDSPM_statusRegister);
2297 			return (status >> 1) & 0xF;
2298 		default:
2299 			break;
2300 		}
2301 	}
2302 
2303 	return 0;
2304 }
2305 
2306 
2307 /*
2308  * Returns the SYNC_IN sample rate class for the given card.
2309  */
2310 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2311 {
2312 	int status;
2313 
2314 	if (hdspm->tco) {
2315 		switch (hdspm->io_type) {
2316 		case RayDAT:
2317 		case AIO:
2318 			status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2319 			return (status >> 12) & 0xF;
2320 		default:
2321 			break;
2322 		}
2323 	}
2324 
2325 	return 0;
2326 }
2327 
2328 /*
2329  * Returns the AES sample rate class for the given card.
2330  */
2331 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2332 {
2333 	int timecode;
2334 
2335 	switch (hdspm->io_type) {
2336 	case AES32:
2337 		timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2338 		return (timecode >> (4*index)) & 0xF;
2339 	default:
2340 		break;
2341 	}
2342 	return 0;
2343 }
2344 
2345 /*
2346  * Returns the sample rate class for input source <idx> for
2347  * 'new style' cards like the AIO and RayDAT.
2348  */
2349 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2350 {
2351 	int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2352 
2353 	return (status >> (idx*4)) & 0xF;
2354 }
2355 
2356 #define ENUMERATED_CTL_INFO(info, texts) \
2357 	snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2358 
2359 
2360 /* Helper function to query the external sample rate and return the
2361  * corresponding enum to be returned to userspace.
2362  */
2363 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2364 {
2365 	int rate = hdspm_external_sample_rate(hdspm);
2366 	int i, selected_rate = 0;
2367 	for (i = 1; i < 10; i++)
2368 		if (HDSPM_bit2freq(i) == rate) {
2369 			selected_rate = i;
2370 			break;
2371 		}
2372 	return selected_rate;
2373 }
2374 
2375 
2376 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2377 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2378 	.name = xname, \
2379 	.private_value = xindex, \
2380 	.access = SNDRV_CTL_ELEM_ACCESS_READ, \
2381 	.info = snd_hdspm_info_autosync_sample_rate, \
2382 	.get = snd_hdspm_get_autosync_sample_rate \
2383 }
2384 
2385 
2386 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2387 					       struct snd_ctl_elem_info *uinfo)
2388 {
2389 	ENUMERATED_CTL_INFO(uinfo, texts_freq);
2390 	return 0;
2391 }
2392 
2393 
2394 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2395 					      struct snd_ctl_elem_value *
2396 					      ucontrol)
2397 {
2398 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2399 
2400 	switch (hdspm->io_type) {
2401 	case RayDAT:
2402 		switch (kcontrol->private_value) {
2403 		case 0:
2404 			ucontrol->value.enumerated.item[0] =
2405 				hdspm_get_wc_sample_rate(hdspm);
2406 			break;
2407 		case 7:
2408 			ucontrol->value.enumerated.item[0] =
2409 				hdspm_get_tco_sample_rate(hdspm);
2410 			break;
2411 		case 8:
2412 			ucontrol->value.enumerated.item[0] =
2413 				hdspm_get_sync_in_sample_rate(hdspm);
2414 			break;
2415 		default:
2416 			ucontrol->value.enumerated.item[0] =
2417 				hdspm_get_s1_sample_rate(hdspm,
2418 						kcontrol->private_value-1);
2419 		}
2420 		break;
2421 
2422 	case AIO:
2423 		switch (kcontrol->private_value) {
2424 		case 0: /* WC */
2425 			ucontrol->value.enumerated.item[0] =
2426 				hdspm_get_wc_sample_rate(hdspm);
2427 			break;
2428 		case 4: /* TCO */
2429 			ucontrol->value.enumerated.item[0] =
2430 				hdspm_get_tco_sample_rate(hdspm);
2431 			break;
2432 		case 5: /* SYNC_IN */
2433 			ucontrol->value.enumerated.item[0] =
2434 				hdspm_get_sync_in_sample_rate(hdspm);
2435 			break;
2436 		default:
2437 			ucontrol->value.enumerated.item[0] =
2438 				hdspm_get_s1_sample_rate(hdspm,
2439 						kcontrol->private_value-1);
2440 		}
2441 		break;
2442 
2443 	case AES32:
2444 
2445 		switch (kcontrol->private_value) {
2446 		case 0: /* WC */
2447 			ucontrol->value.enumerated.item[0] =
2448 				hdspm_get_wc_sample_rate(hdspm);
2449 			break;
2450 		case 9: /* TCO */
2451 			ucontrol->value.enumerated.item[0] =
2452 				hdspm_get_tco_sample_rate(hdspm);
2453 			break;
2454 		case 10: /* SYNC_IN */
2455 			ucontrol->value.enumerated.item[0] =
2456 				hdspm_get_sync_in_sample_rate(hdspm);
2457 			break;
2458 		case 11: /* External Rate */
2459 			ucontrol->value.enumerated.item[0] =
2460 				hdspm_external_rate_to_enum(hdspm);
2461 			break;
2462 		default: /* AES1 to AES8 */
2463 			ucontrol->value.enumerated.item[0] =
2464 				hdspm_get_aes_sample_rate(hdspm,
2465 						kcontrol->private_value -
2466 						HDSPM_AES32_AUTOSYNC_FROM_AES1);
2467 			break;
2468 		}
2469 		break;
2470 
2471 	case MADI:
2472 	case MADIface:
2473 		ucontrol->value.enumerated.item[0] =
2474 			hdspm_external_rate_to_enum(hdspm);
2475 		break;
2476 	default:
2477 		break;
2478 	}
2479 
2480 	return 0;
2481 }
2482 
2483 
2484 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2485 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2486 	.name = xname, \
2487 	.index = xindex, \
2488 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2489 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2490 	.info = snd_hdspm_info_system_clock_mode, \
2491 	.get = snd_hdspm_get_system_clock_mode, \
2492 	.put = snd_hdspm_put_system_clock_mode, \
2493 }
2494 
2495 
2496 /*
2497  * Returns the system clock mode for the given card.
2498  * @returns 0 - master, 1 - slave
2499  */
2500 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2501 {
2502 	switch (hdspm->io_type) {
2503 	case AIO:
2504 	case RayDAT:
2505 		if (hdspm->settings_register & HDSPM_c0Master)
2506 			return 0;
2507 		break;
2508 
2509 	default:
2510 		if (hdspm->control_register & HDSPM_ClockModeMaster)
2511 			return 0;
2512 	}
2513 
2514 	return 1;
2515 }
2516 
2517 
2518 /*
2519  * Sets the system clock mode.
2520  * @param mode 0 - master, 1 - slave
2521  */
2522 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2523 {
2524 	hdspm_set_toggle_setting(hdspm,
2525 			(hdspm_is_raydat_or_aio(hdspm)) ?
2526 			HDSPM_c0Master : HDSPM_ClockModeMaster,
2527 			(0 == mode));
2528 }
2529 
2530 
2531 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2532 					    struct snd_ctl_elem_info *uinfo)
2533 {
2534 	static const char *const texts[] = { "Master", "AutoSync" };
2535 	ENUMERATED_CTL_INFO(uinfo, texts);
2536 	return 0;
2537 }
2538 
2539 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2540 					   struct snd_ctl_elem_value *ucontrol)
2541 {
2542 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2543 
2544 	ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2545 	return 0;
2546 }
2547 
2548 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2549 					   struct snd_ctl_elem_value *ucontrol)
2550 {
2551 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2552 	int val;
2553 
2554 	if (!snd_hdspm_use_is_exclusive(hdspm))
2555 		return -EBUSY;
2556 
2557 	val = ucontrol->value.enumerated.item[0];
2558 	if (val < 0)
2559 		val = 0;
2560 	else if (val > 1)
2561 		val = 1;
2562 
2563 	hdspm_set_system_clock_mode(hdspm, val);
2564 
2565 	return 0;
2566 }
2567 
2568 
2569 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2570 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2571 	.name = xname, \
2572 	.index = xindex, \
2573 	.info = snd_hdspm_info_clock_source, \
2574 	.get = snd_hdspm_get_clock_source, \
2575 	.put = snd_hdspm_put_clock_source \
2576 }
2577 
2578 
2579 static int hdspm_clock_source(struct hdspm * hdspm)
2580 {
2581 	switch (hdspm->system_sample_rate) {
2582 	case 32000: return 0;
2583 	case 44100: return 1;
2584 	case 48000: return 2;
2585 	case 64000: return 3;
2586 	case 88200: return 4;
2587 	case 96000: return 5;
2588 	case 128000: return 6;
2589 	case 176400: return 7;
2590 	case 192000: return 8;
2591 	}
2592 
2593 	return -1;
2594 }
2595 
2596 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2597 {
2598 	int rate;
2599 	switch (mode) {
2600 	case 0:
2601 		rate = 32000; break;
2602 	case 1:
2603 		rate = 44100; break;
2604 	case 2:
2605 		rate = 48000; break;
2606 	case 3:
2607 		rate = 64000; break;
2608 	case 4:
2609 		rate = 88200; break;
2610 	case 5:
2611 		rate = 96000; break;
2612 	case 6:
2613 		rate = 128000; break;
2614 	case 7:
2615 		rate = 176400; break;
2616 	case 8:
2617 		rate = 192000; break;
2618 	default:
2619 		rate = 48000;
2620 	}
2621 	hdspm_set_rate(hdspm, rate, 1);
2622 	return 0;
2623 }
2624 
2625 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2626 				       struct snd_ctl_elem_info *uinfo)
2627 {
2628 	return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1);
2629 }
2630 
2631 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2632 				      struct snd_ctl_elem_value *ucontrol)
2633 {
2634 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2635 
2636 	ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2637 	return 0;
2638 }
2639 
2640 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2641 				      struct snd_ctl_elem_value *ucontrol)
2642 {
2643 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2644 	int change;
2645 	int val;
2646 
2647 	if (!snd_hdspm_use_is_exclusive(hdspm))
2648 		return -EBUSY;
2649 	val = ucontrol->value.enumerated.item[0];
2650 	if (val < 0)
2651 		val = 0;
2652 	if (val > 9)
2653 		val = 9;
2654 	guard(spinlock_irq)(&hdspm->lock);
2655 	if (val != hdspm_clock_source(hdspm))
2656 		change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2657 	else
2658 		change = 0;
2659 	return change;
2660 }
2661 
2662 
2663 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2664 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2665 	.name = xname, \
2666 	.index = xindex, \
2667 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2668 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2669 	.info = snd_hdspm_info_pref_sync_ref, \
2670 	.get = snd_hdspm_get_pref_sync_ref, \
2671 	.put = snd_hdspm_put_pref_sync_ref \
2672 }
2673 
2674 
2675 /*
2676  * Returns the current preferred sync reference setting.
2677  * The semantics of the return value are depending on the
2678  * card, please see the comments for clarification.
2679  */
2680 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2681 {
2682 	switch (hdspm->io_type) {
2683 	case AES32:
2684 		switch (hdspm->control_register & HDSPM_SyncRefMask) {
2685 		case 0: return 0;  /* WC */
2686 		case HDSPM_SyncRef0: return 1; /* AES 1 */
2687 		case HDSPM_SyncRef1: return 2; /* AES 2 */
2688 		case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2689 		case HDSPM_SyncRef2: return 4; /* AES 4 */
2690 		case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2691 		case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2692 		case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2693 						    return 7; /* AES 7 */
2694 		case HDSPM_SyncRef3: return 8; /* AES 8 */
2695 		case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2696 		}
2697 		break;
2698 
2699 	case MADI:
2700 	case MADIface:
2701 		if (hdspm->tco) {
2702 			switch (hdspm->control_register & HDSPM_SyncRefMask) {
2703 			case 0: return 0;  /* WC */
2704 			case HDSPM_SyncRef0: return 1;  /* MADI */
2705 			case HDSPM_SyncRef1: return 2;  /* TCO */
2706 			case HDSPM_SyncRef1+HDSPM_SyncRef0:
2707 					     return 3;  /* SYNC_IN */
2708 			}
2709 		} else {
2710 			switch (hdspm->control_register & HDSPM_SyncRefMask) {
2711 			case 0: return 0;  /* WC */
2712 			case HDSPM_SyncRef0: return 1;  /* MADI */
2713 			case HDSPM_SyncRef1+HDSPM_SyncRef0:
2714 					     return 2;  /* SYNC_IN */
2715 			}
2716 		}
2717 		break;
2718 
2719 	case RayDAT:
2720 		if (hdspm->tco) {
2721 			switch ((hdspm->settings_register &
2722 				HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2723 			case 0: return 0;  /* WC */
2724 			case 3: return 1;  /* ADAT 1 */
2725 			case 4: return 2;  /* ADAT 2 */
2726 			case 5: return 3;  /* ADAT 3 */
2727 			case 6: return 4;  /* ADAT 4 */
2728 			case 1: return 5;  /* AES */
2729 			case 2: return 6;  /* SPDIF */
2730 			case 9: return 7;  /* TCO */
2731 			case 10: return 8; /* SYNC_IN */
2732 			}
2733 		} else {
2734 			switch ((hdspm->settings_register &
2735 				HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2736 			case 0: return 0;  /* WC */
2737 			case 3: return 1;  /* ADAT 1 */
2738 			case 4: return 2;  /* ADAT 2 */
2739 			case 5: return 3;  /* ADAT 3 */
2740 			case 6: return 4;  /* ADAT 4 */
2741 			case 1: return 5;  /* AES */
2742 			case 2: return 6;  /* SPDIF */
2743 			case 10: return 7; /* SYNC_IN */
2744 			}
2745 		}
2746 
2747 		break;
2748 
2749 	case AIO:
2750 		if (hdspm->tco) {
2751 			switch ((hdspm->settings_register &
2752 				HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2753 			case 0: return 0;  /* WC */
2754 			case 3: return 1;  /* ADAT */
2755 			case 1: return 2;  /* AES */
2756 			case 2: return 3;  /* SPDIF */
2757 			case 9: return 4;  /* TCO */
2758 			case 10: return 5; /* SYNC_IN */
2759 			}
2760 		} else {
2761 			switch ((hdspm->settings_register &
2762 				HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2763 			case 0: return 0;  /* WC */
2764 			case 3: return 1;  /* ADAT */
2765 			case 1: return 2;  /* AES */
2766 			case 2: return 3;  /* SPDIF */
2767 			case 10: return 4; /* SYNC_IN */
2768 			}
2769 		}
2770 
2771 		break;
2772 	}
2773 
2774 	return -1;
2775 }
2776 
2777 
2778 /*
2779  * Set the preferred sync reference to <pref>. The semantics
2780  * of <pref> are depending on the card type, see the comments
2781  * for clarification.
2782  */
2783 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2784 {
2785 	int p = 0;
2786 
2787 	switch (hdspm->io_type) {
2788 	case AES32:
2789 		hdspm->control_register &= ~HDSPM_SyncRefMask;
2790 		switch (pref) {
2791 		case 0: /* WC  */
2792 			break;
2793 		case 1: /* AES 1 */
2794 			hdspm->control_register |= HDSPM_SyncRef0;
2795 			break;
2796 		case 2: /* AES 2 */
2797 			hdspm->control_register |= HDSPM_SyncRef1;
2798 			break;
2799 		case 3: /* AES 3 */
2800 			hdspm->control_register |=
2801 				HDSPM_SyncRef1+HDSPM_SyncRef0;
2802 			break;
2803 		case 4: /* AES 4 */
2804 			hdspm->control_register |= HDSPM_SyncRef2;
2805 			break;
2806 		case 5: /* AES 5 */
2807 			hdspm->control_register |=
2808 				HDSPM_SyncRef2+HDSPM_SyncRef0;
2809 			break;
2810 		case 6: /* AES 6 */
2811 			hdspm->control_register |=
2812 				HDSPM_SyncRef2+HDSPM_SyncRef1;
2813 			break;
2814 		case 7: /* AES 7 */
2815 			hdspm->control_register |=
2816 				HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2817 			break;
2818 		case 8: /* AES 8 */
2819 			hdspm->control_register |= HDSPM_SyncRef3;
2820 			break;
2821 		case 9: /* TCO */
2822 			hdspm->control_register |=
2823 				HDSPM_SyncRef3+HDSPM_SyncRef0;
2824 			break;
2825 		default:
2826 			return -1;
2827 		}
2828 
2829 		break;
2830 
2831 	case MADI:
2832 	case MADIface:
2833 		hdspm->control_register &= ~HDSPM_SyncRefMask;
2834 		if (hdspm->tco) {
2835 			switch (pref) {
2836 			case 0: /* WC */
2837 				break;
2838 			case 1: /* MADI */
2839 				hdspm->control_register |= HDSPM_SyncRef0;
2840 				break;
2841 			case 2: /* TCO */
2842 				hdspm->control_register |= HDSPM_SyncRef1;
2843 				break;
2844 			case 3: /* SYNC_IN */
2845 				hdspm->control_register |=
2846 					HDSPM_SyncRef0+HDSPM_SyncRef1;
2847 				break;
2848 			default:
2849 				return -1;
2850 			}
2851 		} else {
2852 			switch (pref) {
2853 			case 0: /* WC */
2854 				break;
2855 			case 1: /* MADI */
2856 				hdspm->control_register |= HDSPM_SyncRef0;
2857 				break;
2858 			case 2: /* SYNC_IN */
2859 				hdspm->control_register |=
2860 					HDSPM_SyncRef0+HDSPM_SyncRef1;
2861 				break;
2862 			default:
2863 				return -1;
2864 			}
2865 		}
2866 
2867 		break;
2868 
2869 	case RayDAT:
2870 		if (hdspm->tco) {
2871 			switch (pref) {
2872 			case 0: p = 0; break;  /* WC */
2873 			case 1: p = 3; break;  /* ADAT 1 */
2874 			case 2: p = 4; break;  /* ADAT 2 */
2875 			case 3: p = 5; break;  /* ADAT 3 */
2876 			case 4: p = 6; break;  /* ADAT 4 */
2877 			case 5: p = 1; break;  /* AES */
2878 			case 6: p = 2; break;  /* SPDIF */
2879 			case 7: p = 9; break;  /* TCO */
2880 			case 8: p = 10; break; /* SYNC_IN */
2881 			default: return -1;
2882 			}
2883 		} else {
2884 			switch (pref) {
2885 			case 0: p = 0; break;  /* WC */
2886 			case 1: p = 3; break;  /* ADAT 1 */
2887 			case 2: p = 4; break;  /* ADAT 2 */
2888 			case 3: p = 5; break;  /* ADAT 3 */
2889 			case 4: p = 6; break;  /* ADAT 4 */
2890 			case 5: p = 1; break;  /* AES */
2891 			case 6: p = 2; break;  /* SPDIF */
2892 			case 7: p = 10; break; /* SYNC_IN */
2893 			default: return -1;
2894 			}
2895 		}
2896 		break;
2897 
2898 	case AIO:
2899 		if (hdspm->tco) {
2900 			switch (pref) {
2901 			case 0: p = 0; break;  /* WC */
2902 			case 1: p = 3; break;  /* ADAT */
2903 			case 2: p = 1; break;  /* AES */
2904 			case 3: p = 2; break;  /* SPDIF */
2905 			case 4: p = 9; break;  /* TCO */
2906 			case 5: p = 10; break; /* SYNC_IN */
2907 			default: return -1;
2908 			}
2909 		} else {
2910 			switch (pref) {
2911 			case 0: p = 0; break;  /* WC */
2912 			case 1: p = 3; break;  /* ADAT */
2913 			case 2: p = 1; break;  /* AES */
2914 			case 3: p = 2; break;  /* SPDIF */
2915 			case 4: p = 10; break; /* SYNC_IN */
2916 			default: return -1;
2917 			}
2918 		}
2919 		break;
2920 	}
2921 
2922 	switch (hdspm->io_type) {
2923 	case RayDAT:
2924 	case AIO:
2925 		hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2926 		hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2927 		hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2928 		break;
2929 
2930 	case MADI:
2931 	case MADIface:
2932 	case AES32:
2933 		hdspm_write(hdspm, HDSPM_controlRegister,
2934 				hdspm->control_register);
2935 	}
2936 
2937 	return 0;
2938 }
2939 
2940 
2941 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2942 					struct snd_ctl_elem_info *uinfo)
2943 {
2944 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2945 
2946 	snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2947 
2948 	return 0;
2949 }
2950 
2951 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2952 				       struct snd_ctl_elem_value *ucontrol)
2953 {
2954 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2955 	int psf = hdspm_pref_sync_ref(hdspm);
2956 
2957 	if (psf >= 0) {
2958 		ucontrol->value.enumerated.item[0] = psf;
2959 		return 0;
2960 	}
2961 
2962 	return -1;
2963 }
2964 
2965 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2966 				       struct snd_ctl_elem_value *ucontrol)
2967 {
2968 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2969 	int val, change = 0;
2970 
2971 	if (!snd_hdspm_use_is_exclusive(hdspm))
2972 		return -EBUSY;
2973 
2974 	val = ucontrol->value.enumerated.item[0];
2975 
2976 	if (val < 0)
2977 		val = 0;
2978 	else if (val >= hdspm->texts_autosync_items)
2979 		val = hdspm->texts_autosync_items-1;
2980 
2981 	guard(spinlock_irq)(&hdspm->lock);
2982 	if (val != hdspm_pref_sync_ref(hdspm))
2983 		change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2984 
2985 	return change;
2986 }
2987 
2988 
2989 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2990 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2991 	.name = xname, \
2992 	.index = xindex, \
2993 	.access = SNDRV_CTL_ELEM_ACCESS_READ, \
2994 	.info = snd_hdspm_info_autosync_ref, \
2995 	.get = snd_hdspm_get_autosync_ref, \
2996 }
2997 
2998 static int hdspm_autosync_ref(struct hdspm *hdspm)
2999 {
3000 	/* This looks at the autosync selected sync reference */
3001 	if (AES32 == hdspm->io_type) {
3002 
3003 		unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3004 		unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3005 		/* syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD is always true */
3006 		if (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN) {
3007 			return syncref;
3008 		}
3009 		return HDSPM_AES32_AUTOSYNC_FROM_NONE;
3010 
3011 	} else if (MADI == hdspm->io_type) {
3012 
3013 		unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3014 		switch (status2 & HDSPM_SelSyncRefMask) {
3015 		case HDSPM_SelSyncRef_WORD:
3016 			return HDSPM_AUTOSYNC_FROM_WORD;
3017 		case HDSPM_SelSyncRef_MADI:
3018 			return HDSPM_AUTOSYNC_FROM_MADI;
3019 		case HDSPM_SelSyncRef_TCO:
3020 			return HDSPM_AUTOSYNC_FROM_TCO;
3021 		case HDSPM_SelSyncRef_SyncIn:
3022 			return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3023 		case HDSPM_SelSyncRef_NVALID:
3024 			return HDSPM_AUTOSYNC_FROM_NONE;
3025 		default:
3026 			return HDSPM_AUTOSYNC_FROM_NONE;
3027 		}
3028 
3029 	}
3030 	return 0;
3031 }
3032 
3033 
3034 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3035 				       struct snd_ctl_elem_info *uinfo)
3036 {
3037 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3038 
3039 	if (AES32 == hdspm->io_type) {
3040 		static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
3041 			"AES4",	"AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3042 
3043 		ENUMERATED_CTL_INFO(uinfo, texts);
3044 	} else if (MADI == hdspm->io_type) {
3045 		static const char *const texts[] = {"Word Clock", "MADI", "TCO",
3046 			"Sync In", "None" };
3047 
3048 		ENUMERATED_CTL_INFO(uinfo, texts);
3049 	}
3050 	return 0;
3051 }
3052 
3053 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3054 				      struct snd_ctl_elem_value *ucontrol)
3055 {
3056 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3057 
3058 	ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3059 	return 0;
3060 }
3061 
3062 
3063 
3064 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname) \
3065 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3066 	.name = xname, \
3067 	.access = SNDRV_CTL_ELEM_ACCESS_READ |\
3068 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3069 	.info = snd_hdspm_info_tco_video_input_format, \
3070 	.get = snd_hdspm_get_tco_video_input_format, \
3071 }
3072 
3073 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3074 				       struct snd_ctl_elem_info *uinfo)
3075 {
3076 	static const char *const texts[] = {"No video", "NTSC", "PAL"};
3077 	ENUMERATED_CTL_INFO(uinfo, texts);
3078 	return 0;
3079 }
3080 
3081 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3082 				      struct snd_ctl_elem_value *ucontrol)
3083 {
3084 	u32 status;
3085 	int ret = 0;
3086 
3087 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3088 	status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3089 	switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3090 			HDSPM_TCO1_Video_Input_Format_PAL)) {
3091 	case HDSPM_TCO1_Video_Input_Format_NTSC:
3092 		/* ntsc */
3093 		ret = 1;
3094 		break;
3095 	case HDSPM_TCO1_Video_Input_Format_PAL:
3096 		/* pal */
3097 		ret = 2;
3098 		break;
3099 	default:
3100 		/* no video */
3101 		ret = 0;
3102 		break;
3103 	}
3104 	ucontrol->value.enumerated.item[0] = ret;
3105 	return 0;
3106 }
3107 
3108 
3109 
3110 #define HDSPM_TCO_LTC_FRAMES(xname) \
3111 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3112 	.name = xname, \
3113 	.access = SNDRV_CTL_ELEM_ACCESS_READ |\
3114 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3115 	.info = snd_hdspm_info_tco_ltc_frames, \
3116 	.get = snd_hdspm_get_tco_ltc_frames, \
3117 }
3118 
3119 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3120 				       struct snd_ctl_elem_info *uinfo)
3121 {
3122 	static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3123 				"30 fps"};
3124 	ENUMERATED_CTL_INFO(uinfo, texts);
3125 	return 0;
3126 }
3127 
3128 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3129 {
3130 	u32 status;
3131 	int ret = 0;
3132 
3133 	status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3134 	if (status & HDSPM_TCO1_LTC_Input_valid) {
3135 		switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3136 					HDSPM_TCO1_LTC_Format_MSB)) {
3137 		case 0:
3138 			/* 24 fps */
3139 			ret = fps_24;
3140 			break;
3141 		case HDSPM_TCO1_LTC_Format_LSB:
3142 			/* 25 fps */
3143 			ret = fps_25;
3144 			break;
3145 		case HDSPM_TCO1_LTC_Format_MSB:
3146 			/* 29.97 fps */
3147 			ret = fps_2997;
3148 			break;
3149 		default:
3150 			/* 30 fps */
3151 			ret = fps_30;
3152 			break;
3153 		}
3154 	}
3155 
3156 	return ret;
3157 }
3158 
3159 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3160 				      struct snd_ctl_elem_value *ucontrol)
3161 {
3162 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3163 
3164 	ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3165 	return 0;
3166 }
3167 
3168 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3169 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3170 	.name = xname, \
3171 	.private_value = xindex, \
3172 	.info = snd_hdspm_info_toggle_setting, \
3173 	.get = snd_hdspm_get_toggle_setting, \
3174 	.put = snd_hdspm_put_toggle_setting \
3175 }
3176 
3177 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3178 {
3179 	u32 reg;
3180 
3181 	if (hdspm_is_raydat_or_aio(hdspm))
3182 		reg = hdspm->settings_register;
3183 	else
3184 		reg = hdspm->control_register;
3185 
3186 	return (reg & regmask) ? 1 : 0;
3187 }
3188 
3189 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3190 {
3191 	u32 *reg;
3192 	u32 target_reg;
3193 
3194 	if (hdspm_is_raydat_or_aio(hdspm)) {
3195 		reg = &(hdspm->settings_register);
3196 		target_reg = HDSPM_WR_SETTINGS;
3197 	} else {
3198 		reg = &(hdspm->control_register);
3199 		target_reg = HDSPM_controlRegister;
3200 	}
3201 
3202 	if (out)
3203 		*reg |= regmask;
3204 	else
3205 		*reg &= ~regmask;
3206 
3207 	hdspm_write(hdspm, target_reg, *reg);
3208 
3209 	return 0;
3210 }
3211 
3212 #define snd_hdspm_info_toggle_setting		snd_ctl_boolean_mono_info
3213 
3214 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3215 			       struct snd_ctl_elem_value *ucontrol)
3216 {
3217 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3218 	u32 regmask = kcontrol->private_value;
3219 
3220 	guard(spinlock_irq)(&hdspm->lock);
3221 	ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3222 	return 0;
3223 }
3224 
3225 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3226 			       struct snd_ctl_elem_value *ucontrol)
3227 {
3228 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3229 	u32 regmask = kcontrol->private_value;
3230 	int change;
3231 	unsigned int val;
3232 
3233 	if (!snd_hdspm_use_is_exclusive(hdspm))
3234 		return -EBUSY;
3235 	val = ucontrol->value.integer.value[0] & 1;
3236 	guard(spinlock_irq)(&hdspm->lock);
3237 	change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3238 	hdspm_set_toggle_setting(hdspm, regmask, val);
3239 	return change;
3240 }
3241 
3242 #define HDSPM_INPUT_SELECT(xname, xindex) \
3243 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3244 	.name = xname, \
3245 	.index = xindex, \
3246 	.info = snd_hdspm_info_input_select, \
3247 	.get = snd_hdspm_get_input_select, \
3248 	.put = snd_hdspm_put_input_select \
3249 }
3250 
3251 static int hdspm_input_select(struct hdspm * hdspm)
3252 {
3253 	return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3254 }
3255 
3256 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3257 {
3258 	if (out)
3259 		hdspm->control_register |= HDSPM_InputSelect0;
3260 	else
3261 		hdspm->control_register &= ~HDSPM_InputSelect0;
3262 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3263 
3264 	return 0;
3265 }
3266 
3267 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3268 				       struct snd_ctl_elem_info *uinfo)
3269 {
3270 	static const char *const texts[] = { "optical", "coaxial" };
3271 	ENUMERATED_CTL_INFO(uinfo, texts);
3272 	return 0;
3273 }
3274 
3275 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3276 				      struct snd_ctl_elem_value *ucontrol)
3277 {
3278 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3279 
3280 	guard(spinlock_irq)(&hdspm->lock);
3281 	ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3282 	return 0;
3283 }
3284 
3285 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3286 				      struct snd_ctl_elem_value *ucontrol)
3287 {
3288 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3289 	int change;
3290 	unsigned int val;
3291 
3292 	if (!snd_hdspm_use_is_exclusive(hdspm))
3293 		return -EBUSY;
3294 	val = ucontrol->value.integer.value[0] & 1;
3295 	guard(spinlock_irq)(&hdspm->lock);
3296 	change = (int) val != hdspm_input_select(hdspm);
3297 	hdspm_set_input_select(hdspm, val);
3298 	return change;
3299 }
3300 
3301 
3302 #define HDSPM_DS_WIRE(xname, xindex) \
3303 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3304 	.name = xname, \
3305 	.index = xindex, \
3306 	.info = snd_hdspm_info_ds_wire, \
3307 	.get = snd_hdspm_get_ds_wire, \
3308 	.put = snd_hdspm_put_ds_wire \
3309 }
3310 
3311 static int hdspm_ds_wire(struct hdspm * hdspm)
3312 {
3313 	return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3314 }
3315 
3316 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3317 {
3318 	if (ds)
3319 		hdspm->control_register |= HDSPM_DS_DoubleWire;
3320 	else
3321 		hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3322 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3323 
3324 	return 0;
3325 }
3326 
3327 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3328 				  struct snd_ctl_elem_info *uinfo)
3329 {
3330 	static const char *const texts[] = { "Single", "Double" };
3331 	ENUMERATED_CTL_INFO(uinfo, texts);
3332 	return 0;
3333 }
3334 
3335 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3336 				 struct snd_ctl_elem_value *ucontrol)
3337 {
3338 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3339 
3340 	guard(spinlock_irq)(&hdspm->lock);
3341 	ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3342 	return 0;
3343 }
3344 
3345 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3346 				 struct snd_ctl_elem_value *ucontrol)
3347 {
3348 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3349 	int change;
3350 	unsigned int val;
3351 
3352 	if (!snd_hdspm_use_is_exclusive(hdspm))
3353 		return -EBUSY;
3354 	val = ucontrol->value.integer.value[0] & 1;
3355 	guard(spinlock_irq)(&hdspm->lock);
3356 	change = (int) val != hdspm_ds_wire(hdspm);
3357 	hdspm_set_ds_wire(hdspm, val);
3358 	return change;
3359 }
3360 
3361 
3362 #define HDSPM_QS_WIRE(xname, xindex) \
3363 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3364 	.name = xname, \
3365 	.index = xindex, \
3366 	.info = snd_hdspm_info_qs_wire, \
3367 	.get = snd_hdspm_get_qs_wire, \
3368 	.put = snd_hdspm_put_qs_wire \
3369 }
3370 
3371 static int hdspm_qs_wire(struct hdspm * hdspm)
3372 {
3373 	if (hdspm->control_register & HDSPM_QS_DoubleWire)
3374 		return 1;
3375 	if (hdspm->control_register & HDSPM_QS_QuadWire)
3376 		return 2;
3377 	return 0;
3378 }
3379 
3380 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3381 {
3382 	hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3383 	switch (mode) {
3384 	case 0:
3385 		break;
3386 	case 1:
3387 		hdspm->control_register |= HDSPM_QS_DoubleWire;
3388 		break;
3389 	case 2:
3390 		hdspm->control_register |= HDSPM_QS_QuadWire;
3391 		break;
3392 	}
3393 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3394 
3395 	return 0;
3396 }
3397 
3398 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3399 				       struct snd_ctl_elem_info *uinfo)
3400 {
3401 	static const char *const texts[] = { "Single", "Double", "Quad" };
3402 	ENUMERATED_CTL_INFO(uinfo, texts);
3403 	return 0;
3404 }
3405 
3406 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3407 				      struct snd_ctl_elem_value *ucontrol)
3408 {
3409 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3410 
3411 	guard(spinlock_irq)(&hdspm->lock);
3412 	ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3413 	return 0;
3414 }
3415 
3416 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3417 				      struct snd_ctl_elem_value *ucontrol)
3418 {
3419 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3420 	int change;
3421 	int val;
3422 
3423 	if (!snd_hdspm_use_is_exclusive(hdspm))
3424 		return -EBUSY;
3425 	val = ucontrol->value.integer.value[0];
3426 	if (val < 0)
3427 		val = 0;
3428 	if (val > 2)
3429 		val = 2;
3430 	guard(spinlock_irq)(&hdspm->lock);
3431 	change = val != hdspm_qs_wire(hdspm);
3432 	hdspm_set_qs_wire(hdspm, val);
3433 	return change;
3434 }
3435 
3436 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3437 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3438 	.name = xname, \
3439 	.private_value = xindex, \
3440 	.info = snd_hdspm_info_tristate, \
3441 	.get = snd_hdspm_get_tristate, \
3442 	.put = snd_hdspm_put_tristate \
3443 }
3444 
3445 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3446 {
3447 	u32 reg = hdspm->settings_register & (regmask * 3);
3448 	return reg / regmask;
3449 }
3450 
3451 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3452 {
3453 	hdspm->settings_register &= ~(regmask * 3);
3454 	hdspm->settings_register |= (regmask * mode);
3455 	hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3456 
3457 	return 0;
3458 }
3459 
3460 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3461 				       struct snd_ctl_elem_info *uinfo)
3462 {
3463 	u32 regmask = kcontrol->private_value;
3464 
3465 	static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3466 	static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3467 
3468 	switch (regmask) {
3469 	case HDSPM_c0_Input0:
3470 		ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3471 		break;
3472 	default:
3473 		ENUMERATED_CTL_INFO(uinfo, texts_levels);
3474 		break;
3475 	}
3476 	return 0;
3477 }
3478 
3479 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3480 				      struct snd_ctl_elem_value *ucontrol)
3481 {
3482 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3483 	u32 regmask = kcontrol->private_value;
3484 
3485 	guard(spinlock_irq)(&hdspm->lock);
3486 	ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3487 	return 0;
3488 }
3489 
3490 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3491 				      struct snd_ctl_elem_value *ucontrol)
3492 {
3493 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3494 	u32 regmask = kcontrol->private_value;
3495 	int change;
3496 	int val;
3497 
3498 	if (!snd_hdspm_use_is_exclusive(hdspm))
3499 		return -EBUSY;
3500 	val = ucontrol->value.integer.value[0];
3501 	if (val < 0)
3502 		val = 0;
3503 	if (val > 2)
3504 		val = 2;
3505 
3506 	guard(spinlock_irq)(&hdspm->lock);
3507 	change = val != hdspm_tristate(hdspm, regmask);
3508 	hdspm_set_tristate(hdspm, val, regmask);
3509 	return change;
3510 }
3511 
3512 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3513 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3514 	.name = xname, \
3515 	.index = xindex, \
3516 	.info = snd_hdspm_info_madi_speedmode, \
3517 	.get = snd_hdspm_get_madi_speedmode, \
3518 	.put = snd_hdspm_put_madi_speedmode \
3519 }
3520 
3521 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3522 {
3523 	if (hdspm->control_register & HDSPM_QuadSpeed)
3524 		return 2;
3525 	if (hdspm->control_register & HDSPM_DoubleSpeed)
3526 		return 1;
3527 	return 0;
3528 }
3529 
3530 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3531 {
3532 	hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3533 	switch (mode) {
3534 	case 0:
3535 		break;
3536 	case 1:
3537 		hdspm->control_register |= HDSPM_DoubleSpeed;
3538 		break;
3539 	case 2:
3540 		hdspm->control_register |= HDSPM_QuadSpeed;
3541 		break;
3542 	}
3543 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3544 
3545 	return 0;
3546 }
3547 
3548 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3549 				       struct snd_ctl_elem_info *uinfo)
3550 {
3551 	static const char *const texts[] = { "Single", "Double", "Quad" };
3552 	ENUMERATED_CTL_INFO(uinfo, texts);
3553 	return 0;
3554 }
3555 
3556 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3557 				      struct snd_ctl_elem_value *ucontrol)
3558 {
3559 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3560 
3561 	guard(spinlock_irq)(&hdspm->lock);
3562 	ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3563 	return 0;
3564 }
3565 
3566 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3567 				      struct snd_ctl_elem_value *ucontrol)
3568 {
3569 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3570 	int change;
3571 	int val;
3572 
3573 	if (!snd_hdspm_use_is_exclusive(hdspm))
3574 		return -EBUSY;
3575 	val = ucontrol->value.integer.value[0];
3576 	if (val < 0)
3577 		val = 0;
3578 	if (val > 2)
3579 		val = 2;
3580 	guard(spinlock_irq)(&hdspm->lock);
3581 	change = val != hdspm_madi_speedmode(hdspm);
3582 	hdspm_set_madi_speedmode(hdspm, val);
3583 	return change;
3584 }
3585 
3586 #define HDSPM_MIXER(xname, xindex) \
3587 {	.iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3588 	.name = xname, \
3589 	.index = xindex, \
3590 	.device = 0, \
3591 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3592 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3593 	.info = snd_hdspm_info_mixer, \
3594 	.get = snd_hdspm_get_mixer, \
3595 	.put = snd_hdspm_put_mixer \
3596 }
3597 
3598 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3599 				struct snd_ctl_elem_info *uinfo)
3600 {
3601 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3602 	uinfo->count = 3;
3603 	uinfo->value.integer.min = 0;
3604 	uinfo->value.integer.max = 65535;
3605 	uinfo->value.integer.step = 1;
3606 	return 0;
3607 }
3608 
3609 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3610 			       struct snd_ctl_elem_value *ucontrol)
3611 {
3612 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3613 	int source;
3614 	int destination;
3615 
3616 	source = ucontrol->value.integer.value[0];
3617 	if (source < 0)
3618 		source = 0;
3619 	else if (source >= 2 * HDSPM_MAX_CHANNELS)
3620 		source = 2 * HDSPM_MAX_CHANNELS - 1;
3621 
3622 	destination = ucontrol->value.integer.value[1];
3623 	if (destination < 0)
3624 		destination = 0;
3625 	else if (destination >= HDSPM_MAX_CHANNELS)
3626 		destination = HDSPM_MAX_CHANNELS - 1;
3627 
3628 	guard(spinlock_irq)(&hdspm->lock);
3629 	if (source >= HDSPM_MAX_CHANNELS)
3630 		ucontrol->value.integer.value[2] =
3631 		    hdspm_read_pb_gain(hdspm, destination,
3632 				       source - HDSPM_MAX_CHANNELS);
3633 	else
3634 		ucontrol->value.integer.value[2] =
3635 		    hdspm_read_in_gain(hdspm, destination, source);
3636 
3637 	return 0;
3638 }
3639 
3640 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3641 			       struct snd_ctl_elem_value *ucontrol)
3642 {
3643 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3644 	int change;
3645 	int source;
3646 	int destination;
3647 	int gain;
3648 
3649 	if (!snd_hdspm_use_is_exclusive(hdspm))
3650 		return -EBUSY;
3651 
3652 	source = ucontrol->value.integer.value[0];
3653 	destination = ucontrol->value.integer.value[1];
3654 
3655 	if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3656 		return -1;
3657 	if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3658 		return -1;
3659 
3660 	gain = ucontrol->value.integer.value[2];
3661 
3662 	guard(spinlock_irq)(&hdspm->lock);
3663 
3664 	if (source >= HDSPM_MAX_CHANNELS)
3665 		change = gain != hdspm_read_pb_gain(hdspm, destination,
3666 						    source -
3667 						    HDSPM_MAX_CHANNELS);
3668 	else
3669 		change = gain != hdspm_read_in_gain(hdspm, destination,
3670 						    source);
3671 
3672 	if (change) {
3673 		if (source >= HDSPM_MAX_CHANNELS)
3674 			hdspm_write_pb_gain(hdspm, destination,
3675 					    source - HDSPM_MAX_CHANNELS,
3676 					    gain);
3677 		else
3678 			hdspm_write_in_gain(hdspm, destination, source,
3679 					    gain);
3680 	}
3681 
3682 	return change;
3683 }
3684 
3685 /* The simple mixer control(s) provide gain control for the
3686    basic 1:1 mappings of playback streams to output
3687    streams.
3688 */
3689 
3690 #define HDSPM_PLAYBACK_MIXER \
3691 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3692 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3693 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3694 	.info = snd_hdspm_info_playback_mixer, \
3695 	.get = snd_hdspm_get_playback_mixer, \
3696 	.put = snd_hdspm_put_playback_mixer \
3697 }
3698 
3699 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3700 					 struct snd_ctl_elem_info *uinfo)
3701 {
3702 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3703 	uinfo->count = 1;
3704 	uinfo->value.integer.min = 0;
3705 	uinfo->value.integer.max = 64;
3706 	uinfo->value.integer.step = 1;
3707 	return 0;
3708 }
3709 
3710 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3711 					struct snd_ctl_elem_value *ucontrol)
3712 {
3713 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3714 	int channel;
3715 
3716 	channel = ucontrol->id.index - 1;
3717 
3718 	if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3719 		return -EINVAL;
3720 
3721 	guard(spinlock_irq)(&hdspm->lock);
3722 	ucontrol->value.integer.value[0] =
3723 	  (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3724 
3725 	return 0;
3726 }
3727 
3728 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3729 					struct snd_ctl_elem_value *ucontrol)
3730 {
3731 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3732 	int change;
3733 	int channel;
3734 	int gain;
3735 
3736 	if (!snd_hdspm_use_is_exclusive(hdspm))
3737 		return -EBUSY;
3738 
3739 	channel = ucontrol->id.index - 1;
3740 
3741 	if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3742 		return -EINVAL;
3743 
3744 	gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3745 
3746 	guard(spinlock_irq)(&hdspm->lock);
3747 	change =
3748 	    gain != hdspm_read_pb_gain(hdspm, channel,
3749 				       channel);
3750 	if (change)
3751 		hdspm_write_pb_gain(hdspm, channel, channel,
3752 				    gain);
3753 	return change;
3754 }
3755 
3756 #define HDSPM_SYNC_CHECK(xname, xindex) \
3757 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3758 	.name = xname, \
3759 	.private_value = xindex, \
3760 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3761 	.info = snd_hdspm_info_sync_check, \
3762 	.get = snd_hdspm_get_sync_check \
3763 }
3764 
3765 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3766 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3767 	.name = xname, \
3768 	.private_value = xindex, \
3769 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3770 	.info = snd_hdspm_tco_info_lock_check, \
3771 	.get = snd_hdspm_get_sync_check \
3772 }
3773 
3774 
3775 
3776 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3777 				     struct snd_ctl_elem_info *uinfo)
3778 {
3779 	static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3780 	ENUMERATED_CTL_INFO(uinfo, texts);
3781 	return 0;
3782 }
3783 
3784 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3785 				     struct snd_ctl_elem_info *uinfo)
3786 {
3787 	static const char *const texts[] = { "No Lock", "Lock" };
3788 	ENUMERATED_CTL_INFO(uinfo, texts);
3789 	return 0;
3790 }
3791 
3792 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3793 {
3794 	int status, status2;
3795 
3796 	switch (hdspm->io_type) {
3797 	case AES32:
3798 		status = hdspm_read(hdspm, HDSPM_statusRegister);
3799 		if (status & HDSPM_AES32_wcLock) {
3800 			if (status & HDSPM_AES32_wcSync)
3801 				return 2;
3802 			else
3803 				return 1;
3804 		}
3805 		return 0;
3806 
3807 	case MADI:
3808 		status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3809 		if (status2 & HDSPM_wcLock) {
3810 			if (status2 & HDSPM_wcSync)
3811 				return 2;
3812 			else
3813 				return 1;
3814 		}
3815 		return 0;
3816 
3817 	case RayDAT:
3818 	case AIO:
3819 		status = hdspm_read(hdspm, HDSPM_statusRegister);
3820 
3821 		if (status & 0x2000000)
3822 			return 2;
3823 		else if (status & 0x1000000)
3824 			return 1;
3825 		return 0;
3826 
3827 	case MADIface:
3828 		break;
3829 	}
3830 
3831 
3832 	return 3;
3833 }
3834 
3835 
3836 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3837 {
3838 	int status = hdspm_read(hdspm, HDSPM_statusRegister);
3839 	if (status & HDSPM_madiLock) {
3840 		if (status & HDSPM_madiSync)
3841 			return 2;
3842 		else
3843 			return 1;
3844 	}
3845 	return 0;
3846 }
3847 
3848 
3849 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3850 {
3851 	int status, lock, sync;
3852 
3853 	status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3854 
3855 	lock = (status & (0x1<<idx)) ? 1 : 0;
3856 	sync = (status & (0x100<<idx)) ? 1 : 0;
3857 
3858 	if (lock && sync)
3859 		return 2;
3860 	else if (lock)
3861 		return 1;
3862 	return 0;
3863 }
3864 
3865 
3866 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3867 {
3868 	int status, lock = 0, sync = 0;
3869 
3870 	switch (hdspm->io_type) {
3871 	case RayDAT:
3872 	case AIO:
3873 		status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3874 		lock = (status & 0x400) ? 1 : 0;
3875 		sync = (status & 0x800) ? 1 : 0;
3876 		break;
3877 
3878 	case MADI:
3879 		status = hdspm_read(hdspm, HDSPM_statusRegister);
3880 		lock = (status & HDSPM_syncInLock) ? 1 : 0;
3881 		sync = (status & HDSPM_syncInSync) ? 1 : 0;
3882 		break;
3883 
3884 	case AES32:
3885 		status = hdspm_read(hdspm, HDSPM_statusRegister2);
3886 		lock = (status & 0x100000) ? 1 : 0;
3887 		sync = (status & 0x200000) ? 1 : 0;
3888 		break;
3889 
3890 	case MADIface:
3891 		break;
3892 	}
3893 
3894 	if (lock && sync)
3895 		return 2;
3896 	else if (lock)
3897 		return 1;
3898 
3899 	return 0;
3900 }
3901 
3902 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3903 {
3904 	int status2, lock, sync;
3905 	status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3906 
3907 	lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3908 	sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3909 
3910 	if (sync)
3911 		return 2;
3912 	else if (lock)
3913 		return 1;
3914 	return 0;
3915 }
3916 
3917 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3918 {
3919 	u32 status;
3920 	status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3921 
3922 	return (status & mask) ? 1 : 0;
3923 }
3924 
3925 
3926 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3927 {
3928 	int status;
3929 
3930 	if (hdspm->tco) {
3931 		switch (hdspm->io_type) {
3932 		case MADI:
3933 			status = hdspm_read(hdspm, HDSPM_statusRegister);
3934 			if (status & HDSPM_tcoLockMadi) {
3935 				if (status & HDSPM_tcoSync)
3936 					return 2;
3937 				else
3938 					return 1;
3939 			}
3940 			return 0;
3941 		case AES32:
3942 			status = hdspm_read(hdspm, HDSPM_statusRegister);
3943 			if (status & HDSPM_tcoLockAes) {
3944 				if (status & HDSPM_tcoSync)
3945 					return 2;
3946 				else
3947 					return 1;
3948 			}
3949 			return 0;
3950 		case RayDAT:
3951 		case AIO:
3952 			status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3953 
3954 			if (status & 0x8000000)
3955 				return 2; /* Sync */
3956 			if (status & 0x4000000)
3957 				return 1; /* Lock */
3958 			return 0; /* No signal */
3959 
3960 		default:
3961 			break;
3962 		}
3963 	}
3964 
3965 	return 3; /* N/A */
3966 }
3967 
3968 
3969 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3970 				    struct snd_ctl_elem_value *ucontrol)
3971 {
3972 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3973 	int val = -1;
3974 
3975 	switch (hdspm->io_type) {
3976 	case RayDAT:
3977 		switch (kcontrol->private_value) {
3978 		case 0: /* WC */
3979 			val = hdspm_wc_sync_check(hdspm); break;
3980 		case 7: /* TCO */
3981 			val = hdspm_tco_sync_check(hdspm); break;
3982 		case 8: /* SYNC IN */
3983 			val = hdspm_sync_in_sync_check(hdspm); break;
3984 		default:
3985 			val = hdspm_s1_sync_check(hdspm,
3986 					kcontrol->private_value-1);
3987 		}
3988 		break;
3989 
3990 	case AIO:
3991 		switch (kcontrol->private_value) {
3992 		case 0: /* WC */
3993 			val = hdspm_wc_sync_check(hdspm); break;
3994 		case 4: /* TCO */
3995 			val = hdspm_tco_sync_check(hdspm); break;
3996 		case 5: /* SYNC IN */
3997 			val = hdspm_sync_in_sync_check(hdspm); break;
3998 		default:
3999 			val = hdspm_s1_sync_check(hdspm,
4000 					kcontrol->private_value-1);
4001 		}
4002 		break;
4003 
4004 	case MADI:
4005 		switch (kcontrol->private_value) {
4006 		case 0: /* WC */
4007 			val = hdspm_wc_sync_check(hdspm); break;
4008 		case 1: /* MADI */
4009 			val = hdspm_madi_sync_check(hdspm); break;
4010 		case 2: /* TCO */
4011 			val = hdspm_tco_sync_check(hdspm); break;
4012 		case 3: /* SYNC_IN */
4013 			val = hdspm_sync_in_sync_check(hdspm); break;
4014 		}
4015 		break;
4016 
4017 	case MADIface:
4018 		val = hdspm_madi_sync_check(hdspm); /* MADI */
4019 		break;
4020 
4021 	case AES32:
4022 		switch (kcontrol->private_value) {
4023 		case 0: /* WC */
4024 			val = hdspm_wc_sync_check(hdspm); break;
4025 		case 9: /* TCO */
4026 			val = hdspm_tco_sync_check(hdspm); break;
4027 		case 10 /* SYNC IN */:
4028 			val = hdspm_sync_in_sync_check(hdspm); break;
4029 		default: /* AES1 to AES8 */
4030 			 val = hdspm_aes_sync_check(hdspm,
4031 					 kcontrol->private_value-1);
4032 		}
4033 		break;
4034 
4035 	}
4036 
4037 	if (hdspm->tco) {
4038 		switch (kcontrol->private_value) {
4039 		case 11:
4040 			/* Check TCO for lock state of its current input */
4041 			val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4042 			break;
4043 		case 12:
4044 			/* Check TCO for valid time code on LTC input. */
4045 			val = hdspm_tco_input_check(hdspm,
4046 				HDSPM_TCO1_LTC_Input_valid);
4047 			break;
4048 		default:
4049 			break;
4050 		}
4051 	}
4052 
4053 	if (-1 == val)
4054 		val = 3;
4055 
4056 	ucontrol->value.enumerated.item[0] = val;
4057 	return 0;
4058 }
4059 
4060 
4061 
4062 /*
4063  * TCO controls
4064  */
4065 static void hdspm_tco_write(struct hdspm *hdspm)
4066 {
4067 	unsigned int tc[4] = { 0, 0, 0, 0};
4068 
4069 	switch (hdspm->tco->input) {
4070 	case 0:
4071 		tc[2] |= HDSPM_TCO2_set_input_MSB;
4072 		break;
4073 	case 1:
4074 		tc[2] |= HDSPM_TCO2_set_input_LSB;
4075 		break;
4076 	default:
4077 		break;
4078 	}
4079 
4080 	switch (hdspm->tco->framerate) {
4081 	case 1:
4082 		tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4083 		break;
4084 	case 2:
4085 		tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4086 		break;
4087 	case 3:
4088 		tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4089 			HDSPM_TCO1_set_drop_frame_flag;
4090 		break;
4091 	case 4:
4092 		tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4093 			HDSPM_TCO1_LTC_Format_MSB;
4094 		break;
4095 	case 5:
4096 		tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4097 			HDSPM_TCO1_LTC_Format_MSB +
4098 			HDSPM_TCO1_set_drop_frame_flag;
4099 		break;
4100 	default:
4101 		break;
4102 	}
4103 
4104 	switch (hdspm->tco->wordclock) {
4105 	case 1:
4106 		tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4107 		break;
4108 	case 2:
4109 		tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4110 		break;
4111 	default:
4112 		break;
4113 	}
4114 
4115 	switch (hdspm->tco->samplerate) {
4116 	case 1:
4117 		tc[2] |= HDSPM_TCO2_set_freq;
4118 		break;
4119 	case 2:
4120 		tc[2] |= HDSPM_TCO2_set_freq_from_app;
4121 		break;
4122 	default:
4123 		break;
4124 	}
4125 
4126 	switch (hdspm->tco->pull) {
4127 	case 1:
4128 		tc[2] |= HDSPM_TCO2_set_pull_up;
4129 		break;
4130 	case 2:
4131 		tc[2] |= HDSPM_TCO2_set_pull_down;
4132 		break;
4133 	case 3:
4134 		tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4135 		break;
4136 	case 4:
4137 		tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4138 		break;
4139 	default:
4140 		break;
4141 	}
4142 
4143 	if (1 == hdspm->tco->term) {
4144 		tc[2] |= HDSPM_TCO2_set_term_75R;
4145 	}
4146 
4147 	hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4148 	hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4149 	hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4150 	hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4151 }
4152 
4153 
4154 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4155 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4156 	.name = xname, \
4157 	.index = xindex, \
4158 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4159 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4160 	.info = snd_hdspm_info_tco_sample_rate, \
4161 	.get = snd_hdspm_get_tco_sample_rate, \
4162 	.put = snd_hdspm_put_tco_sample_rate \
4163 }
4164 
4165 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4166 					  struct snd_ctl_elem_info *uinfo)
4167 {
4168 	/* TODO freq from app could be supported here, see tco->samplerate */
4169 	static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4170 	ENUMERATED_CTL_INFO(uinfo, texts);
4171 	return 0;
4172 }
4173 
4174 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4175 				      struct snd_ctl_elem_value *ucontrol)
4176 {
4177 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4178 
4179 	ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4180 
4181 	return 0;
4182 }
4183 
4184 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4185 					 struct snd_ctl_elem_value *ucontrol)
4186 {
4187 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4188 
4189 	if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4190 		hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4191 
4192 		hdspm_tco_write(hdspm);
4193 
4194 		return 1;
4195 	}
4196 
4197 	return 0;
4198 }
4199 
4200 
4201 #define HDSPM_TCO_PULL(xname, xindex) \
4202 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4203 	.name = xname, \
4204 	.index = xindex, \
4205 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4206 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4207 	.info = snd_hdspm_info_tco_pull, \
4208 	.get = snd_hdspm_get_tco_pull, \
4209 	.put = snd_hdspm_put_tco_pull \
4210 }
4211 
4212 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4213 				   struct snd_ctl_elem_info *uinfo)
4214 {
4215 	static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4216 		"+ 4 %", "- 4 %" };
4217 	ENUMERATED_CTL_INFO(uinfo, texts);
4218 	return 0;
4219 }
4220 
4221 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4222 				  struct snd_ctl_elem_value *ucontrol)
4223 {
4224 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4225 
4226 	ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4227 
4228 	return 0;
4229 }
4230 
4231 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4232 				  struct snd_ctl_elem_value *ucontrol)
4233 {
4234 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4235 
4236 	if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4237 		hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4238 
4239 		hdspm_tco_write(hdspm);
4240 
4241 		return 1;
4242 	}
4243 
4244 	return 0;
4245 }
4246 
4247 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4248 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4249 	.name = xname, \
4250 	.index = xindex, \
4251 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4252 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4253 	.info = snd_hdspm_info_tco_wck_conversion, \
4254 	.get = snd_hdspm_get_tco_wck_conversion, \
4255 	.put = snd_hdspm_put_tco_wck_conversion \
4256 }
4257 
4258 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4259 					     struct snd_ctl_elem_info *uinfo)
4260 {
4261 	static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4262 	ENUMERATED_CTL_INFO(uinfo, texts);
4263 	return 0;
4264 }
4265 
4266 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4267 					    struct snd_ctl_elem_value *ucontrol)
4268 {
4269 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4270 
4271 	ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4272 
4273 	return 0;
4274 }
4275 
4276 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4277 					    struct snd_ctl_elem_value *ucontrol)
4278 {
4279 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4280 
4281 	if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4282 		hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4283 
4284 		hdspm_tco_write(hdspm);
4285 
4286 		return 1;
4287 	}
4288 
4289 	return 0;
4290 }
4291 
4292 
4293 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4294 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4295 	.name = xname, \
4296 	.index = xindex, \
4297 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4298 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4299 	.info = snd_hdspm_info_tco_frame_rate, \
4300 	.get = snd_hdspm_get_tco_frame_rate, \
4301 	.put = snd_hdspm_put_tco_frame_rate \
4302 }
4303 
4304 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4305 					  struct snd_ctl_elem_info *uinfo)
4306 {
4307 	static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4308 		"29.97 dfps", "30 fps", "30 dfps" };
4309 	ENUMERATED_CTL_INFO(uinfo, texts);
4310 	return 0;
4311 }
4312 
4313 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4314 					struct snd_ctl_elem_value *ucontrol)
4315 {
4316 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4317 
4318 	ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4319 
4320 	return 0;
4321 }
4322 
4323 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4324 					struct snd_ctl_elem_value *ucontrol)
4325 {
4326 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4327 
4328 	if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4329 		hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4330 
4331 		hdspm_tco_write(hdspm);
4332 
4333 		return 1;
4334 	}
4335 
4336 	return 0;
4337 }
4338 
4339 
4340 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4341 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4342 	.name = xname, \
4343 	.index = xindex, \
4344 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4345 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4346 	.info = snd_hdspm_info_tco_sync_source, \
4347 	.get = snd_hdspm_get_tco_sync_source, \
4348 	.put = snd_hdspm_put_tco_sync_source \
4349 }
4350 
4351 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4352 					  struct snd_ctl_elem_info *uinfo)
4353 {
4354 	static const char *const texts[] = { "LTC", "Video", "WCK" };
4355 	ENUMERATED_CTL_INFO(uinfo, texts);
4356 	return 0;
4357 }
4358 
4359 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4360 					 struct snd_ctl_elem_value *ucontrol)
4361 {
4362 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4363 
4364 	ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4365 
4366 	return 0;
4367 }
4368 
4369 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4370 					 struct snd_ctl_elem_value *ucontrol)
4371 {
4372 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4373 
4374 	if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4375 		hdspm->tco->input = ucontrol->value.enumerated.item[0];
4376 
4377 		hdspm_tco_write(hdspm);
4378 
4379 		return 1;
4380 	}
4381 
4382 	return 0;
4383 }
4384 
4385 
4386 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4387 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4388 	.name = xname, \
4389 	.index = xindex, \
4390 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4391 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4392 	.info = snd_hdspm_info_tco_word_term, \
4393 	.get = snd_hdspm_get_tco_word_term, \
4394 	.put = snd_hdspm_put_tco_word_term \
4395 }
4396 
4397 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4398 					struct snd_ctl_elem_info *uinfo)
4399 {
4400 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4401 	uinfo->count = 1;
4402 	uinfo->value.integer.min = 0;
4403 	uinfo->value.integer.max = 1;
4404 
4405 	return 0;
4406 }
4407 
4408 
4409 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4410 				       struct snd_ctl_elem_value *ucontrol)
4411 {
4412 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4413 
4414 	ucontrol->value.integer.value[0] = hdspm->tco->term;
4415 
4416 	return 0;
4417 }
4418 
4419 
4420 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4421 				       struct snd_ctl_elem_value *ucontrol)
4422 {
4423 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4424 
4425 	if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4426 		hdspm->tco->term = ucontrol->value.integer.value[0];
4427 
4428 		hdspm_tco_write(hdspm);
4429 
4430 		return 1;
4431 	}
4432 
4433 	return 0;
4434 }
4435 
4436 
4437 
4438 
4439 static const struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4440 	HDSPM_MIXER("Mixer", 0),
4441 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4442 	HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4443 	HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4444 	HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4445 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4446 	HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4447 	HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4448 	HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4449 	HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4450 	HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4451 	HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4452 	HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4453 	HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4454 	HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4455 	HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4456 	HDSPM_INPUT_SELECT("Input Select", 0),
4457 	HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4458 };
4459 
4460 
4461 static const struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4462 	HDSPM_MIXER("Mixer", 0),
4463 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4464 	HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4465 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4466 	HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4467 	HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4468 	HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4469 	HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4470 	HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4471 	HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4472 };
4473 
4474 static const struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4475 	HDSPM_MIXER("Mixer", 0),
4476 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4477 	HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4478 	HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4479 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4480 	HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4481 	HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4482 	HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4483 	HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4484 	HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4485 	HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4486 	HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4487 	HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4488 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4489 	HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4490 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4491 	HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4492 	HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4493 	HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4494 	HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4495 	HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4496 	HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4497 	HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4498 	HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4499 	HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4500 	HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4501 	HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4502 
4503 		/*
4504 		   HDSPM_INPUT_SELECT("Input Select", 0),
4505 		   HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4506 		   HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4507 		   HDSPM_SPDIF_IN("SPDIF In", 0);
4508 		   HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4509 		   HDSPM_INPUT_LEVEL("Input Level", 0);
4510 		   HDSPM_OUTPUT_LEVEL("Output Level", 0);
4511 		   HDSPM_PHONES("Phones", 0);
4512 		   */
4513 };
4514 
4515 static const struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4516 	HDSPM_MIXER("Mixer", 0),
4517 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4518 	HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4519 	HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4520 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4521 	HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4522 	HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4523 	HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4524 	HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4525 	HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4526 	HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4527 	HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4528 	HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4529 	HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4530 	HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4531 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4532 	HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4533 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4534 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4535 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4536 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4537 	HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4538 	HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4539 	HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4540 	HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4541 };
4542 
4543 static const struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4544 	HDSPM_MIXER("Mixer", 0),
4545 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4546 	HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4547 	HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4548 	HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4549 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4550 	HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4551 	HDSPM_SYNC_CHECK("WC Sync Check", 0),
4552 	HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4553 	HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4554 	HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4555 	HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4556 	HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4557 	HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4558 	HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4559 	HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4560 	HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4561 	HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4562 	HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4563 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4564 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4565 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4566 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4567 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4568 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4569 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4570 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4571 	HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4572 	HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4573 	HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4574 	HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4575 	HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4576 	HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4577 	HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4578 	HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4579 	HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4580 };
4581 
4582 
4583 
4584 /* Control elements for the optional TCO module */
4585 static const struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4586 	HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4587 	HDSPM_TCO_PULL("TCO Pull", 0),
4588 	HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4589 	HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4590 	HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4591 	HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4592 	HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4593 	HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4594 	HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate"),
4595 	HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format")
4596 };
4597 
4598 
4599 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4600 
4601 
4602 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4603 {
4604 	int i;
4605 
4606 	for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4607 		if (hdspm->system_sample_rate > 48000) {
4608 			hdspm->playback_mixer_ctls[i]->vd[0].access =
4609 				SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4610 				SNDRV_CTL_ELEM_ACCESS_READ |
4611 				SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4612 		} else {
4613 			hdspm->playback_mixer_ctls[i]->vd[0].access =
4614 				SNDRV_CTL_ELEM_ACCESS_READWRITE |
4615 				SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4616 		}
4617 		snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4618 				SNDRV_CTL_EVENT_MASK_INFO,
4619 				&hdspm->playback_mixer_ctls[i]->id);
4620 	}
4621 
4622 	return 0;
4623 }
4624 
4625 
4626 static int snd_hdspm_create_controls(struct snd_card *card,
4627 					struct hdspm *hdspm)
4628 {
4629 	unsigned int idx, limit;
4630 	int err;
4631 	struct snd_kcontrol *kctl;
4632 	const struct snd_kcontrol_new *list = NULL;
4633 
4634 	switch (hdspm->io_type) {
4635 	case MADI:
4636 		list = snd_hdspm_controls_madi;
4637 		limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4638 		break;
4639 	case MADIface:
4640 		list = snd_hdspm_controls_madiface;
4641 		limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4642 		break;
4643 	case AIO:
4644 		list = snd_hdspm_controls_aio;
4645 		limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4646 		break;
4647 	case RayDAT:
4648 		list = snd_hdspm_controls_raydat;
4649 		limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4650 		break;
4651 	case AES32:
4652 		list = snd_hdspm_controls_aes32;
4653 		limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4654 		break;
4655 	}
4656 
4657 	if (list) {
4658 		for (idx = 0; idx < limit; idx++) {
4659 			err = snd_ctl_add(card,
4660 					snd_ctl_new1(&list[idx], hdspm));
4661 			if (err < 0)
4662 				return err;
4663 		}
4664 	}
4665 
4666 
4667 	/* create simple 1:1 playback mixer controls */
4668 	snd_hdspm_playback_mixer.name = "Chn";
4669 	if (hdspm->system_sample_rate >= 128000) {
4670 		limit = hdspm->qs_out_channels;
4671 	} else if (hdspm->system_sample_rate >= 64000) {
4672 		limit = hdspm->ds_out_channels;
4673 	} else {
4674 		limit = hdspm->ss_out_channels;
4675 	}
4676 	for (idx = 0; idx < limit; ++idx) {
4677 		snd_hdspm_playback_mixer.index = idx + 1;
4678 		kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4679 		err = snd_ctl_add(card, kctl);
4680 		if (err < 0)
4681 			return err;
4682 		hdspm->playback_mixer_ctls[idx] = kctl;
4683 	}
4684 
4685 
4686 	if (hdspm->tco) {
4687 		/* add tco control elements */
4688 		list = snd_hdspm_controls_tco;
4689 		limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4690 		for (idx = 0; idx < limit; idx++) {
4691 			err = snd_ctl_add(card,
4692 					snd_ctl_new1(&list[idx], hdspm));
4693 			if (err < 0)
4694 				return err;
4695 		}
4696 	}
4697 
4698 	return 0;
4699 }
4700 
4701 /*------------------------------------------------------------
4702    /proc interface
4703  ------------------------------------------------------------*/
4704 
4705 static void
4706 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4707 					struct snd_info_buffer *buffer)
4708 {
4709 	struct hdspm *hdspm = entry->private_data;
4710 	unsigned int status, control;
4711 	int a, ltc, frames, seconds, minutes, hours;
4712 	unsigned int period;
4713 	u64 freq_const = 0;
4714 	u32 rate;
4715 
4716 	snd_iprintf(buffer, "--- TCO ---\n");
4717 
4718 	status = hdspm_read(hdspm, HDSPM_statusRegister);
4719 	control = hdspm->control_register;
4720 
4721 
4722 	if (status & HDSPM_tco_detect) {
4723 		snd_iprintf(buffer, "TCO module detected.\n");
4724 		a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4725 		if (a & HDSPM_TCO1_LTC_Input_valid) {
4726 			snd_iprintf(buffer, "  LTC valid, ");
4727 			switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4728 						HDSPM_TCO1_LTC_Format_MSB)) {
4729 			case 0:
4730 				snd_iprintf(buffer, "24 fps, ");
4731 				break;
4732 			case HDSPM_TCO1_LTC_Format_LSB:
4733 				snd_iprintf(buffer, "25 fps, ");
4734 				break;
4735 			case HDSPM_TCO1_LTC_Format_MSB:
4736 				snd_iprintf(buffer, "29.97 fps, ");
4737 				break;
4738 			default:
4739 				snd_iprintf(buffer, "30 fps, ");
4740 				break;
4741 			}
4742 			if (a & HDSPM_TCO1_set_drop_frame_flag) {
4743 				snd_iprintf(buffer, "drop frame\n");
4744 			} else {
4745 				snd_iprintf(buffer, "full frame\n");
4746 			}
4747 		} else {
4748 			snd_iprintf(buffer, "  no LTC\n");
4749 		}
4750 		if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4751 			snd_iprintf(buffer, "  Video: NTSC\n");
4752 		} else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4753 			snd_iprintf(buffer, "  Video: PAL\n");
4754 		} else {
4755 			snd_iprintf(buffer, "  No video\n");
4756 		}
4757 		if (a & HDSPM_TCO1_TCO_lock) {
4758 			snd_iprintf(buffer, "  Sync: lock\n");
4759 		} else {
4760 			snd_iprintf(buffer, "  Sync: no lock\n");
4761 		}
4762 
4763 		switch (hdspm->io_type) {
4764 		case MADI:
4765 		case AES32:
4766 			freq_const = 110069313433624ULL;
4767 			break;
4768 		case RayDAT:
4769 		case AIO:
4770 			freq_const = 104857600000000ULL;
4771 			break;
4772 		case MADIface:
4773 			break; /* no TCO possible */
4774 		}
4775 
4776 		period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4777 		snd_iprintf(buffer, "    period: %u\n", period);
4778 
4779 
4780 		/* rate = freq_const/period; */
4781 		rate = div_u64(freq_const, period);
4782 
4783 		if (control & HDSPM_QuadSpeed) {
4784 			rate *= 4;
4785 		} else if (control & HDSPM_DoubleSpeed) {
4786 			rate *= 2;
4787 		}
4788 
4789 		snd_iprintf(buffer, "  Frequency: %u Hz\n",
4790 				(unsigned int) rate);
4791 
4792 		ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4793 		frames = ltc & 0xF;
4794 		ltc >>= 4;
4795 		frames += (ltc & 0x3) * 10;
4796 		ltc >>= 4;
4797 		seconds = ltc & 0xF;
4798 		ltc >>= 4;
4799 		seconds += (ltc & 0x7) * 10;
4800 		ltc >>= 4;
4801 		minutes = ltc & 0xF;
4802 		ltc >>= 4;
4803 		minutes += (ltc & 0x7) * 10;
4804 		ltc >>= 4;
4805 		hours = ltc & 0xF;
4806 		ltc >>= 4;
4807 		hours += (ltc & 0x3) * 10;
4808 		snd_iprintf(buffer,
4809 			"  LTC In: %02d:%02d:%02d:%02d\n",
4810 			hours, minutes, seconds, frames);
4811 
4812 	} else {
4813 		snd_iprintf(buffer, "No TCO module detected.\n");
4814 	}
4815 }
4816 
4817 static void
4818 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4819 			 struct snd_info_buffer *buffer)
4820 {
4821 	struct hdspm *hdspm = entry->private_data;
4822 	unsigned int status, status2;
4823 
4824 	char *pref_sync_ref;
4825 	char *autosync_ref;
4826 	char *system_clock_mode;
4827 	int x, x2;
4828 
4829 	status = hdspm_read(hdspm, HDSPM_statusRegister);
4830 	status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4831 
4832 	snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4833 			hdspm->card_name, hdspm->card->number + 1,
4834 			hdspm->firmware_rev,
4835 			(status2 & HDSPM_version0) |
4836 			(status2 & HDSPM_version1) | (status2 &
4837 				HDSPM_version2));
4838 
4839 	snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4840 			(hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4841 			hdspm->serial);
4842 
4843 	snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4844 			hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4845 
4846 	snd_iprintf(buffer, "--- System ---\n");
4847 
4848 	snd_iprintf(buffer,
4849 		"IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4850 		status & HDSPM_audioIRQPending,
4851 		(status & HDSPM_midi0IRQPending) ? 1 : 0,
4852 		(status & HDSPM_midi1IRQPending) ? 1 : 0,
4853 		hdspm->irq_count);
4854 	snd_iprintf(buffer,
4855 		"HW pointer: id = %d, rawptr = %d (%d->%d) "
4856 		"estimated= %ld (bytes)\n",
4857 		((status & HDSPM_BufferID) ? 1 : 0),
4858 		(status & HDSPM_BufferPositionMask),
4859 		(status & HDSPM_BufferPositionMask) %
4860 		(2 * (int)hdspm->period_bytes),
4861 		((status & HDSPM_BufferPositionMask) - 64) %
4862 		(2 * (int)hdspm->period_bytes),
4863 		(long) hdspm_hw_pointer(hdspm) * 4);
4864 
4865 	snd_iprintf(buffer,
4866 		"MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4867 		hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4868 		hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4869 		hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4870 		hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4871 	snd_iprintf(buffer,
4872 		"MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4873 		hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4874 		hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4875 	snd_iprintf(buffer,
4876 		"Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4877 		"status2=0x%x\n",
4878 		hdspm->control_register, hdspm->control2_register,
4879 		status, status2);
4880 
4881 
4882 	snd_iprintf(buffer, "--- Settings ---\n");
4883 
4884 	x = hdspm_get_latency(hdspm);
4885 
4886 	snd_iprintf(buffer,
4887 		"Size (Latency): %d samples (2 periods of %lu bytes)\n",
4888 		x, (unsigned long) hdspm->period_bytes);
4889 
4890 	snd_iprintf(buffer, "Line out: %s\n",
4891 		    str_on_off(hdspm->control_register & HDSPM_LineOut));
4892 
4893 	snd_iprintf(buffer,
4894 		"ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4895 		"Auto Input %s\n",
4896 		str_on_off(hdspm->control_register & HDSPM_clr_tms),
4897 		(hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4898 		str_on_off(hdspm->control_register & HDSPM_AutoInp));
4899 
4900 
4901 	if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4902 		system_clock_mode = "AutoSync";
4903 	else
4904 		system_clock_mode = "Master";
4905 	snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4906 
4907 	switch (hdspm_pref_sync_ref(hdspm)) {
4908 	case HDSPM_SYNC_FROM_WORD:
4909 		pref_sync_ref = "Word Clock";
4910 		break;
4911 	case HDSPM_SYNC_FROM_MADI:
4912 		pref_sync_ref = "MADI Sync";
4913 		break;
4914 	case HDSPM_SYNC_FROM_TCO:
4915 		pref_sync_ref = "TCO";
4916 		break;
4917 	case HDSPM_SYNC_FROM_SYNC_IN:
4918 		pref_sync_ref = "Sync In";
4919 		break;
4920 	default:
4921 		pref_sync_ref = "XXXX Clock";
4922 		break;
4923 	}
4924 	snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4925 			pref_sync_ref);
4926 
4927 	snd_iprintf(buffer, "System Clock Frequency: %d\n",
4928 			hdspm->system_sample_rate);
4929 
4930 
4931 	snd_iprintf(buffer, "--- Status:\n");
4932 
4933 	x = status & HDSPM_madiSync;
4934 	x2 = status2 & HDSPM_wcSync;
4935 
4936 	snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4937 			(status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4938 			"NoLock",
4939 			(status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4940 			"NoLock");
4941 
4942 	switch (hdspm_autosync_ref(hdspm)) {
4943 	case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4944 		autosync_ref = "Sync In";
4945 		break;
4946 	case HDSPM_AUTOSYNC_FROM_TCO:
4947 		autosync_ref = "TCO";
4948 		break;
4949 	case HDSPM_AUTOSYNC_FROM_WORD:
4950 		autosync_ref = "Word Clock";
4951 		break;
4952 	case HDSPM_AUTOSYNC_FROM_MADI:
4953 		autosync_ref = "MADI Sync";
4954 		break;
4955 	case HDSPM_AUTOSYNC_FROM_NONE:
4956 		autosync_ref = "Input not valid";
4957 		break;
4958 	default:
4959 		autosync_ref = "---";
4960 		break;
4961 	}
4962 	snd_iprintf(buffer,
4963 		"AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4964 		autosync_ref, hdspm_external_sample_rate(hdspm),
4965 		(status & HDSPM_madiFreqMask) >> 22,
4966 		(status2 & HDSPM_wcFreqMask) >> 5);
4967 
4968 	snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4969 		(status & HDSPM_AB_int) ? "Coax" : "Optical",
4970 		(status & HDSPM_RX_64ch) ? "64 channels" :
4971 		"56 channels");
4972 
4973 	/* call readout function for TCO specific status */
4974 	snd_hdspm_proc_read_tco(entry, buffer);
4975 
4976 	snd_iprintf(buffer, "\n");
4977 }
4978 
4979 static void
4980 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4981 			  struct snd_info_buffer *buffer)
4982 {
4983 	struct hdspm *hdspm = entry->private_data;
4984 	unsigned int status;
4985 	unsigned int status2;
4986 	unsigned int timecode;
4987 	unsigned int wcLock, wcSync;
4988 	int pref_syncref;
4989 	char *autosync_ref;
4990 	int x;
4991 
4992 	status = hdspm_read(hdspm, HDSPM_statusRegister);
4993 	status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4994 	timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4995 
4996 	snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4997 		    hdspm->card_name, hdspm->card->number + 1,
4998 		    hdspm->firmware_rev);
4999 
5000 	snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5001 		    hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5002 
5003 	snd_iprintf(buffer, "--- System ---\n");
5004 
5005 	snd_iprintf(buffer,
5006 		    "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5007 		    status & HDSPM_audioIRQPending,
5008 		    (status & HDSPM_midi0IRQPending) ? 1 : 0,
5009 		    (status & HDSPM_midi1IRQPending) ? 1 : 0,
5010 		    hdspm->irq_count);
5011 	snd_iprintf(buffer,
5012 		    "HW pointer: id = %d, rawptr = %d (%d->%d) "
5013 		    "estimated= %ld (bytes)\n",
5014 		    ((status & HDSPM_BufferID) ? 1 : 0),
5015 		    (status & HDSPM_BufferPositionMask),
5016 		    (status & HDSPM_BufferPositionMask) %
5017 		    (2 * (int)hdspm->period_bytes),
5018 		    ((status & HDSPM_BufferPositionMask) - 64) %
5019 		    (2 * (int)hdspm->period_bytes),
5020 		    (long) hdspm_hw_pointer(hdspm) * 4);
5021 
5022 	snd_iprintf(buffer,
5023 		    "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5024 		    hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5025 		    hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5026 		    hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5027 		    hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5028 	snd_iprintf(buffer,
5029 		    "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5030 		    hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5031 		    hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5032 	snd_iprintf(buffer,
5033 		    "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5034 		    "status2=0x%x\n",
5035 		    hdspm->control_register, hdspm->control2_register,
5036 		    status, status2);
5037 
5038 	snd_iprintf(buffer, "--- Settings ---\n");
5039 
5040 	x = hdspm_get_latency(hdspm);
5041 
5042 	snd_iprintf(buffer,
5043 		    "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5044 		    x, (unsigned long) hdspm->period_bytes);
5045 
5046 	snd_iprintf(buffer, "Line out: %s\n",
5047 		    (hdspm->
5048 		     control_register & HDSPM_LineOut) ? "on " : "off");
5049 
5050 	snd_iprintf(buffer,
5051 		    "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5052 		    str_on_off(hdspm->control_register & HDSPM_clr_tms),
5053 		    str_on_off(hdspm->control_register & HDSPM_Emphasis),
5054 		    str_on_off(hdspm->control_register & HDSPM_Dolby));
5055 
5056 
5057 	pref_syncref = hdspm_pref_sync_ref(hdspm);
5058 	if (pref_syncref == 0)
5059 		snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5060 	else
5061 		snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5062 				pref_syncref);
5063 
5064 	snd_iprintf(buffer, "System Clock Frequency: %d\n",
5065 		    hdspm->system_sample_rate);
5066 
5067 	snd_iprintf(buffer, "Double speed: %s\n",
5068 			hdspm->control_register & HDSPM_DS_DoubleWire?
5069 			"Double wire" : "Single wire");
5070 	snd_iprintf(buffer, "Quad speed: %s\n",
5071 			hdspm->control_register & HDSPM_QS_DoubleWire?
5072 			"Double wire" :
5073 			hdspm->control_register & HDSPM_QS_QuadWire?
5074 			"Quad wire" : "Single wire");
5075 
5076 	snd_iprintf(buffer, "--- Status:\n");
5077 
5078 	wcLock = status & HDSPM_AES32_wcLock;
5079 	wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5080 
5081 	snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5082 		    (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5083 		    HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5084 
5085 	for (x = 0; x < 8; x++) {
5086 		snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5087 			    x+1,
5088 			    (status2 & (HDSPM_LockAES >> x)) ?
5089 			    "Sync   " : "No Lock",
5090 			    HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5091 	}
5092 
5093 	switch (hdspm_autosync_ref(hdspm)) {
5094 	case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5095 		autosync_ref = "None"; break;
5096 	case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5097 		autosync_ref = "Word Clock"; break;
5098 	case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5099 		autosync_ref = "AES1"; break;
5100 	case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5101 		autosync_ref = "AES2"; break;
5102 	case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5103 		autosync_ref = "AES3"; break;
5104 	case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5105 		autosync_ref = "AES4"; break;
5106 	case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5107 		autosync_ref = "AES5"; break;
5108 	case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5109 		autosync_ref = "AES6"; break;
5110 	case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5111 		autosync_ref = "AES7"; break;
5112 	case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5113 		autosync_ref = "AES8"; break;
5114 	case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5115 		autosync_ref = "TCO"; break;
5116 	case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5117 		autosync_ref = "Sync In"; break;
5118 	default:
5119 		autosync_ref = "---"; break;
5120 	}
5121 	snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5122 
5123 	/* call readout function for TCO specific status */
5124 	snd_hdspm_proc_read_tco(entry, buffer);
5125 
5126 	snd_iprintf(buffer, "\n");
5127 }
5128 
5129 static void
5130 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5131 			 struct snd_info_buffer *buffer)
5132 {
5133 	struct hdspm *hdspm = entry->private_data;
5134 	unsigned int status1, status2, status3, i;
5135 	unsigned int lock, sync;
5136 
5137 	status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5138 	status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5139 	status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5140 
5141 	snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5142 	snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5143 	snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5144 
5145 
5146 	snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5147 
5148 	snd_iprintf(buffer, "Clock mode      : %s\n",
5149 		(hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5150 	snd_iprintf(buffer, "System frequency: %d Hz\n",
5151 		hdspm_get_system_sample_rate(hdspm));
5152 
5153 	snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5154 
5155 	lock = 0x1;
5156 	sync = 0x100;
5157 
5158 	for (i = 0; i < 8; i++) {
5159 		snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5160 				i,
5161 				(status1 & lock) ? 1 : 0,
5162 				(status1 & sync) ? 1 : 0,
5163 				texts_freq[(status2 >> (i * 4)) & 0xF]);
5164 
5165 		lock = lock<<1;
5166 		sync = sync<<1;
5167 	}
5168 
5169 	snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5170 			(status1 & 0x1000000) ? 1 : 0,
5171 			(status1 & 0x2000000) ? 1 : 0,
5172 			texts_freq[(status1 >> 16) & 0xF]);
5173 
5174 	snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5175 			(status1 & 0x4000000) ? 1 : 0,
5176 			(status1 & 0x8000000) ? 1 : 0,
5177 			texts_freq[(status1 >> 20) & 0xF]);
5178 
5179 	snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5180 			(status3 & 0x400) ? 1 : 0,
5181 			(status3 & 0x800) ? 1 : 0,
5182 			texts_freq[(status2 >> 12) & 0xF]);
5183 
5184 }
5185 
5186 #ifdef CONFIG_SND_DEBUG
5187 static void
5188 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5189 			  struct snd_info_buffer *buffer)
5190 {
5191 	struct hdspm *hdspm = entry->private_data;
5192 
5193 	int j,i;
5194 
5195 	for (i = 0; i < 256 /* 1024*64 */; i += j) {
5196 		snd_iprintf(buffer, "0x%08X: ", i);
5197 		for (j = 0; j < 16; j += 4)
5198 			snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5199 		snd_iprintf(buffer, "\n");
5200 	}
5201 }
5202 #endif
5203 
5204 
5205 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5206 			  struct snd_info_buffer *buffer)
5207 {
5208 	struct hdspm *hdspm = entry->private_data;
5209 	int i;
5210 
5211 	snd_iprintf(buffer, "# generated by hdspm\n");
5212 
5213 	for (i = 0; i < hdspm->max_channels_in; i++) {
5214 		snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5215 	}
5216 }
5217 
5218 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5219 			  struct snd_info_buffer *buffer)
5220 {
5221 	struct hdspm *hdspm = entry->private_data;
5222 	int i;
5223 
5224 	snd_iprintf(buffer, "# generated by hdspm\n");
5225 
5226 	for (i = 0; i < hdspm->max_channels_out; i++) {
5227 		snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5228 	}
5229 }
5230 
5231 
5232 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5233 {
5234 	void (*read)(struct snd_info_entry *, struct snd_info_buffer *) = NULL;
5235 
5236 	switch (hdspm->io_type) {
5237 	case AES32:
5238 		read = snd_hdspm_proc_read_aes32;
5239 		break;
5240 	case MADI:
5241 		read = snd_hdspm_proc_read_madi;
5242 		break;
5243 	case MADIface:
5244 		/* read = snd_hdspm_proc_read_madiface; */
5245 		break;
5246 	case RayDAT:
5247 		read = snd_hdspm_proc_read_raydat;
5248 		break;
5249 	case AIO:
5250 		break;
5251 	}
5252 
5253 	snd_card_ro_proc_new(hdspm->card, "hdspm", hdspm, read);
5254 	snd_card_ro_proc_new(hdspm->card, "ports.in", hdspm,
5255 			     snd_hdspm_proc_ports_in);
5256 	snd_card_ro_proc_new(hdspm->card, "ports.out", hdspm,
5257 			     snd_hdspm_proc_ports_out);
5258 
5259 #ifdef CONFIG_SND_DEBUG
5260 	/* debug file to read all hdspm registers */
5261 	snd_card_ro_proc_new(hdspm->card, "debug", hdspm,
5262 			     snd_hdspm_proc_read_debug);
5263 #endif
5264 }
5265 
5266 /*------------------------------------------------------------
5267    hdspm intitialize
5268  ------------------------------------------------------------*/
5269 
5270 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5271 {
5272 	/* ASSUMPTION: hdspm->lock is either held, or there is no need to
5273 	   hold it (e.g. during module initialization).
5274 	   */
5275 
5276 	/* set defaults:       */
5277 
5278 	hdspm->settings_register = 0;
5279 
5280 	switch (hdspm->io_type) {
5281 	case MADI:
5282 	case MADIface:
5283 		hdspm->control_register =
5284 			0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5285 		break;
5286 
5287 	case RayDAT:
5288 	case AIO:
5289 		hdspm->settings_register = 0x1 + 0x1000;
5290 		/* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5291 		 * line_out */
5292 		hdspm->control_register =
5293 			0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5294 		break;
5295 
5296 	case AES32:
5297 		hdspm->control_register =
5298 			HDSPM_ClockModeMaster |	/* Master Clock Mode on */
5299 			hdspm_encode_latency(7) | /* latency max=8192samples */
5300 			HDSPM_SyncRef0 |	/* AES1 is syncclock */
5301 			HDSPM_LineOut |	/* Analog output in */
5302 			HDSPM_Professional;  /* Professional mode */
5303 		break;
5304 	}
5305 
5306 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5307 
5308 	if (AES32 == hdspm->io_type) {
5309 		/* No control2 register for AES32 */
5310 #ifdef SNDRV_BIG_ENDIAN
5311 		hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5312 #else
5313 		hdspm->control2_register = 0;
5314 #endif
5315 
5316 		hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5317 	}
5318 	hdspm_compute_period_size(hdspm);
5319 
5320 	/* silence everything */
5321 
5322 	all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5323 
5324 	if (hdspm_is_raydat_or_aio(hdspm))
5325 		hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5326 
5327 	/* set a default rate so that the channel map is set up. */
5328 	hdspm_set_rate(hdspm, 48000, 1);
5329 
5330 	return 0;
5331 }
5332 
5333 
5334 /*------------------------------------------------------------
5335    interrupt
5336  ------------------------------------------------------------*/
5337 
5338 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5339 {
5340 	struct hdspm *hdspm = (struct hdspm *) dev_id;
5341 	unsigned int status;
5342 	int i, audio, midi, schedule = 0;
5343 	/* cycles_t now; */
5344 
5345 	status = hdspm_read(hdspm, HDSPM_statusRegister);
5346 
5347 	audio = status & HDSPM_audioIRQPending;
5348 	midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5349 			HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5350 
5351 	/* now = get_cycles(); */
5352 	/*
5353 	 *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5354 	 *          6       4096   ~256053425     ~514672358
5355 	 *          5       2048   ~128024983     ~257373821
5356 	 *          4       1024    ~64023706     ~128718089
5357 	 *          3        512    ~32005945      ~64385999
5358 	 *          2        256    ~16003039      ~32260176
5359 	 *          1        128     ~7998738      ~16194507
5360 	 *          0         64     ~3998231       ~8191558
5361 	 */
5362 	/*
5363 	  dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
5364 	   now-hdspm->last_interrupt, status & 0xFFC0);
5365 	   hdspm->last_interrupt = now;
5366 	*/
5367 
5368 	if (!audio && !midi)
5369 		return IRQ_NONE;
5370 
5371 	hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5372 	hdspm->irq_count++;
5373 
5374 
5375 	if (audio) {
5376 		if (hdspm->capture_substream)
5377 			snd_pcm_period_elapsed(hdspm->capture_substream);
5378 
5379 		if (hdspm->playback_substream)
5380 			snd_pcm_period_elapsed(hdspm->playback_substream);
5381 	}
5382 
5383 	if (midi) {
5384 		i = 0;
5385 		while (i < hdspm->midiPorts) {
5386 			if ((hdspm_read(hdspm,
5387 				hdspm->midi[i].statusIn) & 0xff) &&
5388 					(status & hdspm->midi[i].irq)) {
5389 				/* we disable interrupts for this input until
5390 				 * processing is done
5391 				 */
5392 				hdspm->control_register &= ~hdspm->midi[i].ie;
5393 				hdspm_write(hdspm, HDSPM_controlRegister,
5394 						hdspm->control_register);
5395 				hdspm->midi[i].pending = 1;
5396 				schedule = 1;
5397 			}
5398 
5399 			i++;
5400 		}
5401 
5402 		if (schedule)
5403 			queue_work(system_highpri_wq, &hdspm->midi_work);
5404 	}
5405 
5406 	return IRQ_HANDLED;
5407 }
5408 
5409 /*------------------------------------------------------------
5410    pcm interface
5411   ------------------------------------------------------------*/
5412 
5413 
5414 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5415 					      *substream)
5416 {
5417 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5418 	return hdspm_hw_pointer(hdspm);
5419 }
5420 
5421 
5422 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5423 {
5424 	struct snd_pcm_runtime *runtime = substream->runtime;
5425 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5426 	struct snd_pcm_substream *other;
5427 
5428 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5429 		other = hdspm->capture_substream;
5430 	else
5431 		other = hdspm->playback_substream;
5432 
5433 	if (hdspm->running)
5434 		runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5435 	else
5436 		runtime->status->hw_ptr = 0;
5437 	if (other) {
5438 		struct snd_pcm_substream *s;
5439 		struct snd_pcm_runtime *oruntime = other->runtime;
5440 		snd_pcm_group_for_each_entry(s, substream) {
5441 			if (s == other) {
5442 				oruntime->status->hw_ptr =
5443 					runtime->status->hw_ptr;
5444 				break;
5445 			}
5446 		}
5447 	}
5448 	return 0;
5449 }
5450 
5451 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5452 			       struct snd_pcm_hw_params *params)
5453 {
5454 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5455 	int err;
5456 	int i;
5457 	pid_t this_pid;
5458 	pid_t other_pid;
5459 
5460 	scoped_guard(spinlock_irq, &hdspm->lock) {
5461 
5462 		if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5463 			this_pid = hdspm->playback_pid;
5464 			other_pid = hdspm->capture_pid;
5465 		} else {
5466 			this_pid = hdspm->capture_pid;
5467 			other_pid = hdspm->playback_pid;
5468 		}
5469 
5470 		if (other_pid > 0 && this_pid != other_pid) {
5471 
5472 			/* The other stream is open, and not by the same
5473 			   task as this one. Make sure that the parameters
5474 			   that matter are the same.
5475 			*/
5476 
5477 			if (params_rate(params) != hdspm->system_sample_rate) {
5478 				_snd_pcm_hw_param_setempty(params,
5479 							   SNDRV_PCM_HW_PARAM_RATE);
5480 				return -EBUSY;
5481 			}
5482 
5483 			if (params_period_size(params) != hdspm->period_bytes / 4) {
5484 				_snd_pcm_hw_param_setempty(params,
5485 							   SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5486 				return -EBUSY;
5487 			}
5488 
5489 		}
5490 	}
5491 	/* We're fine. */
5492 
5493 	/* how to make sure that the rate matches an externally-set one ?   */
5494 
5495 	scoped_guard(spinlock_irq, &hdspm->lock) {
5496 		err = hdspm_set_rate(hdspm, params_rate(params), 0);
5497 		if (err < 0) {
5498 			dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
5499 			_snd_pcm_hw_param_setempty(params,
5500 						   SNDRV_PCM_HW_PARAM_RATE);
5501 			return err;
5502 		}
5503 	}
5504 
5505 	err = hdspm_set_interrupt_interval(hdspm,
5506 			params_period_size(params));
5507 	if (err < 0) {
5508 		dev_info(hdspm->card->dev,
5509 			 "err on hdspm_set_interrupt_interval: %d\n", err);
5510 		_snd_pcm_hw_param_setempty(params,
5511 				SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5512 		return err;
5513 	}
5514 
5515 	/* Memory allocation, takashi's method, dont know if we should
5516 	 * spinlock
5517 	 */
5518 	/* malloc all buffer even if not enabled to get sure */
5519 	/* Update for MADI rev 204: we need to allocate for all channels,
5520 	 * otherwise it doesn't work at 96kHz */
5521 
5522 	err =
5523 		snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5524 	if (err < 0) {
5525 		dev_info(hdspm->card->dev,
5526 			 "err on snd_pcm_lib_malloc_pages: %d\n", err);
5527 		return err;
5528 	}
5529 
5530 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5531 
5532 		for (i = 0; i < params_channels(params); ++i) {
5533 			int c = hdspm->channel_map_out[i];
5534 
5535 			if (c < 0)
5536 				continue;      /* just make sure */
5537 			hdspm_set_channel_dma_addr(hdspm, substream,
5538 						   HDSPM_pageAddressBufferOut,
5539 						   c);
5540 			snd_hdspm_enable_out(hdspm, c, 1);
5541 		}
5542 
5543 		hdspm->playback_buffer =
5544 			(unsigned char *) substream->runtime->dma_area;
5545 		dev_dbg(hdspm->card->dev,
5546 			"Allocated sample buffer for playback at %p\n",
5547 				hdspm->playback_buffer);
5548 	} else {
5549 		for (i = 0; i < params_channels(params); ++i) {
5550 			int c = hdspm->channel_map_in[i];
5551 
5552 			if (c < 0)
5553 				continue;
5554 			hdspm_set_channel_dma_addr(hdspm, substream,
5555 						   HDSPM_pageAddressBufferIn,
5556 						   c);
5557 			snd_hdspm_enable_in(hdspm, c, 1);
5558 		}
5559 
5560 		hdspm->capture_buffer =
5561 			(unsigned char *) substream->runtime->dma_area;
5562 		dev_dbg(hdspm->card->dev,
5563 			"Allocated sample buffer for capture at %p\n",
5564 				hdspm->capture_buffer);
5565 	}
5566 
5567 	/*
5568 	   dev_dbg(hdspm->card->dev,
5569 	   "Allocated sample buffer for %s at 0x%08X\n",
5570 	   snd_pcm_direction_name(substream->stream),
5571 	   snd_pcm_sgbuf_get_addr(substream, 0));
5572 	   */
5573 	/*
5574 	   dev_dbg(hdspm->card->dev,
5575 	   "set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5576 	   snd_pcm_direction_name(substream->stream),
5577 	   params_rate(params), params_channels(params),
5578 	   params_buffer_size(params));
5579 	   */
5580 
5581 
5582 	/*  For AES cards, the float format bit is the same as the
5583 	 *  preferred sync reference. Since we don't want to break
5584 	 *  sync settings, we have to skip the remaining part of this
5585 	 *  function.
5586 	 */
5587 	if (hdspm->io_type == AES32) {
5588 		return 0;
5589 	}
5590 
5591 
5592 	/* Switch to native float format if requested */
5593 	if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5594 		if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5595 			dev_info(hdspm->card->dev,
5596 				 "Switching to native 32bit LE float format.\n");
5597 
5598 		hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5599 	} else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5600 		if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5601 			dev_info(hdspm->card->dev,
5602 				 "Switching to native 32bit LE integer format.\n");
5603 
5604 		hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5605 	}
5606 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5607 
5608 	return 0;
5609 }
5610 
5611 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5612 {
5613 	int i;
5614 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5615 
5616 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5617 		/* Just disable all channels. The saving when disabling a */
5618 		/* smaller set is not worth the trouble. */
5619 		for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
5620 			snd_hdspm_enable_out(hdspm, i, 0);
5621 
5622 		hdspm->playback_buffer = NULL;
5623 	} else {
5624 		for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
5625 			snd_hdspm_enable_in(hdspm, i, 0);
5626 
5627 		hdspm->capture_buffer = NULL;
5628 	}
5629 
5630 	snd_pcm_lib_free_pages(substream);
5631 
5632 	return 0;
5633 }
5634 
5635 
5636 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5637 		struct snd_pcm_channel_info *info)
5638 {
5639 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5640 	unsigned int channel = info->channel;
5641 
5642 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5643 		if (snd_BUG_ON(channel >= hdspm->max_channels_out)) {
5644 			dev_info(hdspm->card->dev,
5645 				 "snd_hdspm_channel_info: output channel out of range (%d)\n",
5646 				 channel);
5647 			return -EINVAL;
5648 		}
5649 
5650 		channel = array_index_nospec(channel, hdspm->max_channels_out);
5651 		if (hdspm->channel_map_out[channel] < 0) {
5652 			dev_info(hdspm->card->dev,
5653 				 "snd_hdspm_channel_info: output channel %d mapped out\n",
5654 				 channel);
5655 			return -EINVAL;
5656 		}
5657 
5658 		info->offset = hdspm->channel_map_out[channel] *
5659 			HDSPM_CHANNEL_BUFFER_BYTES;
5660 	} else {
5661 		if (snd_BUG_ON(channel >= hdspm->max_channels_in)) {
5662 			dev_info(hdspm->card->dev,
5663 				 "snd_hdspm_channel_info: input channel out of range (%d)\n",
5664 				 channel);
5665 			return -EINVAL;
5666 		}
5667 
5668 		channel = array_index_nospec(channel, hdspm->max_channels_in);
5669 		if (hdspm->channel_map_in[channel] < 0) {
5670 			dev_info(hdspm->card->dev,
5671 				 "snd_hdspm_channel_info: input channel %d mapped out\n",
5672 				 channel);
5673 			return -EINVAL;
5674 		}
5675 
5676 		info->offset = hdspm->channel_map_in[channel] *
5677 			HDSPM_CHANNEL_BUFFER_BYTES;
5678 	}
5679 
5680 	info->first = 0;
5681 	info->step = 32;
5682 	return 0;
5683 }
5684 
5685 
5686 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5687 		unsigned int cmd, void *arg)
5688 {
5689 	switch (cmd) {
5690 	case SNDRV_PCM_IOCTL1_RESET:
5691 		return snd_hdspm_reset(substream);
5692 
5693 	case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5694 		{
5695 			struct snd_pcm_channel_info *info = arg;
5696 			return snd_hdspm_channel_info(substream, info);
5697 		}
5698 	default:
5699 		break;
5700 	}
5701 
5702 	return snd_pcm_lib_ioctl(substream, cmd, arg);
5703 }
5704 
5705 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5706 {
5707 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5708 	struct snd_pcm_substream *other;
5709 	int running;
5710 
5711 	guard(spinlock)(&hdspm->lock);
5712 	running = hdspm->running;
5713 	switch (cmd) {
5714 	case SNDRV_PCM_TRIGGER_START:
5715 		running |= 1 << substream->stream;
5716 		break;
5717 	case SNDRV_PCM_TRIGGER_STOP:
5718 		running &= ~(1 << substream->stream);
5719 		break;
5720 	default:
5721 		snd_BUG();
5722 		return -EINVAL;
5723 	}
5724 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5725 		other = hdspm->capture_substream;
5726 	else
5727 		other = hdspm->playback_substream;
5728 
5729 	if (other) {
5730 		struct snd_pcm_substream *s;
5731 		snd_pcm_group_for_each_entry(s, substream) {
5732 			if (s == other) {
5733 				snd_pcm_trigger_done(s, substream);
5734 				if (cmd == SNDRV_PCM_TRIGGER_START)
5735 					running |= 1 << s->stream;
5736 				else
5737 					running &= ~(1 << s->stream);
5738 				goto _ok;
5739 			}
5740 		}
5741 		if (cmd == SNDRV_PCM_TRIGGER_START) {
5742 			if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5743 					&& substream->stream ==
5744 					SNDRV_PCM_STREAM_CAPTURE)
5745 				hdspm_silence_playback(hdspm);
5746 		} else {
5747 			if (running &&
5748 				substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5749 				hdspm_silence_playback(hdspm);
5750 		}
5751 	} else {
5752 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5753 			hdspm_silence_playback(hdspm);
5754 	}
5755 _ok:
5756 	snd_pcm_trigger_done(substream, substream);
5757 	if (!hdspm->running && running)
5758 		hdspm_start_audio(hdspm);
5759 	else if (hdspm->running && !running)
5760 		hdspm_stop_audio(hdspm);
5761 	hdspm->running = running;
5762 
5763 	return 0;
5764 }
5765 
5766 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5767 {
5768 	return 0;
5769 }
5770 
5771 static const struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5772 	.info = (SNDRV_PCM_INFO_MMAP |
5773 		 SNDRV_PCM_INFO_MMAP_VALID |
5774 		 SNDRV_PCM_INFO_NONINTERLEAVED |
5775 		 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5776 	.formats = SNDRV_PCM_FMTBIT_S32_LE,
5777 	.rates = (SNDRV_PCM_RATE_32000 |
5778 		  SNDRV_PCM_RATE_44100 |
5779 		  SNDRV_PCM_RATE_48000 |
5780 		  SNDRV_PCM_RATE_64000 |
5781 		  SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5782 		  SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5783 	.rate_min = 32000,
5784 	.rate_max = 192000,
5785 	.channels_min = 1,
5786 	.channels_max = HDSPM_MAX_CHANNELS,
5787 	.buffer_bytes_max =
5788 	    HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5789 	.period_bytes_min = (32 * 4),
5790 	.period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5791 	.periods_min = 2,
5792 	.periods_max = 512,
5793 	.fifo_size = 0
5794 };
5795 
5796 static const struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5797 	.info = (SNDRV_PCM_INFO_MMAP |
5798 		 SNDRV_PCM_INFO_MMAP_VALID |
5799 		 SNDRV_PCM_INFO_NONINTERLEAVED |
5800 		 SNDRV_PCM_INFO_SYNC_START),
5801 	.formats = SNDRV_PCM_FMTBIT_S32_LE,
5802 	.rates = (SNDRV_PCM_RATE_32000 |
5803 		  SNDRV_PCM_RATE_44100 |
5804 		  SNDRV_PCM_RATE_48000 |
5805 		  SNDRV_PCM_RATE_64000 |
5806 		  SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5807 		  SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5808 	.rate_min = 32000,
5809 	.rate_max = 192000,
5810 	.channels_min = 1,
5811 	.channels_max = HDSPM_MAX_CHANNELS,
5812 	.buffer_bytes_max =
5813 	    HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5814 	.period_bytes_min = (32 * 4),
5815 	.period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5816 	.periods_min = 2,
5817 	.periods_max = 512,
5818 	.fifo_size = 0
5819 };
5820 
5821 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5822 					   struct snd_pcm_hw_rule *rule)
5823 {
5824 	struct hdspm *hdspm = rule->private;
5825 	struct snd_interval *c =
5826 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5827 	struct snd_interval *r =
5828 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5829 
5830 	if (r->min > 96000 && r->max <= 192000) {
5831 		struct snd_interval t = {
5832 			.min = hdspm->qs_in_channels,
5833 			.max = hdspm->qs_in_channels,
5834 			.integer = 1,
5835 		};
5836 		return snd_interval_refine(c, &t);
5837 	} else if (r->min > 48000 && r->max <= 96000) {
5838 		struct snd_interval t = {
5839 			.min = hdspm->ds_in_channels,
5840 			.max = hdspm->ds_in_channels,
5841 			.integer = 1,
5842 		};
5843 		return snd_interval_refine(c, &t);
5844 	} else if (r->max < 64000) {
5845 		struct snd_interval t = {
5846 			.min = hdspm->ss_in_channels,
5847 			.max = hdspm->ss_in_channels,
5848 			.integer = 1,
5849 		};
5850 		return snd_interval_refine(c, &t);
5851 	}
5852 
5853 	return 0;
5854 }
5855 
5856 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5857 					   struct snd_pcm_hw_rule * rule)
5858 {
5859 	struct hdspm *hdspm = rule->private;
5860 	struct snd_interval *c =
5861 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5862 	struct snd_interval *r =
5863 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5864 
5865 	if (r->min > 96000 && r->max <= 192000) {
5866 		struct snd_interval t = {
5867 			.min = hdspm->qs_out_channels,
5868 			.max = hdspm->qs_out_channels,
5869 			.integer = 1,
5870 		};
5871 		return snd_interval_refine(c, &t);
5872 	} else if (r->min > 48000 && r->max <= 96000) {
5873 		struct snd_interval t = {
5874 			.min = hdspm->ds_out_channels,
5875 			.max = hdspm->ds_out_channels,
5876 			.integer = 1,
5877 		};
5878 		return snd_interval_refine(c, &t);
5879 	} else if (r->max < 64000) {
5880 		struct snd_interval t = {
5881 			.min = hdspm->ss_out_channels,
5882 			.max = hdspm->ss_out_channels,
5883 			.integer = 1,
5884 		};
5885 		return snd_interval_refine(c, &t);
5886 	} else {
5887 	}
5888 	return 0;
5889 }
5890 
5891 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5892 					   struct snd_pcm_hw_rule * rule)
5893 {
5894 	struct hdspm *hdspm = rule->private;
5895 	struct snd_interval *c =
5896 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5897 	struct snd_interval *r =
5898 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5899 
5900 	if (c->min >= hdspm->ss_in_channels) {
5901 		struct snd_interval t = {
5902 			.min = 32000,
5903 			.max = 48000,
5904 			.integer = 1,
5905 		};
5906 		return snd_interval_refine(r, &t);
5907 	} else if (c->max <= hdspm->qs_in_channels) {
5908 		struct snd_interval t = {
5909 			.min = 128000,
5910 			.max = 192000,
5911 			.integer = 1,
5912 		};
5913 		return snd_interval_refine(r, &t);
5914 	} else if (c->max <= hdspm->ds_in_channels) {
5915 		struct snd_interval t = {
5916 			.min = 64000,
5917 			.max = 96000,
5918 			.integer = 1,
5919 		};
5920 		return snd_interval_refine(r, &t);
5921 	}
5922 
5923 	return 0;
5924 }
5925 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5926 					   struct snd_pcm_hw_rule *rule)
5927 {
5928 	struct hdspm *hdspm = rule->private;
5929 	struct snd_interval *c =
5930 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5931 	struct snd_interval *r =
5932 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5933 
5934 	if (c->min >= hdspm->ss_out_channels) {
5935 		struct snd_interval t = {
5936 			.min = 32000,
5937 			.max = 48000,
5938 			.integer = 1,
5939 		};
5940 		return snd_interval_refine(r, &t);
5941 	} else if (c->max <= hdspm->qs_out_channels) {
5942 		struct snd_interval t = {
5943 			.min = 128000,
5944 			.max = 192000,
5945 			.integer = 1,
5946 		};
5947 		return snd_interval_refine(r, &t);
5948 	} else if (c->max <= hdspm->ds_out_channels) {
5949 		struct snd_interval t = {
5950 			.min = 64000,
5951 			.max = 96000,
5952 			.integer = 1,
5953 		};
5954 		return snd_interval_refine(r, &t);
5955 	}
5956 
5957 	return 0;
5958 }
5959 
5960 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5961 				      struct snd_pcm_hw_rule *rule)
5962 {
5963 	unsigned int list[3];
5964 	struct hdspm *hdspm = rule->private;
5965 	struct snd_interval *c = hw_param_interval(params,
5966 			SNDRV_PCM_HW_PARAM_CHANNELS);
5967 
5968 	list[0] = hdspm->qs_in_channels;
5969 	list[1] = hdspm->ds_in_channels;
5970 	list[2] = hdspm->ss_in_channels;
5971 	return snd_interval_list(c, 3, list, 0);
5972 }
5973 
5974 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5975 				      struct snd_pcm_hw_rule *rule)
5976 {
5977 	unsigned int list[3];
5978 	struct hdspm *hdspm = rule->private;
5979 	struct snd_interval *c = hw_param_interval(params,
5980 			SNDRV_PCM_HW_PARAM_CHANNELS);
5981 
5982 	list[0] = hdspm->qs_out_channels;
5983 	list[1] = hdspm->ds_out_channels;
5984 	list[2] = hdspm->ss_out_channels;
5985 	return snd_interval_list(c, 3, list, 0);
5986 }
5987 
5988 static int snd_hdspm_open(struct snd_pcm_substream *substream)
5989 {
5990 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5991 	struct snd_pcm_runtime *runtime = substream->runtime;
5992 	bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
5993 
5994 	scoped_guard(spinlock_irq, &hdspm->lock) {
5995 		snd_pcm_set_sync(substream);
5996 		runtime->hw = (playback) ? snd_hdspm_playback_subinfo :
5997 			snd_hdspm_capture_subinfo;
5998 
5999 		if (playback) {
6000 			if (!hdspm->capture_substream)
6001 				hdspm_stop_audio(hdspm);
6002 
6003 			hdspm->playback_pid = current->pid;
6004 			hdspm->playback_substream = substream;
6005 		} else {
6006 			if (!hdspm->playback_substream)
6007 				hdspm_stop_audio(hdspm);
6008 
6009 			hdspm->capture_pid = current->pid;
6010 			hdspm->capture_substream = substream;
6011 		}
6012 	}
6013 
6014 	snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6015 	snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6016 
6017 	switch (hdspm->io_type) {
6018 	case AIO:
6019 	case RayDAT:
6020 		snd_pcm_hw_constraint_minmax(runtime,
6021 					     SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6022 					     32, 4096);
6023 		/* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6024 		snd_pcm_hw_constraint_single(runtime,
6025 					     SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6026 					     16384);
6027 		break;
6028 
6029 	default:
6030 		snd_pcm_hw_constraint_minmax(runtime,
6031 					     SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6032 					     64, 8192);
6033 		snd_pcm_hw_constraint_single(runtime,
6034 					     SNDRV_PCM_HW_PARAM_PERIODS, 2);
6035 		break;
6036 	}
6037 
6038 	if (AES32 == hdspm->io_type) {
6039 		runtime->hw.rates |= SNDRV_PCM_RATE_128000;
6040 	} else {
6041 		snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6042 				(playback ?
6043 				 snd_hdspm_hw_rule_rate_out_channels :
6044 				 snd_hdspm_hw_rule_rate_in_channels), hdspm,
6045 				SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6046 	}
6047 
6048 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6049 			(playback ? snd_hdspm_hw_rule_out_channels :
6050 			 snd_hdspm_hw_rule_in_channels), hdspm,
6051 			SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6052 
6053 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6054 			(playback ? snd_hdspm_hw_rule_out_channels_rate :
6055 			 snd_hdspm_hw_rule_in_channels_rate), hdspm,
6056 			SNDRV_PCM_HW_PARAM_RATE, -1);
6057 
6058 	return 0;
6059 }
6060 
6061 static int snd_hdspm_release(struct snd_pcm_substream *substream)
6062 {
6063 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6064 	bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
6065 
6066 	guard(spinlock_irq)(&hdspm->lock);
6067 
6068 	if (playback) {
6069 		hdspm->playback_pid = -1;
6070 		hdspm->playback_substream = NULL;
6071 	} else {
6072 		hdspm->capture_pid = -1;
6073 		hdspm->capture_substream = NULL;
6074 	}
6075 
6076 	return 0;
6077 }
6078 
6079 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6080 {
6081 	/* we have nothing to initialize but the call is required */
6082 	return 0;
6083 }
6084 
6085 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6086 		unsigned int cmd, unsigned long arg)
6087 {
6088 	void __user *argp = (void __user *)arg;
6089 	struct hdspm *hdspm = hw->private_data;
6090 	struct hdspm_mixer_ioctl mixer;
6091 	struct hdspm_config info;
6092 	struct hdspm_status status;
6093 	struct hdspm_version hdspm_version;
6094 	struct hdspm_peak_rms *levels;
6095 	struct hdspm_ltc ltc;
6096 	unsigned int statusregister;
6097 	long unsigned int s;
6098 	int i = 0;
6099 
6100 	switch (cmd) {
6101 
6102 	case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6103 		levels = &hdspm->peak_rms;
6104 		for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6105 			levels->input_peaks[i] =
6106 				readl(hdspm->iobase +
6107 						HDSPM_MADI_INPUT_PEAK + i*4);
6108 			levels->playback_peaks[i] =
6109 				readl(hdspm->iobase +
6110 						HDSPM_MADI_PLAYBACK_PEAK + i*4);
6111 			levels->output_peaks[i] =
6112 				readl(hdspm->iobase +
6113 						HDSPM_MADI_OUTPUT_PEAK + i*4);
6114 
6115 			levels->input_rms[i] =
6116 				((uint64_t) readl(hdspm->iobase +
6117 					HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6118 				(uint64_t) readl(hdspm->iobase +
6119 						HDSPM_MADI_INPUT_RMS_L + i*4);
6120 			levels->playback_rms[i] =
6121 				((uint64_t)readl(hdspm->iobase +
6122 					HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6123 				(uint64_t)readl(hdspm->iobase +
6124 					HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6125 			levels->output_rms[i] =
6126 				((uint64_t)readl(hdspm->iobase +
6127 					HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6128 				(uint64_t)readl(hdspm->iobase +
6129 						HDSPM_MADI_OUTPUT_RMS_L + i*4);
6130 		}
6131 
6132 		if (hdspm->system_sample_rate > 96000) {
6133 			levels->speed = qs;
6134 		} else if (hdspm->system_sample_rate > 48000) {
6135 			levels->speed = ds;
6136 		} else {
6137 			levels->speed = ss;
6138 		}
6139 		levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6140 
6141 		s = copy_to_user(argp, levels, sizeof(*levels));
6142 		if (0 != s) {
6143 			/* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu
6144 			 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6145 			 */
6146 			return -EFAULT;
6147 		}
6148 		break;
6149 
6150 	case SNDRV_HDSPM_IOCTL_GET_LTC:
6151 		ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6152 		i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6153 		if (i & HDSPM_TCO1_LTC_Input_valid) {
6154 			switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6155 				HDSPM_TCO1_LTC_Format_MSB)) {
6156 			case 0:
6157 				ltc.format = fps_24;
6158 				break;
6159 			case HDSPM_TCO1_LTC_Format_LSB:
6160 				ltc.format = fps_25;
6161 				break;
6162 			case HDSPM_TCO1_LTC_Format_MSB:
6163 				ltc.format = fps_2997;
6164 				break;
6165 			default:
6166 				ltc.format = fps_30;
6167 				break;
6168 			}
6169 			if (i & HDSPM_TCO1_set_drop_frame_flag) {
6170 				ltc.frame = drop_frame;
6171 			} else {
6172 				ltc.frame = full_frame;
6173 			}
6174 		} else {
6175 			ltc.format = format_invalid;
6176 			ltc.frame = frame_invalid;
6177 		}
6178 		if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6179 			ltc.input_format = ntsc;
6180 		} else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6181 			ltc.input_format = pal;
6182 		} else {
6183 			ltc.input_format = no_video;
6184 		}
6185 
6186 		s = copy_to_user(argp, &ltc, sizeof(ltc));
6187 		if (0 != s) {
6188 			/*
6189 			  dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6190 			return -EFAULT;
6191 		}
6192 
6193 		break;
6194 
6195 	case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6196 
6197 		memset(&info, 0, sizeof(info));
6198 		scoped_guard(spinlock_irq, &hdspm->lock) {
6199 			info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6200 			info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6201 
6202 			info.system_sample_rate = hdspm->system_sample_rate;
6203 			info.autosync_sample_rate =
6204 				hdspm_external_sample_rate(hdspm);
6205 			info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6206 			info.clock_source = hdspm_clock_source(hdspm);
6207 			info.autosync_ref = hdspm_autosync_ref(hdspm);
6208 			info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6209 			info.passthru = 0;
6210 		}
6211 		if (copy_to_user(argp, &info, sizeof(info)))
6212 			return -EFAULT;
6213 		break;
6214 
6215 	case SNDRV_HDSPM_IOCTL_GET_STATUS:
6216 		memset(&status, 0, sizeof(status));
6217 
6218 		status.card_type = hdspm->io_type;
6219 
6220 		status.autosync_source = hdspm_autosync_ref(hdspm);
6221 
6222 		status.card_clock = 110069313433624ULL;
6223 		status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6224 
6225 		switch (hdspm->io_type) {
6226 		case MADI:
6227 		case MADIface:
6228 			status.card_specific.madi.sync_wc =
6229 				hdspm_wc_sync_check(hdspm);
6230 			status.card_specific.madi.sync_madi =
6231 				hdspm_madi_sync_check(hdspm);
6232 			status.card_specific.madi.sync_tco =
6233 				hdspm_tco_sync_check(hdspm);
6234 			status.card_specific.madi.sync_in =
6235 				hdspm_sync_in_sync_check(hdspm);
6236 
6237 			statusregister =
6238 				hdspm_read(hdspm, HDSPM_statusRegister);
6239 			status.card_specific.madi.madi_input =
6240 				(statusregister & HDSPM_AB_int) ? 1 : 0;
6241 			status.card_specific.madi.channel_format =
6242 				(statusregister & HDSPM_RX_64ch) ? 1 : 0;
6243 			/* TODO: Mac driver sets it when f_s>48kHz */
6244 			status.card_specific.madi.frame_format = 0;
6245 			break;
6246 
6247 		default:
6248 			break;
6249 		}
6250 
6251 		if (copy_to_user(argp, &status, sizeof(status)))
6252 			return -EFAULT;
6253 
6254 
6255 		break;
6256 
6257 	case SNDRV_HDSPM_IOCTL_GET_VERSION:
6258 		memset(&hdspm_version, 0, sizeof(hdspm_version));
6259 
6260 		hdspm_version.card_type = hdspm->io_type;
6261 		strscpy(hdspm_version.cardname, hdspm->card_name,
6262 				sizeof(hdspm_version.cardname));
6263 		hdspm_version.serial = hdspm->serial;
6264 		hdspm_version.firmware_rev = hdspm->firmware_rev;
6265 		hdspm_version.addons = 0;
6266 		if (hdspm->tco)
6267 			hdspm_version.addons |= HDSPM_ADDON_TCO;
6268 
6269 		if (copy_to_user(argp, &hdspm_version,
6270 					sizeof(hdspm_version)))
6271 			return -EFAULT;
6272 		break;
6273 
6274 	case SNDRV_HDSPM_IOCTL_GET_MIXER:
6275 		if (copy_from_user(&mixer, argp, sizeof(mixer)))
6276 			return -EFAULT;
6277 		if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6278 				 sizeof(*mixer.mixer)))
6279 			return -EFAULT;
6280 		break;
6281 
6282 	default:
6283 		return -EINVAL;
6284 	}
6285 	return 0;
6286 }
6287 
6288 static const struct snd_pcm_ops snd_hdspm_ops = {
6289 	.open = snd_hdspm_open,
6290 	.close = snd_hdspm_release,
6291 	.ioctl = snd_hdspm_ioctl,
6292 	.hw_params = snd_hdspm_hw_params,
6293 	.hw_free = snd_hdspm_hw_free,
6294 	.prepare = snd_hdspm_prepare,
6295 	.trigger = snd_hdspm_trigger,
6296 	.pointer = snd_hdspm_hw_pointer,
6297 };
6298 
6299 static int snd_hdspm_create_hwdep(struct snd_card *card,
6300 				  struct hdspm *hdspm)
6301 {
6302 	struct snd_hwdep *hw;
6303 	int err;
6304 
6305 	err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6306 	if (err < 0)
6307 		return err;
6308 
6309 	hdspm->hwdep = hw;
6310 	hw->private_data = hdspm;
6311 	strscpy(hw->name, "HDSPM hwdep interface");
6312 
6313 	hw->ops.open = snd_hdspm_hwdep_dummy_op;
6314 	hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6315 	hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6316 	hw->ops.release = snd_hdspm_hwdep_dummy_op;
6317 
6318 	return 0;
6319 }
6320 
6321 
6322 /*------------------------------------------------------------
6323    memory interface
6324  ------------------------------------------------------------*/
6325 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6326 {
6327 	struct snd_pcm *pcm;
6328 	size_t wanted;
6329 
6330 	pcm = hdspm->pcm;
6331 
6332 	wanted = HDSPM_DMA_AREA_BYTES;
6333 
6334 	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
6335 					      &hdspm->pci->dev,
6336 					      wanted, wanted);
6337 	dev_dbg(hdspm->card->dev, " Preallocated %zd Bytes\n", wanted);
6338 	return 0;
6339 }
6340 
6341 /* Inform the card what DMA addresses to use for the indicated channel. */
6342 /* Each channel got 16 4K pages allocated for DMA transfers. */
6343 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm,
6344 				       struct snd_pcm_substream *substream,
6345 				       unsigned int reg, int channel)
6346 {
6347 	int i;
6348 
6349 	for (i = channel * 16; i < channel * 16 + 16; i++)
6350 		hdspm_write(hdspm, reg + 4 * i,
6351 			    snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6352 }
6353 
6354 
6355 /* ------------- ALSA Devices ---------------------------- */
6356 static int snd_hdspm_create_pcm(struct snd_card *card,
6357 				struct hdspm *hdspm)
6358 {
6359 	struct snd_pcm *pcm;
6360 	int err;
6361 
6362 	err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6363 	if (err < 0)
6364 		return err;
6365 
6366 	hdspm->pcm = pcm;
6367 	pcm->private_data = hdspm;
6368 	strscpy(pcm->name, hdspm->card_name);
6369 
6370 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6371 			&snd_hdspm_ops);
6372 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6373 			&snd_hdspm_ops);
6374 
6375 	pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6376 
6377 	err = snd_hdspm_preallocate_memory(hdspm);
6378 	if (err < 0)
6379 		return err;
6380 
6381 	return 0;
6382 }
6383 
6384 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6385 {
6386 	int i;
6387 
6388 	for (i = 0; i < hdspm->midiPorts; i++)
6389 		snd_hdspm_flush_midi_input(hdspm, i);
6390 }
6391 
6392 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6393 					 struct hdspm *hdspm)
6394 {
6395 	int err, i;
6396 
6397 	dev_dbg(card->dev, "Create card...\n");
6398 	err = snd_hdspm_create_pcm(card, hdspm);
6399 	if (err < 0)
6400 		return err;
6401 
6402 	i = 0;
6403 	while (i < hdspm->midiPorts) {
6404 		err = snd_hdspm_create_midi(card, hdspm, i);
6405 		if (err < 0) {
6406 			return err;
6407 		}
6408 		i++;
6409 	}
6410 
6411 	err = snd_hdspm_create_controls(card, hdspm);
6412 	if (err < 0)
6413 		return err;
6414 
6415 	err = snd_hdspm_create_hwdep(card, hdspm);
6416 	if (err < 0)
6417 		return err;
6418 
6419 	dev_dbg(card->dev, "proc init...\n");
6420 	snd_hdspm_proc_init(hdspm);
6421 
6422 	hdspm->system_sample_rate = -1;
6423 	hdspm->last_external_sample_rate = -1;
6424 	hdspm->last_internal_sample_rate = -1;
6425 	hdspm->playback_pid = -1;
6426 	hdspm->capture_pid = -1;
6427 	hdspm->capture_substream = NULL;
6428 	hdspm->playback_substream = NULL;
6429 
6430 	dev_dbg(card->dev, "Set defaults...\n");
6431 	err = snd_hdspm_set_defaults(hdspm);
6432 	if (err < 0)
6433 		return err;
6434 
6435 	dev_dbg(card->dev, "Update mixer controls...\n");
6436 	hdspm_update_simple_mixer_controls(hdspm);
6437 
6438 	dev_dbg(card->dev, "Initializing complete?\n");
6439 
6440 	err = snd_card_register(card);
6441 	if (err < 0) {
6442 		dev_err(card->dev, "error registering card\n");
6443 		return err;
6444 	}
6445 
6446 	dev_dbg(card->dev, "... yes now\n");
6447 
6448 	return 0;
6449 }
6450 
6451 static int snd_hdspm_create(struct snd_card *card,
6452 			    struct hdspm *hdspm)
6453 {
6454 
6455 	struct pci_dev *pci = hdspm->pci;
6456 	int err;
6457 	unsigned long io_extent;
6458 
6459 	hdspm->irq = -1;
6460 	hdspm->card = card;
6461 
6462 	spin_lock_init(&hdspm->lock);
6463 	INIT_WORK(&hdspm->midi_work, hdspm_midi_work);
6464 
6465 	pci_read_config_word(hdspm->pci,
6466 			PCI_CLASS_REVISION, &hdspm->firmware_rev);
6467 
6468 	strscpy(card->mixername, "Xilinx FPGA");
6469 	strscpy(card->driver, "HDSPM");
6470 
6471 	switch (hdspm->firmware_rev) {
6472 	case HDSPM_RAYDAT_REV:
6473 		hdspm->io_type = RayDAT;
6474 		hdspm->card_name = "RME RayDAT";
6475 		hdspm->midiPorts = 2;
6476 		break;
6477 	case HDSPM_AIO_REV:
6478 		hdspm->io_type = AIO;
6479 		hdspm->card_name = "RME AIO";
6480 		hdspm->midiPorts = 1;
6481 		break;
6482 	case HDSPM_MADIFACE_REV:
6483 		hdspm->io_type = MADIface;
6484 		hdspm->card_name = "RME MADIface";
6485 		hdspm->midiPorts = 1;
6486 		break;
6487 	default:
6488 		if ((hdspm->firmware_rev == 0xf0) ||
6489 			((hdspm->firmware_rev >= 0xe6) &&
6490 					(hdspm->firmware_rev <= 0xea))) {
6491 			hdspm->io_type = AES32;
6492 			hdspm->card_name = "RME AES32";
6493 			hdspm->midiPorts = 2;
6494 		} else if ((hdspm->firmware_rev == 0xd2) ||
6495 			((hdspm->firmware_rev >= 0xc8)  &&
6496 				(hdspm->firmware_rev <= 0xcf))) {
6497 			hdspm->io_type = MADI;
6498 			hdspm->card_name = "RME MADI";
6499 			hdspm->midiPorts = 3;
6500 		} else {
6501 			dev_err(card->dev,
6502 				"unknown firmware revision %x\n",
6503 				hdspm->firmware_rev);
6504 			return -ENODEV;
6505 		}
6506 	}
6507 
6508 	err = pcim_enable_device(pci);
6509 	if (err < 0)
6510 		return err;
6511 
6512 	pci_set_master(hdspm->pci);
6513 
6514 	hdspm->iobase = pcim_iomap_region(pci, 0, "hdspm");
6515 	if (IS_ERR(hdspm->iobase))
6516 		return PTR_ERR(hdspm->iobase);
6517 
6518 	hdspm->port = pci_resource_start(pci, 0);
6519 	io_extent = pci_resource_len(pci, 0);
6520 	dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n",
6521 			(unsigned long)hdspm->iobase, hdspm->port,
6522 			hdspm->port + io_extent - 1);
6523 
6524 	if (devm_request_irq(&pci->dev, pci->irq, snd_hdspm_interrupt,
6525 			     IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6526 		dev_err(card->dev, "unable to use IRQ %d\n", pci->irq);
6527 		return -EBUSY;
6528 	}
6529 
6530 	dev_dbg(card->dev, "use IRQ %d\n", pci->irq);
6531 
6532 	hdspm->irq = pci->irq;
6533 	card->sync_irq = hdspm->irq;
6534 
6535 	dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n",
6536 		sizeof(*hdspm->mixer));
6537 	hdspm->mixer = devm_kzalloc(&pci->dev, sizeof(*hdspm->mixer), GFP_KERNEL);
6538 	if (!hdspm->mixer)
6539 		return -ENOMEM;
6540 
6541 	hdspm->port_names_in = NULL;
6542 	hdspm->port_names_out = NULL;
6543 
6544 	switch (hdspm->io_type) {
6545 	case AES32:
6546 		hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6547 		hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6548 		hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6549 
6550 		hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6551 			channel_map_aes32;
6552 		hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6553 			channel_map_aes32;
6554 		hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6555 			channel_map_aes32;
6556 		hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6557 			texts_ports_aes32;
6558 		hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6559 			texts_ports_aes32;
6560 		hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6561 			texts_ports_aes32;
6562 
6563 		hdspm->max_channels_out = hdspm->max_channels_in =
6564 			AES32_CHANNELS;
6565 		hdspm->port_names_in = hdspm->port_names_out =
6566 			texts_ports_aes32;
6567 		hdspm->channel_map_in = hdspm->channel_map_out =
6568 			channel_map_aes32;
6569 
6570 		break;
6571 
6572 	case MADI:
6573 	case MADIface:
6574 		hdspm->ss_in_channels = hdspm->ss_out_channels =
6575 			MADI_SS_CHANNELS;
6576 		hdspm->ds_in_channels = hdspm->ds_out_channels =
6577 			MADI_DS_CHANNELS;
6578 		hdspm->qs_in_channels = hdspm->qs_out_channels =
6579 			MADI_QS_CHANNELS;
6580 
6581 		hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6582 			channel_map_unity_ss;
6583 		hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6584 			channel_map_unity_ss;
6585 		hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6586 			channel_map_unity_ss;
6587 
6588 		hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6589 			texts_ports_madi;
6590 		hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6591 			texts_ports_madi;
6592 		hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6593 			texts_ports_madi;
6594 		break;
6595 
6596 	case AIO:
6597 		hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6598 		hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6599 		hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6600 		hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6601 		hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6602 		hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6603 
6604 		if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6605 			dev_info(card->dev, "AEB input board found\n");
6606 			hdspm->ss_in_channels += 4;
6607 			hdspm->ds_in_channels += 4;
6608 			hdspm->qs_in_channels += 4;
6609 		}
6610 
6611 		if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6612 			dev_info(card->dev, "AEB output board found\n");
6613 			hdspm->ss_out_channels += 4;
6614 			hdspm->ds_out_channels += 4;
6615 			hdspm->qs_out_channels += 4;
6616 		}
6617 
6618 		hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6619 		hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6620 		hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6621 
6622 		hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6623 		hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6624 		hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6625 
6626 		hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6627 		hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6628 		hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6629 		hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6630 		hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6631 		hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6632 
6633 		break;
6634 
6635 	case RayDAT:
6636 		hdspm->ss_in_channels = hdspm->ss_out_channels =
6637 			RAYDAT_SS_CHANNELS;
6638 		hdspm->ds_in_channels = hdspm->ds_out_channels =
6639 			RAYDAT_DS_CHANNELS;
6640 		hdspm->qs_in_channels = hdspm->qs_out_channels =
6641 			RAYDAT_QS_CHANNELS;
6642 
6643 		hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6644 		hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6645 
6646 		hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6647 			channel_map_raydat_ss;
6648 		hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6649 			channel_map_raydat_ds;
6650 		hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6651 			channel_map_raydat_qs;
6652 		hdspm->channel_map_in = hdspm->channel_map_out =
6653 			channel_map_raydat_ss;
6654 
6655 		hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6656 			texts_ports_raydat_ss;
6657 		hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6658 			texts_ports_raydat_ds;
6659 		hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6660 			texts_ports_raydat_qs;
6661 
6662 
6663 		break;
6664 
6665 	}
6666 
6667 	/* TCO detection */
6668 	switch (hdspm->io_type) {
6669 	case AIO:
6670 	case RayDAT:
6671 		if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6672 				HDSPM_s2_tco_detect) {
6673 			hdspm->midiPorts++;
6674 			hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL);
6675 			if (hdspm->tco)
6676 				hdspm_tco_write(hdspm);
6677 
6678 			dev_info(card->dev, "AIO/RayDAT TCO module found\n");
6679 		} else {
6680 			hdspm->tco = NULL;
6681 		}
6682 		break;
6683 
6684 	case MADI:
6685 	case AES32:
6686 		if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6687 			hdspm->midiPorts++;
6688 			hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL);
6689 			if (hdspm->tco)
6690 				hdspm_tco_write(hdspm);
6691 
6692 			dev_info(card->dev, "MADI/AES TCO module found\n");
6693 		} else {
6694 			hdspm->tco = NULL;
6695 		}
6696 		break;
6697 
6698 	default:
6699 		hdspm->tco = NULL;
6700 	}
6701 
6702 	/* texts */
6703 	switch (hdspm->io_type) {
6704 	case AES32:
6705 		if (hdspm->tco) {
6706 			hdspm->texts_autosync = texts_autosync_aes_tco;
6707 			hdspm->texts_autosync_items =
6708 				ARRAY_SIZE(texts_autosync_aes_tco);
6709 		} else {
6710 			hdspm->texts_autosync = texts_autosync_aes;
6711 			hdspm->texts_autosync_items =
6712 				ARRAY_SIZE(texts_autosync_aes);
6713 		}
6714 		break;
6715 
6716 	case MADI:
6717 		if (hdspm->tco) {
6718 			hdspm->texts_autosync = texts_autosync_madi_tco;
6719 			hdspm->texts_autosync_items = 4;
6720 		} else {
6721 			hdspm->texts_autosync = texts_autosync_madi;
6722 			hdspm->texts_autosync_items = 3;
6723 		}
6724 		break;
6725 
6726 	case MADIface:
6727 
6728 		break;
6729 
6730 	case RayDAT:
6731 		if (hdspm->tco) {
6732 			hdspm->texts_autosync = texts_autosync_raydat_tco;
6733 			hdspm->texts_autosync_items = 9;
6734 		} else {
6735 			hdspm->texts_autosync = texts_autosync_raydat;
6736 			hdspm->texts_autosync_items = 8;
6737 		}
6738 		break;
6739 
6740 	case AIO:
6741 		if (hdspm->tco) {
6742 			hdspm->texts_autosync = texts_autosync_aio_tco;
6743 			hdspm->texts_autosync_items = 6;
6744 		} else {
6745 			hdspm->texts_autosync = texts_autosync_aio;
6746 			hdspm->texts_autosync_items = 5;
6747 		}
6748 		break;
6749 
6750 	}
6751 
6752 	if (hdspm->io_type != MADIface) {
6753 		hdspm->serial = (hdspm_read(hdspm,
6754 				HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6755 		/* id contains either a user-provided value or the default
6756 		 * NULL. If it's the default, we're safe to
6757 		 * fill card->id with the serial number.
6758 		 *
6759 		 * If the serial number is 0xFFFFFF, then we're dealing with
6760 		 * an old PCI revision that comes without a sane number. In
6761 		 * this case, we don't set card->id to avoid collisions
6762 		 * when running with multiple cards.
6763 		 */
6764 		if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6765 			snprintf(card->id, sizeof(card->id),
6766 				 "HDSPMx%06x", hdspm->serial);
6767 			snd_card_set_id(card, card->id);
6768 		}
6769 	}
6770 
6771 	dev_dbg(card->dev, "create alsa devices.\n");
6772 	err = snd_hdspm_create_alsa_devices(card, hdspm);
6773 	if (err < 0)
6774 		return err;
6775 
6776 	snd_hdspm_initialize_midi_flush(hdspm);
6777 
6778 	return 0;
6779 }
6780 
6781 
6782 static void snd_hdspm_card_free(struct snd_card *card)
6783 {
6784 	struct hdspm *hdspm = card->private_data;
6785 
6786 	if (hdspm->port) {
6787 		cancel_work_sync(&hdspm->midi_work);
6788 
6789 		/* stop th audio, and cancel all interrupts */
6790 		hdspm->control_register &=
6791 		    ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6792 		      HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6793 		      HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6794 		hdspm_write(hdspm, HDSPM_controlRegister,
6795 			    hdspm->control_register);
6796 	}
6797 }
6798 
6799 
6800 static int snd_hdspm_probe(struct pci_dev *pci,
6801 			   const struct pci_device_id *pci_id)
6802 {
6803 	static int dev;
6804 	struct hdspm *hdspm;
6805 	struct snd_card *card;
6806 	int err;
6807 
6808 	if (dev >= SNDRV_CARDS)
6809 		return -ENODEV;
6810 	if (!enable[dev]) {
6811 		dev++;
6812 		return -ENOENT;
6813 	}
6814 
6815 	err = snd_devm_card_new(&pci->dev, index[dev], id[dev],
6816 				THIS_MODULE, sizeof(*hdspm), &card);
6817 	if (err < 0)
6818 		return err;
6819 
6820 	hdspm = card->private_data;
6821 	card->private_free = snd_hdspm_card_free;
6822 	hdspm->dev = dev;
6823 	hdspm->pci = pci;
6824 
6825 	err = snd_hdspm_create(card, hdspm);
6826 	if (err < 0)
6827 		goto error;
6828 
6829 	if (hdspm->io_type != MADIface) {
6830 		snprintf(card->shortname, sizeof(card->shortname), "%s_%x",
6831 			hdspm->card_name, hdspm->serial);
6832 		snprintf(card->longname, sizeof(card->longname),
6833 			 "%s S/N 0x%x at 0x%lx, irq %d",
6834 			 hdspm->card_name, hdspm->serial,
6835 			 hdspm->port, hdspm->irq);
6836 	} else {
6837 		snprintf(card->shortname, sizeof(card->shortname), "%s",
6838 			 hdspm->card_name);
6839 		snprintf(card->longname, sizeof(card->longname),
6840 			 "%s at 0x%lx, irq %d",
6841 			 hdspm->card_name, hdspm->port, hdspm->irq);
6842 	}
6843 
6844 	err = snd_card_register(card);
6845 	if (err < 0)
6846 		goto error;
6847 
6848 	pci_set_drvdata(pci, card);
6849 
6850 	dev++;
6851 	return 0;
6852 
6853  error:
6854 	snd_card_free(card);
6855 	return err;
6856 }
6857 
6858 static struct pci_driver hdspm_driver = {
6859 	.name = KBUILD_MODNAME,
6860 	.id_table = snd_hdspm_ids,
6861 	.probe = snd_hdspm_probe,
6862 };
6863 
6864 module_pci_driver(hdspm_driver);
6865