1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm8962.c -- WM8962 ALSA SoC Audio driver 4 * 5 * Copyright 2010-2 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/init.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/gcd.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/i2c.h> 19 #include <linux/input.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/workqueue.h> 25 #include <linux/mutex.h> 26 #include <sound/core.h> 27 #include <sound/jack.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <sound/wm8962.h> 34 #include <trace/events/asoc.h> 35 36 #include "wm8962.h" 37 38 #define WM8962_NUM_SUPPLIES 8 39 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { 40 "DCVDD", 41 "DBVDD", 42 "AVDD", 43 "CPVDD", 44 "MICVDD", 45 "PLLVDD", 46 "SPKVDD1", 47 "SPKVDD2", 48 }; 49 50 /* codec private data */ 51 struct wm8962_priv { 52 struct wm8962_pdata pdata; 53 struct regmap *regmap; 54 struct snd_soc_component *component; 55 56 int sysclk; 57 int sysclk_rate; 58 59 int bclk; /* Desired BCLK */ 60 int lrclk; 61 62 struct completion fll_lock; 63 int fll_src; 64 int fll_fref; 65 int fll_fout; 66 67 struct mutex dsp2_ena_lock; 68 u16 dsp2_ena; 69 70 struct delayed_work mic_work; 71 struct snd_soc_jack *jack; 72 73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; 74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; 75 76 struct input_dev *beep; 77 struct work_struct beep_work; 78 int beep_rate; 79 80 #ifdef CONFIG_GPIOLIB 81 struct gpio_chip gpio_chip; 82 #endif 83 84 int irq; 85 bool master_flag; 86 }; 87 88 /* We can't use the same notifier block for more than one supply and 89 * there's no way I can see to get from a callback to the caller 90 * except container_of(). 91 */ 92 #define WM8962_REGULATOR_EVENT(n) \ 93 static int wm8962_regulator_event_##n(struct notifier_block *nb, \ 94 unsigned long event, void *data) \ 95 { \ 96 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \ 97 disable_nb[n]); \ 98 if (event & REGULATOR_EVENT_DISABLE) { \ 99 regcache_mark_dirty(wm8962->regmap); \ 100 } \ 101 return 0; \ 102 } 103 104 WM8962_REGULATOR_EVENT(0) 105 WM8962_REGULATOR_EVENT(1) 106 WM8962_REGULATOR_EVENT(2) 107 WM8962_REGULATOR_EVENT(3) 108 WM8962_REGULATOR_EVENT(4) 109 WM8962_REGULATOR_EVENT(5) 110 WM8962_REGULATOR_EVENT(6) 111 WM8962_REGULATOR_EVENT(7) 112 113 static const struct reg_default wm8962_reg[] = { 114 { 0, 0x009F }, /* R0 - Left Input volume */ 115 { 1, 0x049F }, /* R1 - Right Input volume */ 116 { 2, 0x0000 }, /* R2 - HPOUTL volume */ 117 { 3, 0x0000 }, /* R3 - HPOUTR volume */ 118 119 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */ 120 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */ 121 { 7, 0x000A }, /* R7 - Audio Interface 0 */ 122 { 8, 0x01E4 }, /* R8 - Clocking2 */ 123 { 9, 0x0300 }, /* R9 - Audio Interface 1 */ 124 { 10, 0x00C0 }, /* R10 - Left DAC volume */ 125 { 11, 0x00C0 }, /* R11 - Right DAC volume */ 126 127 { 14, 0x0040 }, /* R14 - Audio Interface 2 */ 128 { 15, 0x6243 }, /* R15 - Software Reset */ 129 130 { 17, 0x007B }, /* R17 - ALC1 */ 131 { 18, 0x0000 }, /* R18 - ALC2 */ 132 { 19, 0x1C32 }, /* R19 - ALC3 */ 133 { 20, 0x3200 }, /* R20 - Noise Gate */ 134 { 21, 0x00C0 }, /* R21 - Left ADC volume */ 135 { 22, 0x00C0 }, /* R22 - Right ADC volume */ 136 { 23, 0x0160 }, /* R23 - Additional control(1) */ 137 { 24, 0x0000 }, /* R24 - Additional control(2) */ 138 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */ 139 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */ 140 { 27, 0x0010 }, /* R27 - Additional Control (3) */ 141 { 28, 0x0000 }, /* R28 - Anti-pop */ 142 143 { 30, 0x005E }, /* R30 - Clocking 3 */ 144 { 31, 0x0000 }, /* R31 - Input mixer control (1) */ 145 { 32, 0x0145 }, /* R32 - Left input mixer volume */ 146 { 33, 0x0145 }, /* R33 - Right input mixer volume */ 147 { 34, 0x0009 }, /* R34 - Input mixer control (2) */ 148 { 35, 0x0003 }, /* R35 - Input bias control */ 149 { 37, 0x0008 }, /* R37 - Left input PGA control */ 150 { 38, 0x0008 }, /* R38 - Right input PGA control */ 151 152 { 40, 0x0000 }, /* R40 - SPKOUTL volume */ 153 { 41, 0x0000 }, /* R41 - SPKOUTR volume */ 154 155 { 49, 0x0010 }, /* R49 - Class D Control 1 */ 156 { 51, 0x0003 }, /* R51 - Class D Control 2 */ 157 158 { 56, 0x0506 }, /* R56 - Clocking 4 */ 159 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */ 160 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */ 161 162 { 60, 0x0300 }, /* R60 - DC Servo 0 */ 163 { 61, 0x0300 }, /* R61 - DC Servo 1 */ 164 165 { 64, 0x0810 }, /* R64 - DC Servo 4 */ 166 167 { 68, 0x001B }, /* R68 - Analogue PGA Bias */ 168 { 69, 0x0000 }, /* R69 - Analogue HP 0 */ 169 170 { 71, 0x01FB }, /* R71 - Analogue HP 2 */ 171 { 72, 0x0000 }, /* R72 - Charge Pump 1 */ 172 173 { 82, 0x0004 }, /* R82 - Charge Pump B */ 174 175 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */ 176 177 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */ 178 179 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */ 180 { 94, 0x0000 }, /* R94 - Control Interface */ 181 182 { 99, 0x0000 }, /* R99 - Mixer Enables */ 183 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */ 184 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */ 185 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */ 186 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */ 187 188 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */ 189 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */ 190 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */ 191 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */ 192 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */ 193 { 110, 0x0002 }, /* R110 - Beep Generator (1) */ 194 195 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */ 196 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */ 197 198 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */ 199 200 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */ 201 { 125, 0x004B }, /* R125 - Analogue Clocking2 */ 202 { 126, 0x000D }, /* R126 - Analogue Clocking3 */ 203 { 127, 0x0000 }, /* R127 - PLL Software Reset */ 204 205 { 131, 0x0000 }, /* R131 - PLL 4 */ 206 207 { 136, 0x0067 }, /* R136 - PLL 9 */ 208 { 137, 0x001C }, /* R137 - PLL 10 */ 209 { 138, 0x0071 }, /* R138 - PLL 11 */ 210 { 139, 0x00C7 }, /* R139 - PLL 12 */ 211 { 140, 0x0067 }, /* R140 - PLL 13 */ 212 { 141, 0x0048 }, /* R141 - PLL 14 */ 213 { 142, 0x0022 }, /* R142 - PLL 15 */ 214 { 143, 0x0097 }, /* R143 - PLL 16 */ 215 216 { 155, 0x000C }, /* R155 - FLL Control (1) */ 217 { 156, 0x0039 }, /* R156 - FLL Control (2) */ 218 { 157, 0x0180 }, /* R157 - FLL Control (3) */ 219 220 { 159, 0x0032 }, /* R159 - FLL Control (5) */ 221 { 160, 0x0018 }, /* R160 - FLL Control (6) */ 222 { 161, 0x007D }, /* R161 - FLL Control (7) */ 223 { 162, 0x0008 }, /* R162 - FLL Control (8) */ 224 225 { 252, 0x0005 }, /* R252 - General test 1 */ 226 227 { 256, 0x0000 }, /* R256 - DF1 */ 228 { 257, 0x0000 }, /* R257 - DF2 */ 229 { 258, 0x0000 }, /* R258 - DF3 */ 230 { 259, 0x0000 }, /* R259 - DF4 */ 231 { 260, 0x0000 }, /* R260 - DF5 */ 232 { 261, 0x0000 }, /* R261 - DF6 */ 233 { 262, 0x0000 }, /* R262 - DF7 */ 234 235 { 264, 0x0000 }, /* R264 - LHPF1 */ 236 { 265, 0x0000 }, /* R265 - LHPF2 */ 237 238 { 268, 0x0000 }, /* R268 - THREED1 */ 239 { 269, 0x0000 }, /* R269 - THREED2 */ 240 { 270, 0x0000 }, /* R270 - THREED3 */ 241 { 271, 0x0000 }, /* R271 - THREED4 */ 242 243 { 276, 0x000C }, /* R276 - DRC 1 */ 244 { 277, 0x0925 }, /* R277 - DRC 2 */ 245 { 278, 0x0000 }, /* R278 - DRC 3 */ 246 { 279, 0x0000 }, /* R279 - DRC 4 */ 247 { 280, 0x0000 }, /* R280 - DRC 5 */ 248 249 { 285, 0x0000 }, /* R285 - Tloopback */ 250 251 { 335, 0x0004 }, /* R335 - EQ1 */ 252 { 336, 0x6318 }, /* R336 - EQ2 */ 253 { 337, 0x6300 }, /* R337 - EQ3 */ 254 { 338, 0x0FCA }, /* R338 - EQ4 */ 255 { 339, 0x0400 }, /* R339 - EQ5 */ 256 { 340, 0x00D8 }, /* R340 - EQ6 */ 257 { 341, 0x1EB5 }, /* R341 - EQ7 */ 258 { 342, 0xF145 }, /* R342 - EQ8 */ 259 { 343, 0x0B75 }, /* R343 - EQ9 */ 260 { 344, 0x01C5 }, /* R344 - EQ10 */ 261 { 345, 0x1C58 }, /* R345 - EQ11 */ 262 { 346, 0xF373 }, /* R346 - EQ12 */ 263 { 347, 0x0A54 }, /* R347 - EQ13 */ 264 { 348, 0x0558 }, /* R348 - EQ14 */ 265 { 349, 0x168E }, /* R349 - EQ15 */ 266 { 350, 0xF829 }, /* R350 - EQ16 */ 267 { 351, 0x07AD }, /* R351 - EQ17 */ 268 { 352, 0x1103 }, /* R352 - EQ18 */ 269 { 353, 0x0564 }, /* R353 - EQ19 */ 270 { 354, 0x0559 }, /* R354 - EQ20 */ 271 { 355, 0x4000 }, /* R355 - EQ21 */ 272 { 356, 0x6318 }, /* R356 - EQ22 */ 273 { 357, 0x6300 }, /* R357 - EQ23 */ 274 { 358, 0x0FCA }, /* R358 - EQ24 */ 275 { 359, 0x0400 }, /* R359 - EQ25 */ 276 { 360, 0x00D8 }, /* R360 - EQ26 */ 277 { 361, 0x1EB5 }, /* R361 - EQ27 */ 278 { 362, 0xF145 }, /* R362 - EQ28 */ 279 { 363, 0x0B75 }, /* R363 - EQ29 */ 280 { 364, 0x01C5 }, /* R364 - EQ30 */ 281 { 365, 0x1C58 }, /* R365 - EQ31 */ 282 { 366, 0xF373 }, /* R366 - EQ32 */ 283 { 367, 0x0A54 }, /* R367 - EQ33 */ 284 { 368, 0x0558 }, /* R368 - EQ34 */ 285 { 369, 0x168E }, /* R369 - EQ35 */ 286 { 370, 0xF829 }, /* R370 - EQ36 */ 287 { 371, 0x07AD }, /* R371 - EQ37 */ 288 { 372, 0x1103 }, /* R372 - EQ38 */ 289 { 373, 0x0564 }, /* R373 - EQ39 */ 290 { 374, 0x0559 }, /* R374 - EQ40 */ 291 { 375, 0x4000 }, /* R375 - EQ41 */ 292 293 { 513, 0x0000 }, /* R513 - GPIO 2 */ 294 { 514, 0x0000 }, /* R514 - GPIO 3 */ 295 296 { 516, 0x8100 }, /* R516 - GPIO 5 */ 297 { 517, 0x8100 }, /* R517 - GPIO 6 */ 298 299 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */ 300 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */ 301 302 { 576, 0x0000 }, /* R576 - Interrupt Control */ 303 304 { 584, 0x002D }, /* R584 - IRQ Debounce */ 305 306 { 586, 0x0000 }, /* R586 - MICINT Source Pol */ 307 308 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */ 309 310 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */ 311 312 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */ 313 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */ 314 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */ 315 316 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */ 317 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */ 318 319 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */ 320 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */ 321 322 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */ 323 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */ 324 325 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */ 326 327 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ 328 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ 329 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ 330 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ 331 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */ 332 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */ 333 334 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */ 335 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */ 336 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */ 337 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */ 338 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */ 339 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */ 340 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */ 341 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */ 342 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */ 343 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */ 344 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */ 345 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */ 346 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */ 347 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */ 348 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */ 349 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */ 350 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */ 351 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */ 352 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */ 353 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */ 354 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */ 355 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */ 356 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */ 357 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */ 358 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */ 359 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */ 360 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */ 361 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */ 362 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */ 363 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */ 364 365 { 17408, 0x0083 }, /* R17408 - HPF_C_1 */ 366 { 17409, 0x98AD }, /* R17409 - HPF_C_0 */ 367 368 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */ 369 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */ 370 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */ 371 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */ 372 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */ 373 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */ 374 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */ 375 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */ 376 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */ 377 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */ 378 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */ 379 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */ 380 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */ 381 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */ 382 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */ 383 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */ 384 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */ 385 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */ 386 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */ 387 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */ 388 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */ 389 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */ 390 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */ 391 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */ 392 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */ 393 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */ 394 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */ 395 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */ 396 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */ 397 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */ 398 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */ 399 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */ 400 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */ 401 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */ 402 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */ 403 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */ 404 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */ 405 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */ 406 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */ 407 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */ 408 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */ 409 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */ 410 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */ 411 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */ 412 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */ 413 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */ 414 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */ 415 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */ 416 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */ 417 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */ 418 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */ 419 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */ 420 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */ 421 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */ 422 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */ 423 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */ 424 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */ 425 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */ 426 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */ 427 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */ 428 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */ 429 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */ 430 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */ 431 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */ 432 433 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */ 434 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */ 435 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */ 436 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */ 437 438 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */ 439 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */ 440 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */ 441 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */ 442 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */ 443 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */ 444 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */ 445 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */ 446 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */ 447 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */ 448 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */ 449 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */ 450 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */ 451 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */ 452 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */ 453 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */ 454 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */ 455 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */ 456 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */ 457 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */ 458 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */ 459 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */ 460 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */ 461 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */ 462 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */ 463 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */ 464 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */ 465 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */ 466 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */ 467 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */ 468 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */ 469 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */ 470 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */ 471 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */ 472 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */ 473 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */ 474 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */ 475 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */ 476 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */ 477 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */ 478 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */ 479 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */ 480 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */ 481 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */ 482 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */ 483 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */ 484 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */ 485 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */ 486 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */ 487 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */ 488 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */ 489 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */ 490 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */ 491 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */ 492 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */ 493 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */ 494 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */ 495 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */ 496 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */ 497 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */ 498 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */ 499 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */ 500 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */ 501 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */ 502 503 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */ 504 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */ 505 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */ 506 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */ 507 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */ 508 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */ 509 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */ 510 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */ 511 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */ 512 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */ 513 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */ 514 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */ 515 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */ 516 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */ 517 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */ 518 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */ 519 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */ 520 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */ 521 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */ 522 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */ 523 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */ 524 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */ 525 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */ 526 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */ 527 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */ 528 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */ 529 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */ 530 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */ 531 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */ 532 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */ 533 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */ 534 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */ 535 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */ 536 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */ 537 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */ 538 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */ 539 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */ 540 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */ 541 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */ 542 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */ 543 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */ 544 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */ 545 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */ 546 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */ 547 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */ 548 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */ 549 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */ 550 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */ 551 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */ 552 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */ 553 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */ 554 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */ 555 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */ 556 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */ 557 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */ 558 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */ 559 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */ 560 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */ 561 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */ 562 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */ 563 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */ 564 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */ 565 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */ 566 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */ 567 568 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */ 569 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */ 570 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */ 571 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */ 572 573 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */ 574 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */ 575 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */ 576 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */ 577 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */ 578 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */ 579 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */ 580 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */ 581 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */ 582 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */ 583 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */ 584 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */ 585 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */ 586 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */ 587 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */ 588 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */ 589 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */ 590 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */ 591 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */ 592 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */ 593 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */ 594 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */ 595 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */ 596 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */ 597 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */ 598 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */ 599 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */ 600 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */ 601 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */ 602 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */ 603 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */ 604 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */ 605 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */ 606 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */ 607 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */ 608 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */ 609 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */ 610 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */ 611 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */ 612 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */ 613 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */ 614 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */ 615 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */ 616 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */ 617 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */ 618 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */ 619 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */ 620 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */ 621 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */ 622 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */ 623 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */ 624 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */ 625 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */ 626 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */ 627 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */ 628 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */ 629 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */ 630 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */ 631 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */ 632 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */ 633 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */ 634 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */ 635 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */ 636 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */ 637 638 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */ 639 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */ 640 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */ 641 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */ 642 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */ 643 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */ 644 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */ 645 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */ 646 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */ 647 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */ 648 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */ 649 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */ 650 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */ 651 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */ 652 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */ 653 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */ 654 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */ 655 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */ 656 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */ 657 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */ 658 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */ 659 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */ 660 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */ 661 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */ 662 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */ 663 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */ 664 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */ 665 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */ 666 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */ 667 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */ 668 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */ 669 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */ 670 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */ 671 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */ 672 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */ 673 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */ 674 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */ 675 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */ 676 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */ 677 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */ 678 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */ 679 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */ 680 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */ 681 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */ 682 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */ 683 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */ 684 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */ 685 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */ 686 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */ 687 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */ 688 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */ 689 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */ 690 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */ 691 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */ 692 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */ 693 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */ 694 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */ 695 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */ 696 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */ 697 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */ 698 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */ 699 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */ 700 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */ 701 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */ 702 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */ 703 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */ 704 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */ 705 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */ 706 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */ 707 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */ 708 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */ 709 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */ 710 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */ 711 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */ 712 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */ 713 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */ 714 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */ 715 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */ 716 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */ 717 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */ 718 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */ 719 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */ 720 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */ 721 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */ 722 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */ 723 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */ 724 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */ 725 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */ 726 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */ 727 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */ 728 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */ 729 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */ 730 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */ 731 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */ 732 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */ 733 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */ 734 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */ 735 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */ 736 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */ 737 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */ 738 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */ 739 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */ 740 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */ 741 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */ 742 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */ 743 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */ 744 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */ 745 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */ 746 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */ 747 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */ 748 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */ 749 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */ 750 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */ 751 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */ 752 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */ 753 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */ 754 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */ 755 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */ 756 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */ 757 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */ 758 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */ 759 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */ 760 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */ 761 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */ 762 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */ 763 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */ 764 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */ 765 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */ 766 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */ 767 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */ 768 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */ 769 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */ 770 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */ 771 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */ 772 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */ 773 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */ 774 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */ 775 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */ 776 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */ 777 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */ 778 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */ 779 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */ 780 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */ 781 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */ 782 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */ 783 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */ 784 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */ 785 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */ 786 }; 787 788 static bool wm8962_volatile_register(struct device *dev, unsigned int reg) 789 { 790 switch (reg) { 791 case WM8962_CLOCKING1: 792 case WM8962_SOFTWARE_RESET: 793 case WM8962_THERMAL_SHUTDOWN_STATUS: 794 case WM8962_ADDITIONAL_CONTROL_4: 795 case WM8962_DC_SERVO_6: 796 case WM8962_INTERRUPT_STATUS_1: 797 case WM8962_INTERRUPT_STATUS_2: 798 case WM8962_DSP2_EXECCONTROL: 799 return true; 800 default: 801 return false; 802 } 803 } 804 805 static bool wm8962_readable_register(struct device *dev, unsigned int reg) 806 { 807 switch (reg) { 808 case WM8962_LEFT_INPUT_VOLUME: 809 case WM8962_RIGHT_INPUT_VOLUME: 810 case WM8962_HPOUTL_VOLUME: 811 case WM8962_HPOUTR_VOLUME: 812 case WM8962_CLOCKING1: 813 case WM8962_ADC_DAC_CONTROL_1: 814 case WM8962_ADC_DAC_CONTROL_2: 815 case WM8962_AUDIO_INTERFACE_0: 816 case WM8962_CLOCKING2: 817 case WM8962_AUDIO_INTERFACE_1: 818 case WM8962_LEFT_DAC_VOLUME: 819 case WM8962_RIGHT_DAC_VOLUME: 820 case WM8962_AUDIO_INTERFACE_2: 821 case WM8962_SOFTWARE_RESET: 822 case WM8962_ALC1: 823 case WM8962_ALC2: 824 case WM8962_ALC3: 825 case WM8962_NOISE_GATE: 826 case WM8962_LEFT_ADC_VOLUME: 827 case WM8962_RIGHT_ADC_VOLUME: 828 case WM8962_ADDITIONAL_CONTROL_1: 829 case WM8962_ADDITIONAL_CONTROL_2: 830 case WM8962_PWR_MGMT_1: 831 case WM8962_PWR_MGMT_2: 832 case WM8962_ADDITIONAL_CONTROL_3: 833 case WM8962_ANTI_POP: 834 case WM8962_CLOCKING_3: 835 case WM8962_INPUT_MIXER_CONTROL_1: 836 case WM8962_LEFT_INPUT_MIXER_VOLUME: 837 case WM8962_RIGHT_INPUT_MIXER_VOLUME: 838 case WM8962_INPUT_MIXER_CONTROL_2: 839 case WM8962_INPUT_BIAS_CONTROL: 840 case WM8962_LEFT_INPUT_PGA_CONTROL: 841 case WM8962_RIGHT_INPUT_PGA_CONTROL: 842 case WM8962_SPKOUTL_VOLUME: 843 case WM8962_SPKOUTR_VOLUME: 844 case WM8962_THERMAL_SHUTDOWN_STATUS: 845 case WM8962_ADDITIONAL_CONTROL_4: 846 case WM8962_CLASS_D_CONTROL_1: 847 case WM8962_CLASS_D_CONTROL_2: 848 case WM8962_CLOCKING_4: 849 case WM8962_DAC_DSP_MIXING_1: 850 case WM8962_DAC_DSP_MIXING_2: 851 case WM8962_DC_SERVO_0: 852 case WM8962_DC_SERVO_1: 853 case WM8962_DC_SERVO_4: 854 case WM8962_DC_SERVO_6: 855 case WM8962_ANALOGUE_PGA_BIAS: 856 case WM8962_ANALOGUE_HP_0: 857 case WM8962_ANALOGUE_HP_2: 858 case WM8962_CHARGE_PUMP_1: 859 case WM8962_CHARGE_PUMP_B: 860 case WM8962_WRITE_SEQUENCER_CONTROL_1: 861 case WM8962_WRITE_SEQUENCER_CONTROL_2: 862 case WM8962_WRITE_SEQUENCER_CONTROL_3: 863 case WM8962_CONTROL_INTERFACE: 864 case WM8962_MIXER_ENABLES: 865 case WM8962_HEADPHONE_MIXER_1: 866 case WM8962_HEADPHONE_MIXER_2: 867 case WM8962_HEADPHONE_MIXER_3: 868 case WM8962_HEADPHONE_MIXER_4: 869 case WM8962_SPEAKER_MIXER_1: 870 case WM8962_SPEAKER_MIXER_2: 871 case WM8962_SPEAKER_MIXER_3: 872 case WM8962_SPEAKER_MIXER_4: 873 case WM8962_SPEAKER_MIXER_5: 874 case WM8962_BEEP_GENERATOR_1: 875 case WM8962_OSCILLATOR_TRIM_3: 876 case WM8962_OSCILLATOR_TRIM_4: 877 case WM8962_OSCILLATOR_TRIM_7: 878 case WM8962_ANALOGUE_CLOCKING1: 879 case WM8962_ANALOGUE_CLOCKING2: 880 case WM8962_ANALOGUE_CLOCKING3: 881 case WM8962_PLL_SOFTWARE_RESET: 882 case WM8962_PLL2: 883 case WM8962_PLL_4: 884 case WM8962_PLL_9: 885 case WM8962_PLL_10: 886 case WM8962_PLL_11: 887 case WM8962_PLL_12: 888 case WM8962_PLL_13: 889 case WM8962_PLL_14: 890 case WM8962_PLL_15: 891 case WM8962_PLL_16: 892 case WM8962_FLL_CONTROL_1: 893 case WM8962_FLL_CONTROL_2: 894 case WM8962_FLL_CONTROL_3: 895 case WM8962_FLL_CONTROL_5: 896 case WM8962_FLL_CONTROL_6: 897 case WM8962_FLL_CONTROL_7: 898 case WM8962_FLL_CONTROL_8: 899 case WM8962_GENERAL_TEST_1: 900 case WM8962_DF1: 901 case WM8962_DF2: 902 case WM8962_DF3: 903 case WM8962_DF4: 904 case WM8962_DF5: 905 case WM8962_DF6: 906 case WM8962_DF7: 907 case WM8962_LHPF1: 908 case WM8962_LHPF2: 909 case WM8962_THREED1: 910 case WM8962_THREED2: 911 case WM8962_THREED3: 912 case WM8962_THREED4: 913 case WM8962_DRC_1: 914 case WM8962_DRC_2: 915 case WM8962_DRC_3: 916 case WM8962_DRC_4: 917 case WM8962_DRC_5: 918 case WM8962_TLOOPBACK: 919 case WM8962_EQ1: 920 case WM8962_EQ2: 921 case WM8962_EQ3: 922 case WM8962_EQ4: 923 case WM8962_EQ5: 924 case WM8962_EQ6: 925 case WM8962_EQ7: 926 case WM8962_EQ8: 927 case WM8962_EQ9: 928 case WM8962_EQ10: 929 case WM8962_EQ11: 930 case WM8962_EQ12: 931 case WM8962_EQ13: 932 case WM8962_EQ14: 933 case WM8962_EQ15: 934 case WM8962_EQ16: 935 case WM8962_EQ17: 936 case WM8962_EQ18: 937 case WM8962_EQ19: 938 case WM8962_EQ20: 939 case WM8962_EQ21: 940 case WM8962_EQ22: 941 case WM8962_EQ23: 942 case WM8962_EQ24: 943 case WM8962_EQ25: 944 case WM8962_EQ26: 945 case WM8962_EQ27: 946 case WM8962_EQ28: 947 case WM8962_EQ29: 948 case WM8962_EQ30: 949 case WM8962_EQ31: 950 case WM8962_EQ32: 951 case WM8962_EQ33: 952 case WM8962_EQ34: 953 case WM8962_EQ35: 954 case WM8962_EQ36: 955 case WM8962_EQ37: 956 case WM8962_EQ38: 957 case WM8962_EQ39: 958 case WM8962_EQ40: 959 case WM8962_EQ41: 960 case WM8962_GPIO_2: 961 case WM8962_GPIO_3: 962 case WM8962_GPIO_5: 963 case WM8962_GPIO_6: 964 case WM8962_INTERRUPT_STATUS_1: 965 case WM8962_INTERRUPT_STATUS_2: 966 case WM8962_INTERRUPT_STATUS_1_MASK: 967 case WM8962_INTERRUPT_STATUS_2_MASK: 968 case WM8962_INTERRUPT_CONTROL: 969 case WM8962_IRQ_DEBOUNCE: 970 case WM8962_MICINT_SOURCE_POL: 971 case WM8962_DSP2_POWER_MANAGEMENT: 972 case WM8962_DSP2_EXECCONTROL: 973 case WM8962_DSP2_INSTRUCTION_RAM_0: 974 case WM8962_DSP2_ADDRESS_RAM_2: 975 case WM8962_DSP2_ADDRESS_RAM_1: 976 case WM8962_DSP2_ADDRESS_RAM_0: 977 case WM8962_DSP2_DATA1_RAM_1: 978 case WM8962_DSP2_DATA1_RAM_0: 979 case WM8962_DSP2_DATA2_RAM_1: 980 case WM8962_DSP2_DATA2_RAM_0: 981 case WM8962_DSP2_DATA3_RAM_1: 982 case WM8962_DSP2_DATA3_RAM_0: 983 case WM8962_DSP2_COEFF_RAM_0: 984 case WM8962_RETUNEADC_SHARED_COEFF_1: 985 case WM8962_RETUNEADC_SHARED_COEFF_0: 986 case WM8962_RETUNEDAC_SHARED_COEFF_1: 987 case WM8962_RETUNEDAC_SHARED_COEFF_0: 988 case WM8962_SOUNDSTAGE_ENABLES_1: 989 case WM8962_SOUNDSTAGE_ENABLES_0: 990 case WM8962_HDBASS_AI_1: 991 case WM8962_HDBASS_AI_0: 992 case WM8962_HDBASS_AR_1: 993 case WM8962_HDBASS_AR_0: 994 case WM8962_HDBASS_B_1: 995 case WM8962_HDBASS_B_0: 996 case WM8962_HDBASS_K_1: 997 case WM8962_HDBASS_K_0: 998 case WM8962_HDBASS_N1_1: 999 case WM8962_HDBASS_N1_0: 1000 case WM8962_HDBASS_N2_1: 1001 case WM8962_HDBASS_N2_0: 1002 case WM8962_HDBASS_N3_1: 1003 case WM8962_HDBASS_N3_0: 1004 case WM8962_HDBASS_N4_1: 1005 case WM8962_HDBASS_N4_0: 1006 case WM8962_HDBASS_N5_1: 1007 case WM8962_HDBASS_N5_0: 1008 case WM8962_HDBASS_X1_1: 1009 case WM8962_HDBASS_X1_0: 1010 case WM8962_HDBASS_X2_1: 1011 case WM8962_HDBASS_X2_0: 1012 case WM8962_HDBASS_X3_1: 1013 case WM8962_HDBASS_X3_0: 1014 case WM8962_HDBASS_ATK_1: 1015 case WM8962_HDBASS_ATK_0: 1016 case WM8962_HDBASS_DCY_1: 1017 case WM8962_HDBASS_DCY_0: 1018 case WM8962_HDBASS_PG_1: 1019 case WM8962_HDBASS_PG_0: 1020 case WM8962_HPF_C_1: 1021 case WM8962_HPF_C_0: 1022 case WM8962_ADCL_RETUNE_C1_1: 1023 case WM8962_ADCL_RETUNE_C1_0: 1024 case WM8962_ADCL_RETUNE_C2_1: 1025 case WM8962_ADCL_RETUNE_C2_0: 1026 case WM8962_ADCL_RETUNE_C3_1: 1027 case WM8962_ADCL_RETUNE_C3_0: 1028 case WM8962_ADCL_RETUNE_C4_1: 1029 case WM8962_ADCL_RETUNE_C4_0: 1030 case WM8962_ADCL_RETUNE_C5_1: 1031 case WM8962_ADCL_RETUNE_C5_0: 1032 case WM8962_ADCL_RETUNE_C6_1: 1033 case WM8962_ADCL_RETUNE_C6_0: 1034 case WM8962_ADCL_RETUNE_C7_1: 1035 case WM8962_ADCL_RETUNE_C7_0: 1036 case WM8962_ADCL_RETUNE_C8_1: 1037 case WM8962_ADCL_RETUNE_C8_0: 1038 case WM8962_ADCL_RETUNE_C9_1: 1039 case WM8962_ADCL_RETUNE_C9_0: 1040 case WM8962_ADCL_RETUNE_C10_1: 1041 case WM8962_ADCL_RETUNE_C10_0: 1042 case WM8962_ADCL_RETUNE_C11_1: 1043 case WM8962_ADCL_RETUNE_C11_0: 1044 case WM8962_ADCL_RETUNE_C12_1: 1045 case WM8962_ADCL_RETUNE_C12_0: 1046 case WM8962_ADCL_RETUNE_C13_1: 1047 case WM8962_ADCL_RETUNE_C13_0: 1048 case WM8962_ADCL_RETUNE_C14_1: 1049 case WM8962_ADCL_RETUNE_C14_0: 1050 case WM8962_ADCL_RETUNE_C15_1: 1051 case WM8962_ADCL_RETUNE_C15_0: 1052 case WM8962_ADCL_RETUNE_C16_1: 1053 case WM8962_ADCL_RETUNE_C16_0: 1054 case WM8962_ADCL_RETUNE_C17_1: 1055 case WM8962_ADCL_RETUNE_C17_0: 1056 case WM8962_ADCL_RETUNE_C18_1: 1057 case WM8962_ADCL_RETUNE_C18_0: 1058 case WM8962_ADCL_RETUNE_C19_1: 1059 case WM8962_ADCL_RETUNE_C19_0: 1060 case WM8962_ADCL_RETUNE_C20_1: 1061 case WM8962_ADCL_RETUNE_C20_0: 1062 case WM8962_ADCL_RETUNE_C21_1: 1063 case WM8962_ADCL_RETUNE_C21_0: 1064 case WM8962_ADCL_RETUNE_C22_1: 1065 case WM8962_ADCL_RETUNE_C22_0: 1066 case WM8962_ADCL_RETUNE_C23_1: 1067 case WM8962_ADCL_RETUNE_C23_0: 1068 case WM8962_ADCL_RETUNE_C24_1: 1069 case WM8962_ADCL_RETUNE_C24_0: 1070 case WM8962_ADCL_RETUNE_C25_1: 1071 case WM8962_ADCL_RETUNE_C25_0: 1072 case WM8962_ADCL_RETUNE_C26_1: 1073 case WM8962_ADCL_RETUNE_C26_0: 1074 case WM8962_ADCL_RETUNE_C27_1: 1075 case WM8962_ADCL_RETUNE_C27_0: 1076 case WM8962_ADCL_RETUNE_C28_1: 1077 case WM8962_ADCL_RETUNE_C28_0: 1078 case WM8962_ADCL_RETUNE_C29_1: 1079 case WM8962_ADCL_RETUNE_C29_0: 1080 case WM8962_ADCL_RETUNE_C30_1: 1081 case WM8962_ADCL_RETUNE_C30_0: 1082 case WM8962_ADCL_RETUNE_C31_1: 1083 case WM8962_ADCL_RETUNE_C31_0: 1084 case WM8962_ADCL_RETUNE_C32_1: 1085 case WM8962_ADCL_RETUNE_C32_0: 1086 case WM8962_RETUNEADC_PG2_1: 1087 case WM8962_RETUNEADC_PG2_0: 1088 case WM8962_RETUNEADC_PG_1: 1089 case WM8962_RETUNEADC_PG_0: 1090 case WM8962_ADCR_RETUNE_C1_1: 1091 case WM8962_ADCR_RETUNE_C1_0: 1092 case WM8962_ADCR_RETUNE_C2_1: 1093 case WM8962_ADCR_RETUNE_C2_0: 1094 case WM8962_ADCR_RETUNE_C3_1: 1095 case WM8962_ADCR_RETUNE_C3_0: 1096 case WM8962_ADCR_RETUNE_C4_1: 1097 case WM8962_ADCR_RETUNE_C4_0: 1098 case WM8962_ADCR_RETUNE_C5_1: 1099 case WM8962_ADCR_RETUNE_C5_0: 1100 case WM8962_ADCR_RETUNE_C6_1: 1101 case WM8962_ADCR_RETUNE_C6_0: 1102 case WM8962_ADCR_RETUNE_C7_1: 1103 case WM8962_ADCR_RETUNE_C7_0: 1104 case WM8962_ADCR_RETUNE_C8_1: 1105 case WM8962_ADCR_RETUNE_C8_0: 1106 case WM8962_ADCR_RETUNE_C9_1: 1107 case WM8962_ADCR_RETUNE_C9_0: 1108 case WM8962_ADCR_RETUNE_C10_1: 1109 case WM8962_ADCR_RETUNE_C10_0: 1110 case WM8962_ADCR_RETUNE_C11_1: 1111 case WM8962_ADCR_RETUNE_C11_0: 1112 case WM8962_ADCR_RETUNE_C12_1: 1113 case WM8962_ADCR_RETUNE_C12_0: 1114 case WM8962_ADCR_RETUNE_C13_1: 1115 case WM8962_ADCR_RETUNE_C13_0: 1116 case WM8962_ADCR_RETUNE_C14_1: 1117 case WM8962_ADCR_RETUNE_C14_0: 1118 case WM8962_ADCR_RETUNE_C15_1: 1119 case WM8962_ADCR_RETUNE_C15_0: 1120 case WM8962_ADCR_RETUNE_C16_1: 1121 case WM8962_ADCR_RETUNE_C16_0: 1122 case WM8962_ADCR_RETUNE_C17_1: 1123 case WM8962_ADCR_RETUNE_C17_0: 1124 case WM8962_ADCR_RETUNE_C18_1: 1125 case WM8962_ADCR_RETUNE_C18_0: 1126 case WM8962_ADCR_RETUNE_C19_1: 1127 case WM8962_ADCR_RETUNE_C19_0: 1128 case WM8962_ADCR_RETUNE_C20_1: 1129 case WM8962_ADCR_RETUNE_C20_0: 1130 case WM8962_ADCR_RETUNE_C21_1: 1131 case WM8962_ADCR_RETUNE_C21_0: 1132 case WM8962_ADCR_RETUNE_C22_1: 1133 case WM8962_ADCR_RETUNE_C22_0: 1134 case WM8962_ADCR_RETUNE_C23_1: 1135 case WM8962_ADCR_RETUNE_C23_0: 1136 case WM8962_ADCR_RETUNE_C24_1: 1137 case WM8962_ADCR_RETUNE_C24_0: 1138 case WM8962_ADCR_RETUNE_C25_1: 1139 case WM8962_ADCR_RETUNE_C25_0: 1140 case WM8962_ADCR_RETUNE_C26_1: 1141 case WM8962_ADCR_RETUNE_C26_0: 1142 case WM8962_ADCR_RETUNE_C27_1: 1143 case WM8962_ADCR_RETUNE_C27_0: 1144 case WM8962_ADCR_RETUNE_C28_1: 1145 case WM8962_ADCR_RETUNE_C28_0: 1146 case WM8962_ADCR_RETUNE_C29_1: 1147 case WM8962_ADCR_RETUNE_C29_0: 1148 case WM8962_ADCR_RETUNE_C30_1: 1149 case WM8962_ADCR_RETUNE_C30_0: 1150 case WM8962_ADCR_RETUNE_C31_1: 1151 case WM8962_ADCR_RETUNE_C31_0: 1152 case WM8962_ADCR_RETUNE_C32_1: 1153 case WM8962_ADCR_RETUNE_C32_0: 1154 case WM8962_DACL_RETUNE_C1_1: 1155 case WM8962_DACL_RETUNE_C1_0: 1156 case WM8962_DACL_RETUNE_C2_1: 1157 case WM8962_DACL_RETUNE_C2_0: 1158 case WM8962_DACL_RETUNE_C3_1: 1159 case WM8962_DACL_RETUNE_C3_0: 1160 case WM8962_DACL_RETUNE_C4_1: 1161 case WM8962_DACL_RETUNE_C4_0: 1162 case WM8962_DACL_RETUNE_C5_1: 1163 case WM8962_DACL_RETUNE_C5_0: 1164 case WM8962_DACL_RETUNE_C6_1: 1165 case WM8962_DACL_RETUNE_C6_0: 1166 case WM8962_DACL_RETUNE_C7_1: 1167 case WM8962_DACL_RETUNE_C7_0: 1168 case WM8962_DACL_RETUNE_C8_1: 1169 case WM8962_DACL_RETUNE_C8_0: 1170 case WM8962_DACL_RETUNE_C9_1: 1171 case WM8962_DACL_RETUNE_C9_0: 1172 case WM8962_DACL_RETUNE_C10_1: 1173 case WM8962_DACL_RETUNE_C10_0: 1174 case WM8962_DACL_RETUNE_C11_1: 1175 case WM8962_DACL_RETUNE_C11_0: 1176 case WM8962_DACL_RETUNE_C12_1: 1177 case WM8962_DACL_RETUNE_C12_0: 1178 case WM8962_DACL_RETUNE_C13_1: 1179 case WM8962_DACL_RETUNE_C13_0: 1180 case WM8962_DACL_RETUNE_C14_1: 1181 case WM8962_DACL_RETUNE_C14_0: 1182 case WM8962_DACL_RETUNE_C15_1: 1183 case WM8962_DACL_RETUNE_C15_0: 1184 case WM8962_DACL_RETUNE_C16_1: 1185 case WM8962_DACL_RETUNE_C16_0: 1186 case WM8962_DACL_RETUNE_C17_1: 1187 case WM8962_DACL_RETUNE_C17_0: 1188 case WM8962_DACL_RETUNE_C18_1: 1189 case WM8962_DACL_RETUNE_C18_0: 1190 case WM8962_DACL_RETUNE_C19_1: 1191 case WM8962_DACL_RETUNE_C19_0: 1192 case WM8962_DACL_RETUNE_C20_1: 1193 case WM8962_DACL_RETUNE_C20_0: 1194 case WM8962_DACL_RETUNE_C21_1: 1195 case WM8962_DACL_RETUNE_C21_0: 1196 case WM8962_DACL_RETUNE_C22_1: 1197 case WM8962_DACL_RETUNE_C22_0: 1198 case WM8962_DACL_RETUNE_C23_1: 1199 case WM8962_DACL_RETUNE_C23_0: 1200 case WM8962_DACL_RETUNE_C24_1: 1201 case WM8962_DACL_RETUNE_C24_0: 1202 case WM8962_DACL_RETUNE_C25_1: 1203 case WM8962_DACL_RETUNE_C25_0: 1204 case WM8962_DACL_RETUNE_C26_1: 1205 case WM8962_DACL_RETUNE_C26_0: 1206 case WM8962_DACL_RETUNE_C27_1: 1207 case WM8962_DACL_RETUNE_C27_0: 1208 case WM8962_DACL_RETUNE_C28_1: 1209 case WM8962_DACL_RETUNE_C28_0: 1210 case WM8962_DACL_RETUNE_C29_1: 1211 case WM8962_DACL_RETUNE_C29_0: 1212 case WM8962_DACL_RETUNE_C30_1: 1213 case WM8962_DACL_RETUNE_C30_0: 1214 case WM8962_DACL_RETUNE_C31_1: 1215 case WM8962_DACL_RETUNE_C31_0: 1216 case WM8962_DACL_RETUNE_C32_1: 1217 case WM8962_DACL_RETUNE_C32_0: 1218 case WM8962_RETUNEDAC_PG2_1: 1219 case WM8962_RETUNEDAC_PG2_0: 1220 case WM8962_RETUNEDAC_PG_1: 1221 case WM8962_RETUNEDAC_PG_0: 1222 case WM8962_DACR_RETUNE_C1_1: 1223 case WM8962_DACR_RETUNE_C1_0: 1224 case WM8962_DACR_RETUNE_C2_1: 1225 case WM8962_DACR_RETUNE_C2_0: 1226 case WM8962_DACR_RETUNE_C3_1: 1227 case WM8962_DACR_RETUNE_C3_0: 1228 case WM8962_DACR_RETUNE_C4_1: 1229 case WM8962_DACR_RETUNE_C4_0: 1230 case WM8962_DACR_RETUNE_C5_1: 1231 case WM8962_DACR_RETUNE_C5_0: 1232 case WM8962_DACR_RETUNE_C6_1: 1233 case WM8962_DACR_RETUNE_C6_0: 1234 case WM8962_DACR_RETUNE_C7_1: 1235 case WM8962_DACR_RETUNE_C7_0: 1236 case WM8962_DACR_RETUNE_C8_1: 1237 case WM8962_DACR_RETUNE_C8_0: 1238 case WM8962_DACR_RETUNE_C9_1: 1239 case WM8962_DACR_RETUNE_C9_0: 1240 case WM8962_DACR_RETUNE_C10_1: 1241 case WM8962_DACR_RETUNE_C10_0: 1242 case WM8962_DACR_RETUNE_C11_1: 1243 case WM8962_DACR_RETUNE_C11_0: 1244 case WM8962_DACR_RETUNE_C12_1: 1245 case WM8962_DACR_RETUNE_C12_0: 1246 case WM8962_DACR_RETUNE_C13_1: 1247 case WM8962_DACR_RETUNE_C13_0: 1248 case WM8962_DACR_RETUNE_C14_1: 1249 case WM8962_DACR_RETUNE_C14_0: 1250 case WM8962_DACR_RETUNE_C15_1: 1251 case WM8962_DACR_RETUNE_C15_0: 1252 case WM8962_DACR_RETUNE_C16_1: 1253 case WM8962_DACR_RETUNE_C16_0: 1254 case WM8962_DACR_RETUNE_C17_1: 1255 case WM8962_DACR_RETUNE_C17_0: 1256 case WM8962_DACR_RETUNE_C18_1: 1257 case WM8962_DACR_RETUNE_C18_0: 1258 case WM8962_DACR_RETUNE_C19_1: 1259 case WM8962_DACR_RETUNE_C19_0: 1260 case WM8962_DACR_RETUNE_C20_1: 1261 case WM8962_DACR_RETUNE_C20_0: 1262 case WM8962_DACR_RETUNE_C21_1: 1263 case WM8962_DACR_RETUNE_C21_0: 1264 case WM8962_DACR_RETUNE_C22_1: 1265 case WM8962_DACR_RETUNE_C22_0: 1266 case WM8962_DACR_RETUNE_C23_1: 1267 case WM8962_DACR_RETUNE_C23_0: 1268 case WM8962_DACR_RETUNE_C24_1: 1269 case WM8962_DACR_RETUNE_C24_0: 1270 case WM8962_DACR_RETUNE_C25_1: 1271 case WM8962_DACR_RETUNE_C25_0: 1272 case WM8962_DACR_RETUNE_C26_1: 1273 case WM8962_DACR_RETUNE_C26_0: 1274 case WM8962_DACR_RETUNE_C27_1: 1275 case WM8962_DACR_RETUNE_C27_0: 1276 case WM8962_DACR_RETUNE_C28_1: 1277 case WM8962_DACR_RETUNE_C28_0: 1278 case WM8962_DACR_RETUNE_C29_1: 1279 case WM8962_DACR_RETUNE_C29_0: 1280 case WM8962_DACR_RETUNE_C30_1: 1281 case WM8962_DACR_RETUNE_C30_0: 1282 case WM8962_DACR_RETUNE_C31_1: 1283 case WM8962_DACR_RETUNE_C31_0: 1284 case WM8962_DACR_RETUNE_C32_1: 1285 case WM8962_DACR_RETUNE_C32_0: 1286 case WM8962_VSS_XHD2_1: 1287 case WM8962_VSS_XHD2_0: 1288 case WM8962_VSS_XHD3_1: 1289 case WM8962_VSS_XHD3_0: 1290 case WM8962_VSS_XHN1_1: 1291 case WM8962_VSS_XHN1_0: 1292 case WM8962_VSS_XHN2_1: 1293 case WM8962_VSS_XHN2_0: 1294 case WM8962_VSS_XHN3_1: 1295 case WM8962_VSS_XHN3_0: 1296 case WM8962_VSS_XLA_1: 1297 case WM8962_VSS_XLA_0: 1298 case WM8962_VSS_XLB_1: 1299 case WM8962_VSS_XLB_0: 1300 case WM8962_VSS_XLG_1: 1301 case WM8962_VSS_XLG_0: 1302 case WM8962_VSS_PG2_1: 1303 case WM8962_VSS_PG2_0: 1304 case WM8962_VSS_PG_1: 1305 case WM8962_VSS_PG_0: 1306 case WM8962_VSS_XTD1_1: 1307 case WM8962_VSS_XTD1_0: 1308 case WM8962_VSS_XTD2_1: 1309 case WM8962_VSS_XTD2_0: 1310 case WM8962_VSS_XTD3_1: 1311 case WM8962_VSS_XTD3_0: 1312 case WM8962_VSS_XTD4_1: 1313 case WM8962_VSS_XTD4_0: 1314 case WM8962_VSS_XTD5_1: 1315 case WM8962_VSS_XTD5_0: 1316 case WM8962_VSS_XTD6_1: 1317 case WM8962_VSS_XTD6_0: 1318 case WM8962_VSS_XTD7_1: 1319 case WM8962_VSS_XTD7_0: 1320 case WM8962_VSS_XTD8_1: 1321 case WM8962_VSS_XTD8_0: 1322 case WM8962_VSS_XTD9_1: 1323 case WM8962_VSS_XTD9_0: 1324 case WM8962_VSS_XTD10_1: 1325 case WM8962_VSS_XTD10_0: 1326 case WM8962_VSS_XTD11_1: 1327 case WM8962_VSS_XTD11_0: 1328 case WM8962_VSS_XTD12_1: 1329 case WM8962_VSS_XTD12_0: 1330 case WM8962_VSS_XTD13_1: 1331 case WM8962_VSS_XTD13_0: 1332 case WM8962_VSS_XTD14_1: 1333 case WM8962_VSS_XTD14_0: 1334 case WM8962_VSS_XTD15_1: 1335 case WM8962_VSS_XTD15_0: 1336 case WM8962_VSS_XTD16_1: 1337 case WM8962_VSS_XTD16_0: 1338 case WM8962_VSS_XTD17_1: 1339 case WM8962_VSS_XTD17_0: 1340 case WM8962_VSS_XTD18_1: 1341 case WM8962_VSS_XTD18_0: 1342 case WM8962_VSS_XTD19_1: 1343 case WM8962_VSS_XTD19_0: 1344 case WM8962_VSS_XTD20_1: 1345 case WM8962_VSS_XTD20_0: 1346 case WM8962_VSS_XTD21_1: 1347 case WM8962_VSS_XTD21_0: 1348 case WM8962_VSS_XTD22_1: 1349 case WM8962_VSS_XTD22_0: 1350 case WM8962_VSS_XTD23_1: 1351 case WM8962_VSS_XTD23_0: 1352 case WM8962_VSS_XTD24_1: 1353 case WM8962_VSS_XTD24_0: 1354 case WM8962_VSS_XTD25_1: 1355 case WM8962_VSS_XTD25_0: 1356 case WM8962_VSS_XTD26_1: 1357 case WM8962_VSS_XTD26_0: 1358 case WM8962_VSS_XTD27_1: 1359 case WM8962_VSS_XTD27_0: 1360 case WM8962_VSS_XTD28_1: 1361 case WM8962_VSS_XTD28_0: 1362 case WM8962_VSS_XTD29_1: 1363 case WM8962_VSS_XTD29_0: 1364 case WM8962_VSS_XTD30_1: 1365 case WM8962_VSS_XTD30_0: 1366 case WM8962_VSS_XTD31_1: 1367 case WM8962_VSS_XTD31_0: 1368 case WM8962_VSS_XTD32_1: 1369 case WM8962_VSS_XTD32_0: 1370 case WM8962_VSS_XTS1_1: 1371 case WM8962_VSS_XTS1_0: 1372 case WM8962_VSS_XTS2_1: 1373 case WM8962_VSS_XTS2_0: 1374 case WM8962_VSS_XTS3_1: 1375 case WM8962_VSS_XTS3_0: 1376 case WM8962_VSS_XTS4_1: 1377 case WM8962_VSS_XTS4_0: 1378 case WM8962_VSS_XTS5_1: 1379 case WM8962_VSS_XTS5_0: 1380 case WM8962_VSS_XTS6_1: 1381 case WM8962_VSS_XTS6_0: 1382 case WM8962_VSS_XTS7_1: 1383 case WM8962_VSS_XTS7_0: 1384 case WM8962_VSS_XTS8_1: 1385 case WM8962_VSS_XTS8_0: 1386 case WM8962_VSS_XTS9_1: 1387 case WM8962_VSS_XTS9_0: 1388 case WM8962_VSS_XTS10_1: 1389 case WM8962_VSS_XTS10_0: 1390 case WM8962_VSS_XTS11_1: 1391 case WM8962_VSS_XTS11_0: 1392 case WM8962_VSS_XTS12_1: 1393 case WM8962_VSS_XTS12_0: 1394 case WM8962_VSS_XTS13_1: 1395 case WM8962_VSS_XTS13_0: 1396 case WM8962_VSS_XTS14_1: 1397 case WM8962_VSS_XTS14_0: 1398 case WM8962_VSS_XTS15_1: 1399 case WM8962_VSS_XTS15_0: 1400 case WM8962_VSS_XTS16_1: 1401 case WM8962_VSS_XTS16_0: 1402 case WM8962_VSS_XTS17_1: 1403 case WM8962_VSS_XTS17_0: 1404 case WM8962_VSS_XTS18_1: 1405 case WM8962_VSS_XTS18_0: 1406 case WM8962_VSS_XTS19_1: 1407 case WM8962_VSS_XTS19_0: 1408 case WM8962_VSS_XTS20_1: 1409 case WM8962_VSS_XTS20_0: 1410 case WM8962_VSS_XTS21_1: 1411 case WM8962_VSS_XTS21_0: 1412 case WM8962_VSS_XTS22_1: 1413 case WM8962_VSS_XTS22_0: 1414 case WM8962_VSS_XTS23_1: 1415 case WM8962_VSS_XTS23_0: 1416 case WM8962_VSS_XTS24_1: 1417 case WM8962_VSS_XTS24_0: 1418 case WM8962_VSS_XTS25_1: 1419 case WM8962_VSS_XTS25_0: 1420 case WM8962_VSS_XTS26_1: 1421 case WM8962_VSS_XTS26_0: 1422 case WM8962_VSS_XTS27_1: 1423 case WM8962_VSS_XTS27_0: 1424 case WM8962_VSS_XTS28_1: 1425 case WM8962_VSS_XTS28_0: 1426 case WM8962_VSS_XTS29_1: 1427 case WM8962_VSS_XTS29_0: 1428 case WM8962_VSS_XTS30_1: 1429 case WM8962_VSS_XTS30_0: 1430 case WM8962_VSS_XTS31_1: 1431 case WM8962_VSS_XTS31_0: 1432 case WM8962_VSS_XTS32_1: 1433 case WM8962_VSS_XTS32_0: 1434 return true; 1435 default: 1436 return false; 1437 } 1438 } 1439 1440 static int wm8962_reset(struct wm8962_priv *wm8962) 1441 { 1442 int ret; 1443 1444 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243); 1445 if (ret != 0) 1446 return ret; 1447 1448 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0); 1449 } 1450 1451 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); 1452 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0); 1453 static const DECLARE_TLV_DB_RANGE(mixinpga_tlv, 1454 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0), 1455 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0), 1456 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0), 1457 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0), 1458 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0) 1459 ); 1460 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1); 1461 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 1462 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 1463 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0); 1464 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 1465 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); 1466 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0); 1467 static const DECLARE_TLV_DB_RANGE(classd_tlv, 1468 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0), 1469 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0) 1470 ); 1471 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 1472 1473 static int wm8962_dsp2_write_config(struct snd_soc_component *component) 1474 { 1475 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 1476 1477 return regcache_sync_region(wm8962->regmap, 1478 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER); 1479 } 1480 1481 static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val) 1482 { 1483 u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME); 1484 u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME); 1485 u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1); 1486 1487 /* Mute the ADCs and DACs */ 1488 snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0); 1489 snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU); 1490 snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, 1491 WM8962_DAC_MUTE, WM8962_DAC_MUTE); 1492 1493 snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val); 1494 1495 /* Restore the ADCs and DACs */ 1496 snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, adcl); 1497 snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, adcr); 1498 snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, 1499 WM8962_DAC_MUTE, dac); 1500 1501 return 0; 1502 } 1503 1504 static int wm8962_dsp2_start(struct snd_soc_component *component) 1505 { 1506 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 1507 1508 wm8962_dsp2_write_config(component); 1509 1510 snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR); 1511 1512 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena); 1513 1514 return 0; 1515 } 1516 1517 static int wm8962_dsp2_stop(struct snd_soc_component *component) 1518 { 1519 wm8962_dsp2_set_enable(component, 0); 1520 1521 snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP); 1522 1523 return 0; 1524 } 1525 1526 #define WM8962_DSP2_ENABLE(xname, xshift) \ 1527 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1528 .info = wm8962_dsp2_ena_info, \ 1529 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \ 1530 .private_value = xshift } 1531 1532 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol, 1533 struct snd_ctl_elem_info *uinfo) 1534 { 1535 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1536 1537 uinfo->count = 1; 1538 uinfo->value.integer.min = 0; 1539 uinfo->value.integer.max = 1; 1540 1541 return 0; 1542 } 1543 1544 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol, 1545 struct snd_ctl_elem_value *ucontrol) 1546 { 1547 int shift = kcontrol->private_value; 1548 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1549 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 1550 1551 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); 1552 1553 return 0; 1554 } 1555 1556 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol, 1557 struct snd_ctl_elem_value *ucontrol) 1558 { 1559 int shift = kcontrol->private_value; 1560 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1561 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 1562 int old = wm8962->dsp2_ena; 1563 int ret = 0; 1564 int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) & 1565 WM8962_DSP2_ENA; 1566 1567 mutex_lock(&wm8962->dsp2_ena_lock); 1568 1569 if (ucontrol->value.integer.value[0]) 1570 wm8962->dsp2_ena |= 1 << shift; 1571 else 1572 wm8962->dsp2_ena &= ~(1 << shift); 1573 1574 if (wm8962->dsp2_ena == old) 1575 goto out; 1576 1577 ret = 1; 1578 1579 if (dsp2_running) { 1580 if (wm8962->dsp2_ena) 1581 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena); 1582 else 1583 wm8962_dsp2_stop(component); 1584 } 1585 1586 out: 1587 mutex_unlock(&wm8962->dsp2_ena_lock); 1588 1589 return ret; 1590 } 1591 1592 /* The VU bits for the headphones are in a different register to the mute 1593 * bits and only take effect on the PGA if it is actually powered. 1594 */ 1595 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, 1596 struct snd_ctl_elem_value *ucontrol) 1597 { 1598 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1599 int ret; 1600 1601 /* Apply the update (if any) */ 1602 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1603 if (ret == 0) 1604 return 0; 1605 1606 /* If the left PGA is enabled hit that VU bit... */ 1607 ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2); 1608 if (ret & WM8962_HPOUTL_PGA_ENA) { 1609 snd_soc_component_write(component, WM8962_HPOUTL_VOLUME, 1610 snd_soc_component_read(component, WM8962_HPOUTL_VOLUME)); 1611 return 1; 1612 } 1613 1614 /* ...otherwise the right. The VU is stereo. */ 1615 if (ret & WM8962_HPOUTR_PGA_ENA) 1616 snd_soc_component_write(component, WM8962_HPOUTR_VOLUME, 1617 snd_soc_component_read(component, WM8962_HPOUTR_VOLUME)); 1618 1619 return 1; 1620 } 1621 1622 /* The VU bits for the speakers are in a different register to the mute 1623 * bits and only take effect on the PGA if it is actually powered. 1624 */ 1625 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, 1626 struct snd_ctl_elem_value *ucontrol) 1627 { 1628 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1629 int ret; 1630 1631 /* Apply the update (if any) */ 1632 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1633 if (ret == 0) 1634 return 0; 1635 1636 /* If the left PGA is enabled hit that VU bit... */ 1637 ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2); 1638 if (ret & WM8962_SPKOUTL_PGA_ENA) { 1639 snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME, 1640 snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME)); 1641 return 1; 1642 } 1643 1644 /* ...otherwise the right. The VU is stereo. */ 1645 if (ret & WM8962_SPKOUTR_PGA_ENA) 1646 snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME, 1647 snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME)); 1648 1649 return 1; 1650 } 1651 1652 static const char *cap_hpf_mode_text[] = { 1653 "Hi-fi", "Application" 1654 }; 1655 1656 static SOC_ENUM_SINGLE_DECL(cap_hpf_mode, 1657 WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text); 1658 1659 1660 static const char *cap_lhpf_mode_text[] = { 1661 "LPF", "HPF" 1662 }; 1663 1664 static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode, 1665 WM8962_LHPF1, 1, cap_lhpf_mode_text); 1666 1667 static const struct snd_kcontrol_new wm8962_snd_controls[] = { 1668 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1), 1669 1670 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0, 1671 mixin_tlv), 1672 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0, 1673 mixinpga_tlv), 1674 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0, 1675 mixin_tlv), 1676 1677 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0, 1678 mixin_tlv), 1679 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0, 1680 mixinpga_tlv), 1681 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0, 1682 mixin_tlv), 1683 1684 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME, 1685 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv), 1686 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME, 1687 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv), 1688 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME, 1689 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1), 1690 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME, 1691 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1), 1692 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1), 1693 SOC_ENUM("Capture HPF Mode", cap_hpf_mode), 1694 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0), 1695 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0), 1696 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode), 1697 1698 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1, 1699 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv), 1700 1701 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME, 1702 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv), 1703 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0), 1704 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0), 1705 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0), 1706 SOC_SINGLE("DAC Monomix Switch", WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0), 1707 SOC_SINGLE("ADC Monomix Switch", WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0), 1708 1709 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1, 1710 5, 1, 0), 1711 1712 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv), 1713 1714 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME, 1715 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv), 1716 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1, 1717 snd_soc_get_volsw, wm8962_put_hp_sw), 1718 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME, 1719 7, 1, 0), 1720 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0, 1721 hp_tlv), 1722 1723 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3, 1724 WM8962_HEADPHONE_MIXER_4, 8, 1, 1), 1725 1726 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3, 1727 3, 7, 0, bypass_tlv), 1728 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3, 1729 0, 7, 0, bypass_tlv), 1730 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3, 1731 7, 1, 1, inmix_tlv), 1732 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3, 1733 6, 1, 1, inmix_tlv), 1734 1735 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4, 1736 3, 7, 0, bypass_tlv), 1737 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4, 1738 0, 7, 0, bypass_tlv), 1739 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4, 1740 7, 1, 1, inmix_tlv), 1741 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4, 1742 6, 1, 1, inmix_tlv), 1743 1744 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0, 1745 classd_tlv), 1746 1747 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0), 1748 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22, 1749 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv), 1750 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22, 1751 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv), 1752 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22, 1753 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv), 1754 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23, 1755 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv), 1756 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23, 1757 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv), 1758 SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18), 1759 SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18), 1760 1761 1762 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0), 1763 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA), 1764 1765 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0), 1766 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA), 1767 1768 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0), 1769 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA), 1770 1771 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), 1772 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148), 1773 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), 1774 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), 1775 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1), 1776 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT), 1777 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30), 1778 1779 SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT, 1780 WM8962_ALCR_ENA_SHIFT, 1, 0), 1781 SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4, 1782 WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK), 1783 }; 1784 1785 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { 1786 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv), 1787 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1, 1788 snd_soc_get_volsw, wm8962_put_spk_sw), 1789 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0), 1790 1791 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1), 1792 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, 1793 3, 7, 0, bypass_tlv), 1794 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, 1795 0, 7, 0, bypass_tlv), 1796 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, 1797 7, 1, 1, inmix_tlv), 1798 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, 1799 6, 1, 1, inmix_tlv), 1800 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1801 7, 1, 0, inmix_tlv), 1802 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1803 6, 1, 0, inmix_tlv), 1804 }; 1805 1806 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = { 1807 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 1808 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv), 1809 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1, 1810 snd_soc_get_volsw, wm8962_put_spk_sw), 1811 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME, 1812 7, 1, 0), 1813 1814 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 1815 WM8962_SPEAKER_MIXER_4, 8, 1, 1), 1816 1817 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, 1818 3, 7, 0, bypass_tlv), 1819 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, 1820 0, 7, 0, bypass_tlv), 1821 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, 1822 7, 1, 1, inmix_tlv), 1823 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, 1824 6, 1, 1, inmix_tlv), 1825 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1826 7, 1, 0, inmix_tlv), 1827 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1828 6, 1, 0, inmix_tlv), 1829 1830 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4, 1831 3, 7, 0, bypass_tlv), 1832 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4, 1833 0, 7, 0, bypass_tlv), 1834 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4, 1835 7, 1, 1, inmix_tlv), 1836 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4, 1837 6, 1, 1, inmix_tlv), 1838 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1839 5, 1, 0, inmix_tlv), 1840 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1841 4, 1, 0, inmix_tlv), 1842 }; 1843 1844 static int tp_event(struct snd_soc_dapm_widget *w, 1845 struct snd_kcontrol *kcontrol, int event) 1846 { 1847 int ret, reg, val, mask; 1848 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1849 1850 ret = pm_runtime_resume_and_get(component->dev); 1851 if (ret < 0) { 1852 dev_err(component->dev, "Failed to resume device: %d\n", ret); 1853 return ret; 1854 } 1855 1856 reg = WM8962_ADDITIONAL_CONTROL_4; 1857 1858 if (!snd_soc_dapm_widget_name_cmp(w, "TEMP_HP")) { 1859 mask = WM8962_TEMP_ENA_HP_MASK; 1860 val = WM8962_TEMP_ENA_HP; 1861 } else if (!snd_soc_dapm_widget_name_cmp(w, "TEMP_SPK")) { 1862 mask = WM8962_TEMP_ENA_SPK_MASK; 1863 val = WM8962_TEMP_ENA_SPK; 1864 } else { 1865 pm_runtime_put(component->dev); 1866 return -EINVAL; 1867 } 1868 1869 switch (event) { 1870 case SND_SOC_DAPM_POST_PMD: 1871 val = 0; 1872 fallthrough; 1873 case SND_SOC_DAPM_POST_PMU: 1874 ret = snd_soc_component_update_bits(component, reg, mask, val); 1875 break; 1876 default: 1877 WARN(1, "Invalid event %d\n", event); 1878 pm_runtime_put(component->dev); 1879 return -EINVAL; 1880 } 1881 1882 pm_runtime_put(component->dev); 1883 1884 return 0; 1885 } 1886 1887 static int cp_event(struct snd_soc_dapm_widget *w, 1888 struct snd_kcontrol *kcontrol, int event) 1889 { 1890 switch (event) { 1891 case SND_SOC_DAPM_POST_PMU: 1892 msleep(5); 1893 break; 1894 1895 default: 1896 WARN(1, "Invalid event %d\n", event); 1897 return -EINVAL; 1898 } 1899 1900 return 0; 1901 } 1902 1903 static int hp_event(struct snd_soc_dapm_widget *w, 1904 struct snd_kcontrol *kcontrol, int event) 1905 { 1906 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1907 int timeout; 1908 int reg; 1909 int expected = (WM8962_DCS_STARTUP_DONE_HP1L | 1910 WM8962_DCS_STARTUP_DONE_HP1R); 1911 1912 switch (event) { 1913 case SND_SOC_DAPM_POST_PMU: 1914 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1915 WM8962_HP1L_ENA | WM8962_HP1R_ENA, 1916 WM8962_HP1L_ENA | WM8962_HP1R_ENA); 1917 udelay(20); 1918 1919 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1920 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY, 1921 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY); 1922 1923 /* Start the DC servo */ 1924 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1, 1925 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1926 WM8962_HP1L_DCS_STARTUP | 1927 WM8962_HP1R_DCS_STARTUP, 1928 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1929 WM8962_HP1L_DCS_STARTUP | 1930 WM8962_HP1R_DCS_STARTUP); 1931 1932 /* Wait for it to complete, should be well under 100ms */ 1933 timeout = 0; 1934 do { 1935 msleep(1); 1936 reg = snd_soc_component_read(component, WM8962_DC_SERVO_6); 1937 if (reg < 0) { 1938 dev_err(component->dev, 1939 "Failed to read DCS status: %d\n", 1940 reg); 1941 continue; 1942 } 1943 dev_dbg(component->dev, "DCS status: %x\n", reg); 1944 } while (++timeout < 200 && (reg & expected) != expected); 1945 1946 if ((reg & expected) != expected) 1947 dev_err(component->dev, "DC servo timed out\n"); 1948 else 1949 dev_dbg(component->dev, "DC servo complete after %dms\n", 1950 timeout); 1951 1952 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1953 WM8962_HP1L_ENA_OUTP | 1954 WM8962_HP1R_ENA_OUTP, 1955 WM8962_HP1L_ENA_OUTP | 1956 WM8962_HP1R_ENA_OUTP); 1957 udelay(20); 1958 1959 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1960 WM8962_HP1L_RMV_SHORT | 1961 WM8962_HP1R_RMV_SHORT, 1962 WM8962_HP1L_RMV_SHORT | 1963 WM8962_HP1R_RMV_SHORT); 1964 break; 1965 1966 case SND_SOC_DAPM_PRE_PMD: 1967 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1968 WM8962_HP1L_RMV_SHORT | 1969 WM8962_HP1R_RMV_SHORT, 0); 1970 1971 udelay(20); 1972 1973 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1, 1974 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1975 WM8962_HP1L_DCS_STARTUP | 1976 WM8962_HP1R_DCS_STARTUP, 1977 0); 1978 1979 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1980 WM8962_HP1L_ENA | WM8962_HP1R_ENA | 1981 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY | 1982 WM8962_HP1L_ENA_OUTP | 1983 WM8962_HP1R_ENA_OUTP, 0); 1984 1985 break; 1986 1987 default: 1988 WARN(1, "Invalid event %d\n", event); 1989 return -EINVAL; 1990 1991 } 1992 1993 return 0; 1994 } 1995 1996 /* VU bits for the output PGAs only take effect while the PGA is powered */ 1997 static int out_pga_event(struct snd_soc_dapm_widget *w, 1998 struct snd_kcontrol *kcontrol, int event) 1999 { 2000 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2001 int reg; 2002 2003 switch (w->shift) { 2004 case WM8962_HPOUTR_PGA_ENA_SHIFT: 2005 reg = WM8962_HPOUTR_VOLUME; 2006 break; 2007 case WM8962_HPOUTL_PGA_ENA_SHIFT: 2008 reg = WM8962_HPOUTL_VOLUME; 2009 break; 2010 case WM8962_SPKOUTR_PGA_ENA_SHIFT: 2011 reg = WM8962_SPKOUTR_VOLUME; 2012 break; 2013 case WM8962_SPKOUTL_PGA_ENA_SHIFT: 2014 reg = WM8962_SPKOUTL_VOLUME; 2015 break; 2016 default: 2017 WARN(1, "Invalid shift %d\n", w->shift); 2018 return -EINVAL; 2019 } 2020 2021 switch (event) { 2022 case SND_SOC_DAPM_POST_PMU: 2023 return snd_soc_component_write(component, reg, 2024 snd_soc_component_read(component, reg)); 2025 default: 2026 WARN(1, "Invalid event %d\n", event); 2027 return -EINVAL; 2028 } 2029 } 2030 2031 static int dsp2_event(struct snd_soc_dapm_widget *w, 2032 struct snd_kcontrol *kcontrol, int event) 2033 { 2034 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2035 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2036 2037 switch (event) { 2038 case SND_SOC_DAPM_POST_PMU: 2039 if (wm8962->dsp2_ena) 2040 wm8962_dsp2_start(component); 2041 break; 2042 2043 case SND_SOC_DAPM_PRE_PMD: 2044 if (wm8962->dsp2_ena) 2045 wm8962_dsp2_stop(component); 2046 break; 2047 2048 default: 2049 WARN(1, "Invalid event %d\n", event); 2050 return -EINVAL; 2051 } 2052 2053 return 0; 2054 } 2055 2056 static const char *st_text[] = { "None", "Left", "Right" }; 2057 2058 static SOC_ENUM_SINGLE_DECL(str_enum, 2059 WM8962_DAC_DSP_MIXING_1, 2, st_text); 2060 2061 static const struct snd_kcontrol_new str_mux = 2062 SOC_DAPM_ENUM("Right Sidetone", str_enum); 2063 2064 static SOC_ENUM_SINGLE_DECL(stl_enum, 2065 WM8962_DAC_DSP_MIXING_2, 2, st_text); 2066 2067 static const struct snd_kcontrol_new stl_mux = 2068 SOC_DAPM_ENUM("Left Sidetone", stl_enum); 2069 2070 static const char *outmux_text[] = { "DAC", "Mixer" }; 2071 2072 static SOC_ENUM_SINGLE_DECL(spkoutr_enum, 2073 WM8962_SPEAKER_MIXER_2, 7, outmux_text); 2074 2075 static const struct snd_kcontrol_new spkoutr_mux = 2076 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum); 2077 2078 static SOC_ENUM_SINGLE_DECL(spkoutl_enum, 2079 WM8962_SPEAKER_MIXER_1, 7, outmux_text); 2080 2081 static const struct snd_kcontrol_new spkoutl_mux = 2082 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum); 2083 2084 static SOC_ENUM_SINGLE_DECL(hpoutr_enum, 2085 WM8962_HEADPHONE_MIXER_2, 7, outmux_text); 2086 2087 static const struct snd_kcontrol_new hpoutr_mux = 2088 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum); 2089 2090 static SOC_ENUM_SINGLE_DECL(hpoutl_enum, 2091 WM8962_HEADPHONE_MIXER_1, 7, outmux_text); 2092 2093 static const struct snd_kcontrol_new hpoutl_mux = 2094 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum); 2095 2096 static const char * const input_mode_text[] = { "Analog", "Digital" }; 2097 2098 static SOC_ENUM_SINGLE_VIRT_DECL(input_mode_enum, input_mode_text); 2099 2100 static const struct snd_kcontrol_new input_mode_mux = 2101 SOC_DAPM_ENUM("Input Mode", input_mode_enum); 2102 2103 static const struct snd_kcontrol_new inpgal[] = { 2104 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0), 2105 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0), 2106 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0), 2107 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0), 2108 }; 2109 2110 static const struct snd_kcontrol_new inpgar[] = { 2111 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0), 2112 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0), 2113 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0), 2114 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0), 2115 }; 2116 2117 static const struct snd_kcontrol_new mixinl[] = { 2118 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0), 2119 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0), 2120 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0), 2121 }; 2122 2123 static const struct snd_kcontrol_new mixinr[] = { 2124 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0), 2125 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0), 2126 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0), 2127 }; 2128 2129 static const struct snd_kcontrol_new hpmixl[] = { 2130 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0), 2131 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0), 2132 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0), 2133 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0), 2134 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0), 2135 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0), 2136 }; 2137 2138 static const struct snd_kcontrol_new hpmixr[] = { 2139 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0), 2140 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0), 2141 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0), 2142 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0), 2143 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0), 2144 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0), 2145 }; 2146 2147 static const struct snd_kcontrol_new spkmixl[] = { 2148 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0), 2149 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0), 2150 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0), 2151 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0), 2152 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0), 2153 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0), 2154 }; 2155 2156 static const struct snd_kcontrol_new spkmixr[] = { 2157 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0), 2158 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0), 2159 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0), 2160 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0), 2161 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0), 2162 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0), 2163 }; 2164 2165 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = { 2166 SND_SOC_DAPM_INPUT("IN1L"), 2167 SND_SOC_DAPM_INPUT("IN1R"), 2168 SND_SOC_DAPM_INPUT("IN2L"), 2169 SND_SOC_DAPM_INPUT("IN2R"), 2170 SND_SOC_DAPM_INPUT("IN3L"), 2171 SND_SOC_DAPM_INPUT("IN3R"), 2172 SND_SOC_DAPM_INPUT("IN4L"), 2173 SND_SOC_DAPM_INPUT("IN4R"), 2174 SND_SOC_DAPM_SIGGEN("Beep"), 2175 SND_SOC_DAPM_INPUT("DMICDAT"), 2176 2177 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0), 2178 2179 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0), 2180 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0), 2181 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event, 2182 SND_SOC_DAPM_POST_PMU), 2183 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0), 2184 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT, 2185 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event, 2186 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2187 SND_SOC_DAPM_SUPPLY("TEMP_HP", SND_SOC_NOPM, 0, 0, tp_event, 2188 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 2189 SND_SOC_DAPM_SUPPLY("TEMP_SPK", SND_SOC_NOPM, 0, 0, tp_event, 2190 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 2191 2192 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0, 2193 inpgal, ARRAY_SIZE(inpgal)), 2194 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0, 2195 inpgar, ARRAY_SIZE(inpgar)), 2196 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0, 2197 mixinl, ARRAY_SIZE(mixinl)), 2198 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0, 2199 mixinr, ARRAY_SIZE(mixinr)), 2200 2201 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0), 2202 2203 SND_SOC_DAPM_MUX("Input Mode L", SND_SOC_NOPM, 0, 0, &input_mode_mux), 2204 SND_SOC_DAPM_MUX("Input Mode R", SND_SOC_NOPM, 0, 0, &input_mode_mux), 2205 2206 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0), 2207 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0), 2208 2209 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux), 2210 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux), 2211 2212 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0), 2213 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0), 2214 2215 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 2216 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 2217 2218 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0, 2219 hpmixl, ARRAY_SIZE(hpmixl)), 2220 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0, 2221 hpmixr, ARRAY_SIZE(hpmixr)), 2222 2223 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux, 2224 out_pga_event, SND_SOC_DAPM_POST_PMU), 2225 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux, 2226 out_pga_event, SND_SOC_DAPM_POST_PMU), 2227 2228 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event, 2229 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2230 2231 SND_SOC_DAPM_OUTPUT("HPOUTL"), 2232 SND_SOC_DAPM_OUTPUT("HPOUTR"), 2233 2234 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), 2235 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), 2236 }; 2237 2238 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = { 2239 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0, 2240 spkmixl, ARRAY_SIZE(spkmixl)), 2241 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, 2242 out_pga_event, SND_SOC_DAPM_POST_PMU), 2243 SND_SOC_DAPM_OUTPUT("SPKOUT"), 2244 }; 2245 2246 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = { 2247 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0, 2248 spkmixl, ARRAY_SIZE(spkmixl)), 2249 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0, 2250 spkmixr, ARRAY_SIZE(spkmixr)), 2251 2252 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, 2253 out_pga_event, SND_SOC_DAPM_POST_PMU), 2254 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux, 2255 out_pga_event, SND_SOC_DAPM_POST_PMU), 2256 2257 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 2258 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 2259 }; 2260 2261 static const struct snd_soc_dapm_route wm8962_intercon[] = { 2262 { "INPGAL", "IN1L Switch", "IN1L" }, 2263 { "INPGAL", "IN2L Switch", "IN2L" }, 2264 { "INPGAL", "IN3L Switch", "IN3L" }, 2265 { "INPGAL", "IN4L Switch", "IN4L" }, 2266 2267 { "INPGAR", "IN1R Switch", "IN1R" }, 2268 { "INPGAR", "IN2R Switch", "IN2R" }, 2269 { "INPGAR", "IN3R Switch", "IN3R" }, 2270 { "INPGAR", "IN4R Switch", "IN4R" }, 2271 2272 { "MIXINL", "IN2L Switch", "IN2L" }, 2273 { "MIXINL", "IN3L Switch", "IN3L" }, 2274 { "MIXINL", "PGA Switch", "INPGAL" }, 2275 2276 { "MIXINR", "IN2R Switch", "IN2R" }, 2277 { "MIXINR", "IN3R Switch", "IN3R" }, 2278 { "MIXINR", "PGA Switch", "INPGAR" }, 2279 2280 { "MICBIAS", NULL, "SYSCLK" }, 2281 2282 { "DMIC_ENA", NULL, "DMICDAT" }, 2283 2284 { "Input Mode L", "Analog", "MIXINL" }, 2285 { "Input Mode L", "Digital", "DMIC_ENA" }, 2286 { "Input Mode R", "Analog", "MIXINR" }, 2287 { "Input Mode R", "Digital", "DMIC_ENA" }, 2288 2289 { "ADCL", NULL, "SYSCLK" }, 2290 { "ADCL", NULL, "TOCLK" }, 2291 { "ADCL", NULL, "Input Mode L" }, 2292 { "ADCL", NULL, "DSP2" }, 2293 2294 { "ADCR", NULL, "SYSCLK" }, 2295 { "ADCR", NULL, "TOCLK" }, 2296 { "ADCR", NULL, "Input Mode R" }, 2297 { "ADCR", NULL, "DSP2" }, 2298 2299 { "STL", "Left", "ADCL" }, 2300 { "STL", "Right", "ADCR" }, 2301 { "STL", NULL, "Class G" }, 2302 2303 { "STR", "Left", "ADCL" }, 2304 { "STR", "Right", "ADCR" }, 2305 { "STR", NULL, "Class G" }, 2306 2307 { "DACL", NULL, "SYSCLK" }, 2308 { "DACL", NULL, "TOCLK" }, 2309 { "DACL", NULL, "Beep" }, 2310 { "DACL", NULL, "STL" }, 2311 { "DACL", NULL, "DSP2" }, 2312 2313 { "DACR", NULL, "SYSCLK" }, 2314 { "DACR", NULL, "TOCLK" }, 2315 { "DACR", NULL, "Beep" }, 2316 { "DACR", NULL, "STR" }, 2317 { "DACR", NULL, "DSP2" }, 2318 2319 { "HPMIXL", "IN4L Switch", "IN4L" }, 2320 { "HPMIXL", "IN4R Switch", "IN4R" }, 2321 { "HPMIXL", "DACL Switch", "DACL" }, 2322 { "HPMIXL", "DACR Switch", "DACR" }, 2323 { "HPMIXL", "MIXINL Switch", "MIXINL" }, 2324 { "HPMIXL", "MIXINR Switch", "MIXINR" }, 2325 2326 { "HPMIXR", "IN4L Switch", "IN4L" }, 2327 { "HPMIXR", "IN4R Switch", "IN4R" }, 2328 { "HPMIXR", "DACL Switch", "DACL" }, 2329 { "HPMIXR", "DACR Switch", "DACR" }, 2330 { "HPMIXR", "MIXINL Switch", "MIXINL" }, 2331 { "HPMIXR", "MIXINR Switch", "MIXINR" }, 2332 2333 { "Left Bypass", NULL, "HPMIXL" }, 2334 { "Left Bypass", NULL, "Class G" }, 2335 2336 { "Right Bypass", NULL, "HPMIXR" }, 2337 { "Right Bypass", NULL, "Class G" }, 2338 2339 { "HPOUTL PGA", "Mixer", "Left Bypass" }, 2340 { "HPOUTL PGA", "DAC", "DACL" }, 2341 2342 { "HPOUTR PGA", "Mixer", "Right Bypass" }, 2343 { "HPOUTR PGA", "DAC", "DACR" }, 2344 2345 { "HPOUT", NULL, "HPOUTL PGA" }, 2346 { "HPOUT", NULL, "HPOUTR PGA" }, 2347 { "HPOUT", NULL, "Charge Pump" }, 2348 { "HPOUT", NULL, "SYSCLK" }, 2349 { "HPOUT", NULL, "TOCLK" }, 2350 2351 { "HPOUTL", NULL, "HPOUT" }, 2352 { "HPOUTR", NULL, "HPOUT" }, 2353 2354 { "HPOUTL", NULL, "TEMP_HP" }, 2355 { "HPOUTR", NULL, "TEMP_HP" }, 2356 }; 2357 2358 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = { 2359 { "Speaker Mixer", "IN4L Switch", "IN4L" }, 2360 { "Speaker Mixer", "IN4R Switch", "IN4R" }, 2361 { "Speaker Mixer", "DACL Switch", "DACL" }, 2362 { "Speaker Mixer", "DACR Switch", "DACR" }, 2363 { "Speaker Mixer", "MIXINL Switch", "MIXINL" }, 2364 { "Speaker Mixer", "MIXINR Switch", "MIXINR" }, 2365 2366 { "Speaker PGA", "Mixer", "Speaker Mixer" }, 2367 { "Speaker PGA", "DAC", "DACL" }, 2368 2369 { "SPKOUTL Output", NULL, "Speaker PGA" }, 2370 { "SPKOUTL Output", NULL, "SYSCLK" }, 2371 { "SPKOUTL Output", NULL, "TOCLK" }, 2372 { "SPKOUTL Output", NULL, "TEMP_SPK" }, 2373 2374 { "SPKOUTR Output", NULL, "Speaker PGA" }, 2375 { "SPKOUTR Output", NULL, "SYSCLK" }, 2376 { "SPKOUTR Output", NULL, "TOCLK" }, 2377 { "SPKOUTR Output", NULL, "TEMP_SPK" }, 2378 2379 { "SPKOUT", NULL, "SPKOUTL Output" }, 2380 { "SPKOUT", NULL, "SPKOUTR Output" }, 2381 }; 2382 2383 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { 2384 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" }, 2385 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" }, 2386 { "SPKOUTL Mixer", "DACL Switch", "DACL" }, 2387 { "SPKOUTL Mixer", "DACR Switch", "DACR" }, 2388 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" }, 2389 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" }, 2390 2391 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" }, 2392 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" }, 2393 { "SPKOUTR Mixer", "DACL Switch", "DACL" }, 2394 { "SPKOUTR Mixer", "DACR Switch", "DACR" }, 2395 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" }, 2396 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" }, 2397 2398 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" }, 2399 { "SPKOUTL PGA", "DAC", "DACL" }, 2400 2401 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" }, 2402 { "SPKOUTR PGA", "DAC", "DACR" }, 2403 2404 { "SPKOUTL Output", NULL, "SPKOUTL PGA" }, 2405 { "SPKOUTL Output", NULL, "SYSCLK" }, 2406 { "SPKOUTL Output", NULL, "TOCLK" }, 2407 { "SPKOUTL Output", NULL, "TEMP_SPK" }, 2408 2409 { "SPKOUTR Output", NULL, "SPKOUTR PGA" }, 2410 { "SPKOUTR Output", NULL, "SYSCLK" }, 2411 { "SPKOUTR Output", NULL, "TOCLK" }, 2412 { "SPKOUTR Output", NULL, "TEMP_SPK" }, 2413 2414 { "SPKOUTL", NULL, "SPKOUTL Output" }, 2415 { "SPKOUTR", NULL, "SPKOUTR Output" }, 2416 }; 2417 2418 static int wm8962_add_widgets(struct snd_soc_component *component) 2419 { 2420 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2421 struct wm8962_pdata *pdata = &wm8962->pdata; 2422 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2423 2424 snd_soc_add_component_controls(component, wm8962_snd_controls, 2425 ARRAY_SIZE(wm8962_snd_controls)); 2426 if (pdata->spk_mono) 2427 snd_soc_add_component_controls(component, wm8962_spk_mono_controls, 2428 ARRAY_SIZE(wm8962_spk_mono_controls)); 2429 else 2430 snd_soc_add_component_controls(component, wm8962_spk_stereo_controls, 2431 ARRAY_SIZE(wm8962_spk_stereo_controls)); 2432 2433 2434 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets, 2435 ARRAY_SIZE(wm8962_dapm_widgets)); 2436 if (pdata->spk_mono) 2437 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets, 2438 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); 2439 else 2440 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets, 2441 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); 2442 2443 snd_soc_dapm_add_routes(dapm, wm8962_intercon, 2444 ARRAY_SIZE(wm8962_intercon)); 2445 if (pdata->spk_mono) 2446 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon, 2447 ARRAY_SIZE(wm8962_spk_mono_intercon)); 2448 else 2449 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon, 2450 ARRAY_SIZE(wm8962_spk_stereo_intercon)); 2451 2452 2453 snd_soc_dapm_disable_pin(dapm, "Beep"); 2454 2455 return 0; 2456 } 2457 2458 /* -1 for reserved values */ 2459 static const int bclk_divs[] = { 2460 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32 2461 }; 2462 2463 static const int sysclk_rates[] = { 2464 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144 2465 }; 2466 2467 static void wm8962_configure_bclk(struct snd_soc_component *component) 2468 { 2469 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2470 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2471 int best, min_diff, diff; 2472 int dspclk, i; 2473 int clocking2 = 0; 2474 int clocking4 = 0; 2475 int aif2 = 0; 2476 2477 if (!wm8962->sysclk_rate) { 2478 dev_dbg(component->dev, "No SYSCLK configured\n"); 2479 return; 2480 } 2481 2482 if (!wm8962->bclk || !wm8962->lrclk) { 2483 dev_dbg(component->dev, "No audio clocks configured\n"); 2484 return; 2485 } 2486 2487 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) { 2488 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) { 2489 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT; 2490 break; 2491 } 2492 } 2493 2494 if (i == ARRAY_SIZE(sysclk_rates)) { 2495 dev_err(component->dev, "Unsupported sysclk ratio %d\n", 2496 wm8962->sysclk_rate / wm8962->lrclk); 2497 return; 2498 } 2499 2500 dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]); 2501 2502 snd_soc_component_update_bits(component, WM8962_CLOCKING_4, 2503 WM8962_SYSCLK_RATE_MASK, clocking4); 2504 2505 /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK. 2506 * So we here provisionally enable it and then disable it afterward 2507 * if current bias_level hasn't reached SND_SOC_BIAS_ON. 2508 */ 2509 if (snd_soc_dapm_get_bias_level(dapm) != SND_SOC_BIAS_ON) 2510 snd_soc_component_update_bits(component, WM8962_CLOCKING2, 2511 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA); 2512 2513 /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate 2514 * correct frequency of LRCLK and BCLK. Sometimes the read-only value 2515 * can't be updated timely after enabling SYSCLK. This results in wrong 2516 * calculation values. Delay is introduced here to wait for newest 2517 * value from register. The time of the delay should be at least 2518 * 500~1000us according to test. 2519 */ 2520 usleep_range(500, 1000); 2521 dspclk = snd_soc_component_read(component, WM8962_CLOCKING1); 2522 2523 if (snd_soc_dapm_get_bias_level(dapm) != SND_SOC_BIAS_ON) 2524 snd_soc_component_update_bits(component, WM8962_CLOCKING2, 2525 WM8962_SYSCLK_ENA_MASK, 0); 2526 2527 if (dspclk < 0) { 2528 dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk); 2529 return; 2530 } 2531 2532 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT; 2533 switch (dspclk) { 2534 case 0: 2535 dspclk = wm8962->sysclk_rate; 2536 break; 2537 case 1: 2538 dspclk = wm8962->sysclk_rate / 2; 2539 break; 2540 case 2: 2541 dspclk = wm8962->sysclk_rate / 4; 2542 break; 2543 default: 2544 dev_warn(component->dev, "Unknown DSPCLK divisor read back\n"); 2545 dspclk = wm8962->sysclk_rate; 2546 } 2547 2548 dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); 2549 2550 /* Search a proper bclk, not exact match. */ 2551 best = 0; 2552 min_diff = INT_MAX; 2553 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2554 if (bclk_divs[i] < 0) 2555 continue; 2556 2557 diff = (dspclk / bclk_divs[i]) - wm8962->bclk; 2558 if (diff < 0) /* Table is sorted */ 2559 break; 2560 if (diff < min_diff) { 2561 best = i; 2562 min_diff = diff; 2563 } 2564 } 2565 wm8962->bclk = dspclk / bclk_divs[best]; 2566 clocking2 |= best; 2567 dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n", 2568 bclk_divs[best], wm8962->bclk); 2569 2570 aif2 |= wm8962->bclk / wm8962->lrclk; 2571 dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n", 2572 wm8962->bclk / wm8962->lrclk, wm8962->lrclk); 2573 2574 snd_soc_component_update_bits(component, WM8962_CLOCKING2, 2575 WM8962_BCLK_DIV_MASK, clocking2); 2576 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2, 2577 WM8962_AIF_RATE_MASK, aif2); 2578 } 2579 2580 static int wm8962_set_bias_level(struct snd_soc_component *component, 2581 enum snd_soc_bias_level level) 2582 { 2583 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2584 2585 switch (level) { 2586 case SND_SOC_BIAS_ON: 2587 break; 2588 2589 case SND_SOC_BIAS_PREPARE: 2590 /* VMID 2*50k */ 2591 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1, 2592 WM8962_VMID_SEL_MASK, 0x80); 2593 2594 wm8962_configure_bclk(component); 2595 break; 2596 2597 case SND_SOC_BIAS_STANDBY: 2598 /* VMID 2*250k */ 2599 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1, 2600 WM8962_VMID_SEL_MASK, 0x100); 2601 2602 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) 2603 msleep(100); 2604 break; 2605 2606 case SND_SOC_BIAS_OFF: 2607 break; 2608 } 2609 2610 return 0; 2611 } 2612 2613 static const struct { 2614 int rate; 2615 int reg; 2616 } sr_vals[] = { 2617 { 48000, 0 }, 2618 { 44100, 0 }, 2619 { 32000, 1 }, 2620 { 22050, 2 }, 2621 { 24000, 2 }, 2622 { 16000, 3 }, 2623 { 11025, 4 }, 2624 { 12000, 4 }, 2625 { 8000, 5 }, 2626 { 88200, 6 }, 2627 { 96000, 6 }, 2628 }; 2629 2630 static int wm8962_hw_params(struct snd_pcm_substream *substream, 2631 struct snd_pcm_hw_params *params, 2632 struct snd_soc_dai *dai) 2633 { 2634 struct snd_soc_component *component = dai->component; 2635 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2636 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2637 int i; 2638 int aif0 = 0; 2639 int adctl3 = 0; 2640 2641 wm8962->bclk = snd_soc_params_to_bclk(params); 2642 if (params_channels(params) == 1) 2643 wm8962->bclk *= 2; 2644 2645 wm8962->lrclk = params_rate(params); 2646 2647 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) { 2648 if (sr_vals[i].rate == wm8962->lrclk) { 2649 adctl3 |= sr_vals[i].reg; 2650 break; 2651 } 2652 } 2653 if (i == ARRAY_SIZE(sr_vals)) { 2654 dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk); 2655 return -EINVAL; 2656 } 2657 2658 if (wm8962->lrclk % 8000 == 0) 2659 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE; 2660 2661 switch (params_width(params)) { 2662 case 16: 2663 break; 2664 case 20: 2665 aif0 |= 0x4; 2666 break; 2667 case 24: 2668 aif0 |= 0x8; 2669 break; 2670 case 32: 2671 aif0 |= 0xc; 2672 break; 2673 default: 2674 return -EINVAL; 2675 } 2676 2677 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0, 2678 WM8962_WL_MASK, aif0); 2679 snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3, 2680 WM8962_SAMPLE_RATE_INT_MODE | 2681 WM8962_SAMPLE_RATE_MASK, adctl3); 2682 2683 dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n", 2684 wm8962->bclk, wm8962->lrclk); 2685 2686 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_ON) 2687 wm8962_configure_bclk(component); 2688 2689 return 0; 2690 } 2691 2692 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 2693 unsigned int freq, int dir) 2694 { 2695 struct snd_soc_component *component = dai->component; 2696 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2697 int src; 2698 2699 switch (clk_id) { 2700 case WM8962_SYSCLK_MCLK: 2701 wm8962->sysclk = WM8962_SYSCLK_MCLK; 2702 src = 0; 2703 break; 2704 case WM8962_SYSCLK_FLL: 2705 wm8962->sysclk = WM8962_SYSCLK_FLL; 2706 src = 1 << WM8962_SYSCLK_SRC_SHIFT; 2707 break; 2708 default: 2709 return -EINVAL; 2710 } 2711 2712 snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK, 2713 src); 2714 2715 wm8962->sysclk_rate = freq; 2716 2717 return 0; 2718 } 2719 2720 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2721 { 2722 struct snd_soc_component *component = dai->component; 2723 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2724 int aif0 = 0; 2725 2726 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2727 case SND_SOC_DAIFMT_DSP_B: 2728 aif0 |= WM8962_LRCLK_INV | 3; 2729 fallthrough; 2730 case SND_SOC_DAIFMT_DSP_A: 2731 aif0 |= 3; 2732 2733 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2734 case SND_SOC_DAIFMT_NB_NF: 2735 case SND_SOC_DAIFMT_IB_NF: 2736 break; 2737 default: 2738 return -EINVAL; 2739 } 2740 break; 2741 2742 case SND_SOC_DAIFMT_RIGHT_J: 2743 break; 2744 case SND_SOC_DAIFMT_LEFT_J: 2745 aif0 |= 1; 2746 break; 2747 case SND_SOC_DAIFMT_I2S: 2748 aif0 |= 2; 2749 break; 2750 default: 2751 return -EINVAL; 2752 } 2753 2754 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2755 case SND_SOC_DAIFMT_NB_NF: 2756 break; 2757 case SND_SOC_DAIFMT_IB_NF: 2758 aif0 |= WM8962_BCLK_INV; 2759 break; 2760 case SND_SOC_DAIFMT_NB_IF: 2761 aif0 |= WM8962_LRCLK_INV; 2762 break; 2763 case SND_SOC_DAIFMT_IB_IF: 2764 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV; 2765 break; 2766 default: 2767 return -EINVAL; 2768 } 2769 2770 wm8962->master_flag = false; 2771 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2772 case SND_SOC_DAIFMT_CBP_CFP: 2773 aif0 |= WM8962_MSTR; 2774 wm8962->master_flag = true; 2775 break; 2776 case SND_SOC_DAIFMT_CBC_CFC: 2777 break; 2778 default: 2779 return -EINVAL; 2780 } 2781 2782 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0, 2783 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR | 2784 WM8962_LRCLK_INV, aif0); 2785 2786 return 0; 2787 } 2788 2789 struct _fll_div { 2790 u16 fll_fratio; 2791 u16 fll_outdiv; 2792 u16 fll_refclk_div; 2793 u16 n; 2794 u16 theta; 2795 u16 lambda; 2796 }; 2797 2798 /* The size in bits of the FLL divide multiplied by 10 2799 * to allow rounding later */ 2800 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2801 2802 static struct { 2803 unsigned int min; 2804 unsigned int max; 2805 u16 fll_fratio; 2806 int ratio; 2807 } fll_fratios[] = { 2808 { 0, 64000, 4, 16 }, 2809 { 64000, 128000, 3, 8 }, 2810 { 128000, 256000, 2, 4 }, 2811 { 256000, 1000000, 1, 2 }, 2812 { 1000000, 13500000, 0, 1 }, 2813 }; 2814 2815 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 2816 unsigned int Fout) 2817 { 2818 unsigned int target; 2819 unsigned int div; 2820 unsigned int fratio, gcd_fll; 2821 int i; 2822 2823 /* Fref must be <=13.5MHz */ 2824 div = 1; 2825 fll_div->fll_refclk_div = 0; 2826 while ((Fref / div) > 13500000) { 2827 div *= 2; 2828 fll_div->fll_refclk_div++; 2829 2830 if (div > 4) { 2831 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 2832 Fref); 2833 return -EINVAL; 2834 } 2835 } 2836 2837 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 2838 2839 /* Apply the division for our remaining calculations */ 2840 Fref /= div; 2841 2842 /* Fvco should be 90-100MHz; don't check the upper bound */ 2843 div = 2; 2844 while (Fout * div < 90000000) { 2845 div++; 2846 if (div > 64) { 2847 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 2848 Fout); 2849 return -EINVAL; 2850 } 2851 } 2852 target = Fout * div; 2853 fll_div->fll_outdiv = div - 1; 2854 2855 pr_debug("FLL Fvco=%dHz\n", target); 2856 2857 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 2858 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 2859 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 2860 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 2861 fratio = fll_fratios[i].ratio; 2862 break; 2863 } 2864 } 2865 if (i == ARRAY_SIZE(fll_fratios)) { 2866 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 2867 return -EINVAL; 2868 } 2869 2870 fll_div->n = target / (fratio * Fref); 2871 2872 if (target % Fref == 0) { 2873 fll_div->theta = 0; 2874 fll_div->lambda = 1; 2875 } else { 2876 gcd_fll = gcd(target, fratio * Fref); 2877 2878 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 2879 / gcd_fll; 2880 fll_div->lambda = (fratio * Fref) / gcd_fll; 2881 } 2882 2883 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 2884 fll_div->n, fll_div->theta, fll_div->lambda); 2885 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 2886 fll_div->fll_fratio, fll_div->fll_outdiv, 2887 fll_div->fll_refclk_div); 2888 2889 return 0; 2890 } 2891 2892 static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source, 2893 unsigned int Fref, unsigned int Fout) 2894 { 2895 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2896 struct _fll_div fll_div; 2897 unsigned long time_left; 2898 int ret; 2899 int fll1 = 0; 2900 2901 /* Any change? */ 2902 if (source == wm8962->fll_src && Fref == wm8962->fll_fref && 2903 Fout == wm8962->fll_fout) 2904 return 0; 2905 2906 if (Fout == 0) { 2907 dev_dbg(component->dev, "FLL disabled\n"); 2908 2909 wm8962->fll_fref = 0; 2910 wm8962->fll_fout = 0; 2911 2912 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, 2913 WM8962_FLL_ENA, 0); 2914 2915 pm_runtime_put(component->dev); 2916 2917 return 0; 2918 } 2919 2920 ret = fll_factors(&fll_div, Fref, Fout); 2921 if (ret != 0) 2922 return ret; 2923 2924 /* Parameters good, disable so we can reprogram */ 2925 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); 2926 2927 switch (fll_id) { 2928 case WM8962_FLL_MCLK: 2929 case WM8962_FLL_BCLK: 2930 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; 2931 break; 2932 case WM8962_FLL_OSC: 2933 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; 2934 snd_soc_component_update_bits(component, WM8962_PLL2, 2935 WM8962_OSC_ENA, WM8962_OSC_ENA); 2936 break; 2937 case WM8962_FLL_INT: 2938 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, 2939 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA); 2940 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5, 2941 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO); 2942 break; 2943 default: 2944 dev_err(component->dev, "Unknown FLL source %d\n", source); 2945 return -EINVAL; 2946 } 2947 2948 if (fll_div.theta) 2949 fll1 |= WM8962_FLL_FRAC; 2950 2951 /* Stop the FLL while we reconfigure */ 2952 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); 2953 2954 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2, 2955 WM8962_FLL_OUTDIV_MASK | 2956 WM8962_FLL_REFCLK_DIV_MASK, 2957 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) | 2958 (fll_div.fll_refclk_div)); 2959 2960 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3, 2961 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio); 2962 2963 snd_soc_component_write(component, WM8962_FLL_CONTROL_6, fll_div.theta); 2964 snd_soc_component_write(component, WM8962_FLL_CONTROL_7, fll_div.lambda); 2965 snd_soc_component_write(component, WM8962_FLL_CONTROL_8, fll_div.n); 2966 2967 reinit_completion(&wm8962->fll_lock); 2968 2969 ret = pm_runtime_resume_and_get(component->dev); 2970 if (ret < 0) { 2971 dev_err(component->dev, "Failed to resume device: %d\n", ret); 2972 return ret; 2973 } 2974 2975 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, 2976 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK | 2977 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA); 2978 2979 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2980 2981 /* This should be a massive overestimate but go even 2982 * higher if we'll error out 2983 */ 2984 if (wm8962->irq) 2985 time_left = msecs_to_jiffies(5); 2986 else 2987 time_left = msecs_to_jiffies(1); 2988 2989 time_left = wait_for_completion_timeout(&wm8962->fll_lock, 2990 time_left); 2991 2992 if (time_left == 0 && wm8962->irq) { 2993 dev_err(component->dev, "FLL lock timed out"); 2994 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, 2995 WM8962_FLL_ENA, 0); 2996 pm_runtime_put(component->dev); 2997 return -ETIMEDOUT; 2998 } 2999 3000 wm8962->fll_fref = Fref; 3001 wm8962->fll_fout = Fout; 3002 wm8962->fll_src = source; 3003 3004 return 0; 3005 } 3006 3007 static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction) 3008 { 3009 struct snd_soc_component *component = dai->component; 3010 int val, ret; 3011 3012 if (mute) 3013 val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT; 3014 else 3015 val = 0; 3016 3017 /** 3018 * The DAC mute bit is mirrored in two registers, update both to keep 3019 * the register cache consistent. 3020 */ 3021 ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1, 3022 WM8962_DAC_MUTE_ALT, val); 3023 if (ret < 0) 3024 return ret; 3025 3026 return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, 3027 WM8962_DAC_MUTE, val); 3028 } 3029 3030 #define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\ 3031 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) 3032 3033 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3034 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3035 3036 static const struct snd_soc_dai_ops wm8962_dai_ops = { 3037 .hw_params = wm8962_hw_params, 3038 .set_sysclk = wm8962_set_dai_sysclk, 3039 .set_fmt = wm8962_set_dai_fmt, 3040 .mute_stream = wm8962_mute, 3041 .no_capture_mute = 1, 3042 }; 3043 3044 static struct snd_soc_dai_driver wm8962_dai = { 3045 .name = "wm8962", 3046 .playback = { 3047 .stream_name = "Playback", 3048 .channels_min = 1, 3049 .channels_max = 2, 3050 .rates = WM8962_RATES, 3051 .formats = WM8962_FORMATS, 3052 }, 3053 .capture = { 3054 .stream_name = "Capture", 3055 .channels_min = 1, 3056 .channels_max = 2, 3057 .rates = WM8962_RATES, 3058 .formats = WM8962_FORMATS, 3059 }, 3060 .ops = &wm8962_dai_ops, 3061 .symmetric_rate = 1, 3062 }; 3063 3064 static void wm8962_mic_work(struct work_struct *work) 3065 { 3066 struct wm8962_priv *wm8962 = container_of(work, 3067 struct wm8962_priv, 3068 mic_work.work); 3069 struct snd_soc_component *component = wm8962->component; 3070 int status = 0; 3071 int irq_pol = 0; 3072 int reg; 3073 3074 reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4); 3075 3076 if (reg & WM8962_MICDET_STS) { 3077 status |= SND_JACK_MICROPHONE; 3078 irq_pol |= WM8962_MICD_IRQ_POL; 3079 } 3080 3081 if (reg & WM8962_MICSHORT_STS) { 3082 status |= SND_JACK_BTN_0; 3083 irq_pol |= WM8962_MICSCD_IRQ_POL; 3084 } 3085 3086 snd_soc_jack_report(wm8962->jack, status, 3087 SND_JACK_MICROPHONE | SND_JACK_BTN_0); 3088 3089 snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL, 3090 WM8962_MICSCD_IRQ_POL | 3091 WM8962_MICD_IRQ_POL, irq_pol); 3092 } 3093 3094 static irqreturn_t wm8962_irq(int irq, void *data) 3095 { 3096 struct device *dev = data; 3097 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3098 unsigned int mask; 3099 unsigned int active; 3100 int reg, ret; 3101 3102 ret = pm_runtime_resume_and_get(dev); 3103 if (ret < 0) { 3104 dev_err(dev, "Failed to resume: %d\n", ret); 3105 return IRQ_NONE; 3106 } 3107 3108 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK, 3109 &mask); 3110 if (ret != 0) { 3111 pm_runtime_put(dev); 3112 dev_err(dev, "Failed to read interrupt mask: %d\n", 3113 ret); 3114 return IRQ_NONE; 3115 } 3116 3117 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active); 3118 if (ret != 0) { 3119 pm_runtime_put(dev); 3120 dev_err(dev, "Failed to read interrupt: %d\n", ret); 3121 return IRQ_NONE; 3122 } 3123 3124 active &= ~mask; 3125 3126 if (!active) { 3127 pm_runtime_put(dev); 3128 return IRQ_NONE; 3129 } 3130 3131 /* Acknowledge the interrupts */ 3132 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active); 3133 if (ret != 0) 3134 dev_warn(dev, "Failed to ack interrupt: %d\n", ret); 3135 3136 if (active & WM8962_FLL_LOCK_EINT) { 3137 dev_dbg(dev, "FLL locked\n"); 3138 complete(&wm8962->fll_lock); 3139 } 3140 3141 if (active & WM8962_FIFOS_ERR_EINT) 3142 dev_err(dev, "FIFO error\n"); 3143 3144 if (active & WM8962_TEMP_SHUT_EINT) { 3145 dev_crit(dev, "Thermal shutdown\n"); 3146 3147 ret = regmap_read(wm8962->regmap, 3148 WM8962_THERMAL_SHUTDOWN_STATUS, ®); 3149 if (ret != 0) { 3150 dev_warn(dev, "Failed to read thermal status: %d\n", 3151 ret); 3152 reg = 0; 3153 } 3154 3155 if (reg & WM8962_TEMP_ERR_HP) 3156 dev_crit(dev, "Headphone thermal error\n"); 3157 if (reg & WM8962_TEMP_WARN_HP) 3158 dev_crit(dev, "Headphone thermal warning\n"); 3159 if (reg & WM8962_TEMP_ERR_SPK) 3160 dev_crit(dev, "Speaker thermal error\n"); 3161 if (reg & WM8962_TEMP_WARN_SPK) 3162 dev_crit(dev, "Speaker thermal warning\n"); 3163 } 3164 3165 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { 3166 dev_dbg(dev, "Microphone event detected\n"); 3167 3168 #ifndef CONFIG_SND_SOC_WM8962_MODULE 3169 trace_snd_soc_jack_irq(dev_name(dev)); 3170 #endif 3171 3172 pm_wakeup_event(dev, 300); 3173 3174 queue_delayed_work(system_power_efficient_wq, 3175 &wm8962->mic_work, 3176 msecs_to_jiffies(250)); 3177 } 3178 3179 pm_runtime_put(dev); 3180 3181 return IRQ_HANDLED; 3182 } 3183 3184 /** 3185 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ 3186 * 3187 * @component: WM8962 component 3188 * @jack: jack to report detection events on 3189 * 3190 * Enable microphone detection via IRQ on the WM8962. If GPIOs are 3191 * being used to bring out signals to the processor then only platform 3192 * data configuration is needed for WM8962 and processor GPIOs should 3193 * be configured using snd_soc_jack_add_gpios() instead. 3194 * 3195 * If no jack is supplied detection will be disabled. 3196 */ 3197 int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack) 3198 { 3199 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3200 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3201 int irq_mask, enable; 3202 3203 wm8962->jack = jack; 3204 if (jack) { 3205 irq_mask = 0; 3206 enable = WM8962_MICDET_ENA; 3207 } else { 3208 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT; 3209 enable = 0; 3210 } 3211 3212 snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK, 3213 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask); 3214 snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4, 3215 WM8962_MICDET_ENA, enable); 3216 3217 /* Send an initial empty report */ 3218 snd_soc_jack_report(wm8962->jack, 0, 3219 SND_JACK_MICROPHONE | SND_JACK_BTN_0); 3220 3221 snd_soc_dapm_mutex_lock(dapm); 3222 3223 if (jack) { 3224 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK"); 3225 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 3226 } else { 3227 snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK"); 3228 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 3229 } 3230 3231 snd_soc_dapm_mutex_unlock(dapm); 3232 3233 return 0; 3234 } 3235 EXPORT_SYMBOL_GPL(wm8962_mic_detect); 3236 3237 static int beep_rates[] = { 3238 500, 1000, 2000, 4000, 3239 }; 3240 3241 static void wm8962_beep_work(struct work_struct *work) 3242 { 3243 struct wm8962_priv *wm8962 = 3244 container_of(work, struct wm8962_priv, beep_work); 3245 struct snd_soc_component *component = wm8962->component; 3246 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3247 int i; 3248 int reg = 0; 3249 int best = 0; 3250 3251 if (wm8962->beep_rate) { 3252 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { 3253 if (abs(wm8962->beep_rate - beep_rates[i]) < 3254 abs(wm8962->beep_rate - beep_rates[best])) 3255 best = i; 3256 } 3257 3258 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n", 3259 beep_rates[best], wm8962->beep_rate); 3260 3261 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); 3262 3263 snd_soc_dapm_enable_pin(dapm, "Beep"); 3264 } else { 3265 dev_dbg(component->dev, "Disabling beep\n"); 3266 snd_soc_dapm_disable_pin(dapm, "Beep"); 3267 } 3268 3269 snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, 3270 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); 3271 3272 snd_soc_dapm_sync(dapm); 3273 } 3274 3275 /* For usability define a way of injecting beep events for the device - 3276 * many systems will not have a keyboard. 3277 */ 3278 static int wm8962_beep_event(struct input_dev *dev, unsigned int type, 3279 unsigned int code, int hz) 3280 { 3281 struct snd_soc_component *component = input_get_drvdata(dev); 3282 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3283 3284 dev_dbg(component->dev, "Beep event %x %x\n", code, hz); 3285 3286 switch (code) { 3287 case SND_BELL: 3288 if (hz) 3289 hz = 1000; 3290 fallthrough; 3291 case SND_TONE: 3292 break; 3293 default: 3294 return -1; 3295 } 3296 3297 /* Kick the beep from a workqueue */ 3298 wm8962->beep_rate = hz; 3299 schedule_work(&wm8962->beep_work); 3300 return 0; 3301 } 3302 3303 static ssize_t beep_store(struct device *dev, struct device_attribute *attr, 3304 const char *buf, size_t count) 3305 { 3306 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3307 long int time; 3308 int ret; 3309 3310 ret = kstrtol(buf, 10, &time); 3311 if (ret != 0) 3312 return ret; 3313 3314 input_event(wm8962->beep, EV_SND, SND_TONE, time); 3315 3316 return count; 3317 } 3318 3319 static DEVICE_ATTR_WO(beep); 3320 3321 static void wm8962_init_beep(struct snd_soc_component *component) 3322 { 3323 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3324 int ret; 3325 3326 wm8962->beep = devm_input_allocate_device(component->dev); 3327 if (!wm8962->beep) { 3328 dev_err(component->dev, "Failed to allocate beep device\n"); 3329 return; 3330 } 3331 3332 INIT_WORK(&wm8962->beep_work, wm8962_beep_work); 3333 wm8962->beep_rate = 0; 3334 3335 wm8962->beep->name = "WM8962 Beep Generator"; 3336 wm8962->beep->phys = dev_name(component->dev); 3337 wm8962->beep->id.bustype = BUS_I2C; 3338 3339 wm8962->beep->evbit[0] = BIT_MASK(EV_SND); 3340 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); 3341 wm8962->beep->event = wm8962_beep_event; 3342 wm8962->beep->dev.parent = component->dev; 3343 input_set_drvdata(wm8962->beep, component); 3344 3345 ret = input_register_device(wm8962->beep); 3346 if (ret != 0) { 3347 wm8962->beep = NULL; 3348 dev_err(component->dev, "Failed to register beep device\n"); 3349 } 3350 3351 ret = device_create_file(component->dev, &dev_attr_beep); 3352 if (ret != 0) { 3353 dev_err(component->dev, "Failed to create keyclick file: %d\n", 3354 ret); 3355 } 3356 } 3357 3358 static void wm8962_free_beep(struct snd_soc_component *component) 3359 { 3360 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3361 3362 device_remove_file(component->dev, &dev_attr_beep); 3363 cancel_work_sync(&wm8962->beep_work); 3364 wm8962->beep = NULL; 3365 3366 snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0); 3367 } 3368 3369 static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio) 3370 { 3371 int mask = 0; 3372 int val = 0; 3373 3374 /* Some of the GPIOs are behind MFP configuration and need to 3375 * be put into GPIO mode. */ 3376 switch (gpio) { 3377 case 2: 3378 mask = WM8962_CLKOUT2_SEL_MASK; 3379 val = 1 << WM8962_CLKOUT2_SEL_SHIFT; 3380 break; 3381 case 3: 3382 mask = WM8962_CLKOUT3_SEL_MASK; 3383 val = 1 << WM8962_CLKOUT3_SEL_SHIFT; 3384 break; 3385 default: 3386 break; 3387 } 3388 3389 if (mask) 3390 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1, 3391 mask, val); 3392 } 3393 3394 #ifdef CONFIG_GPIOLIB 3395 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset) 3396 { 3397 struct wm8962_priv *wm8962 = gpiochip_get_data(chip); 3398 3399 /* The WM8962 GPIOs aren't linearly numbered. For simplicity 3400 * we export linear numbers and error out if the unsupported 3401 * ones are requsted. 3402 */ 3403 switch (offset + 1) { 3404 case 2: 3405 case 3: 3406 case 5: 3407 case 6: 3408 break; 3409 default: 3410 return -EINVAL; 3411 } 3412 3413 wm8962_set_gpio_mode(wm8962, offset + 1); 3414 3415 return 0; 3416 } 3417 3418 static int wm8962_gpio_set(struct gpio_chip *chip, unsigned int offset, 3419 int value) 3420 { 3421 struct wm8962_priv *wm8962 = gpiochip_get_data(chip); 3422 struct snd_soc_component *component = wm8962->component; 3423 3424 return snd_soc_component_update_bits(component, 3425 WM8962_GPIO_BASE + offset, 3426 WM8962_GP2_LVL, 3427 !!value << WM8962_GP2_LVL_SHIFT); 3428 } 3429 3430 static int wm8962_gpio_direction_out(struct gpio_chip *chip, 3431 unsigned offset, int value) 3432 { 3433 struct wm8962_priv *wm8962 = gpiochip_get_data(chip); 3434 struct snd_soc_component *component = wm8962->component; 3435 int ret, val; 3436 3437 /* Force function 1 (logic output) */ 3438 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); 3439 3440 ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset, 3441 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); 3442 if (ret < 0) 3443 return ret; 3444 3445 return 0; 3446 } 3447 3448 static const struct gpio_chip wm8962_template_chip = { 3449 .label = "wm8962", 3450 .owner = THIS_MODULE, 3451 .request = wm8962_gpio_request, 3452 .direction_output = wm8962_gpio_direction_out, 3453 .set = wm8962_gpio_set, 3454 .can_sleep = 1, 3455 }; 3456 3457 static void wm8962_init_gpio(struct snd_soc_component *component) 3458 { 3459 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3460 struct wm8962_pdata *pdata = &wm8962->pdata; 3461 int ret; 3462 3463 wm8962->gpio_chip = wm8962_template_chip; 3464 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; 3465 wm8962->gpio_chip.parent = component->dev; 3466 3467 if (pdata->gpio_base) 3468 wm8962->gpio_chip.base = pdata->gpio_base; 3469 else 3470 wm8962->gpio_chip.base = -1; 3471 3472 ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962); 3473 if (ret != 0) 3474 dev_err(component->dev, "Failed to add GPIOs: %d\n", ret); 3475 } 3476 3477 static void wm8962_free_gpio(struct snd_soc_component *component) 3478 { 3479 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3480 3481 gpiochip_remove(&wm8962->gpio_chip); 3482 } 3483 #else 3484 static void wm8962_init_gpio(struct snd_soc_component *component) 3485 { 3486 } 3487 3488 static void wm8962_free_gpio(struct snd_soc_component *component) 3489 { 3490 } 3491 #endif 3492 3493 static int wm8962_probe(struct snd_soc_component *component) 3494 { 3495 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3496 int ret; 3497 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3498 int i; 3499 bool dmicclk, dmicdat; 3500 3501 wm8962->component = component; 3502 3503 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; 3504 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; 3505 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; 3506 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; 3507 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; 3508 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; 3509 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; 3510 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; 3511 3512 /* This should really be moved into the regulator core */ 3513 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { 3514 ret = devm_regulator_register_notifier( 3515 wm8962->supplies[i].consumer, 3516 &wm8962->disable_nb[i]); 3517 if (ret != 0) { 3518 dev_err(component->dev, 3519 "Failed to register regulator notifier: %d\n", 3520 ret); 3521 } 3522 } 3523 3524 wm8962_add_widgets(component); 3525 3526 /* Save boards having to disable DMIC when not in use */ 3527 dmicclk = false; 3528 dmicdat = false; 3529 for (i = 1; i < WM8962_MAX_GPIO; i++) { 3530 /* 3531 * Register 515 (WM8962_GPIO_BASE + 3) does not exist, 3532 * so skip its access 3533 */ 3534 if (i == 3) 3535 continue; 3536 switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i) 3537 & WM8962_GP2_FN_MASK) { 3538 case WM8962_GPIO_FN_DMICCLK: 3539 dmicclk = true; 3540 break; 3541 case WM8962_GPIO_FN_DMICDAT: 3542 dmicdat = true; 3543 break; 3544 default: 3545 break; 3546 } 3547 } 3548 if (!dmicclk || !dmicdat) { 3549 dev_dbg(component->dev, "DMIC not in use, disabling\n"); 3550 snd_soc_dapm_disable_pin(dapm, "DMICDAT"); 3551 } 3552 if (dmicclk != dmicdat) 3553 dev_warn(component->dev, "DMIC GPIOs partially configured\n"); 3554 3555 wm8962_init_beep(component); 3556 wm8962_init_gpio(component); 3557 3558 return 0; 3559 } 3560 3561 static void wm8962_remove(struct snd_soc_component *component) 3562 { 3563 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3564 3565 cancel_delayed_work_sync(&wm8962->mic_work); 3566 3567 wm8962_free_gpio(component); 3568 wm8962_free_beep(component); 3569 } 3570 3571 static const struct snd_soc_component_driver soc_component_dev_wm8962 = { 3572 .probe = wm8962_probe, 3573 .remove = wm8962_remove, 3574 .set_bias_level = wm8962_set_bias_level, 3575 .set_pll = wm8962_set_fll, 3576 .use_pmdown_time = 1, 3577 .endianness = 1, 3578 }; 3579 3580 /* Improve power consumption for IN4 DC measurement mode */ 3581 static const struct reg_sequence wm8962_dc_measure[] = { 3582 { 0xfd, 0x1 }, 3583 { 0xcc, 0x40 }, 3584 { 0xfd, 0 }, 3585 }; 3586 3587 static const struct regmap_config wm8962_regmap = { 3588 .reg_bits = 16, 3589 .val_bits = 16, 3590 3591 .max_register = WM8962_MAX_REGISTER, 3592 .reg_defaults = wm8962_reg, 3593 .num_reg_defaults = ARRAY_SIZE(wm8962_reg), 3594 .volatile_reg = wm8962_volatile_register, 3595 .readable_reg = wm8962_readable_register, 3596 .cache_type = REGCACHE_MAPLE, 3597 }; 3598 3599 static int wm8962_set_pdata_from_of(struct i2c_client *i2c, 3600 struct wm8962_pdata *pdata) 3601 { 3602 const struct device_node *np = i2c->dev.of_node; 3603 u32 val32; 3604 int i; 3605 3606 if (of_property_read_bool(np, "spk-mono")) 3607 pdata->spk_mono = true; 3608 3609 if (of_property_read_u32(np, "mic-cfg", &val32) >= 0) 3610 pdata->mic_cfg = val32; 3611 3612 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init, 3613 ARRAY_SIZE(pdata->gpio_init)) >= 0) 3614 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) { 3615 /* 3616 * The range of GPIO register value is [0x0, 0xffff] 3617 * While the default value of each register is 0x0 3618 * Any other value will be regarded as default value 3619 */ 3620 if (pdata->gpio_init[i] > 0xffff) 3621 pdata->gpio_init[i] = 0x0; 3622 } 3623 3624 pdata->mclk = devm_clk_get_optional(&i2c->dev, NULL); 3625 return PTR_ERR_OR_ZERO(pdata->mclk); 3626 } 3627 3628 static int wm8962_i2c_probe(struct i2c_client *i2c) 3629 { 3630 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev); 3631 struct wm8962_priv *wm8962; 3632 unsigned int reg; 3633 int ret, i, irq_pol, trigger; 3634 3635 wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL); 3636 if (wm8962 == NULL) 3637 return -ENOMEM; 3638 3639 mutex_init(&wm8962->dsp2_ena_lock); 3640 3641 i2c_set_clientdata(i2c, wm8962); 3642 3643 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); 3644 init_completion(&wm8962->fll_lock); 3645 wm8962->irq = i2c->irq; 3646 3647 /* If platform data was supplied, update the default data in priv */ 3648 if (pdata) { 3649 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata)); 3650 } else if (i2c->dev.of_node) { 3651 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata); 3652 if (ret != 0) 3653 return ret; 3654 } 3655 3656 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) 3657 wm8962->supplies[i].supply = wm8962_supply_names[i]; 3658 3659 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies), 3660 wm8962->supplies); 3661 if (ret != 0) { 3662 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3663 goto err; 3664 } 3665 3666 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 3667 wm8962->supplies); 3668 if (ret != 0) { 3669 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3670 return ret; 3671 } 3672 3673 wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap); 3674 if (IS_ERR(wm8962->regmap)) { 3675 ret = PTR_ERR(wm8962->regmap); 3676 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 3677 goto err_enable; 3678 } 3679 3680 /* 3681 * We haven't marked the chip revision as volatile due to 3682 * sharing a register with the right input volume; explicitly 3683 * bypass the cache to read it. 3684 */ 3685 regcache_cache_bypass(wm8962->regmap, true); 3686 3687 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®); 3688 if (ret < 0) { 3689 dev_err(&i2c->dev, "Failed to read ID register\n"); 3690 goto err_enable; 3691 } 3692 if (reg != 0x6243) { 3693 dev_err(&i2c->dev, 3694 "Device is not a WM8962, ID %x != 0x6243\n", reg); 3695 ret = -EINVAL; 3696 goto err_enable; 3697 } 3698 3699 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®); 3700 if (ret < 0) { 3701 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 3702 ret); 3703 goto err_enable; 3704 } 3705 3706 dev_info(&i2c->dev, "customer id %x revision %c\n", 3707 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, 3708 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) 3709 + 'A'); 3710 3711 regcache_cache_bypass(wm8962->regmap, false); 3712 3713 ret = wm8962_reset(wm8962); 3714 if (ret < 0) { 3715 dev_err(&i2c->dev, "Failed to issue reset\n"); 3716 goto err_enable; 3717 } 3718 3719 /* SYSCLK defaults to on; make sure it is off so we can safely 3720 * write to registers if the device is declocked. 3721 */ 3722 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, 3723 WM8962_SYSCLK_ENA, 0); 3724 3725 /* Ensure we have soft control over all registers */ 3726 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, 3727 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); 3728 3729 /* Ensure that the oscillator and PLLs are disabled */ 3730 regmap_update_bits(wm8962->regmap, WM8962_PLL2, 3731 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, 3732 0); 3733 3734 /* Apply static configuration for GPIOs */ 3735 for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++) 3736 if (wm8962->pdata.gpio_init[i]) { 3737 wm8962_set_gpio_mode(wm8962, i + 1); 3738 regmap_write(wm8962->regmap, 0x200 + i, 3739 wm8962->pdata.gpio_init[i] & 0xffff); 3740 } 3741 3742 3743 /* Put the speakers into mono mode? */ 3744 if (wm8962->pdata.spk_mono) 3745 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2, 3746 WM8962_SPK_MONO_MASK, WM8962_SPK_MONO); 3747 3748 /* Micbias setup, detection enable and detection 3749 * threasholds. */ 3750 if (wm8962->pdata.mic_cfg) 3751 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, 3752 WM8962_MICDET_ENA | 3753 WM8962_MICDET_THR_MASK | 3754 WM8962_MICSHORT_THR_MASK | 3755 WM8962_MICBIAS_LVL, 3756 wm8962->pdata.mic_cfg); 3757 3758 /* Latch volume update bits */ 3759 regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME, 3760 WM8962_IN_VU, WM8962_IN_VU); 3761 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, 3762 WM8962_IN_VU, WM8962_IN_VU); 3763 regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME, 3764 WM8962_ADC_VU, WM8962_ADC_VU); 3765 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME, 3766 WM8962_ADC_VU, WM8962_ADC_VU); 3767 regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME, 3768 WM8962_DAC_VU, WM8962_DAC_VU); 3769 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME, 3770 WM8962_DAC_VU, WM8962_DAC_VU); 3771 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME, 3772 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); 3773 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME, 3774 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); 3775 regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME, 3776 WM8962_HPOUT_VU, WM8962_HPOUT_VU); 3777 regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME, 3778 WM8962_HPOUT_VU, WM8962_HPOUT_VU); 3779 3780 /* Stereo control for EQ */ 3781 regmap_update_bits(wm8962->regmap, WM8962_EQ1, 3782 WM8962_EQ_SHARED_COEFF, 0); 3783 3784 /* Don't debouce interrupts so we don't need SYSCLK */ 3785 regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE, 3786 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB | 3787 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB, 3788 0); 3789 3790 if (wm8962->pdata.in4_dc_measure) { 3791 ret = regmap_register_patch(wm8962->regmap, 3792 wm8962_dc_measure, 3793 ARRAY_SIZE(wm8962_dc_measure)); 3794 if (ret != 0) 3795 dev_err(&i2c->dev, 3796 "Failed to configure for DC measurement: %d\n", 3797 ret); 3798 } 3799 3800 if (wm8962->irq) { 3801 if (wm8962->pdata.irq_active_low) { 3802 trigger = IRQF_TRIGGER_LOW; 3803 irq_pol = WM8962_IRQ_POL; 3804 } else { 3805 trigger = IRQF_TRIGGER_HIGH; 3806 irq_pol = 0; 3807 } 3808 3809 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL, 3810 WM8962_IRQ_POL, irq_pol); 3811 3812 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL, 3813 wm8962_irq, 3814 trigger | IRQF_ONESHOT, 3815 "wm8962", &i2c->dev); 3816 if (ret != 0) { 3817 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n", 3818 wm8962->irq, ret); 3819 wm8962->irq = 0; 3820 /* Non-fatal */ 3821 } else { 3822 /* Enable some IRQs by default */ 3823 regmap_update_bits(wm8962->regmap, 3824 WM8962_INTERRUPT_STATUS_2_MASK, 3825 WM8962_FLL_LOCK_EINT | 3826 WM8962_TEMP_SHUT_EINT | 3827 WM8962_FIFOS_ERR_EINT, 0); 3828 } 3829 } 3830 3831 pm_runtime_enable(&i2c->dev); 3832 pm_request_idle(&i2c->dev); 3833 3834 ret = devm_snd_soc_register_component(&i2c->dev, 3835 &soc_component_dev_wm8962, &wm8962_dai, 1); 3836 if (ret < 0) 3837 goto err_pm_runtime; 3838 3839 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, 3840 WM8962_TEMP_ENA_HP_MASK, 0); 3841 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, 3842 WM8962_TEMP_ENA_SPK_MASK, 0); 3843 3844 regcache_cache_only(wm8962->regmap, true); 3845 3846 /* The drivers should power up as needed */ 3847 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3848 3849 return 0; 3850 3851 err_pm_runtime: 3852 pm_runtime_disable(&i2c->dev); 3853 err_enable: 3854 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3855 err: 3856 return ret; 3857 } 3858 3859 static void wm8962_i2c_remove(struct i2c_client *client) 3860 { 3861 pm_runtime_disable(&client->dev); 3862 } 3863 3864 static int wm8962_runtime_resume(struct device *dev) 3865 { 3866 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3867 int ret; 3868 3869 ret = clk_prepare_enable(wm8962->pdata.mclk); 3870 if (ret) { 3871 dev_err(dev, "Failed to enable MCLK: %d\n", ret); 3872 return ret; 3873 } 3874 3875 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 3876 wm8962->supplies); 3877 if (ret != 0) { 3878 dev_err(dev, "Failed to enable supplies: %d\n", ret); 3879 goto disable_clock; 3880 } 3881 3882 regcache_cache_only(wm8962->regmap, false); 3883 3884 wm8962_reset(wm8962); 3885 3886 regcache_mark_dirty(wm8962->regmap); 3887 3888 /* SYSCLK defaults to on; make sure it is off so we can safely 3889 * write to registers if the device is declocked. 3890 */ 3891 regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2, 3892 WM8962_SYSCLK_ENA, 0); 3893 3894 /* Ensure we have soft control over all registers */ 3895 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, 3896 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); 3897 3898 /* Ensure that the oscillator and PLLs are disabled */ 3899 regmap_update_bits(wm8962->regmap, WM8962_PLL2, 3900 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, 3901 0); 3902 3903 regcache_sync(wm8962->regmap); 3904 3905 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, 3906 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA, 3907 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA); 3908 3909 /* Bias enable at 2*5k (fast start-up) */ 3910 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, 3911 WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK, 3912 WM8962_BIAS_ENA | 0x180); 3913 3914 if (wm8962->master_flag) 3915 regmap_update_bits(wm8962->regmap, WM8962_AUDIO_INTERFACE_0, 3916 WM8962_MSTR, WM8962_MSTR); 3917 msleep(5); 3918 3919 return 0; 3920 3921 disable_clock: 3922 clk_disable_unprepare(wm8962->pdata.mclk); 3923 return ret; 3924 } 3925 3926 static int wm8962_runtime_suspend(struct device *dev) 3927 { 3928 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3929 3930 if (wm8962->master_flag) 3931 regmap_update_bits(wm8962->regmap, WM8962_AUDIO_INTERFACE_0, 3932 WM8962_MSTR, 0); 3933 3934 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, 3935 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0); 3936 3937 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, 3938 WM8962_STARTUP_BIAS_ENA | 3939 WM8962_VMID_BUF_ENA, 0); 3940 3941 regcache_cache_only(wm8962->regmap, true); 3942 3943 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), 3944 wm8962->supplies); 3945 3946 clk_disable_unprepare(wm8962->pdata.mclk); 3947 3948 return 0; 3949 } 3950 3951 static const struct dev_pm_ops wm8962_pm = { 3952 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 3953 RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL) 3954 }; 3955 3956 static const struct i2c_device_id wm8962_i2c_id[] = { 3957 { "wm8962" }, 3958 { } 3959 }; 3960 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); 3961 3962 static const struct of_device_id wm8962_of_match[] = { 3963 { .compatible = "wlf,wm8962", }, 3964 { } 3965 }; 3966 MODULE_DEVICE_TABLE(of, wm8962_of_match); 3967 3968 static struct i2c_driver wm8962_i2c_driver = { 3969 .driver = { 3970 .name = "wm8962", 3971 .of_match_table = wm8962_of_match, 3972 .pm = pm_ptr(&wm8962_pm), 3973 }, 3974 .probe = wm8962_i2c_probe, 3975 .remove = wm8962_i2c_remove, 3976 .id_table = wm8962_i2c_id, 3977 }; 3978 3979 module_i2c_driver(wm8962_i2c_driver); 3980 3981 MODULE_DESCRIPTION("ASoC WM8962 driver"); 3982 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3983 MODULE_LICENSE("GPL"); 3984