1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/alpha/kernel/sys_dp264.c
4 *
5 * Copyright (C) 1995 David A Rusling
6 * Copyright (C) 1996, 1999 Jay A Estabrook
7 * Copyright (C) 1998, 1999 Richard Henderson
8 *
9 * Modified by Christopher C. Chimelis, 2001 to
10 * add support for the addition of Shark to the
11 * Tsunami family.
12 *
13 * Code supporting the DP264 (EV6+TSUNAMI).
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/mm.h>
19 #include <linux/sched.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/bitops.h>
23
24 #include <asm/ptrace.h>
25 #include <asm/dma.h>
26 #include <asm/irq.h>
27 #include <asm/mmu_context.h>
28 #include <asm/io.h>
29 #include <asm/core_tsunami.h>
30 #include <asm/hwrpb.h>
31 #include <asm/tlbflush.h>
32
33 #include "proto.h"
34 #include "irq_impl.h"
35 #include "pci_impl.h"
36 #include "machvec_impl.h"
37
38
39 /* Note mask bit is true for ENABLED irqs. */
40 static unsigned long cached_irq_mask;
41 /* dp264 boards handle at max four CPUs */
42 static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
43
44 static DEFINE_RAW_SPINLOCK(dp264_irq_lock);
45
46 static void
tsunami_update_irq_hw(unsigned long mask)47 tsunami_update_irq_hw(unsigned long mask)
48 {
49 register tsunami_cchip *cchip = TSUNAMI_cchip;
50 unsigned long isa_enable = 1UL << 55;
51 register int bcpu = boot_cpuid;
52
53 #ifdef CONFIG_SMP
54 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
55 unsigned long mask0, mask1, mask2, mask3, dummy;
56
57 mask &= ~isa_enable;
58 mask0 = mask & cpu_irq_affinity[0];
59 mask1 = mask & cpu_irq_affinity[1];
60 mask2 = mask & cpu_irq_affinity[2];
61 mask3 = mask & cpu_irq_affinity[3];
62
63 if (bcpu == 0) mask0 |= isa_enable;
64 else if (bcpu == 1) mask1 |= isa_enable;
65 else if (bcpu == 2) mask2 |= isa_enable;
66 else mask3 |= isa_enable;
67
68 dim0 = &cchip->dim0.csr;
69 dim1 = &cchip->dim1.csr;
70 dim2 = &cchip->dim2.csr;
71 dim3 = &cchip->dim3.csr;
72 if (!cpu_possible(0)) dim0 = &dummy;
73 if (!cpu_possible(1)) dim1 = &dummy;
74 if (!cpu_possible(2)) dim2 = &dummy;
75 if (!cpu_possible(3)) dim3 = &dummy;
76
77 *dim0 = mask0;
78 *dim1 = mask1;
79 *dim2 = mask2;
80 *dim3 = mask3;
81 mb();
82 *dim0;
83 *dim1;
84 *dim2;
85 *dim3;
86 #else
87 volatile unsigned long *dimB;
88 if (bcpu == 0) dimB = &cchip->dim0.csr;
89 else if (bcpu == 1) dimB = &cchip->dim1.csr;
90 else if (bcpu == 2) dimB = &cchip->dim2.csr;
91 else dimB = &cchip->dim3.csr;
92
93 *dimB = mask | isa_enable;
94 mb();
95 *dimB;
96 #endif
97 }
98
99 static void
dp264_enable_irq(struct irq_data * d)100 dp264_enable_irq(struct irq_data *d)
101 {
102 unsigned long flags;
103
104 raw_spin_lock_irqsave(&dp264_irq_lock, flags);
105 cached_irq_mask |= 1UL << d->irq;
106 tsunami_update_irq_hw(cached_irq_mask);
107 raw_spin_unlock_irqrestore(&dp264_irq_lock, flags);
108 }
109
110 static void
dp264_disable_irq(struct irq_data * d)111 dp264_disable_irq(struct irq_data *d)
112 {
113 unsigned long flags;
114
115 raw_spin_lock_irqsave(&dp264_irq_lock, flags);
116 cached_irq_mask &= ~(1UL << d->irq);
117 tsunami_update_irq_hw(cached_irq_mask);
118 raw_spin_unlock_irqrestore(&dp264_irq_lock, flags);
119 }
120
121 static void
clipper_enable_irq(struct irq_data * d)122 clipper_enable_irq(struct irq_data *d)
123 {
124 unsigned long flags;
125
126 raw_spin_lock_irqsave(&dp264_irq_lock, flags);
127 cached_irq_mask |= 1UL << (d->irq - 16);
128 tsunami_update_irq_hw(cached_irq_mask);
129 raw_spin_unlock_irqrestore(&dp264_irq_lock, flags);
130 }
131
132 static void
clipper_disable_irq(struct irq_data * d)133 clipper_disable_irq(struct irq_data *d)
134 {
135 unsigned long flags;
136
137 raw_spin_lock_irqsave(&dp264_irq_lock, flags);
138 cached_irq_mask &= ~(1UL << (d->irq - 16));
139 tsunami_update_irq_hw(cached_irq_mask);
140 raw_spin_unlock_irqrestore(&dp264_irq_lock, flags);
141 }
142
143 static void
cpu_set_irq_affinity(unsigned int irq,cpumask_t affinity)144 cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
145 {
146 int cpu;
147
148 for (cpu = 0; cpu < 4; cpu++) {
149 unsigned long aff = cpu_irq_affinity[cpu];
150 if (cpumask_test_cpu(cpu, &affinity))
151 aff |= 1UL << irq;
152 else
153 aff &= ~(1UL << irq);
154 cpu_irq_affinity[cpu] = aff;
155 }
156 }
157
158 static int
dp264_set_affinity(struct irq_data * d,const struct cpumask * affinity,bool force)159 dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
160 bool force)
161 {
162 unsigned long flags;
163
164 raw_spin_lock_irqsave(&dp264_irq_lock, flags);
165 cpu_set_irq_affinity(d->irq, *affinity);
166 tsunami_update_irq_hw(cached_irq_mask);
167 raw_spin_unlock_irqrestore(&dp264_irq_lock, flags);
168
169 return 0;
170 }
171
172 static int
clipper_set_affinity(struct irq_data * d,const struct cpumask * affinity,bool force)173 clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
174 bool force)
175 {
176 unsigned long flags;
177
178 raw_spin_lock_irqsave(&dp264_irq_lock, flags);
179 cpu_set_irq_affinity(d->irq - 16, *affinity);
180 tsunami_update_irq_hw(cached_irq_mask);
181 raw_spin_unlock_irqrestore(&dp264_irq_lock, flags);
182
183 return 0;
184 }
185
186 static struct irq_chip dp264_irq_type = {
187 .name = "DP264",
188 .irq_unmask = dp264_enable_irq,
189 .irq_mask = dp264_disable_irq,
190 .irq_mask_ack = dp264_disable_irq,
191 .irq_set_affinity = dp264_set_affinity,
192 };
193
194 static struct irq_chip clipper_irq_type = {
195 .name = "CLIPPER",
196 .irq_unmask = clipper_enable_irq,
197 .irq_mask = clipper_disable_irq,
198 .irq_mask_ack = clipper_disable_irq,
199 .irq_set_affinity = clipper_set_affinity,
200 };
201
202 static void
dp264_device_interrupt(unsigned long vector)203 dp264_device_interrupt(unsigned long vector)
204 {
205 unsigned long pld;
206 unsigned int i;
207
208 /* Read the interrupt summary register of TSUNAMI */
209 pld = TSUNAMI_cchip->dir0.csr;
210
211 /*
212 * Now for every possible bit set, work through them and call
213 * the appropriate interrupt handler.
214 */
215 while (pld) {
216 i = ffz(~pld);
217 pld &= pld - 1; /* clear least bit set */
218 if (i == 55)
219 isa_device_interrupt(vector);
220 else
221 handle_irq(16 + i);
222 }
223 }
224
225 static void
dp264_srm_device_interrupt(unsigned long vector)226 dp264_srm_device_interrupt(unsigned long vector)
227 {
228 int irq;
229
230 irq = (vector - 0x800) >> 4;
231
232 /*
233 * The SRM console reports PCI interrupts with a vector calculated by:
234 *
235 * 0x900 + (0x10 * DRIR-bit)
236 *
237 * So bit 16 shows up as IRQ 32, etc.
238 *
239 * On DP264/BRICK/MONET, we adjust it down by 16 because at least
240 * that many of the low order bits of the DRIR are not used, and
241 * so we don't count them.
242 */
243 if (irq >= 32)
244 irq -= 16;
245
246 handle_irq(irq);
247 }
248
249 static void
clipper_srm_device_interrupt(unsigned long vector)250 clipper_srm_device_interrupt(unsigned long vector)
251 {
252 int irq;
253
254 irq = (vector - 0x800) >> 4;
255
256 /*
257 * The SRM console reports PCI interrupts with a vector calculated by:
258 *
259 * 0x900 + (0x10 * DRIR-bit)
260 *
261 * So bit 16 shows up as IRQ 32, etc.
262 *
263 * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
264 * to scale down the vector reported, we just use it.
265 *
266 * Eg IRQ 24 is DRIR bit 8, etc, etc
267 */
268 handle_irq(irq);
269 }
270
271 static void __init
init_tsunami_irqs(struct irq_chip * ops,int imin,int imax)272 init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
273 {
274 long i;
275 for (i = imin; i <= imax; ++i) {
276 irq_set_chip_and_handler(i, ops, handle_level_irq);
277 irq_set_status_flags(i, IRQ_LEVEL);
278 }
279 }
280
281 static void __init
dp264_init_irq(void)282 dp264_init_irq(void)
283 {
284 outb(0, DMA1_RESET_REG);
285 outb(0, DMA2_RESET_REG);
286 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
287 outb(0, DMA2_MASK_REG);
288
289 if (alpha_using_srm)
290 alpha_mv.device_interrupt = dp264_srm_device_interrupt;
291
292 tsunami_update_irq_hw(0);
293
294 init_i8259a_irqs();
295 init_tsunami_irqs(&dp264_irq_type, 16, 47);
296 }
297
298 static void __init
clipper_init_irq(void)299 clipper_init_irq(void)
300 {
301 outb(0, DMA1_RESET_REG);
302 outb(0, DMA2_RESET_REG);
303 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
304 outb(0, DMA2_MASK_REG);
305
306 if (alpha_using_srm)
307 alpha_mv.device_interrupt = clipper_srm_device_interrupt;
308
309 tsunami_update_irq_hw(0);
310
311 init_i8259a_irqs();
312 init_tsunami_irqs(&clipper_irq_type, 24, 63);
313 }
314
315
316 /*
317 * PCI Fixup configuration.
318 *
319 * Summary @ TSUNAMI_CSR_DIM0:
320 * Bit Meaning
321 * 0-17 Unused
322 *18 Interrupt SCSI B (Adaptec 7895 builtin)
323 *19 Interrupt SCSI A (Adaptec 7895 builtin)
324 *20 Interrupt Line D from slot 2 PCI0
325 *21 Interrupt Line C from slot 2 PCI0
326 *22 Interrupt Line B from slot 2 PCI0
327 *23 Interrupt Line A from slot 2 PCI0
328 *24 Interrupt Line D from slot 1 PCI0
329 *25 Interrupt Line C from slot 1 PCI0
330 *26 Interrupt Line B from slot 1 PCI0
331 *27 Interrupt Line A from slot 1 PCI0
332 *28 Interrupt Line D from slot 0 PCI0
333 *29 Interrupt Line C from slot 0 PCI0
334 *30 Interrupt Line B from slot 0 PCI0
335 *31 Interrupt Line A from slot 0 PCI0
336 *
337 *32 Interrupt Line D from slot 3 PCI1
338 *33 Interrupt Line C from slot 3 PCI1
339 *34 Interrupt Line B from slot 3 PCI1
340 *35 Interrupt Line A from slot 3 PCI1
341 *36 Interrupt Line D from slot 2 PCI1
342 *37 Interrupt Line C from slot 2 PCI1
343 *38 Interrupt Line B from slot 2 PCI1
344 *39 Interrupt Line A from slot 2 PCI1
345 *40 Interrupt Line D from slot 1 PCI1
346 *41 Interrupt Line C from slot 1 PCI1
347 *42 Interrupt Line B from slot 1 PCI1
348 *43 Interrupt Line A from slot 1 PCI1
349 *44 Interrupt Line D from slot 0 PCI1
350 *45 Interrupt Line C from slot 0 PCI1
351 *46 Interrupt Line B from slot 0 PCI1
352 *47 Interrupt Line A from slot 0 PCI1
353 *48-52 Unused
354 *53 PCI0 NMI (from Cypress)
355 *54 PCI0 SMI INT (from Cypress)
356 *55 PCI0 ISA Interrupt (from Cypress)
357 *56-60 Unused
358 *61 PCI1 Bus Error
359 *62 PCI0 Bus Error
360 *63 Reserved
361 *
362 * IdSel
363 * 5 Cypress Bridge I/O
364 * 6 SCSI Adaptec builtin
365 * 7 64 bit PCI option slot 0 (all busses)
366 * 8 64 bit PCI option slot 1 (all busses)
367 * 9 64 bit PCI option slot 2 (all busses)
368 * 10 64 bit PCI option slot 3 (not bus 0)
369 */
370
371 static int
isa_irq_fixup(const struct pci_dev * dev,int irq)372 isa_irq_fixup(const struct pci_dev *dev, int irq)
373 {
374 u8 irq8;
375
376 if (irq > 0)
377 return irq;
378
379 /* This interrupt is routed via ISA bridge, so we'll
380 just have to trust whatever value the console might
381 have assigned. */
382 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
383
384 return irq8 & 0xf;
385 }
386
387 static int
dp264_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)388 dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
389 {
390 static char irq_tab[6][5] = {
391 /*INT INTA INTB INTC INTD */
392 { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
393 { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
394 { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
395 { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
396 { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
397 { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
398 };
399 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
400 struct pci_controller *hose = dev->sysdata;
401 int irq = COMMON_TABLE_LOOKUP;
402
403 if (irq > 0)
404 irq += 16 * hose->index;
405
406 return isa_irq_fixup(dev, irq);
407 }
408
409 static int
monet_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)410 monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
411 {
412 static char irq_tab[13][5] = {
413 /*INT INTA INTB INTC INTD */
414 { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
415 { -1, -1, -1, -1, -1}, /* IdSel 4 unused */
416 { -1, -1, -1, -1, -1}, /* IdSel 5 unused */
417 { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
418 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
419 { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
420 #if 1
421 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
422 { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
423 #else
424 { -1, -1, -1, -1, -1}, /* IdSel 9 unused */
425 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
426 #endif
427 { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
428 { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
429 { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
430 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
431 { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
432 };
433 const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
434
435 return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
436 }
437
438 static u8
monet_swizzle(struct pci_dev * dev,u8 * pinp)439 monet_swizzle(struct pci_dev *dev, u8 *pinp)
440 {
441 struct pci_controller *hose = dev->sysdata;
442 int slot, pin = *pinp;
443
444 if (!dev->bus->parent) {
445 slot = PCI_SLOT(dev->devfn);
446 }
447 /* Check for the built-in bridge on hose 1. */
448 else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
449 slot = PCI_SLOT(dev->devfn);
450 } else {
451 /* Must be a card-based bridge. */
452 do {
453 /* Check for built-in bridge on hose 1. */
454 if (hose->index == 1 &&
455 PCI_SLOT(dev->bus->self->devfn) == 8) {
456 slot = PCI_SLOT(dev->devfn);
457 break;
458 }
459 pin = pci_swizzle_interrupt_pin(dev, pin);
460
461 /* Move up the chain of bridges. */
462 dev = dev->bus->self;
463 /* Slot of the next bridge. */
464 slot = PCI_SLOT(dev->devfn);
465 } while (dev->bus->self);
466 }
467 *pinp = pin;
468 return slot;
469 }
470
471 static int
webbrick_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)472 webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
473 {
474 static char irq_tab[13][5] = {
475 /*INT INTA INTB INTC INTD */
476 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
477 { -1, -1, -1, -1, -1}, /* IdSel 8 unused */
478 { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
479 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
480 { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
481 { -1, -1, -1, -1, -1}, /* IdSel 12 unused */
482 { -1, -1, -1, -1, -1}, /* IdSel 13 unused */
483 { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
484 { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
485 { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
486 { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
487 };
488 const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
489
490 return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
491 }
492
493 static int
clipper_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)494 clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
495 {
496 static char irq_tab[7][5] = {
497 /*INT INTA INTB INTC INTD */
498 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
499 { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
500 { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
501 { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
502 { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
503 { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
504 { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
505 };
506 const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
507 struct pci_controller *hose = dev->sysdata;
508 int irq = COMMON_TABLE_LOOKUP;
509
510 if (irq > 0)
511 irq += 16 * hose->index;
512
513 return isa_irq_fixup(dev, irq);
514 }
515
516 static void __init
dp264_init_pci(void)517 dp264_init_pci(void)
518 {
519 common_init_pci();
520 SMC669_Init(0);
521 locate_and_init_vga(NULL);
522 }
523
524 static void __init
monet_init_pci(void)525 monet_init_pci(void)
526 {
527 common_init_pci();
528 SMC669_Init(1);
529 es1888_init();
530 locate_and_init_vga(NULL);
531 }
532
533 static void __init
clipper_init_pci(void)534 clipper_init_pci(void)
535 {
536 tsunami_check_console_data_log();
537 common_init_pci();
538 locate_and_init_vga(NULL);
539 }
540
541 static void __init
webbrick_init_arch(void)542 webbrick_init_arch(void)
543 {
544 tsunami_init_arch();
545
546 /* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */
547 hose_head->sg_isa->align_entry = 4;
548 hose_head->sg_pci->align_entry = 4;
549 }
550
551
552 /*
553 * The System Vectors
554 */
555
556 struct alpha_machine_vector dp264_mv __initmv = {
557 .vector_name = "DP264",
558 DO_EV6_MMU,
559 DO_DEFAULT_RTC,
560 DO_TSUNAMI_IO,
561 .machine_check = tsunami_machine_check,
562 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
563 .min_io_address = DEFAULT_IO_BASE,
564 .min_mem_address = DEFAULT_MEM_BASE,
565 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
566
567 .nr_irqs = 64,
568 .device_interrupt = dp264_device_interrupt,
569
570 .init_arch = tsunami_init_arch,
571 .init_irq = dp264_init_irq,
572 .init_rtc = common_init_rtc,
573 .init_pci = dp264_init_pci,
574 .kill_arch = tsunami_kill_arch,
575 .pci_map_irq = dp264_map_irq,
576 .pci_swizzle = common_swizzle,
577 };
578 ALIAS_MV(dp264)
579
580 struct alpha_machine_vector monet_mv __initmv = {
581 .vector_name = "Monet",
582 DO_EV6_MMU,
583 DO_DEFAULT_RTC,
584 DO_TSUNAMI_IO,
585 .machine_check = tsunami_machine_check,
586 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
587 .min_io_address = DEFAULT_IO_BASE,
588 .min_mem_address = DEFAULT_MEM_BASE,
589 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
590
591 .nr_irqs = 64,
592 .device_interrupt = dp264_device_interrupt,
593
594 .init_arch = tsunami_init_arch,
595 .init_irq = dp264_init_irq,
596 .init_rtc = common_init_rtc,
597 .init_pci = monet_init_pci,
598 .kill_arch = tsunami_kill_arch,
599 .pci_map_irq = monet_map_irq,
600 .pci_swizzle = monet_swizzle,
601 };
602
603 struct alpha_machine_vector webbrick_mv __initmv = {
604 .vector_name = "Webbrick",
605 DO_EV6_MMU,
606 DO_DEFAULT_RTC,
607 DO_TSUNAMI_IO,
608 .machine_check = tsunami_machine_check,
609 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
610 .min_io_address = DEFAULT_IO_BASE,
611 .min_mem_address = DEFAULT_MEM_BASE,
612 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
613
614 .nr_irqs = 64,
615 .device_interrupt = dp264_device_interrupt,
616
617 .init_arch = webbrick_init_arch,
618 .init_irq = dp264_init_irq,
619 .init_rtc = common_init_rtc,
620 .init_pci = common_init_pci,
621 .kill_arch = tsunami_kill_arch,
622 .pci_map_irq = webbrick_map_irq,
623 .pci_swizzle = common_swizzle,
624 };
625
626 struct alpha_machine_vector clipper_mv __initmv = {
627 .vector_name = "Clipper",
628 DO_EV6_MMU,
629 DO_DEFAULT_RTC,
630 DO_TSUNAMI_IO,
631 .machine_check = clipper_machine_check,
632 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
633 .min_io_address = DEFAULT_IO_BASE,
634 .min_mem_address = DEFAULT_MEM_BASE,
635 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
636
637 .nr_irqs = 64,
638 .device_interrupt = dp264_device_interrupt,
639
640 .init_arch = tsunami_init_arch,
641 .init_irq = clipper_init_irq,
642 .init_rtc = common_init_rtc,
643 .init_pci = clipper_init_pci,
644 .kill_arch = tsunami_kill_arch,
645 .pci_map_irq = clipper_map_irq,
646 .pci_swizzle = common_swizzle,
647 };
648
649 /* Sharks strongly resemble Clipper, at least as far
650 * as interrupt routing, etc, so we're using the
651 * same functions as Clipper does
652 */
653
654 struct alpha_machine_vector shark_mv __initmv = {
655 .vector_name = "Shark",
656 DO_EV6_MMU,
657 DO_DEFAULT_RTC,
658 DO_TSUNAMI_IO,
659 .machine_check = tsunami_machine_check,
660 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
661 .min_io_address = DEFAULT_IO_BASE,
662 .min_mem_address = DEFAULT_MEM_BASE,
663 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
664
665 .nr_irqs = 64,
666 .device_interrupt = dp264_device_interrupt,
667
668 .init_arch = tsunami_init_arch,
669 .init_irq = clipper_init_irq,
670 .init_rtc = common_init_rtc,
671 .init_pci = common_init_pci,
672 .kill_arch = tsunami_kill_arch,
673 .pci_map_irq = clipper_map_irq,
674 .pci_swizzle = common_swizzle,
675 };
676
677 /* No alpha_mv alias for webbrick/monet/clipper, since we compile them
678 in unconditionally with DP264; setup_arch knows how to cope. */
679